| 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/ratelimit.h> |
| 25 | #include <linux/printk.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/types.h> |
| 29 | #include <linux/bitops.h> |
| 30 | #include <linux/sched.h> |
| 31 | #include "kfd_priv.h" |
| 32 | #include "kfd_device_queue_manager.h" |
| 33 | #include "kfd_mqd_manager.h" |
| 34 | #include "cik_regs.h" |
| 35 | #include "kfd_kernel_queue.h" |
| 36 | #include "amdgpu_amdkfd.h" |
| 37 | |
| 38 | /* Size of the per-pipe EOP queue */ |
| 39 | #define CIK_HPD_EOP_BYTES_LOG2 11 |
| 40 | #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2) |
| 41 | |
| 42 | static int set_pasid_vmid_mapping(struct device_queue_manager *dqm, |
| 43 | unsigned int pasid, unsigned int vmid); |
| 44 | |
| 45 | static int execute_queues_cpsch(struct device_queue_manager *dqm, |
| 46 | enum kfd_unmap_queues_filter filter, |
| 47 | uint32_t filter_param); |
| 48 | static int unmap_queues_cpsch(struct device_queue_manager *dqm, |
| 49 | enum kfd_unmap_queues_filter filter, |
| 50 | uint32_t filter_param); |
| 51 | |
| 52 | static int map_queues_cpsch(struct device_queue_manager *dqm); |
| 53 | |
| 54 | static void deallocate_sdma_queue(struct device_queue_manager *dqm, |
| 55 | struct queue *q); |
| 56 | |
| 57 | static inline void deallocate_hqd(struct device_queue_manager *dqm, |
| 58 | struct queue *q); |
| 59 | static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q); |
| 60 | static int allocate_sdma_queue(struct device_queue_manager *dqm, |
| 61 | struct queue *q); |
| 62 | static void kfd_process_hw_exception(struct work_struct *work); |
| 63 | |
| 64 | static inline |
| 65 | enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) |
| 66 | { |
| 67 | if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI) |
| 68 | return KFD_MQD_TYPE_SDMA; |
| 69 | return KFD_MQD_TYPE_CP; |
| 70 | } |
| 71 | |
| 72 | static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) |
| 73 | { |
| 74 | int i; |
| 75 | int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec |
| 76 | + pipe * dqm->dev->shared_resources.num_queue_per_pipe; |
| 77 | |
| 78 | /* queue is available for KFD usage if bit is 1 */ |
| 79 | for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i) |
| 80 | if (test_bit(pipe_offset + i, |
| 81 | dqm->dev->shared_resources.cp_queue_bitmap)) |
| 82 | return true; |
| 83 | return false; |
| 84 | } |
| 85 | |
| 86 | unsigned int get_cp_queues_num(struct device_queue_manager *dqm) |
| 87 | { |
| 88 | return bitmap_weight(dqm->dev->shared_resources.cp_queue_bitmap, |
| 89 | KGD_MAX_QUEUES); |
| 90 | } |
| 91 | |
| 92 | unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) |
| 93 | { |
| 94 | return dqm->dev->shared_resources.num_queue_per_pipe; |
| 95 | } |
| 96 | |
| 97 | unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) |
| 98 | { |
| 99 | return dqm->dev->shared_resources.num_pipe_per_mec; |
| 100 | } |
| 101 | |
| 102 | static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm) |
| 103 | { |
| 104 | return dqm->dev->device_info->num_sdma_engines; |
| 105 | } |
| 106 | |
| 107 | static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm) |
| 108 | { |
| 109 | return dqm->dev->device_info->num_xgmi_sdma_engines; |
| 110 | } |
| 111 | |
| 112 | unsigned int get_num_sdma_queues(struct device_queue_manager *dqm) |
| 113 | { |
| 114 | return dqm->dev->device_info->num_sdma_engines |
| 115 | * dqm->dev->device_info->num_sdma_queues_per_engine; |
| 116 | } |
| 117 | |
| 118 | unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm) |
| 119 | { |
| 120 | return dqm->dev->device_info->num_xgmi_sdma_engines |
| 121 | * dqm->dev->device_info->num_sdma_queues_per_engine; |
| 122 | } |
| 123 | |
| 124 | void program_sh_mem_settings(struct device_queue_manager *dqm, |
| 125 | struct qcm_process_device *qpd) |
| 126 | { |
| 127 | return dqm->dev->kfd2kgd->program_sh_mem_settings( |
| 128 | dqm->dev->kgd, qpd->vmid, |
| 129 | qpd->sh_mem_config, |
| 130 | qpd->sh_mem_ape1_base, |
| 131 | qpd->sh_mem_ape1_limit, |
| 132 | qpd->sh_mem_bases); |
| 133 | } |
| 134 | |
| 135 | static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q) |
| 136 | { |
| 137 | struct kfd_dev *dev = qpd->dqm->dev; |
| 138 | |
| 139 | if (!KFD_IS_SOC15(dev->device_info->asic_family)) { |
| 140 | /* On pre-SOC15 chips we need to use the queue ID to |
| 141 | * preserve the user mode ABI. |
| 142 | */ |
| 143 | q->doorbell_id = q->properties.queue_id; |
| 144 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 145 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 146 | /* For SDMA queues on SOC15 with 8-byte doorbell, use static |
| 147 | * doorbell assignments based on the engine and queue id. |
| 148 | * The doobell index distance between RLC (2*i) and (2*i+1) |
| 149 | * for a SDMA engine is 512. |
| 150 | */ |
| 151 | uint32_t *idx_offset = |
| 152 | dev->shared_resources.sdma_doorbell_idx; |
| 153 | |
| 154 | q->doorbell_id = idx_offset[q->properties.sdma_engine_id] |
| 155 | + (q->properties.sdma_queue_id & 1) |
| 156 | * KFD_QUEUE_DOORBELL_MIRROR_OFFSET |
| 157 | + (q->properties.sdma_queue_id >> 1); |
| 158 | } else { |
| 159 | /* For CP queues on SOC15 reserve a free doorbell ID */ |
| 160 | unsigned int found; |
| 161 | |
| 162 | found = find_first_zero_bit(qpd->doorbell_bitmap, |
| 163 | KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); |
| 164 | if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { |
| 165 | pr_debug("No doorbells available"); |
| 166 | return -EBUSY; |
| 167 | } |
| 168 | set_bit(found, qpd->doorbell_bitmap); |
| 169 | q->doorbell_id = found; |
| 170 | } |
| 171 | |
| 172 | q->properties.doorbell_off = |
| 173 | kfd_get_doorbell_dw_offset_in_bar(dev, q->process, |
| 174 | q->doorbell_id); |
| 175 | |
| 176 | return 0; |
| 177 | } |
| 178 | |
| 179 | static void deallocate_doorbell(struct qcm_process_device *qpd, |
| 180 | struct queue *q) |
| 181 | { |
| 182 | unsigned int old; |
| 183 | struct kfd_dev *dev = qpd->dqm->dev; |
| 184 | |
| 185 | if (!KFD_IS_SOC15(dev->device_info->asic_family) || |
| 186 | q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 187 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) |
| 188 | return; |
| 189 | |
| 190 | old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap); |
| 191 | WARN_ON(!old); |
| 192 | } |
| 193 | |
| 194 | static int allocate_vmid(struct device_queue_manager *dqm, |
| 195 | struct qcm_process_device *qpd, |
| 196 | struct queue *q) |
| 197 | { |
| 198 | int allocated_vmid = -1, i; |
| 199 | |
| 200 | for (i = dqm->dev->vm_info.first_vmid_kfd; |
| 201 | i <= dqm->dev->vm_info.last_vmid_kfd; i++) { |
| 202 | if (!dqm->vmid_pasid[i]) { |
| 203 | allocated_vmid = i; |
| 204 | break; |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | if (allocated_vmid < 0) { |
| 209 | pr_err("no more vmid to allocate\n"); |
| 210 | return -ENOSPC; |
| 211 | } |
| 212 | |
| 213 | pr_debug("vmid allocated: %d\n", allocated_vmid); |
| 214 | |
| 215 | dqm->vmid_pasid[allocated_vmid] = q->process->pasid; |
| 216 | |
| 217 | set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid); |
| 218 | |
| 219 | qpd->vmid = allocated_vmid; |
| 220 | q->properties.vmid = allocated_vmid; |
| 221 | |
| 222 | program_sh_mem_settings(dqm, qpd); |
| 223 | |
| 224 | /* qpd->page_table_base is set earlier when register_process() |
| 225 | * is called, i.e. when the first queue is created. |
| 226 | */ |
| 227 | dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd, |
| 228 | qpd->vmid, |
| 229 | qpd->page_table_base); |
| 230 | /* invalidate the VM context after pasid and vmid mapping is set up */ |
| 231 | kfd_flush_tlb(qpd_to_pdd(qpd)); |
| 232 | |
| 233 | if (dqm->dev->kfd2kgd->set_scratch_backing_va) |
| 234 | dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd, |
| 235 | qpd->sh_hidden_private_base, qpd->vmid); |
| 236 | |
| 237 | return 0; |
| 238 | } |
| 239 | |
| 240 | static int flush_texture_cache_nocpsch(struct kfd_dev *kdev, |
| 241 | struct qcm_process_device *qpd) |
| 242 | { |
| 243 | const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf; |
| 244 | int ret; |
| 245 | |
| 246 | if (!qpd->ib_kaddr) |
| 247 | return -ENOMEM; |
| 248 | |
| 249 | ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr); |
| 250 | if (ret) |
| 251 | return ret; |
| 252 | |
| 253 | return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid, |
| 254 | qpd->ib_base, (uint32_t *)qpd->ib_kaddr, |
| 255 | pmf->release_mem_size / sizeof(uint32_t)); |
| 256 | } |
| 257 | |
| 258 | static void deallocate_vmid(struct device_queue_manager *dqm, |
| 259 | struct qcm_process_device *qpd, |
| 260 | struct queue *q) |
| 261 | { |
| 262 | /* On GFX v7, CP doesn't flush TC at dequeue */ |
| 263 | if (q->device->device_info->asic_family == CHIP_HAWAII) |
| 264 | if (flush_texture_cache_nocpsch(q->device, qpd)) |
| 265 | pr_err("Failed to flush TC\n"); |
| 266 | |
| 267 | kfd_flush_tlb(qpd_to_pdd(qpd)); |
| 268 | |
| 269 | /* Release the vmid mapping */ |
| 270 | set_pasid_vmid_mapping(dqm, 0, qpd->vmid); |
| 271 | dqm->vmid_pasid[qpd->vmid] = 0; |
| 272 | |
| 273 | qpd->vmid = 0; |
| 274 | q->properties.vmid = 0; |
| 275 | } |
| 276 | |
| 277 | static int create_queue_nocpsch(struct device_queue_manager *dqm, |
| 278 | struct queue *q, |
| 279 | struct qcm_process_device *qpd) |
| 280 | { |
| 281 | struct mqd_manager *mqd_mgr; |
| 282 | int retval; |
| 283 | |
| 284 | print_queue(q); |
| 285 | |
| 286 | dqm_lock(dqm); |
| 287 | |
| 288 | if (dqm->total_queue_count >= max_num_of_queues_per_device) { |
| 289 | pr_warn("Can't create new usermode queue because %d queues were already created\n", |
| 290 | dqm->total_queue_count); |
| 291 | retval = -EPERM; |
| 292 | goto out_unlock; |
| 293 | } |
| 294 | |
| 295 | if (list_empty(&qpd->queues_list)) { |
| 296 | retval = allocate_vmid(dqm, qpd, q); |
| 297 | if (retval) |
| 298 | goto out_unlock; |
| 299 | } |
| 300 | q->properties.vmid = qpd->vmid; |
| 301 | /* |
| 302 | * Eviction state logic: mark all queues as evicted, even ones |
| 303 | * not currently active. Restoring inactive queues later only |
| 304 | * updates the is_evicted flag but is a no-op otherwise. |
| 305 | */ |
| 306 | q->properties.is_evicted = !!qpd->evicted; |
| 307 | |
| 308 | q->properties.tba_addr = qpd->tba_addr; |
| 309 | q->properties.tma_addr = qpd->tma_addr; |
| 310 | |
| 311 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 312 | q->properties.type)]; |
| 313 | if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { |
| 314 | retval = allocate_hqd(dqm, q); |
| 315 | if (retval) |
| 316 | goto deallocate_vmid; |
| 317 | pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", |
| 318 | q->pipe, q->queue); |
| 319 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 320 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 321 | retval = allocate_sdma_queue(dqm, q); |
| 322 | if (retval) |
| 323 | goto deallocate_vmid; |
| 324 | dqm->asic_ops.init_sdma_vm(dqm, q, qpd); |
| 325 | } |
| 326 | |
| 327 | retval = allocate_doorbell(qpd, q); |
| 328 | if (retval) |
| 329 | goto out_deallocate_hqd; |
| 330 | |
| 331 | /* Temporarily release dqm lock to avoid a circular lock dependency */ |
| 332 | dqm_unlock(dqm); |
| 333 | q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); |
| 334 | dqm_lock(dqm); |
| 335 | |
| 336 | if (!q->mqd_mem_obj) { |
| 337 | retval = -ENOMEM; |
| 338 | goto out_deallocate_doorbell; |
| 339 | } |
| 340 | mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, |
| 341 | &q->gart_mqd_addr, &q->properties); |
| 342 | if (q->properties.is_active) { |
| 343 | if (!dqm->sched_running) { |
| 344 | WARN_ONCE(1, "Load non-HWS mqd while stopped\n"); |
| 345 | goto add_queue_to_list; |
| 346 | } |
| 347 | |
| 348 | if (WARN(q->process->mm != current->mm, |
| 349 | "should only run in user thread")) |
| 350 | retval = -EFAULT; |
| 351 | else |
| 352 | retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, |
| 353 | q->queue, &q->properties, current->mm); |
| 354 | if (retval) |
| 355 | goto out_free_mqd; |
| 356 | } |
| 357 | |
| 358 | add_queue_to_list: |
| 359 | list_add(&q->list, &qpd->queues_list); |
| 360 | qpd->queue_count++; |
| 361 | if (q->properties.is_active) |
| 362 | dqm->active_queue_count++; |
| 363 | |
| 364 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA) |
| 365 | dqm->sdma_queue_count++; |
| 366 | else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) |
| 367 | dqm->xgmi_sdma_queue_count++; |
| 368 | |
| 369 | /* |
| 370 | * Unconditionally increment this counter, regardless of the queue's |
| 371 | * type or whether the queue is active. |
| 372 | */ |
| 373 | dqm->total_queue_count++; |
| 374 | pr_debug("Total of %d queues are accountable so far\n", |
| 375 | dqm->total_queue_count); |
| 376 | goto out_unlock; |
| 377 | |
| 378 | out_free_mqd: |
| 379 | mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); |
| 380 | out_deallocate_doorbell: |
| 381 | deallocate_doorbell(qpd, q); |
| 382 | out_deallocate_hqd: |
| 383 | if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) |
| 384 | deallocate_hqd(dqm, q); |
| 385 | else if (q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 386 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) |
| 387 | deallocate_sdma_queue(dqm, q); |
| 388 | deallocate_vmid: |
| 389 | if (list_empty(&qpd->queues_list)) |
| 390 | deallocate_vmid(dqm, qpd, q); |
| 391 | out_unlock: |
| 392 | dqm_unlock(dqm); |
| 393 | return retval; |
| 394 | } |
| 395 | |
| 396 | static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) |
| 397 | { |
| 398 | bool set; |
| 399 | int pipe, bit, i; |
| 400 | |
| 401 | set = false; |
| 402 | |
| 403 | for (pipe = dqm->next_pipe_to_allocate, i = 0; |
| 404 | i < get_pipes_per_mec(dqm); |
| 405 | pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { |
| 406 | |
| 407 | if (!is_pipe_enabled(dqm, 0, pipe)) |
| 408 | continue; |
| 409 | |
| 410 | if (dqm->allocated_queues[pipe] != 0) { |
| 411 | bit = ffs(dqm->allocated_queues[pipe]) - 1; |
| 412 | dqm->allocated_queues[pipe] &= ~(1 << bit); |
| 413 | q->pipe = pipe; |
| 414 | q->queue = bit; |
| 415 | set = true; |
| 416 | break; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | if (!set) |
| 421 | return -EBUSY; |
| 422 | |
| 423 | pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); |
| 424 | /* horizontal hqd allocation */ |
| 425 | dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); |
| 426 | |
| 427 | return 0; |
| 428 | } |
| 429 | |
| 430 | static inline void deallocate_hqd(struct device_queue_manager *dqm, |
| 431 | struct queue *q) |
| 432 | { |
| 433 | dqm->allocated_queues[q->pipe] |= (1 << q->queue); |
| 434 | } |
| 435 | |
| 436 | /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked |
| 437 | * to avoid asynchronized access |
| 438 | */ |
| 439 | static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, |
| 440 | struct qcm_process_device *qpd, |
| 441 | struct queue *q) |
| 442 | { |
| 443 | int retval; |
| 444 | struct mqd_manager *mqd_mgr; |
| 445 | |
| 446 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 447 | q->properties.type)]; |
| 448 | |
| 449 | if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { |
| 450 | deallocate_hqd(dqm, q); |
| 451 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { |
| 452 | dqm->sdma_queue_count--; |
| 453 | deallocate_sdma_queue(dqm, q); |
| 454 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 455 | dqm->xgmi_sdma_queue_count--; |
| 456 | deallocate_sdma_queue(dqm, q); |
| 457 | } else { |
| 458 | pr_debug("q->properties.type %d is invalid\n", |
| 459 | q->properties.type); |
| 460 | return -EINVAL; |
| 461 | } |
| 462 | dqm->total_queue_count--; |
| 463 | |
| 464 | deallocate_doorbell(qpd, q); |
| 465 | |
| 466 | if (!dqm->sched_running) { |
| 467 | WARN_ONCE(1, "Destroy non-HWS queue while stopped\n"); |
| 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, |
| 472 | KFD_PREEMPT_TYPE_WAVEFRONT_RESET, |
| 473 | KFD_UNMAP_LATENCY_MS, |
| 474 | q->pipe, q->queue); |
| 475 | if (retval == -ETIME) |
| 476 | qpd->reset_wavefronts = true; |
| 477 | |
| 478 | mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); |
| 479 | |
| 480 | list_del(&q->list); |
| 481 | if (list_empty(&qpd->queues_list)) { |
| 482 | if (qpd->reset_wavefronts) { |
| 483 | pr_warn("Resetting wave fronts (nocpsch) on dev %p\n", |
| 484 | dqm->dev); |
| 485 | /* dbgdev_wave_reset_wavefronts has to be called before |
| 486 | * deallocate_vmid(), i.e. when vmid is still in use. |
| 487 | */ |
| 488 | dbgdev_wave_reset_wavefronts(dqm->dev, |
| 489 | qpd->pqm->process); |
| 490 | qpd->reset_wavefronts = false; |
| 491 | } |
| 492 | |
| 493 | deallocate_vmid(dqm, qpd, q); |
| 494 | } |
| 495 | qpd->queue_count--; |
| 496 | if (q->properties.is_active) |
| 497 | dqm->active_queue_count--; |
| 498 | |
| 499 | return retval; |
| 500 | } |
| 501 | |
| 502 | static int destroy_queue_nocpsch(struct device_queue_manager *dqm, |
| 503 | struct qcm_process_device *qpd, |
| 504 | struct queue *q) |
| 505 | { |
| 506 | int retval; |
| 507 | |
| 508 | dqm_lock(dqm); |
| 509 | retval = destroy_queue_nocpsch_locked(dqm, qpd, q); |
| 510 | dqm_unlock(dqm); |
| 511 | |
| 512 | return retval; |
| 513 | } |
| 514 | |
| 515 | static int update_queue(struct device_queue_manager *dqm, struct queue *q) |
| 516 | { |
| 517 | int retval = 0; |
| 518 | struct mqd_manager *mqd_mgr; |
| 519 | struct kfd_process_device *pdd; |
| 520 | bool prev_active = false; |
| 521 | |
| 522 | dqm_lock(dqm); |
| 523 | pdd = kfd_get_process_device_data(q->device, q->process); |
| 524 | if (!pdd) { |
| 525 | retval = -ENODEV; |
| 526 | goto out_unlock; |
| 527 | } |
| 528 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 529 | q->properties.type)]; |
| 530 | |
| 531 | /* Save previous activity state for counters */ |
| 532 | prev_active = q->properties.is_active; |
| 533 | |
| 534 | /* Make sure the queue is unmapped before updating the MQD */ |
| 535 | if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) { |
| 536 | retval = unmap_queues_cpsch(dqm, |
| 537 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); |
| 538 | if (retval) { |
| 539 | pr_err("unmap queue failed\n"); |
| 540 | goto out_unlock; |
| 541 | } |
| 542 | } else if (prev_active && |
| 543 | (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || |
| 544 | q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 545 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { |
| 546 | |
| 547 | if (!dqm->sched_running) { |
| 548 | WARN_ONCE(1, "Update non-HWS queue while stopped\n"); |
| 549 | goto out_unlock; |
| 550 | } |
| 551 | |
| 552 | retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, |
| 553 | KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN, |
| 554 | KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); |
| 555 | if (retval) { |
| 556 | pr_err("destroy mqd failed\n"); |
| 557 | goto out_unlock; |
| 558 | } |
| 559 | } |
| 560 | |
| 561 | mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties); |
| 562 | |
| 563 | /* |
| 564 | * check active state vs. the previous state and modify |
| 565 | * counter accordingly. map_queues_cpsch uses the |
| 566 | * dqm->active_queue_count to determine whether a new runlist must be |
| 567 | * uploaded. |
| 568 | */ |
| 569 | if (q->properties.is_active && !prev_active) |
| 570 | dqm->active_queue_count++; |
| 571 | else if (!q->properties.is_active && prev_active) |
| 572 | dqm->active_queue_count--; |
| 573 | |
| 574 | if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) |
| 575 | retval = map_queues_cpsch(dqm); |
| 576 | else if (q->properties.is_active && |
| 577 | (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || |
| 578 | q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 579 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) { |
| 580 | if (WARN(q->process->mm != current->mm, |
| 581 | "should only run in user thread")) |
| 582 | retval = -EFAULT; |
| 583 | else |
| 584 | retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, |
| 585 | q->pipe, q->queue, |
| 586 | &q->properties, current->mm); |
| 587 | } |
| 588 | |
| 589 | out_unlock: |
| 590 | dqm_unlock(dqm); |
| 591 | return retval; |
| 592 | } |
| 593 | |
| 594 | static int evict_process_queues_nocpsch(struct device_queue_manager *dqm, |
| 595 | struct qcm_process_device *qpd) |
| 596 | { |
| 597 | struct queue *q; |
| 598 | struct mqd_manager *mqd_mgr; |
| 599 | struct kfd_process_device *pdd; |
| 600 | int retval, ret = 0; |
| 601 | |
| 602 | dqm_lock(dqm); |
| 603 | if (qpd->evicted++ > 0) /* already evicted, do nothing */ |
| 604 | goto out; |
| 605 | |
| 606 | pdd = qpd_to_pdd(qpd); |
| 607 | pr_info_ratelimited("Evicting PASID 0x%x queues\n", |
| 608 | pdd->process->pasid); |
| 609 | |
| 610 | /* Mark all queues as evicted. Deactivate all active queues on |
| 611 | * the qpd. |
| 612 | */ |
| 613 | list_for_each_entry(q, &qpd->queues_list, list) { |
| 614 | q->properties.is_evicted = true; |
| 615 | if (!q->properties.is_active) |
| 616 | continue; |
| 617 | |
| 618 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 619 | q->properties.type)]; |
| 620 | q->properties.is_active = false; |
| 621 | dqm->active_queue_count--; |
| 622 | |
| 623 | if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n")) |
| 624 | continue; |
| 625 | |
| 626 | retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, |
| 627 | KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN, |
| 628 | KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); |
| 629 | if (retval && !ret) |
| 630 | /* Return the first error, but keep going to |
| 631 | * maintain a consistent eviction state |
| 632 | */ |
| 633 | ret = retval; |
| 634 | } |
| 635 | |
| 636 | out: |
| 637 | dqm_unlock(dqm); |
| 638 | return ret; |
| 639 | } |
| 640 | |
| 641 | static int evict_process_queues_cpsch(struct device_queue_manager *dqm, |
| 642 | struct qcm_process_device *qpd) |
| 643 | { |
| 644 | struct queue *q; |
| 645 | struct kfd_process_device *pdd; |
| 646 | int retval = 0; |
| 647 | |
| 648 | dqm_lock(dqm); |
| 649 | if (qpd->evicted++ > 0) /* already evicted, do nothing */ |
| 650 | goto out; |
| 651 | |
| 652 | pdd = qpd_to_pdd(qpd); |
| 653 | pr_info_ratelimited("Evicting PASID 0x%x queues\n", |
| 654 | pdd->process->pasid); |
| 655 | |
| 656 | /* Mark all queues as evicted. Deactivate all active queues on |
| 657 | * the qpd. |
| 658 | */ |
| 659 | list_for_each_entry(q, &qpd->queues_list, list) { |
| 660 | q->properties.is_evicted = true; |
| 661 | if (!q->properties.is_active) |
| 662 | continue; |
| 663 | |
| 664 | q->properties.is_active = false; |
| 665 | dqm->active_queue_count--; |
| 666 | } |
| 667 | retval = execute_queues_cpsch(dqm, |
| 668 | qpd->is_debug ? |
| 669 | KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : |
| 670 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); |
| 671 | |
| 672 | out: |
| 673 | dqm_unlock(dqm); |
| 674 | return retval; |
| 675 | } |
| 676 | |
| 677 | static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, |
| 678 | struct qcm_process_device *qpd) |
| 679 | { |
| 680 | struct mm_struct *mm = NULL; |
| 681 | struct queue *q; |
| 682 | struct mqd_manager *mqd_mgr; |
| 683 | struct kfd_process_device *pdd; |
| 684 | uint64_t pd_base; |
| 685 | int retval, ret = 0; |
| 686 | |
| 687 | pdd = qpd_to_pdd(qpd); |
| 688 | /* Retrieve PD base */ |
| 689 | pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm); |
| 690 | |
| 691 | dqm_lock(dqm); |
| 692 | if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ |
| 693 | goto out; |
| 694 | if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ |
| 695 | qpd->evicted--; |
| 696 | goto out; |
| 697 | } |
| 698 | |
| 699 | pr_info_ratelimited("Restoring PASID 0x%x queues\n", |
| 700 | pdd->process->pasid); |
| 701 | |
| 702 | /* Update PD Base in QPD */ |
| 703 | qpd->page_table_base = pd_base; |
| 704 | pr_debug("Updated PD address to 0x%llx\n", pd_base); |
| 705 | |
| 706 | if (!list_empty(&qpd->queues_list)) { |
| 707 | dqm->dev->kfd2kgd->set_vm_context_page_table_base( |
| 708 | dqm->dev->kgd, |
| 709 | qpd->vmid, |
| 710 | qpd->page_table_base); |
| 711 | kfd_flush_tlb(pdd); |
| 712 | } |
| 713 | |
| 714 | /* Take a safe reference to the mm_struct, which may otherwise |
| 715 | * disappear even while the kfd_process is still referenced. |
| 716 | */ |
| 717 | mm = get_task_mm(pdd->process->lead_thread); |
| 718 | if (!mm) { |
| 719 | ret = -EFAULT; |
| 720 | goto out; |
| 721 | } |
| 722 | |
| 723 | /* Remove the eviction flags. Activate queues that are not |
| 724 | * inactive for other reasons. |
| 725 | */ |
| 726 | list_for_each_entry(q, &qpd->queues_list, list) { |
| 727 | q->properties.is_evicted = false; |
| 728 | if (!QUEUE_IS_ACTIVE(q->properties)) |
| 729 | continue; |
| 730 | |
| 731 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 732 | q->properties.type)]; |
| 733 | q->properties.is_active = true; |
| 734 | dqm->active_queue_count++; |
| 735 | |
| 736 | if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n")) |
| 737 | continue; |
| 738 | |
| 739 | retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, |
| 740 | q->queue, &q->properties, mm); |
| 741 | if (retval && !ret) |
| 742 | /* Return the first error, but keep going to |
| 743 | * maintain a consistent eviction state |
| 744 | */ |
| 745 | ret = retval; |
| 746 | } |
| 747 | qpd->evicted = 0; |
| 748 | out: |
| 749 | if (mm) |
| 750 | mmput(mm); |
| 751 | dqm_unlock(dqm); |
| 752 | return ret; |
| 753 | } |
| 754 | |
| 755 | static int restore_process_queues_cpsch(struct device_queue_manager *dqm, |
| 756 | struct qcm_process_device *qpd) |
| 757 | { |
| 758 | struct queue *q; |
| 759 | struct kfd_process_device *pdd; |
| 760 | uint64_t pd_base; |
| 761 | int retval = 0; |
| 762 | |
| 763 | pdd = qpd_to_pdd(qpd); |
| 764 | /* Retrieve PD base */ |
| 765 | pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm); |
| 766 | |
| 767 | dqm_lock(dqm); |
| 768 | if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */ |
| 769 | goto out; |
| 770 | if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */ |
| 771 | qpd->evicted--; |
| 772 | goto out; |
| 773 | } |
| 774 | |
| 775 | pr_info_ratelimited("Restoring PASID 0x%x queues\n", |
| 776 | pdd->process->pasid); |
| 777 | |
| 778 | /* Update PD Base in QPD */ |
| 779 | qpd->page_table_base = pd_base; |
| 780 | pr_debug("Updated PD address to 0x%llx\n", pd_base); |
| 781 | |
| 782 | /* activate all active queues on the qpd */ |
| 783 | list_for_each_entry(q, &qpd->queues_list, list) { |
| 784 | q->properties.is_evicted = false; |
| 785 | if (!QUEUE_IS_ACTIVE(q->properties)) |
| 786 | continue; |
| 787 | |
| 788 | q->properties.is_active = true; |
| 789 | dqm->active_queue_count++; |
| 790 | } |
| 791 | retval = execute_queues_cpsch(dqm, |
| 792 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); |
| 793 | qpd->evicted = 0; |
| 794 | out: |
| 795 | dqm_unlock(dqm); |
| 796 | return retval; |
| 797 | } |
| 798 | |
| 799 | static int register_process(struct device_queue_manager *dqm, |
| 800 | struct qcm_process_device *qpd) |
| 801 | { |
| 802 | struct device_process_node *n; |
| 803 | struct kfd_process_device *pdd; |
| 804 | uint64_t pd_base; |
| 805 | int retval; |
| 806 | |
| 807 | n = kzalloc(sizeof(*n), GFP_KERNEL); |
| 808 | if (!n) |
| 809 | return -ENOMEM; |
| 810 | |
| 811 | n->qpd = qpd; |
| 812 | |
| 813 | pdd = qpd_to_pdd(qpd); |
| 814 | /* Retrieve PD base */ |
| 815 | pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm); |
| 816 | |
| 817 | dqm_lock(dqm); |
| 818 | list_add(&n->list, &dqm->queues); |
| 819 | |
| 820 | /* Update PD Base in QPD */ |
| 821 | qpd->page_table_base = pd_base; |
| 822 | pr_debug("Updated PD address to 0x%llx\n", pd_base); |
| 823 | |
| 824 | retval = dqm->asic_ops.update_qpd(dqm, qpd); |
| 825 | |
| 826 | dqm->processes_count++; |
| 827 | |
| 828 | dqm_unlock(dqm); |
| 829 | |
| 830 | /* Outside the DQM lock because under the DQM lock we can't do |
| 831 | * reclaim or take other locks that others hold while reclaiming. |
| 832 | */ |
| 833 | kfd_inc_compute_active(dqm->dev); |
| 834 | |
| 835 | return retval; |
| 836 | } |
| 837 | |
| 838 | static int unregister_process(struct device_queue_manager *dqm, |
| 839 | struct qcm_process_device *qpd) |
| 840 | { |
| 841 | int retval; |
| 842 | struct device_process_node *cur, *next; |
| 843 | |
| 844 | pr_debug("qpd->queues_list is %s\n", |
| 845 | list_empty(&qpd->queues_list) ? "empty" : "not empty"); |
| 846 | |
| 847 | retval = 0; |
| 848 | dqm_lock(dqm); |
| 849 | |
| 850 | list_for_each_entry_safe(cur, next, &dqm->queues, list) { |
| 851 | if (qpd == cur->qpd) { |
| 852 | list_del(&cur->list); |
| 853 | kfree(cur); |
| 854 | dqm->processes_count--; |
| 855 | goto out; |
| 856 | } |
| 857 | } |
| 858 | /* qpd not found in dqm list */ |
| 859 | retval = 1; |
| 860 | out: |
| 861 | dqm_unlock(dqm); |
| 862 | |
| 863 | /* Outside the DQM lock because under the DQM lock we can't do |
| 864 | * reclaim or take other locks that others hold while reclaiming. |
| 865 | */ |
| 866 | if (!retval) |
| 867 | kfd_dec_compute_active(dqm->dev); |
| 868 | |
| 869 | return retval; |
| 870 | } |
| 871 | |
| 872 | static int |
| 873 | set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid, |
| 874 | unsigned int vmid) |
| 875 | { |
| 876 | return dqm->dev->kfd2kgd->set_pasid_vmid_mapping( |
| 877 | dqm->dev->kgd, pasid, vmid); |
| 878 | } |
| 879 | |
| 880 | static void init_interrupts(struct device_queue_manager *dqm) |
| 881 | { |
| 882 | unsigned int i; |
| 883 | |
| 884 | for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) |
| 885 | if (is_pipe_enabled(dqm, 0, i)) |
| 886 | dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i); |
| 887 | } |
| 888 | |
| 889 | static int initialize_nocpsch(struct device_queue_manager *dqm) |
| 890 | { |
| 891 | int pipe, queue; |
| 892 | |
| 893 | pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); |
| 894 | |
| 895 | dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), |
| 896 | sizeof(unsigned int), GFP_KERNEL); |
| 897 | if (!dqm->allocated_queues) |
| 898 | return -ENOMEM; |
| 899 | |
| 900 | mutex_init(&dqm->lock_hidden); |
| 901 | INIT_LIST_HEAD(&dqm->queues); |
| 902 | dqm->active_queue_count = dqm->next_pipe_to_allocate = 0; |
| 903 | dqm->sdma_queue_count = 0; |
| 904 | dqm->xgmi_sdma_queue_count = 0; |
| 905 | |
| 906 | for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { |
| 907 | int pipe_offset = pipe * get_queues_per_pipe(dqm); |
| 908 | |
| 909 | for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) |
| 910 | if (test_bit(pipe_offset + queue, |
| 911 | dqm->dev->shared_resources.cp_queue_bitmap)) |
| 912 | dqm->allocated_queues[pipe] |= 1 << queue; |
| 913 | } |
| 914 | |
| 915 | memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid)); |
| 916 | |
| 917 | dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); |
| 918 | dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); |
| 919 | |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | static void uninitialize(struct device_queue_manager *dqm) |
| 924 | { |
| 925 | int i; |
| 926 | |
| 927 | WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0); |
| 928 | |
| 929 | kfree(dqm->allocated_queues); |
| 930 | for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) |
| 931 | kfree(dqm->mqd_mgrs[i]); |
| 932 | mutex_destroy(&dqm->lock_hidden); |
| 933 | } |
| 934 | |
| 935 | static int start_nocpsch(struct device_queue_manager *dqm) |
| 936 | { |
| 937 | pr_info("SW scheduler is used"); |
| 938 | init_interrupts(dqm); |
| 939 | |
| 940 | if (dqm->dev->device_info->asic_family == CHIP_HAWAII) |
| 941 | return pm_init(&dqm->packets, dqm); |
| 942 | dqm->sched_running = true; |
| 943 | |
| 944 | return 0; |
| 945 | } |
| 946 | |
| 947 | static int stop_nocpsch(struct device_queue_manager *dqm) |
| 948 | { |
| 949 | if (dqm->dev->device_info->asic_family == CHIP_HAWAII) |
| 950 | pm_uninit(&dqm->packets, false); |
| 951 | dqm->sched_running = false; |
| 952 | |
| 953 | return 0; |
| 954 | } |
| 955 | |
| 956 | static void pre_reset(struct device_queue_manager *dqm) |
| 957 | { |
| 958 | dqm_lock(dqm); |
| 959 | dqm->is_resetting = true; |
| 960 | dqm_unlock(dqm); |
| 961 | } |
| 962 | |
| 963 | static int allocate_sdma_queue(struct device_queue_manager *dqm, |
| 964 | struct queue *q) |
| 965 | { |
| 966 | int bit; |
| 967 | |
| 968 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { |
| 969 | if (dqm->sdma_bitmap == 0) |
| 970 | return -ENOMEM; |
| 971 | bit = __ffs64(dqm->sdma_bitmap); |
| 972 | dqm->sdma_bitmap &= ~(1ULL << bit); |
| 973 | q->sdma_id = bit; |
| 974 | q->properties.sdma_engine_id = q->sdma_id % |
| 975 | get_num_sdma_engines(dqm); |
| 976 | q->properties.sdma_queue_id = q->sdma_id / |
| 977 | get_num_sdma_engines(dqm); |
| 978 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 979 | if (dqm->xgmi_sdma_bitmap == 0) |
| 980 | return -ENOMEM; |
| 981 | bit = __ffs64(dqm->xgmi_sdma_bitmap); |
| 982 | dqm->xgmi_sdma_bitmap &= ~(1ULL << bit); |
| 983 | q->sdma_id = bit; |
| 984 | /* sdma_engine_id is sdma id including |
| 985 | * both PCIe-optimized SDMAs and XGMI- |
| 986 | * optimized SDMAs. The calculation below |
| 987 | * assumes the first N engines are always |
| 988 | * PCIe-optimized ones |
| 989 | */ |
| 990 | q->properties.sdma_engine_id = get_num_sdma_engines(dqm) + |
| 991 | q->sdma_id % get_num_xgmi_sdma_engines(dqm); |
| 992 | q->properties.sdma_queue_id = q->sdma_id / |
| 993 | get_num_xgmi_sdma_engines(dqm); |
| 994 | } |
| 995 | |
| 996 | pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); |
| 997 | pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); |
| 998 | |
| 999 | return 0; |
| 1000 | } |
| 1001 | |
| 1002 | static void deallocate_sdma_queue(struct device_queue_manager *dqm, |
| 1003 | struct queue *q) |
| 1004 | { |
| 1005 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { |
| 1006 | if (q->sdma_id >= get_num_sdma_queues(dqm)) |
| 1007 | return; |
| 1008 | dqm->sdma_bitmap |= (1ULL << q->sdma_id); |
| 1009 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 1010 | if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm)) |
| 1011 | return; |
| 1012 | dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id); |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | /* |
| 1017 | * Device Queue Manager implementation for cp scheduler |
| 1018 | */ |
| 1019 | |
| 1020 | static int set_sched_resources(struct device_queue_manager *dqm) |
| 1021 | { |
| 1022 | int i, mec; |
| 1023 | struct scheduling_resources res; |
| 1024 | |
| 1025 | res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap; |
| 1026 | |
| 1027 | res.queue_mask = 0; |
| 1028 | for (i = 0; i < KGD_MAX_QUEUES; ++i) { |
| 1029 | mec = (i / dqm->dev->shared_resources.num_queue_per_pipe) |
| 1030 | / dqm->dev->shared_resources.num_pipe_per_mec; |
| 1031 | |
| 1032 | if (!test_bit(i, dqm->dev->shared_resources.cp_queue_bitmap)) |
| 1033 | continue; |
| 1034 | |
| 1035 | /* only acquire queues from the first MEC */ |
| 1036 | if (mec > 0) |
| 1037 | continue; |
| 1038 | |
| 1039 | /* This situation may be hit in the future if a new HW |
| 1040 | * generation exposes more than 64 queues. If so, the |
| 1041 | * definition of res.queue_mask needs updating |
| 1042 | */ |
| 1043 | if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { |
| 1044 | pr_err("Invalid queue enabled by amdgpu: %d\n", i); |
| 1045 | break; |
| 1046 | } |
| 1047 | |
| 1048 | res.queue_mask |= (1ull << i); |
| 1049 | } |
| 1050 | res.gws_mask = ~0ull; |
| 1051 | res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; |
| 1052 | |
| 1053 | pr_debug("Scheduling resources:\n" |
| 1054 | "vmid mask: 0x%8X\n" |
| 1055 | "queue mask: 0x%8llX\n", |
| 1056 | res.vmid_mask, res.queue_mask); |
| 1057 | |
| 1058 | return pm_send_set_resources(&dqm->packets, &res); |
| 1059 | } |
| 1060 | |
| 1061 | static int initialize_cpsch(struct device_queue_manager *dqm) |
| 1062 | { |
| 1063 | pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); |
| 1064 | |
| 1065 | mutex_init(&dqm->lock_hidden); |
| 1066 | INIT_LIST_HEAD(&dqm->queues); |
| 1067 | dqm->active_queue_count = dqm->processes_count = 0; |
| 1068 | dqm->sdma_queue_count = 0; |
| 1069 | dqm->xgmi_sdma_queue_count = 0; |
| 1070 | dqm->active_runlist = false; |
| 1071 | dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm)); |
| 1072 | dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm)); |
| 1073 | |
| 1074 | INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); |
| 1075 | |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
| 1079 | static int start_cpsch(struct device_queue_manager *dqm) |
| 1080 | { |
| 1081 | int retval; |
| 1082 | |
| 1083 | retval = 0; |
| 1084 | |
| 1085 | retval = pm_init(&dqm->packets, dqm); |
| 1086 | if (retval) |
| 1087 | goto fail_packet_manager_init; |
| 1088 | |
| 1089 | retval = set_sched_resources(dqm); |
| 1090 | if (retval) |
| 1091 | goto fail_set_sched_resources; |
| 1092 | |
| 1093 | pr_debug("Allocating fence memory\n"); |
| 1094 | |
| 1095 | /* allocate fence memory on the gart */ |
| 1096 | retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), |
| 1097 | &dqm->fence_mem); |
| 1098 | |
| 1099 | if (retval) |
| 1100 | goto fail_allocate_vidmem; |
| 1101 | |
| 1102 | dqm->fence_addr = dqm->fence_mem->cpu_ptr; |
| 1103 | dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; |
| 1104 | |
| 1105 | init_interrupts(dqm); |
| 1106 | |
| 1107 | dqm_lock(dqm); |
| 1108 | /* clear hang status when driver try to start the hw scheduler */ |
| 1109 | dqm->is_hws_hang = false; |
| 1110 | dqm->is_resetting = false; |
| 1111 | dqm->sched_running = true; |
| 1112 | execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); |
| 1113 | dqm_unlock(dqm); |
| 1114 | |
| 1115 | return 0; |
| 1116 | fail_allocate_vidmem: |
| 1117 | fail_set_sched_resources: |
| 1118 | pm_uninit(&dqm->packets, false); |
| 1119 | fail_packet_manager_init: |
| 1120 | return retval; |
| 1121 | } |
| 1122 | |
| 1123 | static int stop_cpsch(struct device_queue_manager *dqm) |
| 1124 | { |
| 1125 | bool hanging; |
| 1126 | |
| 1127 | dqm_lock(dqm); |
| 1128 | if (!dqm->is_hws_hang) |
| 1129 | unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); |
| 1130 | hanging = dqm->is_hws_hang || dqm->is_resetting; |
| 1131 | dqm->sched_running = false; |
| 1132 | dqm_unlock(dqm); |
| 1133 | |
| 1134 | kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); |
| 1135 | pm_uninit(&dqm->packets, hanging); |
| 1136 | |
| 1137 | return 0; |
| 1138 | } |
| 1139 | |
| 1140 | static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, |
| 1141 | struct kernel_queue *kq, |
| 1142 | struct qcm_process_device *qpd) |
| 1143 | { |
| 1144 | dqm_lock(dqm); |
| 1145 | if (dqm->total_queue_count >= max_num_of_queues_per_device) { |
| 1146 | pr_warn("Can't create new kernel queue because %d queues were already created\n", |
| 1147 | dqm->total_queue_count); |
| 1148 | dqm_unlock(dqm); |
| 1149 | return -EPERM; |
| 1150 | } |
| 1151 | |
| 1152 | /* |
| 1153 | * Unconditionally increment this counter, regardless of the queue's |
| 1154 | * type or whether the queue is active. |
| 1155 | */ |
| 1156 | dqm->total_queue_count++; |
| 1157 | pr_debug("Total of %d queues are accountable so far\n", |
| 1158 | dqm->total_queue_count); |
| 1159 | |
| 1160 | list_add(&kq->list, &qpd->priv_queue_list); |
| 1161 | dqm->active_queue_count++; |
| 1162 | qpd->is_debug = true; |
| 1163 | execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); |
| 1164 | dqm_unlock(dqm); |
| 1165 | |
| 1166 | return 0; |
| 1167 | } |
| 1168 | |
| 1169 | static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, |
| 1170 | struct kernel_queue *kq, |
| 1171 | struct qcm_process_device *qpd) |
| 1172 | { |
| 1173 | dqm_lock(dqm); |
| 1174 | list_del(&kq->list); |
| 1175 | dqm->active_queue_count--; |
| 1176 | qpd->is_debug = false; |
| 1177 | execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); |
| 1178 | /* |
| 1179 | * Unconditionally decrement this counter, regardless of the queue's |
| 1180 | * type. |
| 1181 | */ |
| 1182 | dqm->total_queue_count--; |
| 1183 | pr_debug("Total of %d queues are accountable so far\n", |
| 1184 | dqm->total_queue_count); |
| 1185 | dqm_unlock(dqm); |
| 1186 | } |
| 1187 | |
| 1188 | static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, |
| 1189 | struct qcm_process_device *qpd) |
| 1190 | { |
| 1191 | int retval; |
| 1192 | struct mqd_manager *mqd_mgr; |
| 1193 | |
| 1194 | if (dqm->total_queue_count >= max_num_of_queues_per_device) { |
| 1195 | pr_warn("Can't create new usermode queue because %d queues were already created\n", |
| 1196 | dqm->total_queue_count); |
| 1197 | retval = -EPERM; |
| 1198 | goto out; |
| 1199 | } |
| 1200 | |
| 1201 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 1202 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 1203 | dqm_lock(dqm); |
| 1204 | retval = allocate_sdma_queue(dqm, q); |
| 1205 | dqm_unlock(dqm); |
| 1206 | if (retval) |
| 1207 | goto out; |
| 1208 | } |
| 1209 | |
| 1210 | retval = allocate_doorbell(qpd, q); |
| 1211 | if (retval) |
| 1212 | goto out_deallocate_sdma_queue; |
| 1213 | |
| 1214 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 1215 | q->properties.type)]; |
| 1216 | |
| 1217 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 1218 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) |
| 1219 | dqm->asic_ops.init_sdma_vm(dqm, q, qpd); |
| 1220 | q->properties.tba_addr = qpd->tba_addr; |
| 1221 | q->properties.tma_addr = qpd->tma_addr; |
| 1222 | q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); |
| 1223 | if (!q->mqd_mem_obj) { |
| 1224 | retval = -ENOMEM; |
| 1225 | goto out_deallocate_doorbell; |
| 1226 | } |
| 1227 | |
| 1228 | dqm_lock(dqm); |
| 1229 | /* |
| 1230 | * Eviction state logic: mark all queues as evicted, even ones |
| 1231 | * not currently active. Restoring inactive queues later only |
| 1232 | * updates the is_evicted flag but is a no-op otherwise. |
| 1233 | */ |
| 1234 | q->properties.is_evicted = !!qpd->evicted; |
| 1235 | mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, |
| 1236 | &q->gart_mqd_addr, &q->properties); |
| 1237 | |
| 1238 | list_add(&q->list, &qpd->queues_list); |
| 1239 | qpd->queue_count++; |
| 1240 | |
| 1241 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA) |
| 1242 | dqm->sdma_queue_count++; |
| 1243 | else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) |
| 1244 | dqm->xgmi_sdma_queue_count++; |
| 1245 | |
| 1246 | if (q->properties.is_active) { |
| 1247 | dqm->active_queue_count++; |
| 1248 | retval = execute_queues_cpsch(dqm, |
| 1249 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); |
| 1250 | } |
| 1251 | |
| 1252 | /* |
| 1253 | * Unconditionally increment this counter, regardless of the queue's |
| 1254 | * type or whether the queue is active. |
| 1255 | */ |
| 1256 | dqm->total_queue_count++; |
| 1257 | |
| 1258 | pr_debug("Total of %d queues are accountable so far\n", |
| 1259 | dqm->total_queue_count); |
| 1260 | |
| 1261 | dqm_unlock(dqm); |
| 1262 | return retval; |
| 1263 | |
| 1264 | out_deallocate_doorbell: |
| 1265 | deallocate_doorbell(qpd, q); |
| 1266 | out_deallocate_sdma_queue: |
| 1267 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA || |
| 1268 | q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 1269 | dqm_lock(dqm); |
| 1270 | deallocate_sdma_queue(dqm, q); |
| 1271 | dqm_unlock(dqm); |
| 1272 | } |
| 1273 | out: |
| 1274 | return retval; |
| 1275 | } |
| 1276 | |
| 1277 | int amdkfd_fence_wait_timeout(unsigned int *fence_addr, |
| 1278 | unsigned int fence_value, |
| 1279 | unsigned int timeout_ms) |
| 1280 | { |
| 1281 | unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; |
| 1282 | |
| 1283 | while (*fence_addr != fence_value) { |
| 1284 | if (time_after(jiffies, end_jiffies)) { |
| 1285 | pr_err("qcm fence wait loop timeout expired\n"); |
| 1286 | /* In HWS case, this is used to halt the driver thread |
| 1287 | * in order not to mess up CP states before doing |
| 1288 | * scandumps for FW debugging. |
| 1289 | */ |
| 1290 | while (halt_if_hws_hang) |
| 1291 | schedule(); |
| 1292 | |
| 1293 | return -ETIME; |
| 1294 | } |
| 1295 | schedule(); |
| 1296 | } |
| 1297 | |
| 1298 | return 0; |
| 1299 | } |
| 1300 | |
| 1301 | static int unmap_sdma_queues(struct device_queue_manager *dqm) |
| 1302 | { |
| 1303 | int i, retval = 0; |
| 1304 | |
| 1305 | for (i = 0; i < dqm->dev->device_info->num_sdma_engines + |
| 1306 | dqm->dev->device_info->num_xgmi_sdma_engines; i++) { |
| 1307 | retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA, |
| 1308 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false, i); |
| 1309 | if (retval) |
| 1310 | return retval; |
| 1311 | } |
| 1312 | return retval; |
| 1313 | } |
| 1314 | |
| 1315 | /* dqm->lock mutex has to be locked before calling this function */ |
| 1316 | static int map_queues_cpsch(struct device_queue_manager *dqm) |
| 1317 | { |
| 1318 | int retval; |
| 1319 | |
| 1320 | if (!dqm->sched_running) |
| 1321 | return 0; |
| 1322 | if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) |
| 1323 | return 0; |
| 1324 | if (dqm->active_runlist) |
| 1325 | return 0; |
| 1326 | |
| 1327 | retval = pm_send_runlist(&dqm->packets, &dqm->queues); |
| 1328 | pr_debug("%s sent runlist\n", __func__); |
| 1329 | if (retval) { |
| 1330 | pr_err("failed to execute runlist\n"); |
| 1331 | return retval; |
| 1332 | } |
| 1333 | dqm->active_runlist = true; |
| 1334 | |
| 1335 | return retval; |
| 1336 | } |
| 1337 | |
| 1338 | /* dqm->lock mutex has to be locked before calling this function */ |
| 1339 | static int unmap_queues_cpsch(struct device_queue_manager *dqm, |
| 1340 | enum kfd_unmap_queues_filter filter, |
| 1341 | uint32_t filter_param) |
| 1342 | { |
| 1343 | int retval = 0; |
| 1344 | |
| 1345 | if (!dqm->sched_running) |
| 1346 | return 0; |
| 1347 | if (dqm->is_hws_hang) |
| 1348 | return -EIO; |
| 1349 | if (!dqm->active_runlist) |
| 1350 | return retval; |
| 1351 | |
| 1352 | pr_debug("Before destroying queues, sdma queue count is : %u, xgmi sdma queue count is : %u\n", |
| 1353 | dqm->sdma_queue_count, dqm->xgmi_sdma_queue_count); |
| 1354 | |
| 1355 | if (dqm->sdma_queue_count > 0 || dqm->xgmi_sdma_queue_count) |
| 1356 | unmap_sdma_queues(dqm); |
| 1357 | |
| 1358 | retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE, |
| 1359 | filter, filter_param, false, 0); |
| 1360 | if (retval) |
| 1361 | return retval; |
| 1362 | |
| 1363 | *dqm->fence_addr = KFD_FENCE_INIT; |
| 1364 | pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr, |
| 1365 | KFD_FENCE_COMPLETED); |
| 1366 | /* should be timed out */ |
| 1367 | retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, |
| 1368 | queue_preemption_timeout_ms); |
| 1369 | if (retval) { |
| 1370 | pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n"); |
| 1371 | dqm->is_hws_hang = true; |
| 1372 | /* It's possible we're detecting a HWS hang in the |
| 1373 | * middle of a GPU reset. No need to schedule another |
| 1374 | * reset in this case. |
| 1375 | */ |
| 1376 | if (!dqm->is_resetting) |
| 1377 | schedule_work(&dqm->hw_exception_work); |
| 1378 | return retval; |
| 1379 | } |
| 1380 | |
| 1381 | pm_release_ib(&dqm->packets); |
| 1382 | dqm->active_runlist = false; |
| 1383 | |
| 1384 | return retval; |
| 1385 | } |
| 1386 | |
| 1387 | /* dqm->lock mutex has to be locked before calling this function */ |
| 1388 | static int execute_queues_cpsch(struct device_queue_manager *dqm, |
| 1389 | enum kfd_unmap_queues_filter filter, |
| 1390 | uint32_t filter_param) |
| 1391 | { |
| 1392 | int retval; |
| 1393 | |
| 1394 | if (dqm->is_hws_hang) |
| 1395 | return -EIO; |
| 1396 | retval = unmap_queues_cpsch(dqm, filter, filter_param); |
| 1397 | if (retval) |
| 1398 | return retval; |
| 1399 | |
| 1400 | return map_queues_cpsch(dqm); |
| 1401 | } |
| 1402 | |
| 1403 | static int destroy_queue_cpsch(struct device_queue_manager *dqm, |
| 1404 | struct qcm_process_device *qpd, |
| 1405 | struct queue *q) |
| 1406 | { |
| 1407 | int retval; |
| 1408 | struct mqd_manager *mqd_mgr; |
| 1409 | |
| 1410 | retval = 0; |
| 1411 | |
| 1412 | /* remove queue from list to prevent rescheduling after preemption */ |
| 1413 | dqm_lock(dqm); |
| 1414 | |
| 1415 | if (qpd->is_debug) { |
| 1416 | /* |
| 1417 | * error, currently we do not allow to destroy a queue |
| 1418 | * of a currently debugged process |
| 1419 | */ |
| 1420 | retval = -EBUSY; |
| 1421 | goto failed_try_destroy_debugged_queue; |
| 1422 | |
| 1423 | } |
| 1424 | |
| 1425 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 1426 | q->properties.type)]; |
| 1427 | |
| 1428 | deallocate_doorbell(qpd, q); |
| 1429 | |
| 1430 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { |
| 1431 | dqm->sdma_queue_count--; |
| 1432 | deallocate_sdma_queue(dqm, q); |
| 1433 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 1434 | dqm->xgmi_sdma_queue_count--; |
| 1435 | deallocate_sdma_queue(dqm, q); |
| 1436 | } |
| 1437 | |
| 1438 | list_del(&q->list); |
| 1439 | qpd->queue_count--; |
| 1440 | if (q->properties.is_active) { |
| 1441 | dqm->active_queue_count--; |
| 1442 | retval = execute_queues_cpsch(dqm, |
| 1443 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0); |
| 1444 | if (retval == -ETIME) |
| 1445 | qpd->reset_wavefronts = true; |
| 1446 | } |
| 1447 | |
| 1448 | /* |
| 1449 | * Unconditionally decrement this counter, regardless of the queue's |
| 1450 | * type |
| 1451 | */ |
| 1452 | dqm->total_queue_count--; |
| 1453 | pr_debug("Total of %d queues are accountable so far\n", |
| 1454 | dqm->total_queue_count); |
| 1455 | |
| 1456 | dqm_unlock(dqm); |
| 1457 | |
| 1458 | /* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */ |
| 1459 | mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); |
| 1460 | |
| 1461 | return retval; |
| 1462 | |
| 1463 | failed_try_destroy_debugged_queue: |
| 1464 | |
| 1465 | dqm_unlock(dqm); |
| 1466 | return retval; |
| 1467 | } |
| 1468 | |
| 1469 | /* |
| 1470 | * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to |
| 1471 | * stay in user mode. |
| 1472 | */ |
| 1473 | #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL |
| 1474 | /* APE1 limit is inclusive and 64K aligned. */ |
| 1475 | #define APE1_LIMIT_ALIGNMENT 0xFFFF |
| 1476 | |
| 1477 | static bool set_cache_memory_policy(struct device_queue_manager *dqm, |
| 1478 | struct qcm_process_device *qpd, |
| 1479 | enum cache_policy default_policy, |
| 1480 | enum cache_policy alternate_policy, |
| 1481 | void __user *alternate_aperture_base, |
| 1482 | uint64_t alternate_aperture_size) |
| 1483 | { |
| 1484 | bool retval = true; |
| 1485 | |
| 1486 | if (!dqm->asic_ops.set_cache_memory_policy) |
| 1487 | return retval; |
| 1488 | |
| 1489 | dqm_lock(dqm); |
| 1490 | |
| 1491 | if (alternate_aperture_size == 0) { |
| 1492 | /* base > limit disables APE1 */ |
| 1493 | qpd->sh_mem_ape1_base = 1; |
| 1494 | qpd->sh_mem_ape1_limit = 0; |
| 1495 | } else { |
| 1496 | /* |
| 1497 | * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, |
| 1498 | * SH_MEM_APE1_BASE[31:0], 0x0000 } |
| 1499 | * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, |
| 1500 | * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } |
| 1501 | * Verify that the base and size parameters can be |
| 1502 | * represented in this format and convert them. |
| 1503 | * Additionally restrict APE1 to user-mode addresses. |
| 1504 | */ |
| 1505 | |
| 1506 | uint64_t base = (uintptr_t)alternate_aperture_base; |
| 1507 | uint64_t limit = base + alternate_aperture_size - 1; |
| 1508 | |
| 1509 | if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || |
| 1510 | (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { |
| 1511 | retval = false; |
| 1512 | goto out; |
| 1513 | } |
| 1514 | |
| 1515 | qpd->sh_mem_ape1_base = base >> 16; |
| 1516 | qpd->sh_mem_ape1_limit = limit >> 16; |
| 1517 | } |
| 1518 | |
| 1519 | retval = dqm->asic_ops.set_cache_memory_policy( |
| 1520 | dqm, |
| 1521 | qpd, |
| 1522 | default_policy, |
| 1523 | alternate_policy, |
| 1524 | alternate_aperture_base, |
| 1525 | alternate_aperture_size); |
| 1526 | |
| 1527 | if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) |
| 1528 | program_sh_mem_settings(dqm, qpd); |
| 1529 | |
| 1530 | pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", |
| 1531 | qpd->sh_mem_config, qpd->sh_mem_ape1_base, |
| 1532 | qpd->sh_mem_ape1_limit); |
| 1533 | |
| 1534 | out: |
| 1535 | dqm_unlock(dqm); |
| 1536 | return retval; |
| 1537 | } |
| 1538 | |
| 1539 | static int set_trap_handler(struct device_queue_manager *dqm, |
| 1540 | struct qcm_process_device *qpd, |
| 1541 | uint64_t tba_addr, |
| 1542 | uint64_t tma_addr) |
| 1543 | { |
| 1544 | uint64_t *tma; |
| 1545 | |
| 1546 | if (dqm->dev->cwsr_enabled) { |
| 1547 | /* Jump from CWSR trap handler to user trap */ |
| 1548 | tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); |
| 1549 | tma[0] = tba_addr; |
| 1550 | tma[1] = tma_addr; |
| 1551 | } else { |
| 1552 | qpd->tba_addr = tba_addr; |
| 1553 | qpd->tma_addr = tma_addr; |
| 1554 | } |
| 1555 | |
| 1556 | return 0; |
| 1557 | } |
| 1558 | |
| 1559 | static int process_termination_nocpsch(struct device_queue_manager *dqm, |
| 1560 | struct qcm_process_device *qpd) |
| 1561 | { |
| 1562 | struct queue *q, *next; |
| 1563 | struct device_process_node *cur, *next_dpn; |
| 1564 | int retval = 0; |
| 1565 | bool found = false; |
| 1566 | |
| 1567 | dqm_lock(dqm); |
| 1568 | |
| 1569 | /* Clear all user mode queues */ |
| 1570 | list_for_each_entry_safe(q, next, &qpd->queues_list, list) { |
| 1571 | int ret; |
| 1572 | |
| 1573 | ret = destroy_queue_nocpsch_locked(dqm, qpd, q); |
| 1574 | if (ret) |
| 1575 | retval = ret; |
| 1576 | } |
| 1577 | |
| 1578 | /* Unregister process */ |
| 1579 | list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { |
| 1580 | if (qpd == cur->qpd) { |
| 1581 | list_del(&cur->list); |
| 1582 | kfree(cur); |
| 1583 | dqm->processes_count--; |
| 1584 | found = true; |
| 1585 | break; |
| 1586 | } |
| 1587 | } |
| 1588 | |
| 1589 | dqm_unlock(dqm); |
| 1590 | |
| 1591 | /* Outside the DQM lock because under the DQM lock we can't do |
| 1592 | * reclaim or take other locks that others hold while reclaiming. |
| 1593 | */ |
| 1594 | if (found) |
| 1595 | kfd_dec_compute_active(dqm->dev); |
| 1596 | |
| 1597 | return retval; |
| 1598 | } |
| 1599 | |
| 1600 | static int get_wave_state(struct device_queue_manager *dqm, |
| 1601 | struct queue *q, |
| 1602 | void __user *ctl_stack, |
| 1603 | u32 *ctl_stack_used_size, |
| 1604 | u32 *save_area_used_size) |
| 1605 | { |
| 1606 | struct mqd_manager *mqd_mgr; |
| 1607 | int r; |
| 1608 | |
| 1609 | dqm_lock(dqm); |
| 1610 | |
| 1611 | if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE || |
| 1612 | q->properties.is_active || !q->device->cwsr_enabled) { |
| 1613 | r = -EINVAL; |
| 1614 | goto dqm_unlock; |
| 1615 | } |
| 1616 | |
| 1617 | mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; |
| 1618 | |
| 1619 | if (!mqd_mgr->get_wave_state) { |
| 1620 | r = -EINVAL; |
| 1621 | goto dqm_unlock; |
| 1622 | } |
| 1623 | |
| 1624 | r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack, |
| 1625 | ctl_stack_used_size, save_area_used_size); |
| 1626 | |
| 1627 | dqm_unlock: |
| 1628 | dqm_unlock(dqm); |
| 1629 | return r; |
| 1630 | } |
| 1631 | |
| 1632 | static int process_termination_cpsch(struct device_queue_manager *dqm, |
| 1633 | struct qcm_process_device *qpd) |
| 1634 | { |
| 1635 | int retval; |
| 1636 | struct queue *q, *next; |
| 1637 | struct kernel_queue *kq, *kq_next; |
| 1638 | struct mqd_manager *mqd_mgr; |
| 1639 | struct device_process_node *cur, *next_dpn; |
| 1640 | enum kfd_unmap_queues_filter filter = |
| 1641 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; |
| 1642 | bool found = false; |
| 1643 | |
| 1644 | retval = 0; |
| 1645 | |
| 1646 | dqm_lock(dqm); |
| 1647 | |
| 1648 | /* Clean all kernel queues */ |
| 1649 | list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) { |
| 1650 | list_del(&kq->list); |
| 1651 | dqm->active_queue_count--; |
| 1652 | qpd->is_debug = false; |
| 1653 | dqm->total_queue_count--; |
| 1654 | filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES; |
| 1655 | } |
| 1656 | |
| 1657 | /* Clear all user mode queues */ |
| 1658 | list_for_each_entry(q, &qpd->queues_list, list) { |
| 1659 | if (q->properties.type == KFD_QUEUE_TYPE_SDMA) { |
| 1660 | dqm->sdma_queue_count--; |
| 1661 | deallocate_sdma_queue(dqm, q); |
| 1662 | } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { |
| 1663 | dqm->xgmi_sdma_queue_count--; |
| 1664 | deallocate_sdma_queue(dqm, q); |
| 1665 | } |
| 1666 | |
| 1667 | if (q->properties.is_active) |
| 1668 | dqm->active_queue_count--; |
| 1669 | |
| 1670 | dqm->total_queue_count--; |
| 1671 | } |
| 1672 | |
| 1673 | /* Unregister process */ |
| 1674 | list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) { |
| 1675 | if (qpd == cur->qpd) { |
| 1676 | list_del(&cur->list); |
| 1677 | kfree(cur); |
| 1678 | dqm->processes_count--; |
| 1679 | found = true; |
| 1680 | break; |
| 1681 | } |
| 1682 | } |
| 1683 | |
| 1684 | retval = execute_queues_cpsch(dqm, filter, 0); |
| 1685 | if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) { |
| 1686 | pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev); |
| 1687 | dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process); |
| 1688 | qpd->reset_wavefronts = false; |
| 1689 | } |
| 1690 | |
| 1691 | dqm_unlock(dqm); |
| 1692 | |
| 1693 | /* Outside the DQM lock because under the DQM lock we can't do |
| 1694 | * reclaim or take other locks that others hold while reclaiming. |
| 1695 | */ |
| 1696 | if (found) |
| 1697 | kfd_dec_compute_active(dqm->dev); |
| 1698 | |
| 1699 | /* Lastly, free mqd resources. |
| 1700 | * Do free_mqd() after dqm_unlock to avoid circular locking. |
| 1701 | */ |
| 1702 | list_for_each_entry_safe(q, next, &qpd->queues_list, list) { |
| 1703 | mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( |
| 1704 | q->properties.type)]; |
| 1705 | list_del(&q->list); |
| 1706 | qpd->queue_count--; |
| 1707 | mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj); |
| 1708 | } |
| 1709 | |
| 1710 | return retval; |
| 1711 | } |
| 1712 | |
| 1713 | static int init_mqd_managers(struct device_queue_manager *dqm) |
| 1714 | { |
| 1715 | int i, j; |
| 1716 | struct mqd_manager *mqd_mgr; |
| 1717 | |
| 1718 | for (i = 0; i < KFD_MQD_TYPE_MAX; i++) { |
| 1719 | mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev); |
| 1720 | if (!mqd_mgr) { |
| 1721 | pr_err("mqd manager [%d] initialization failed\n", i); |
| 1722 | goto out_free; |
| 1723 | } |
| 1724 | dqm->mqd_mgrs[i] = mqd_mgr; |
| 1725 | } |
| 1726 | |
| 1727 | return 0; |
| 1728 | |
| 1729 | out_free: |
| 1730 | for (j = 0; j < i; j++) { |
| 1731 | kfree(dqm->mqd_mgrs[j]); |
| 1732 | dqm->mqd_mgrs[j] = NULL; |
| 1733 | } |
| 1734 | |
| 1735 | return -ENOMEM; |
| 1736 | } |
| 1737 | |
| 1738 | /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/ |
| 1739 | static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) |
| 1740 | { |
| 1741 | int retval; |
| 1742 | struct kfd_dev *dev = dqm->dev; |
| 1743 | struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd; |
| 1744 | uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * |
| 1745 | (dev->device_info->num_sdma_engines + |
| 1746 | dev->device_info->num_xgmi_sdma_engines) * |
| 1747 | dev->device_info->num_sdma_queues_per_engine + |
| 1748 | dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; |
| 1749 | |
| 1750 | retval = amdgpu_amdkfd_alloc_gtt_mem(dev->kgd, size, |
| 1751 | &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), |
| 1752 | (void *)&(mem_obj->cpu_ptr), true); |
| 1753 | |
| 1754 | return retval; |
| 1755 | } |
| 1756 | |
| 1757 | struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) |
| 1758 | { |
| 1759 | struct device_queue_manager *dqm; |
| 1760 | |
| 1761 | pr_debug("Loading device queue manager\n"); |
| 1762 | |
| 1763 | dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); |
| 1764 | if (!dqm) |
| 1765 | return NULL; |
| 1766 | |
| 1767 | switch (dev->device_info->asic_family) { |
| 1768 | /* HWS is not available on Hawaii. */ |
| 1769 | case CHIP_HAWAII: |
| 1770 | /* HWS depends on CWSR for timely dequeue. CWSR is not |
| 1771 | * available on Tonga. |
| 1772 | * |
| 1773 | * FIXME: This argument also applies to Kaveri. |
| 1774 | */ |
| 1775 | case CHIP_TONGA: |
| 1776 | dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS; |
| 1777 | break; |
| 1778 | default: |
| 1779 | dqm->sched_policy = sched_policy; |
| 1780 | break; |
| 1781 | } |
| 1782 | |
| 1783 | dqm->dev = dev; |
| 1784 | switch (dqm->sched_policy) { |
| 1785 | case KFD_SCHED_POLICY_HWS: |
| 1786 | case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: |
| 1787 | /* initialize dqm for cp scheduling */ |
| 1788 | dqm->ops.create_queue = create_queue_cpsch; |
| 1789 | dqm->ops.initialize = initialize_cpsch; |
| 1790 | dqm->ops.start = start_cpsch; |
| 1791 | dqm->ops.stop = stop_cpsch; |
| 1792 | dqm->ops.pre_reset = pre_reset; |
| 1793 | dqm->ops.destroy_queue = destroy_queue_cpsch; |
| 1794 | dqm->ops.update_queue = update_queue; |
| 1795 | dqm->ops.register_process = register_process; |
| 1796 | dqm->ops.unregister_process = unregister_process; |
| 1797 | dqm->ops.uninitialize = uninitialize; |
| 1798 | dqm->ops.create_kernel_queue = create_kernel_queue_cpsch; |
| 1799 | dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch; |
| 1800 | dqm->ops.set_cache_memory_policy = set_cache_memory_policy; |
| 1801 | dqm->ops.set_trap_handler = set_trap_handler; |
| 1802 | dqm->ops.process_termination = process_termination_cpsch; |
| 1803 | dqm->ops.evict_process_queues = evict_process_queues_cpsch; |
| 1804 | dqm->ops.restore_process_queues = restore_process_queues_cpsch; |
| 1805 | dqm->ops.get_wave_state = get_wave_state; |
| 1806 | break; |
| 1807 | case KFD_SCHED_POLICY_NO_HWS: |
| 1808 | /* initialize dqm for no cp scheduling */ |
| 1809 | dqm->ops.start = start_nocpsch; |
| 1810 | dqm->ops.stop = stop_nocpsch; |
| 1811 | dqm->ops.pre_reset = pre_reset; |
| 1812 | dqm->ops.create_queue = create_queue_nocpsch; |
| 1813 | dqm->ops.destroy_queue = destroy_queue_nocpsch; |
| 1814 | dqm->ops.update_queue = update_queue; |
| 1815 | dqm->ops.register_process = register_process; |
| 1816 | dqm->ops.unregister_process = unregister_process; |
| 1817 | dqm->ops.initialize = initialize_nocpsch; |
| 1818 | dqm->ops.uninitialize = uninitialize; |
| 1819 | dqm->ops.set_cache_memory_policy = set_cache_memory_policy; |
| 1820 | dqm->ops.set_trap_handler = set_trap_handler; |
| 1821 | dqm->ops.process_termination = process_termination_nocpsch; |
| 1822 | dqm->ops.evict_process_queues = evict_process_queues_nocpsch; |
| 1823 | dqm->ops.restore_process_queues = |
| 1824 | restore_process_queues_nocpsch; |
| 1825 | dqm->ops.get_wave_state = get_wave_state; |
| 1826 | break; |
| 1827 | default: |
| 1828 | pr_err("Invalid scheduling policy %d\n", dqm->sched_policy); |
| 1829 | goto out_free; |
| 1830 | } |
| 1831 | |
| 1832 | switch (dev->device_info->asic_family) { |
| 1833 | case CHIP_CARRIZO: |
| 1834 | device_queue_manager_init_vi(&dqm->asic_ops); |
| 1835 | break; |
| 1836 | |
| 1837 | case CHIP_KAVERI: |
| 1838 | device_queue_manager_init_cik(&dqm->asic_ops); |
| 1839 | break; |
| 1840 | |
| 1841 | case CHIP_HAWAII: |
| 1842 | device_queue_manager_init_cik_hawaii(&dqm->asic_ops); |
| 1843 | break; |
| 1844 | |
| 1845 | case CHIP_TONGA: |
| 1846 | case CHIP_FIJI: |
| 1847 | case CHIP_POLARIS10: |
| 1848 | case CHIP_POLARIS11: |
| 1849 | case CHIP_POLARIS12: |
| 1850 | case CHIP_VEGAM: |
| 1851 | device_queue_manager_init_vi_tonga(&dqm->asic_ops); |
| 1852 | break; |
| 1853 | |
| 1854 | case CHIP_VEGA10: |
| 1855 | case CHIP_VEGA12: |
| 1856 | case CHIP_VEGA20: |
| 1857 | case CHIP_RAVEN: |
| 1858 | case CHIP_RENOIR: |
| 1859 | case CHIP_ARCTURUS: |
| 1860 | device_queue_manager_init_v9(&dqm->asic_ops); |
| 1861 | break; |
| 1862 | case CHIP_NAVI10: |
| 1863 | case CHIP_NAVI12: |
| 1864 | case CHIP_NAVI14: |
| 1865 | device_queue_manager_init_v10_navi10(&dqm->asic_ops); |
| 1866 | break; |
| 1867 | default: |
| 1868 | WARN(1, "Unexpected ASIC family %u", |
| 1869 | dev->device_info->asic_family); |
| 1870 | goto out_free; |
| 1871 | } |
| 1872 | |
| 1873 | if (init_mqd_managers(dqm)) |
| 1874 | goto out_free; |
| 1875 | |
| 1876 | if (allocate_hiq_sdma_mqd(dqm)) { |
| 1877 | pr_err("Failed to allocate hiq sdma mqd trunk buffer\n"); |
| 1878 | goto out_free; |
| 1879 | } |
| 1880 | |
| 1881 | if (!dqm->ops.initialize(dqm)) |
| 1882 | return dqm; |
| 1883 | |
| 1884 | out_free: |
| 1885 | kfree(dqm); |
| 1886 | return NULL; |
| 1887 | } |
| 1888 | |
| 1889 | static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, |
| 1890 | struct kfd_mem_obj *mqd) |
| 1891 | { |
| 1892 | WARN(!mqd, "No hiq sdma mqd trunk to free"); |
| 1893 | |
| 1894 | amdgpu_amdkfd_free_gtt_mem(dev->kgd, mqd->gtt_mem); |
| 1895 | } |
| 1896 | |
| 1897 | void device_queue_manager_uninit(struct device_queue_manager *dqm) |
| 1898 | { |
| 1899 | dqm->ops.uninitialize(dqm); |
| 1900 | deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd); |
| 1901 | kfree(dqm); |
| 1902 | } |
| 1903 | |
| 1904 | int kfd_process_vm_fault(struct device_queue_manager *dqm, |
| 1905 | unsigned int pasid) |
| 1906 | { |
| 1907 | struct kfd_process_device *pdd; |
| 1908 | struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); |
| 1909 | int ret = 0; |
| 1910 | |
| 1911 | if (!p) |
| 1912 | return -EINVAL; |
| 1913 | pdd = kfd_get_process_device_data(dqm->dev, p); |
| 1914 | if (pdd) |
| 1915 | ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); |
| 1916 | kfd_unref_process(p); |
| 1917 | |
| 1918 | return ret; |
| 1919 | } |
| 1920 | |
| 1921 | static void kfd_process_hw_exception(struct work_struct *work) |
| 1922 | { |
| 1923 | struct device_queue_manager *dqm = container_of(work, |
| 1924 | struct device_queue_manager, hw_exception_work); |
| 1925 | amdgpu_amdkfd_gpu_reset(dqm->dev->kgd); |
| 1926 | } |
| 1927 | |
| 1928 | #if defined(CONFIG_DEBUG_FS) |
| 1929 | |
| 1930 | static void seq_reg_dump(struct seq_file *m, |
| 1931 | uint32_t (*dump)[2], uint32_t n_regs) |
| 1932 | { |
| 1933 | uint32_t i, count; |
| 1934 | |
| 1935 | for (i = 0, count = 0; i < n_regs; i++) { |
| 1936 | if (count == 0 || |
| 1937 | dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) { |
| 1938 | seq_printf(m, "%s %08x: %08x", |
| 1939 | i ? "\n" : "", |
| 1940 | dump[i][0], dump[i][1]); |
| 1941 | count = 7; |
| 1942 | } else { |
| 1943 | seq_printf(m, " %08x", dump[i][1]); |
| 1944 | count--; |
| 1945 | } |
| 1946 | } |
| 1947 | |
| 1948 | seq_puts(m, "\n"); |
| 1949 | } |
| 1950 | |
| 1951 | int dqm_debugfs_hqds(struct seq_file *m, void *data) |
| 1952 | { |
| 1953 | struct device_queue_manager *dqm = data; |
| 1954 | uint32_t (*dump)[2], n_regs; |
| 1955 | int pipe, queue; |
| 1956 | int r = 0; |
| 1957 | |
| 1958 | if (!dqm->sched_running) { |
| 1959 | seq_printf(m, " Device is stopped\n"); |
| 1960 | |
| 1961 | return 0; |
| 1962 | } |
| 1963 | |
| 1964 | r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd, |
| 1965 | KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, |
| 1966 | &dump, &n_regs); |
| 1967 | if (!r) { |
| 1968 | seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n", |
| 1969 | KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1, |
| 1970 | KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm), |
| 1971 | KFD_CIK_HIQ_QUEUE); |
| 1972 | seq_reg_dump(m, dump, n_regs); |
| 1973 | |
| 1974 | kfree(dump); |
| 1975 | } |
| 1976 | |
| 1977 | for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { |
| 1978 | int pipe_offset = pipe * get_queues_per_pipe(dqm); |
| 1979 | |
| 1980 | for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) { |
| 1981 | if (!test_bit(pipe_offset + queue, |
| 1982 | dqm->dev->shared_resources.cp_queue_bitmap)) |
| 1983 | continue; |
| 1984 | |
| 1985 | r = dqm->dev->kfd2kgd->hqd_dump( |
| 1986 | dqm->dev->kgd, pipe, queue, &dump, &n_regs); |
| 1987 | if (r) |
| 1988 | break; |
| 1989 | |
| 1990 | seq_printf(m, " CP Pipe %d, Queue %d\n", |
| 1991 | pipe, queue); |
| 1992 | seq_reg_dump(m, dump, n_regs); |
| 1993 | |
| 1994 | kfree(dump); |
| 1995 | } |
| 1996 | } |
| 1997 | |
| 1998 | for (pipe = 0; pipe < get_num_sdma_engines(dqm) + |
| 1999 | get_num_xgmi_sdma_engines(dqm); pipe++) { |
| 2000 | for (queue = 0; |
| 2001 | queue < dqm->dev->device_info->num_sdma_queues_per_engine; |
| 2002 | queue++) { |
| 2003 | r = dqm->dev->kfd2kgd->hqd_sdma_dump( |
| 2004 | dqm->dev->kgd, pipe, queue, &dump, &n_regs); |
| 2005 | if (r) |
| 2006 | break; |
| 2007 | |
| 2008 | seq_printf(m, " SDMA Engine %d, RLC %d\n", |
| 2009 | pipe, queue); |
| 2010 | seq_reg_dump(m, dump, n_regs); |
| 2011 | |
| 2012 | kfree(dump); |
| 2013 | } |
| 2014 | } |
| 2015 | |
| 2016 | return r; |
| 2017 | } |
| 2018 | |
| 2019 | int dqm_debugfs_execute_queues(struct device_queue_manager *dqm) |
| 2020 | { |
| 2021 | int r = 0; |
| 2022 | |
| 2023 | dqm_lock(dqm); |
| 2024 | dqm->active_runlist = true; |
| 2025 | r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); |
| 2026 | dqm_unlock(dqm); |
| 2027 | |
| 2028 | return r; |
| 2029 | } |
| 2030 | |
| 2031 | #endif |