| 1 | /* |
| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/firmware.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/pci.h> |
| 27 | |
| 28 | #include "amdgpu.h" |
| 29 | #include "amdgpu_atombios.h" |
| 30 | #include "amdgpu_ih.h" |
| 31 | #include "amdgpu_uvd.h" |
| 32 | #include "amdgpu_vce.h" |
| 33 | #include "amdgpu_ucode.h" |
| 34 | #include "amdgpu_psp.h" |
| 35 | #include "atom.h" |
| 36 | #include "amd_pcie.h" |
| 37 | |
| 38 | #include "uvd/uvd_7_0_offset.h" |
| 39 | #include "gc/gc_9_0_offset.h" |
| 40 | #include "gc/gc_9_0_sh_mask.h" |
| 41 | #include "sdma0/sdma0_4_0_offset.h" |
| 42 | #include "sdma1/sdma1_4_0_offset.h" |
| 43 | #include "hdp/hdp_4_0_offset.h" |
| 44 | #include "hdp/hdp_4_0_sh_mask.h" |
| 45 | #include "smuio/smuio_9_0_offset.h" |
| 46 | #include "smuio/smuio_9_0_sh_mask.h" |
| 47 | #include "nbio/nbio_7_0_default.h" |
| 48 | #include "nbio/nbio_7_0_offset.h" |
| 49 | #include "nbio/nbio_7_0_sh_mask.h" |
| 50 | #include "nbio/nbio_7_0_smn.h" |
| 51 | #include "mp/mp_9_0_offset.h" |
| 52 | |
| 53 | #include "soc15.h" |
| 54 | #include "soc15_common.h" |
| 55 | #include "gfx_v9_0.h" |
| 56 | #include "gmc_v9_0.h" |
| 57 | #include "gfxhub_v1_0.h" |
| 58 | #include "mmhub_v1_0.h" |
| 59 | #include "df_v1_7.h" |
| 60 | #include "df_v3_6.h" |
| 61 | #include "vega10_ih.h" |
| 62 | #include "sdma_v4_0.h" |
| 63 | #include "uvd_v7_0.h" |
| 64 | #include "vce_v4_0.h" |
| 65 | #include "vcn_v1_0.h" |
| 66 | #include "vcn_v2_0.h" |
| 67 | #include "vcn_v2_5.h" |
| 68 | #include "dce_virtual.h" |
| 69 | #include "mxgpu_ai.h" |
| 70 | #include "amdgpu_smu.h" |
| 71 | #include "amdgpu_ras.h" |
| 72 | #include "amdgpu_xgmi.h" |
| 73 | #include <uapi/linux/kfd_ioctl.h> |
| 74 | |
| 75 | #define mmMP0_MISC_CGTT_CTRL0 0x01b9 |
| 76 | #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 |
| 77 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba |
| 78 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 |
| 79 | |
| 80 | /* for Vega20 register name change */ |
| 81 | #define mmHDP_MEM_POWER_CTRL 0x00d4 |
| 82 | #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L |
| 83 | #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L |
| 84 | #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L |
| 85 | #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L |
| 86 | #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 |
| 87 | /* |
| 88 | * Indirect registers accessor |
| 89 | */ |
| 90 | static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) |
| 91 | { |
| 92 | unsigned long flags, address, data; |
| 93 | u32 r; |
| 94 | address = adev->nbio_funcs->get_pcie_index_offset(adev); |
| 95 | data = adev->nbio_funcs->get_pcie_data_offset(adev); |
| 96 | |
| 97 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
| 98 | WREG32(address, reg); |
| 99 | (void)RREG32(address); |
| 100 | r = RREG32(data); |
| 101 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); |
| 102 | return r; |
| 103 | } |
| 104 | |
| 105 | static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 106 | { |
| 107 | unsigned long flags, address, data; |
| 108 | |
| 109 | address = adev->nbio_funcs->get_pcie_index_offset(adev); |
| 110 | data = adev->nbio_funcs->get_pcie_data_offset(adev); |
| 111 | |
| 112 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
| 113 | WREG32(address, reg); |
| 114 | (void)RREG32(address); |
| 115 | WREG32(data, v); |
| 116 | (void)RREG32(data); |
| 117 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); |
| 118 | } |
| 119 | |
| 120 | static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) |
| 121 | { |
| 122 | unsigned long flags, address, data; |
| 123 | u64 r; |
| 124 | address = adev->nbio_funcs->get_pcie_index_offset(adev); |
| 125 | data = adev->nbio_funcs->get_pcie_data_offset(adev); |
| 126 | |
| 127 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
| 128 | /* read low 32 bit */ |
| 129 | WREG32(address, reg); |
| 130 | (void)RREG32(address); |
| 131 | r = RREG32(data); |
| 132 | |
| 133 | /* read high 32 bit*/ |
| 134 | WREG32(address, reg + 4); |
| 135 | (void)RREG32(address); |
| 136 | r |= ((u64)RREG32(data) << 32); |
| 137 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); |
| 138 | return r; |
| 139 | } |
| 140 | |
| 141 | static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) |
| 142 | { |
| 143 | unsigned long flags, address, data; |
| 144 | |
| 145 | address = adev->nbio_funcs->get_pcie_index_offset(adev); |
| 146 | data = adev->nbio_funcs->get_pcie_data_offset(adev); |
| 147 | |
| 148 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); |
| 149 | /* write low 32 bit */ |
| 150 | WREG32(address, reg); |
| 151 | (void)RREG32(address); |
| 152 | WREG32(data, (u32)(v & 0xffffffffULL)); |
| 153 | (void)RREG32(data); |
| 154 | |
| 155 | /* write high 32 bit */ |
| 156 | WREG32(address, reg + 4); |
| 157 | (void)RREG32(address); |
| 158 | WREG32(data, (u32)(v >> 32)); |
| 159 | (void)RREG32(data); |
| 160 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); |
| 161 | } |
| 162 | |
| 163 | static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) |
| 164 | { |
| 165 | unsigned long flags, address, data; |
| 166 | u32 r; |
| 167 | |
| 168 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); |
| 169 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); |
| 170 | |
| 171 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); |
| 172 | WREG32(address, ((reg) & 0x1ff)); |
| 173 | r = RREG32(data); |
| 174 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); |
| 175 | return r; |
| 176 | } |
| 177 | |
| 178 | static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 179 | { |
| 180 | unsigned long flags, address, data; |
| 181 | |
| 182 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); |
| 183 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); |
| 184 | |
| 185 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); |
| 186 | WREG32(address, ((reg) & 0x1ff)); |
| 187 | WREG32(data, (v)); |
| 188 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); |
| 189 | } |
| 190 | |
| 191 | static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) |
| 192 | { |
| 193 | unsigned long flags, address, data; |
| 194 | u32 r; |
| 195 | |
| 196 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); |
| 197 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); |
| 198 | |
| 199 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
| 200 | WREG32(address, (reg)); |
| 201 | r = RREG32(data); |
| 202 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); |
| 203 | return r; |
| 204 | } |
| 205 | |
| 206 | static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 207 | { |
| 208 | unsigned long flags, address, data; |
| 209 | |
| 210 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); |
| 211 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); |
| 212 | |
| 213 | spin_lock_irqsave(&adev->didt_idx_lock, flags); |
| 214 | WREG32(address, (reg)); |
| 215 | WREG32(data, (v)); |
| 216 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); |
| 217 | } |
| 218 | |
| 219 | static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) |
| 220 | { |
| 221 | unsigned long flags; |
| 222 | u32 r; |
| 223 | |
| 224 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); |
| 225 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); |
| 226 | r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); |
| 227 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); |
| 228 | return r; |
| 229 | } |
| 230 | |
| 231 | static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 232 | { |
| 233 | unsigned long flags; |
| 234 | |
| 235 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); |
| 236 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); |
| 237 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); |
| 238 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); |
| 239 | } |
| 240 | |
| 241 | static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) |
| 242 | { |
| 243 | unsigned long flags; |
| 244 | u32 r; |
| 245 | |
| 246 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); |
| 247 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); |
| 248 | r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); |
| 249 | spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); |
| 250 | return r; |
| 251 | } |
| 252 | |
| 253 | static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
| 254 | { |
| 255 | unsigned long flags; |
| 256 | |
| 257 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); |
| 258 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); |
| 259 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); |
| 260 | spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); |
| 261 | } |
| 262 | |
| 263 | static u32 soc15_get_config_memsize(struct amdgpu_device *adev) |
| 264 | { |
| 265 | return adev->nbio_funcs->get_memsize(adev); |
| 266 | } |
| 267 | |
| 268 | static u32 soc15_get_xclk(struct amdgpu_device *adev) |
| 269 | { |
| 270 | return adev->clock.spll.reference_freq; |
| 271 | } |
| 272 | |
| 273 | |
| 274 | void soc15_grbm_select(struct amdgpu_device *adev, |
| 275 | u32 me, u32 pipe, u32 queue, u32 vmid) |
| 276 | { |
| 277 | u32 grbm_gfx_cntl = 0; |
| 278 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); |
| 279 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); |
| 280 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); |
| 281 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); |
| 282 | |
| 283 | WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); |
| 284 | } |
| 285 | |
| 286 | static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) |
| 287 | { |
| 288 | /* todo */ |
| 289 | } |
| 290 | |
| 291 | static bool soc15_read_disabled_bios(struct amdgpu_device *adev) |
| 292 | { |
| 293 | /* todo */ |
| 294 | return false; |
| 295 | } |
| 296 | |
| 297 | static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, |
| 298 | u8 *bios, u32 length_bytes) |
| 299 | { |
| 300 | u32 *dw_ptr; |
| 301 | u32 i, length_dw; |
| 302 | |
| 303 | if (bios == NULL) |
| 304 | return false; |
| 305 | if (length_bytes == 0) |
| 306 | return false; |
| 307 | /* APU vbios image is part of sbios image */ |
| 308 | if (adev->flags & AMD_IS_APU) |
| 309 | return false; |
| 310 | |
| 311 | dw_ptr = (u32 *)bios; |
| 312 | length_dw = ALIGN(length_bytes, 4) / 4; |
| 313 | |
| 314 | /* set rom index to 0 */ |
| 315 | WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); |
| 316 | /* read out the rom data */ |
| 317 | for (i = 0; i < length_dw; i++) |
| 318 | dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); |
| 319 | |
| 320 | return true; |
| 321 | } |
| 322 | |
| 323 | static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { |
| 324 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, |
| 325 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, |
| 326 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, |
| 327 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, |
| 328 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, |
| 329 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, |
| 330 | { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, |
| 331 | { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, |
| 332 | { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, |
| 333 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, |
| 334 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, |
| 335 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, |
| 336 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, |
| 337 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, |
| 338 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, |
| 339 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, |
| 340 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, |
| 341 | { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, |
| 342 | { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, |
| 343 | }; |
| 344 | |
| 345 | static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, |
| 346 | u32 sh_num, u32 reg_offset) |
| 347 | { |
| 348 | uint32_t val; |
| 349 | |
| 350 | mutex_lock(&adev->grbm_idx_mutex); |
| 351 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
| 352 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); |
| 353 | |
| 354 | val = RREG32(reg_offset); |
| 355 | |
| 356 | if (se_num != 0xffffffff || sh_num != 0xffffffff) |
| 357 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| 358 | mutex_unlock(&adev->grbm_idx_mutex); |
| 359 | return val; |
| 360 | } |
| 361 | |
| 362 | static uint32_t soc15_get_register_value(struct amdgpu_device *adev, |
| 363 | bool indexed, u32 se_num, |
| 364 | u32 sh_num, u32 reg_offset) |
| 365 | { |
| 366 | if (indexed) { |
| 367 | return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); |
| 368 | } else { |
| 369 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) |
| 370 | return adev->gfx.config.gb_addr_config; |
| 371 | else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) |
| 372 | return adev->gfx.config.db_debug2; |
| 373 | return RREG32(reg_offset); |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, |
| 378 | u32 sh_num, u32 reg_offset, u32 *value) |
| 379 | { |
| 380 | uint32_t i; |
| 381 | struct soc15_allowed_register_entry *en; |
| 382 | |
| 383 | *value = 0; |
| 384 | for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { |
| 385 | en = &soc15_allowed_read_registers[i]; |
| 386 | if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] |
| 387 | + en->reg_offset)) |
| 388 | continue; |
| 389 | |
| 390 | *value = soc15_get_register_value(adev, |
| 391 | soc15_allowed_read_registers[i].grbm_indexed, |
| 392 | se_num, sh_num, reg_offset); |
| 393 | return 0; |
| 394 | } |
| 395 | return -EINVAL; |
| 396 | } |
| 397 | |
| 398 | |
| 399 | /** |
| 400 | * soc15_program_register_sequence - program an array of registers. |
| 401 | * |
| 402 | * @adev: amdgpu_device pointer |
| 403 | * @regs: pointer to the register array |
| 404 | * @array_size: size of the register array |
| 405 | * |
| 406 | * Programs an array or registers with and and or masks. |
| 407 | * This is a helper for setting golden registers. |
| 408 | */ |
| 409 | |
| 410 | void soc15_program_register_sequence(struct amdgpu_device *adev, |
| 411 | const struct soc15_reg_golden *regs, |
| 412 | const u32 array_size) |
| 413 | { |
| 414 | const struct soc15_reg_golden *entry; |
| 415 | u32 tmp, reg; |
| 416 | int i; |
| 417 | |
| 418 | for (i = 0; i < array_size; ++i) { |
| 419 | entry = ®s[i]; |
| 420 | reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; |
| 421 | |
| 422 | if (entry->and_mask == 0xffffffff) { |
| 423 | tmp = entry->or_mask; |
| 424 | } else { |
| 425 | tmp = RREG32(reg); |
| 426 | tmp &= ~(entry->and_mask); |
| 427 | tmp |= (entry->or_mask & entry->and_mask); |
| 428 | } |
| 429 | |
| 430 | if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || |
| 431 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || |
| 432 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || |
| 433 | reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) |
| 434 | WREG32_RLC(reg, tmp); |
| 435 | else |
| 436 | WREG32(reg, tmp); |
| 437 | |
| 438 | } |
| 439 | |
| 440 | } |
| 441 | |
| 442 | static int soc15_asic_mode1_reset(struct amdgpu_device *adev) |
| 443 | { |
| 444 | u32 i; |
| 445 | int ret = 0; |
| 446 | |
| 447 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); |
| 448 | |
| 449 | dev_info(adev->dev, "GPU mode1 reset\n"); |
| 450 | |
| 451 | /* disable BM */ |
| 452 | pci_clear_master(adev->pdev); |
| 453 | |
| 454 | pci_save_state(adev->pdev); |
| 455 | |
| 456 | ret = psp_gpu_reset(adev); |
| 457 | if (ret) |
| 458 | dev_err(adev->dev, "GPU mode1 reset failed\n"); |
| 459 | |
| 460 | pci_restore_state(adev->pdev); |
| 461 | |
| 462 | /* wait for asic to come out of reset */ |
| 463 | for (i = 0; i < adev->usec_timeout; i++) { |
| 464 | u32 memsize = adev->nbio_funcs->get_memsize(adev); |
| 465 | |
| 466 | if (memsize != 0xffffffff) |
| 467 | break; |
| 468 | udelay(1); |
| 469 | } |
| 470 | |
| 471 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); |
| 472 | |
| 473 | return ret; |
| 474 | } |
| 475 | |
| 476 | static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) |
| 477 | { |
| 478 | void *pp_handle = adev->powerplay.pp_handle; |
| 479 | const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; |
| 480 | |
| 481 | if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { |
| 482 | *cap = false; |
| 483 | return -ENOENT; |
| 484 | } |
| 485 | |
| 486 | return pp_funcs->get_asic_baco_capability(pp_handle, cap); |
| 487 | } |
| 488 | |
| 489 | static int soc15_asic_baco_reset(struct amdgpu_device *adev) |
| 490 | { |
| 491 | void *pp_handle = adev->powerplay.pp_handle; |
| 492 | const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; |
| 493 | |
| 494 | if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) |
| 495 | return -ENOENT; |
| 496 | |
| 497 | /* enter BACO state */ |
| 498 | if (pp_funcs->set_asic_baco_state(pp_handle, 1)) |
| 499 | return -EIO; |
| 500 | |
| 501 | /* exit BACO state */ |
| 502 | if (pp_funcs->set_asic_baco_state(pp_handle, 0)) |
| 503 | return -EIO; |
| 504 | |
| 505 | dev_info(adev->dev, "GPU BACO reset\n"); |
| 506 | |
| 507 | adev->in_baco_reset = 1; |
| 508 | |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | static int soc15_mode2_reset(struct amdgpu_device *adev) |
| 513 | { |
| 514 | if (!adev->powerplay.pp_funcs || |
| 515 | !adev->powerplay.pp_funcs->asic_reset_mode_2) |
| 516 | return -ENOENT; |
| 517 | |
| 518 | return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle); |
| 519 | } |
| 520 | |
| 521 | static enum amd_reset_method |
| 522 | soc15_asic_reset_method(struct amdgpu_device *adev) |
| 523 | { |
| 524 | bool baco_reset; |
| 525 | |
| 526 | switch (adev->asic_type) { |
| 527 | case CHIP_RAVEN: |
| 528 | return AMD_RESET_METHOD_MODE2; |
| 529 | case CHIP_VEGA10: |
| 530 | case CHIP_VEGA12: |
| 531 | soc15_asic_get_baco_capability(adev, &baco_reset); |
| 532 | break; |
| 533 | case CHIP_VEGA20: |
| 534 | if (adev->psp.sos_fw_version >= 0x80067) |
| 535 | soc15_asic_get_baco_capability(adev, &baco_reset); |
| 536 | else |
| 537 | baco_reset = false; |
| 538 | if (baco_reset) { |
| 539 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0); |
| 540 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
| 541 | |
| 542 | if (hive || (ras && ras->supported)) |
| 543 | baco_reset = false; |
| 544 | } |
| 545 | break; |
| 546 | default: |
| 547 | baco_reset = false; |
| 548 | break; |
| 549 | } |
| 550 | |
| 551 | if (baco_reset) |
| 552 | return AMD_RESET_METHOD_BACO; |
| 553 | else |
| 554 | return AMD_RESET_METHOD_MODE1; |
| 555 | } |
| 556 | |
| 557 | static int soc15_asic_reset(struct amdgpu_device *adev) |
| 558 | { |
| 559 | switch (soc15_asic_reset_method(adev)) { |
| 560 | case AMD_RESET_METHOD_BACO: |
| 561 | if (!adev->in_suspend) |
| 562 | amdgpu_inc_vram_lost(adev); |
| 563 | return soc15_asic_baco_reset(adev); |
| 564 | case AMD_RESET_METHOD_MODE2: |
| 565 | return soc15_mode2_reset(adev); |
| 566 | default: |
| 567 | if (!adev->in_suspend) |
| 568 | amdgpu_inc_vram_lost(adev); |
| 569 | return soc15_asic_mode1_reset(adev); |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, |
| 574 | u32 cntl_reg, u32 status_reg) |
| 575 | { |
| 576 | return 0; |
| 577 | }*/ |
| 578 | |
| 579 | static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) |
| 580 | { |
| 581 | /*int r; |
| 582 | |
| 583 | r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); |
| 584 | if (r) |
| 585 | return r; |
| 586 | |
| 587 | r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); |
| 588 | */ |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) |
| 593 | { |
| 594 | /* todo */ |
| 595 | |
| 596 | return 0; |
| 597 | } |
| 598 | |
| 599 | static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) |
| 600 | { |
| 601 | if (pci_is_root_bus(adev->pdev->bus)) |
| 602 | return; |
| 603 | |
| 604 | if (amdgpu_pcie_gen2 == 0) |
| 605 | return; |
| 606 | |
| 607 | if (adev->flags & AMD_IS_APU) |
| 608 | return; |
| 609 | |
| 610 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
| 611 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) |
| 612 | return; |
| 613 | |
| 614 | /* todo */ |
| 615 | } |
| 616 | |
| 617 | static void soc15_program_aspm(struct amdgpu_device *adev) |
| 618 | { |
| 619 | |
| 620 | if (amdgpu_aspm == 0) |
| 621 | return; |
| 622 | |
| 623 | /* todo */ |
| 624 | } |
| 625 | |
| 626 | static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, |
| 627 | bool enable) |
| 628 | { |
| 629 | adev->nbio_funcs->enable_doorbell_aperture(adev, enable); |
| 630 | adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); |
| 631 | } |
| 632 | |
| 633 | static const struct amdgpu_ip_block_version vega10_common_ip_block = |
| 634 | { |
| 635 | .type = AMD_IP_BLOCK_TYPE_COMMON, |
| 636 | .major = 2, |
| 637 | .minor = 0, |
| 638 | .rev = 0, |
| 639 | .funcs = &soc15_common_ip_funcs, |
| 640 | }; |
| 641 | |
| 642 | static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) |
| 643 | { |
| 644 | return adev->nbio_funcs->get_rev_id(adev); |
| 645 | } |
| 646 | |
| 647 | int soc15_set_ip_blocks(struct amdgpu_device *adev) |
| 648 | { |
| 649 | /* Set IP register base before any HW register access */ |
| 650 | switch (adev->asic_type) { |
| 651 | case CHIP_VEGA10: |
| 652 | case CHIP_VEGA12: |
| 653 | case CHIP_RAVEN: |
| 654 | case CHIP_RENOIR: |
| 655 | vega10_reg_base_init(adev); |
| 656 | break; |
| 657 | case CHIP_VEGA20: |
| 658 | vega20_reg_base_init(adev); |
| 659 | break; |
| 660 | case CHIP_ARCTURUS: |
| 661 | arct_reg_base_init(adev); |
| 662 | break; |
| 663 | default: |
| 664 | return -EINVAL; |
| 665 | } |
| 666 | |
| 667 | if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) |
| 668 | adev->gmc.xgmi.supported = true; |
| 669 | |
| 670 | if (adev->flags & AMD_IS_APU) |
| 671 | adev->nbio_funcs = &nbio_v7_0_funcs; |
| 672 | else if (adev->asic_type == CHIP_VEGA20 || |
| 673 | adev->asic_type == CHIP_ARCTURUS) |
| 674 | adev->nbio_funcs = &nbio_v7_4_funcs; |
| 675 | else |
| 676 | adev->nbio_funcs = &nbio_v6_1_funcs; |
| 677 | |
| 678 | if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) |
| 679 | adev->df_funcs = &df_v3_6_funcs; |
| 680 | else |
| 681 | adev->df_funcs = &df_v1_7_funcs; |
| 682 | |
| 683 | adev->rev_id = soc15_get_rev_id(adev); |
| 684 | adev->nbio_funcs->detect_hw_virt(adev); |
| 685 | |
| 686 | if (amdgpu_sriov_vf(adev)) |
| 687 | adev->virt.ops = &xgpu_ai_virt_ops; |
| 688 | |
| 689 | switch (adev->asic_type) { |
| 690 | case CHIP_VEGA10: |
| 691 | case CHIP_VEGA12: |
| 692 | case CHIP_VEGA20: |
| 693 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
| 694 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); |
| 695 | |
| 696 | /* For Vega10 SR-IOV, PSP need to be initialized before IH */ |
| 697 | if (amdgpu_sriov_vf(adev)) { |
| 698 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { |
| 699 | if (adev->asic_type == CHIP_VEGA20) |
| 700 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); |
| 701 | else |
| 702 | amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); |
| 703 | } |
| 704 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
| 705 | } else { |
| 706 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
| 707 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { |
| 708 | if (adev->asic_type == CHIP_VEGA20) |
| 709 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); |
| 710 | else |
| 711 | amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); |
| 712 | } |
| 713 | } |
| 714 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
| 715 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); |
| 716 | if (!amdgpu_sriov_vf(adev)) { |
| 717 | if (is_support_sw_smu(adev)) |
| 718 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
| 719 | else |
| 720 | amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); |
| 721 | } |
| 722 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
| 723 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
| 724 | #if defined(CONFIG_DRM_AMD_DC) |
| 725 | else if (amdgpu_device_has_dc_support(adev)) |
| 726 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
| 727 | #endif |
| 728 | if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { |
| 729 | amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); |
| 730 | amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); |
| 731 | } |
| 732 | break; |
| 733 | case CHIP_RAVEN: |
| 734 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
| 735 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); |
| 736 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
| 737 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
| 738 | amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); |
| 739 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
| 740 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); |
| 741 | amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); |
| 742 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
| 743 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
| 744 | #if defined(CONFIG_DRM_AMD_DC) |
| 745 | else if (amdgpu_device_has_dc_support(adev)) |
| 746 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
| 747 | #endif |
| 748 | amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); |
| 749 | break; |
| 750 | case CHIP_ARCTURUS: |
| 751 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
| 752 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); |
| 753 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
| 754 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
| 755 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
| 756 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
| 757 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); |
| 758 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
| 759 | amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); |
| 760 | break; |
| 761 | case CHIP_RENOIR: |
| 762 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
| 763 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); |
| 764 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
| 765 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
| 766 | amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); |
| 767 | if (is_support_sw_smu(adev)) |
| 768 | amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); |
| 769 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
| 770 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); |
| 771 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
| 772 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
| 773 | #if defined(CONFIG_DRM_AMD_DC) |
| 774 | else if (amdgpu_device_has_dc_support(adev)) |
| 775 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
| 776 | #endif |
| 777 | amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); |
| 778 | break; |
| 779 | default: |
| 780 | return -EINVAL; |
| 781 | } |
| 782 | |
| 783 | return 0; |
| 784 | } |
| 785 | |
| 786 | static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) |
| 787 | { |
| 788 | adev->nbio_funcs->hdp_flush(adev, ring); |
| 789 | } |
| 790 | |
| 791 | static void soc15_invalidate_hdp(struct amdgpu_device *adev, |
| 792 | struct amdgpu_ring *ring) |
| 793 | { |
| 794 | if (!ring || !ring->funcs->emit_wreg) |
| 795 | WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); |
| 796 | else |
| 797 | amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( |
| 798 | HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); |
| 799 | } |
| 800 | |
| 801 | static bool soc15_need_full_reset(struct amdgpu_device *adev) |
| 802 | { |
| 803 | /* change this when we implement soft reset */ |
| 804 | return true; |
| 805 | } |
| 806 | static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
| 807 | uint64_t *count1) |
| 808 | { |
| 809 | uint32_t perfctr = 0; |
| 810 | uint64_t cnt0_of, cnt1_of; |
| 811 | int tmp; |
| 812 | |
| 813 | /* This reports 0 on APUs, so return to avoid writing/reading registers |
| 814 | * that may or may not be different from their GPU counterparts |
| 815 | */ |
| 816 | if (adev->flags & AMD_IS_APU) |
| 817 | return; |
| 818 | |
| 819 | /* Set the 2 events that we wish to watch, defined above */ |
| 820 | /* Reg 40 is # received msgs */ |
| 821 | /* Reg 104 is # of posted requests sent */ |
| 822 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); |
| 823 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); |
| 824 | |
| 825 | /* Write to enable desired perf counters */ |
| 826 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); |
| 827 | /* Zero out and enable the perf counters |
| 828 | * Write 0x5: |
| 829 | * Bit 0 = Start all counters(1) |
| 830 | * Bit 2 = Global counter reset enable(1) |
| 831 | */ |
| 832 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); |
| 833 | |
| 834 | msleep(1000); |
| 835 | |
| 836 | /* Load the shadow and disable the perf counters |
| 837 | * Write 0x2: |
| 838 | * Bit 0 = Stop counters(0) |
| 839 | * Bit 1 = Load the shadow counters(1) |
| 840 | */ |
| 841 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); |
| 842 | |
| 843 | /* Read register values to get any >32bit overflow */ |
| 844 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); |
| 845 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); |
| 846 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); |
| 847 | |
| 848 | /* Get the values and add the overflow */ |
| 849 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); |
| 850 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); |
| 851 | } |
| 852 | |
| 853 | static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
| 854 | uint64_t *count1) |
| 855 | { |
| 856 | uint32_t perfctr = 0; |
| 857 | uint64_t cnt0_of, cnt1_of; |
| 858 | int tmp; |
| 859 | |
| 860 | /* This reports 0 on APUs, so return to avoid writing/reading registers |
| 861 | * that may or may not be different from their GPU counterparts |
| 862 | */ |
| 863 | if (adev->flags & AMD_IS_APU) |
| 864 | return; |
| 865 | |
| 866 | /* Set the 2 events that we wish to watch, defined above */ |
| 867 | /* Reg 40 is # received msgs */ |
| 868 | /* Reg 108 is # of posted requests sent on VG20 */ |
| 869 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, |
| 870 | EVENT0_SEL, 40); |
| 871 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, |
| 872 | EVENT1_SEL, 108); |
| 873 | |
| 874 | /* Write to enable desired perf counters */ |
| 875 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); |
| 876 | /* Zero out and enable the perf counters |
| 877 | * Write 0x5: |
| 878 | * Bit 0 = Start all counters(1) |
| 879 | * Bit 2 = Global counter reset enable(1) |
| 880 | */ |
| 881 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); |
| 882 | |
| 883 | msleep(1000); |
| 884 | |
| 885 | /* Load the shadow and disable the perf counters |
| 886 | * Write 0x2: |
| 887 | * Bit 0 = Stop counters(0) |
| 888 | * Bit 1 = Load the shadow counters(1) |
| 889 | */ |
| 890 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); |
| 891 | |
| 892 | /* Read register values to get any >32bit overflow */ |
| 893 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); |
| 894 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); |
| 895 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); |
| 896 | |
| 897 | /* Get the values and add the overflow */ |
| 898 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); |
| 899 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); |
| 900 | } |
| 901 | |
| 902 | static bool soc15_need_reset_on_init(struct amdgpu_device *adev) |
| 903 | { |
| 904 | u32 sol_reg; |
| 905 | |
| 906 | /* Just return false for soc15 GPUs. Reset does not seem to |
| 907 | * be necessary. |
| 908 | */ |
| 909 | if (!amdgpu_passthrough(adev)) |
| 910 | return false; |
| 911 | |
| 912 | if (adev->flags & AMD_IS_APU) |
| 913 | return false; |
| 914 | |
| 915 | /* Check sOS sign of life register to confirm sys driver and sOS |
| 916 | * are already been loaded. |
| 917 | */ |
| 918 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); |
| 919 | if (sol_reg) |
| 920 | return true; |
| 921 | |
| 922 | return false; |
| 923 | } |
| 924 | |
| 925 | static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) |
| 926 | { |
| 927 | uint64_t nak_r, nak_g; |
| 928 | |
| 929 | /* Get the number of NAKs received and generated */ |
| 930 | nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); |
| 931 | nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); |
| 932 | |
| 933 | /* Add the total number of NAKs, i.e the number of replays */ |
| 934 | return (nak_r + nak_g); |
| 935 | } |
| 936 | |
| 937 | static const struct amdgpu_asic_funcs soc15_asic_funcs = |
| 938 | { |
| 939 | .read_disabled_bios = &soc15_read_disabled_bios, |
| 940 | .read_bios_from_rom = &soc15_read_bios_from_rom, |
| 941 | .read_register = &soc15_read_register, |
| 942 | .reset = &soc15_asic_reset, |
| 943 | .reset_method = &soc15_asic_reset_method, |
| 944 | .set_vga_state = &soc15_vga_set_state, |
| 945 | .get_xclk = &soc15_get_xclk, |
| 946 | .set_uvd_clocks = &soc15_set_uvd_clocks, |
| 947 | .set_vce_clocks = &soc15_set_vce_clocks, |
| 948 | .get_config_memsize = &soc15_get_config_memsize, |
| 949 | .flush_hdp = &soc15_flush_hdp, |
| 950 | .invalidate_hdp = &soc15_invalidate_hdp, |
| 951 | .need_full_reset = &soc15_need_full_reset, |
| 952 | .init_doorbell_index = &vega10_doorbell_index_init, |
| 953 | .get_pcie_usage = &soc15_get_pcie_usage, |
| 954 | .need_reset_on_init = &soc15_need_reset_on_init, |
| 955 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
| 956 | }; |
| 957 | |
| 958 | static const struct amdgpu_asic_funcs vega20_asic_funcs = |
| 959 | { |
| 960 | .read_disabled_bios = &soc15_read_disabled_bios, |
| 961 | .read_bios_from_rom = &soc15_read_bios_from_rom, |
| 962 | .read_register = &soc15_read_register, |
| 963 | .reset = &soc15_asic_reset, |
| 964 | .set_vga_state = &soc15_vga_set_state, |
| 965 | .get_xclk = &soc15_get_xclk, |
| 966 | .set_uvd_clocks = &soc15_set_uvd_clocks, |
| 967 | .set_vce_clocks = &soc15_set_vce_clocks, |
| 968 | .get_config_memsize = &soc15_get_config_memsize, |
| 969 | .flush_hdp = &soc15_flush_hdp, |
| 970 | .invalidate_hdp = &soc15_invalidate_hdp, |
| 971 | .need_full_reset = &soc15_need_full_reset, |
| 972 | .init_doorbell_index = &vega20_doorbell_index_init, |
| 973 | .get_pcie_usage = &vega20_get_pcie_usage, |
| 974 | .need_reset_on_init = &soc15_need_reset_on_init, |
| 975 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
| 976 | .reset_method = &soc15_asic_reset_method |
| 977 | }; |
| 978 | |
| 979 | static int soc15_common_early_init(void *handle) |
| 980 | { |
| 981 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) |
| 982 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 983 | |
| 984 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; |
| 985 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; |
| 986 | adev->smc_rreg = NULL; |
| 987 | adev->smc_wreg = NULL; |
| 988 | adev->pcie_rreg = &soc15_pcie_rreg; |
| 989 | adev->pcie_wreg = &soc15_pcie_wreg; |
| 990 | adev->pcie_rreg64 = &soc15_pcie_rreg64; |
| 991 | adev->pcie_wreg64 = &soc15_pcie_wreg64; |
| 992 | adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; |
| 993 | adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; |
| 994 | adev->didt_rreg = &soc15_didt_rreg; |
| 995 | adev->didt_wreg = &soc15_didt_wreg; |
| 996 | adev->gc_cac_rreg = &soc15_gc_cac_rreg; |
| 997 | adev->gc_cac_wreg = &soc15_gc_cac_wreg; |
| 998 | adev->se_cac_rreg = &soc15_se_cac_rreg; |
| 999 | adev->se_cac_wreg = &soc15_se_cac_wreg; |
| 1000 | |
| 1001 | |
| 1002 | adev->external_rev_id = 0xFF; |
| 1003 | switch (adev->asic_type) { |
| 1004 | case CHIP_VEGA10: |
| 1005 | adev->asic_funcs = &soc15_asic_funcs; |
| 1006 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1007 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1008 | AMD_CG_SUPPORT_GFX_RLC_LS | |
| 1009 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1010 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 1011 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 1012 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1013 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1014 | AMD_CG_SUPPORT_BIF_MGCG | |
| 1015 | AMD_CG_SUPPORT_BIF_LS | |
| 1016 | AMD_CG_SUPPORT_HDP_LS | |
| 1017 | AMD_CG_SUPPORT_DRM_MGCG | |
| 1018 | AMD_CG_SUPPORT_DRM_LS | |
| 1019 | AMD_CG_SUPPORT_ROM_MGCG | |
| 1020 | AMD_CG_SUPPORT_DF_MGCG | |
| 1021 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1022 | AMD_CG_SUPPORT_SDMA_LS | |
| 1023 | AMD_CG_SUPPORT_MC_MGCG | |
| 1024 | AMD_CG_SUPPORT_MC_LS; |
| 1025 | adev->pg_flags = 0; |
| 1026 | adev->external_rev_id = 0x1; |
| 1027 | break; |
| 1028 | case CHIP_VEGA12: |
| 1029 | adev->asic_funcs = &soc15_asic_funcs; |
| 1030 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1031 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1032 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1033 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1034 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 1035 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 1036 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1037 | AMD_CG_SUPPORT_MC_LS | |
| 1038 | AMD_CG_SUPPORT_MC_MGCG | |
| 1039 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1040 | AMD_CG_SUPPORT_SDMA_LS | |
| 1041 | AMD_CG_SUPPORT_BIF_MGCG | |
| 1042 | AMD_CG_SUPPORT_BIF_LS | |
| 1043 | AMD_CG_SUPPORT_HDP_MGCG | |
| 1044 | AMD_CG_SUPPORT_HDP_LS | |
| 1045 | AMD_CG_SUPPORT_ROM_MGCG | |
| 1046 | AMD_CG_SUPPORT_VCE_MGCG | |
| 1047 | AMD_CG_SUPPORT_UVD_MGCG; |
| 1048 | adev->pg_flags = 0; |
| 1049 | adev->external_rev_id = adev->rev_id + 0x14; |
| 1050 | break; |
| 1051 | case CHIP_VEGA20: |
| 1052 | adev->asic_funcs = &vega20_asic_funcs; |
| 1053 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1054 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1055 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1056 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1057 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 1058 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 1059 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1060 | AMD_CG_SUPPORT_MC_LS | |
| 1061 | AMD_CG_SUPPORT_MC_MGCG | |
| 1062 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1063 | AMD_CG_SUPPORT_SDMA_LS | |
| 1064 | AMD_CG_SUPPORT_BIF_MGCG | |
| 1065 | AMD_CG_SUPPORT_BIF_LS | |
| 1066 | AMD_CG_SUPPORT_HDP_MGCG | |
| 1067 | AMD_CG_SUPPORT_HDP_LS | |
| 1068 | AMD_CG_SUPPORT_ROM_MGCG | |
| 1069 | AMD_CG_SUPPORT_VCE_MGCG | |
| 1070 | AMD_CG_SUPPORT_UVD_MGCG; |
| 1071 | adev->pg_flags = 0; |
| 1072 | adev->external_rev_id = adev->rev_id + 0x28; |
| 1073 | break; |
| 1074 | case CHIP_RAVEN: |
| 1075 | adev->asic_funcs = &soc15_asic_funcs; |
| 1076 | if (adev->rev_id >= 0x8) |
| 1077 | adev->external_rev_id = adev->rev_id + 0x79; |
| 1078 | else if (adev->pdev->device == 0x15d8) |
| 1079 | adev->external_rev_id = adev->rev_id + 0x41; |
| 1080 | else if (adev->rev_id == 1) |
| 1081 | adev->external_rev_id = adev->rev_id + 0x20; |
| 1082 | else |
| 1083 | adev->external_rev_id = adev->rev_id + 0x01; |
| 1084 | |
| 1085 | if (adev->rev_id >= 0x8) { |
| 1086 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1087 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1088 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1089 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 1090 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 1091 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1092 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1093 | AMD_CG_SUPPORT_BIF_LS | |
| 1094 | AMD_CG_SUPPORT_HDP_LS | |
| 1095 | AMD_CG_SUPPORT_ROM_MGCG | |
| 1096 | AMD_CG_SUPPORT_MC_MGCG | |
| 1097 | AMD_CG_SUPPORT_MC_LS | |
| 1098 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1099 | AMD_CG_SUPPORT_SDMA_LS | |
| 1100 | AMD_CG_SUPPORT_VCN_MGCG; |
| 1101 | |
| 1102 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
| 1103 | } else if (adev->pdev->device == 0x15d8) { |
| 1104 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1105 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1106 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1107 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 1108 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 1109 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1110 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1111 | AMD_CG_SUPPORT_BIF_LS | |
| 1112 | AMD_CG_SUPPORT_HDP_LS | |
| 1113 | AMD_CG_SUPPORT_ROM_MGCG | |
| 1114 | AMD_CG_SUPPORT_MC_MGCG | |
| 1115 | AMD_CG_SUPPORT_MC_LS | |
| 1116 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1117 | AMD_CG_SUPPORT_SDMA_LS; |
| 1118 | |
| 1119 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | |
| 1120 | AMD_PG_SUPPORT_MMHUB | |
| 1121 | AMD_PG_SUPPORT_VCN | |
| 1122 | AMD_PG_SUPPORT_VCN_DPG; |
| 1123 | } else { |
| 1124 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1125 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1126 | AMD_CG_SUPPORT_GFX_RLC_LS | |
| 1127 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1128 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 1129 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 1130 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1131 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1132 | AMD_CG_SUPPORT_BIF_MGCG | |
| 1133 | AMD_CG_SUPPORT_BIF_LS | |
| 1134 | AMD_CG_SUPPORT_HDP_MGCG | |
| 1135 | AMD_CG_SUPPORT_HDP_LS | |
| 1136 | AMD_CG_SUPPORT_DRM_MGCG | |
| 1137 | AMD_CG_SUPPORT_DRM_LS | |
| 1138 | AMD_CG_SUPPORT_ROM_MGCG | |
| 1139 | AMD_CG_SUPPORT_MC_MGCG | |
| 1140 | AMD_CG_SUPPORT_MC_LS | |
| 1141 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1142 | AMD_CG_SUPPORT_SDMA_LS | |
| 1143 | AMD_CG_SUPPORT_VCN_MGCG; |
| 1144 | |
| 1145 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
| 1146 | } |
| 1147 | break; |
| 1148 | case CHIP_ARCTURUS: |
| 1149 | adev->asic_funcs = &vega20_asic_funcs; |
| 1150 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1151 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1152 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1153 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1154 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1155 | AMD_CG_SUPPORT_HDP_MGCG | |
| 1156 | AMD_CG_SUPPORT_HDP_LS | |
| 1157 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1158 | AMD_CG_SUPPORT_SDMA_LS | |
| 1159 | AMD_CG_SUPPORT_MC_MGCG | |
| 1160 | AMD_CG_SUPPORT_MC_LS; |
| 1161 | adev->pg_flags = 0; |
| 1162 | adev->external_rev_id = adev->rev_id + 0x32; |
| 1163 | break; |
| 1164 | case CHIP_RENOIR: |
| 1165 | adev->asic_funcs = &soc15_asic_funcs; |
| 1166 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
| 1167 | AMD_CG_SUPPORT_GFX_MGLS | |
| 1168 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
| 1169 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
| 1170 | AMD_CG_SUPPORT_GFX_CGCG | |
| 1171 | AMD_CG_SUPPORT_GFX_CGLS | |
| 1172 | AMD_CG_SUPPORT_GFX_CP_LS | |
| 1173 | AMD_CG_SUPPORT_MC_MGCG | |
| 1174 | AMD_CG_SUPPORT_MC_LS | |
| 1175 | AMD_CG_SUPPORT_SDMA_MGCG | |
| 1176 | AMD_CG_SUPPORT_SDMA_LS | |
| 1177 | AMD_CG_SUPPORT_BIF_LS | |
| 1178 | AMD_CG_SUPPORT_HDP_LS | |
| 1179 | AMD_CG_SUPPORT_ROM_MGCG | |
| 1180 | AMD_CG_SUPPORT_VCN_MGCG | |
| 1181 | AMD_CG_SUPPORT_IH_CG | |
| 1182 | AMD_CG_SUPPORT_ATHUB_LS | |
| 1183 | AMD_CG_SUPPORT_ATHUB_MGCG | |
| 1184 | AMD_CG_SUPPORT_DF_MGCG; |
| 1185 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | |
| 1186 | AMD_PG_SUPPORT_VCN | |
| 1187 | AMD_PG_SUPPORT_VCN_DPG; |
| 1188 | adev->external_rev_id = adev->rev_id + 0x91; |
| 1189 | |
| 1190 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) |
| 1191 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | |
| 1192 | AMD_PG_SUPPORT_CP | |
| 1193 | AMD_PG_SUPPORT_RLC_SMU_HS; |
| 1194 | break; |
| 1195 | default: |
| 1196 | /* FIXME: not supported yet */ |
| 1197 | return -EINVAL; |
| 1198 | } |
| 1199 | |
| 1200 | if (amdgpu_sriov_vf(adev)) { |
| 1201 | amdgpu_virt_init_setting(adev); |
| 1202 | xgpu_ai_mailbox_set_irq_funcs(adev); |
| 1203 | } |
| 1204 | |
| 1205 | return 0; |
| 1206 | } |
| 1207 | |
| 1208 | static int soc15_common_late_init(void *handle) |
| 1209 | { |
| 1210 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1211 | |
| 1212 | if (amdgpu_sriov_vf(adev)) |
| 1213 | xgpu_ai_mailbox_get_irq(adev); |
| 1214 | |
| 1215 | return 0; |
| 1216 | } |
| 1217 | |
| 1218 | static int soc15_common_sw_init(void *handle) |
| 1219 | { |
| 1220 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1221 | |
| 1222 | if (amdgpu_sriov_vf(adev)) |
| 1223 | xgpu_ai_mailbox_add_irq_id(adev); |
| 1224 | |
| 1225 | adev->df_funcs->sw_init(adev); |
| 1226 | |
| 1227 | return 0; |
| 1228 | } |
| 1229 | |
| 1230 | static int soc15_common_sw_fini(void *handle) |
| 1231 | { |
| 1232 | return 0; |
| 1233 | } |
| 1234 | |
| 1235 | static void soc15_doorbell_range_init(struct amdgpu_device *adev) |
| 1236 | { |
| 1237 | int i; |
| 1238 | struct amdgpu_ring *ring; |
| 1239 | |
| 1240 | /* sdma/ih doorbell range are programed by hypervisor */ |
| 1241 | if (!amdgpu_sriov_vf(adev)) { |
| 1242 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 1243 | ring = &adev->sdma.instance[i].ring; |
| 1244 | adev->nbio_funcs->sdma_doorbell_range(adev, i, |
| 1245 | ring->use_doorbell, ring->doorbell_index, |
| 1246 | adev->doorbell_index.sdma_doorbell_range); |
| 1247 | } |
| 1248 | |
| 1249 | adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, |
| 1250 | adev->irq.ih.doorbell_index); |
| 1251 | } |
| 1252 | } |
| 1253 | |
| 1254 | static int soc15_common_hw_init(void *handle) |
| 1255 | { |
| 1256 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1257 | |
| 1258 | /* enable pcie gen2/3 link */ |
| 1259 | soc15_pcie_gen3_enable(adev); |
| 1260 | /* enable aspm */ |
| 1261 | soc15_program_aspm(adev); |
| 1262 | /* setup nbio registers */ |
| 1263 | adev->nbio_funcs->init_registers(adev); |
| 1264 | /* remap HDP registers to a hole in mmio space, |
| 1265 | * for the purpose of expose those registers |
| 1266 | * to process space |
| 1267 | */ |
| 1268 | if (adev->nbio_funcs->remap_hdp_registers) |
| 1269 | adev->nbio_funcs->remap_hdp_registers(adev); |
| 1270 | |
| 1271 | /* enable the doorbell aperture */ |
| 1272 | soc15_enable_doorbell_aperture(adev, true); |
| 1273 | /* HW doorbell routing policy: doorbell writing not |
| 1274 | * in SDMA/IH/MM/ACV range will be routed to CP. So |
| 1275 | * we need to init SDMA/IH/MM/ACV doorbell range prior |
| 1276 | * to CP ip block init and ring test. |
| 1277 | */ |
| 1278 | soc15_doorbell_range_init(adev); |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | |
| 1283 | static int soc15_common_hw_fini(void *handle) |
| 1284 | { |
| 1285 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1286 | |
| 1287 | /* disable the doorbell aperture */ |
| 1288 | soc15_enable_doorbell_aperture(adev, false); |
| 1289 | if (amdgpu_sriov_vf(adev)) |
| 1290 | xgpu_ai_mailbox_put_irq(adev); |
| 1291 | |
| 1292 | return 0; |
| 1293 | } |
| 1294 | |
| 1295 | static int soc15_common_suspend(void *handle) |
| 1296 | { |
| 1297 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1298 | |
| 1299 | return soc15_common_hw_fini(adev); |
| 1300 | } |
| 1301 | |
| 1302 | static int soc15_common_resume(void *handle) |
| 1303 | { |
| 1304 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1305 | |
| 1306 | return soc15_common_hw_init(adev); |
| 1307 | } |
| 1308 | |
| 1309 | static bool soc15_common_is_idle(void *handle) |
| 1310 | { |
| 1311 | return true; |
| 1312 | } |
| 1313 | |
| 1314 | static int soc15_common_wait_for_idle(void *handle) |
| 1315 | { |
| 1316 | return 0; |
| 1317 | } |
| 1318 | |
| 1319 | static int soc15_common_soft_reset(void *handle) |
| 1320 | { |
| 1321 | return 0; |
| 1322 | } |
| 1323 | |
| 1324 | static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) |
| 1325 | { |
| 1326 | uint32_t def, data; |
| 1327 | |
| 1328 | if (adev->asic_type == CHIP_VEGA20 || |
| 1329 | adev->asic_type == CHIP_ARCTURUS) { |
| 1330 | def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); |
| 1331 | |
| 1332 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) |
| 1333 | data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | |
| 1334 | HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | |
| 1335 | HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | |
| 1336 | HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; |
| 1337 | else |
| 1338 | data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | |
| 1339 | HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | |
| 1340 | HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | |
| 1341 | HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); |
| 1342 | |
| 1343 | if (def != data) |
| 1344 | WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); |
| 1345 | } else { |
| 1346 | def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); |
| 1347 | |
| 1348 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) |
| 1349 | data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; |
| 1350 | else |
| 1351 | data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; |
| 1352 | |
| 1353 | if (def != data) |
| 1354 | WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); |
| 1355 | } |
| 1356 | } |
| 1357 | |
| 1358 | static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) |
| 1359 | { |
| 1360 | uint32_t def, data; |
| 1361 | |
| 1362 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); |
| 1363 | |
| 1364 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) |
| 1365 | data &= ~(0x01000000 | |
| 1366 | 0x02000000 | |
| 1367 | 0x04000000 | |
| 1368 | 0x08000000 | |
| 1369 | 0x10000000 | |
| 1370 | 0x20000000 | |
| 1371 | 0x40000000 | |
| 1372 | 0x80000000); |
| 1373 | else |
| 1374 | data |= (0x01000000 | |
| 1375 | 0x02000000 | |
| 1376 | 0x04000000 | |
| 1377 | 0x08000000 | |
| 1378 | 0x10000000 | |
| 1379 | 0x20000000 | |
| 1380 | 0x40000000 | |
| 1381 | 0x80000000); |
| 1382 | |
| 1383 | if (def != data) |
| 1384 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); |
| 1385 | } |
| 1386 | |
| 1387 | static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) |
| 1388 | { |
| 1389 | uint32_t def, data; |
| 1390 | |
| 1391 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); |
| 1392 | |
| 1393 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) |
| 1394 | data |= 1; |
| 1395 | else |
| 1396 | data &= ~1; |
| 1397 | |
| 1398 | if (def != data) |
| 1399 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); |
| 1400 | } |
| 1401 | |
| 1402 | static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, |
| 1403 | bool enable) |
| 1404 | { |
| 1405 | uint32_t def, data; |
| 1406 | |
| 1407 | def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); |
| 1408 | |
| 1409 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) |
| 1410 | data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | |
| 1411 | CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); |
| 1412 | else |
| 1413 | data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | |
| 1414 | CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; |
| 1415 | |
| 1416 | if (def != data) |
| 1417 | WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); |
| 1418 | } |
| 1419 | |
| 1420 | static int soc15_common_set_clockgating_state(void *handle, |
| 1421 | enum amd_clockgating_state state) |
| 1422 | { |
| 1423 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1424 | |
| 1425 | if (amdgpu_sriov_vf(adev)) |
| 1426 | return 0; |
| 1427 | |
| 1428 | switch (adev->asic_type) { |
| 1429 | case CHIP_VEGA10: |
| 1430 | case CHIP_VEGA12: |
| 1431 | case CHIP_VEGA20: |
| 1432 | adev->nbio_funcs->update_medium_grain_clock_gating(adev, |
| 1433 | state == AMD_CG_STATE_GATE ? true : false); |
| 1434 | adev->nbio_funcs->update_medium_grain_light_sleep(adev, |
| 1435 | state == AMD_CG_STATE_GATE ? true : false); |
| 1436 | soc15_update_hdp_light_sleep(adev, |
| 1437 | state == AMD_CG_STATE_GATE ? true : false); |
| 1438 | soc15_update_drm_clock_gating(adev, |
| 1439 | state == AMD_CG_STATE_GATE ? true : false); |
| 1440 | soc15_update_drm_light_sleep(adev, |
| 1441 | state == AMD_CG_STATE_GATE ? true : false); |
| 1442 | soc15_update_rom_medium_grain_clock_gating(adev, |
| 1443 | state == AMD_CG_STATE_GATE ? true : false); |
| 1444 | adev->df_funcs->update_medium_grain_clock_gating(adev, |
| 1445 | state == AMD_CG_STATE_GATE ? true : false); |
| 1446 | break; |
| 1447 | case CHIP_RAVEN: |
| 1448 | case CHIP_RENOIR: |
| 1449 | adev->nbio_funcs->update_medium_grain_clock_gating(adev, |
| 1450 | state == AMD_CG_STATE_GATE ? true : false); |
| 1451 | adev->nbio_funcs->update_medium_grain_light_sleep(adev, |
| 1452 | state == AMD_CG_STATE_GATE ? true : false); |
| 1453 | soc15_update_hdp_light_sleep(adev, |
| 1454 | state == AMD_CG_STATE_GATE ? true : false); |
| 1455 | soc15_update_drm_clock_gating(adev, |
| 1456 | state == AMD_CG_STATE_GATE ? true : false); |
| 1457 | soc15_update_drm_light_sleep(adev, |
| 1458 | state == AMD_CG_STATE_GATE ? true : false); |
| 1459 | soc15_update_rom_medium_grain_clock_gating(adev, |
| 1460 | state == AMD_CG_STATE_GATE ? true : false); |
| 1461 | break; |
| 1462 | case CHIP_ARCTURUS: |
| 1463 | soc15_update_hdp_light_sleep(adev, |
| 1464 | state == AMD_CG_STATE_GATE ? true : false); |
| 1465 | break; |
| 1466 | default: |
| 1467 | break; |
| 1468 | } |
| 1469 | return 0; |
| 1470 | } |
| 1471 | |
| 1472 | static void soc15_common_get_clockgating_state(void *handle, u32 *flags) |
| 1473 | { |
| 1474 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1475 | int data; |
| 1476 | |
| 1477 | if (amdgpu_sriov_vf(adev)) |
| 1478 | *flags = 0; |
| 1479 | |
| 1480 | adev->nbio_funcs->get_clockgating_state(adev, flags); |
| 1481 | |
| 1482 | /* AMD_CG_SUPPORT_HDP_LS */ |
| 1483 | data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); |
| 1484 | if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) |
| 1485 | *flags |= AMD_CG_SUPPORT_HDP_LS; |
| 1486 | |
| 1487 | /* AMD_CG_SUPPORT_DRM_MGCG */ |
| 1488 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); |
| 1489 | if (!(data & 0x01000000)) |
| 1490 | *flags |= AMD_CG_SUPPORT_DRM_MGCG; |
| 1491 | |
| 1492 | /* AMD_CG_SUPPORT_DRM_LS */ |
| 1493 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); |
| 1494 | if (data & 0x1) |
| 1495 | *flags |= AMD_CG_SUPPORT_DRM_LS; |
| 1496 | |
| 1497 | /* AMD_CG_SUPPORT_ROM_MGCG */ |
| 1498 | data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); |
| 1499 | if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) |
| 1500 | *flags |= AMD_CG_SUPPORT_ROM_MGCG; |
| 1501 | |
| 1502 | adev->df_funcs->get_clockgating_state(adev, flags); |
| 1503 | } |
| 1504 | |
| 1505 | static int soc15_common_set_powergating_state(void *handle, |
| 1506 | enum amd_powergating_state state) |
| 1507 | { |
| 1508 | /* todo */ |
| 1509 | return 0; |
| 1510 | } |
| 1511 | |
| 1512 | const struct amd_ip_funcs soc15_common_ip_funcs = { |
| 1513 | .name = "soc15_common", |
| 1514 | .early_init = soc15_common_early_init, |
| 1515 | .late_init = soc15_common_late_init, |
| 1516 | .sw_init = soc15_common_sw_init, |
| 1517 | .sw_fini = soc15_common_sw_fini, |
| 1518 | .hw_init = soc15_common_hw_init, |
| 1519 | .hw_fini = soc15_common_hw_fini, |
| 1520 | .suspend = soc15_common_suspend, |
| 1521 | .resume = soc15_common_resume, |
| 1522 | .is_idle = soc15_common_is_idle, |
| 1523 | .wait_for_idle = soc15_common_wait_for_idle, |
| 1524 | .soft_reset = soc15_common_soft_reset, |
| 1525 | .set_clockgating_state = soc15_common_set_clockgating_state, |
| 1526 | .set_powergating_state = soc15_common_set_powergating_state, |
| 1527 | .get_clockgating_state= soc15_common_get_clockgating_state, |
| 1528 | }; |