| 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/firmware.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/module.h> |
| 27 | |
| 28 | #include "amdgpu.h" |
| 29 | #include "amdgpu_ucode.h" |
| 30 | |
| 31 | static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) |
| 32 | { |
| 33 | DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); |
| 34 | DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); |
| 35 | DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); |
| 36 | DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); |
| 37 | DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); |
| 38 | DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); |
| 39 | DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); |
| 40 | DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); |
| 41 | DRM_DEBUG("ucode_array_offset_bytes: %u\n", |
| 42 | le32_to_cpu(hdr->ucode_array_offset_bytes)); |
| 43 | DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); |
| 44 | } |
| 45 | |
| 46 | void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) |
| 47 | { |
| 48 | uint16_t version_major = le16_to_cpu(hdr->header_version_major); |
| 49 | uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); |
| 50 | |
| 51 | DRM_DEBUG("MC\n"); |
| 52 | amdgpu_ucode_print_common_hdr(hdr); |
| 53 | |
| 54 | if (version_major == 1) { |
| 55 | const struct mc_firmware_header_v1_0 *mc_hdr = |
| 56 | container_of(hdr, struct mc_firmware_header_v1_0, header); |
| 57 | |
| 58 | DRM_DEBUG("io_debug_size_bytes: %u\n", |
| 59 | le32_to_cpu(mc_hdr->io_debug_size_bytes)); |
| 60 | DRM_DEBUG("io_debug_array_offset_bytes: %u\n", |
| 61 | le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); |
| 62 | } else { |
| 63 | DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); |
| 64 | } |
| 65 | } |
| 66 | |
| 67 | void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) |
| 68 | { |
| 69 | uint16_t version_major = le16_to_cpu(hdr->header_version_major); |
| 70 | uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); |
| 71 | const struct smc_firmware_header_v1_0 *v1_0_hdr; |
| 72 | const struct smc_firmware_header_v2_0 *v2_0_hdr; |
| 73 | const struct smc_firmware_header_v2_1 *v2_1_hdr; |
| 74 | |
| 75 | DRM_DEBUG("SMC\n"); |
| 76 | amdgpu_ucode_print_common_hdr(hdr); |
| 77 | |
| 78 | if (version_major == 1) { |
| 79 | v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); |
| 80 | DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); |
| 81 | } else if (version_major == 2) { |
| 82 | switch (version_minor) { |
| 83 | case 0: |
| 84 | v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); |
| 85 | DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); |
| 86 | DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); |
| 87 | break; |
| 88 | case 1: |
| 89 | v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); |
| 90 | DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); |
| 91 | DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); |
| 92 | break; |
| 93 | default: |
| 94 | break; |
| 95 | } |
| 96 | |
| 97 | } else { |
| 98 | DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) |
| 103 | { |
| 104 | uint16_t version_major = le16_to_cpu(hdr->header_version_major); |
| 105 | uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); |
| 106 | |
| 107 | DRM_DEBUG("GFX\n"); |
| 108 | amdgpu_ucode_print_common_hdr(hdr); |
| 109 | |
| 110 | if (version_major == 1) { |
| 111 | const struct gfx_firmware_header_v1_0 *gfx_hdr = |
| 112 | container_of(hdr, struct gfx_firmware_header_v1_0, header); |
| 113 | |
| 114 | DRM_DEBUG("ucode_feature_version: %u\n", |
| 115 | le32_to_cpu(gfx_hdr->ucode_feature_version)); |
| 116 | DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); |
| 117 | DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); |
| 118 | } else if (version_major == 2) { |
| 119 | const struct gfx_firmware_header_v2_0 *gfx_hdr = |
| 120 | container_of(hdr, struct gfx_firmware_header_v2_0, header); |
| 121 | |
| 122 | DRM_DEBUG("ucode_feature_version: %u\n", |
| 123 | le32_to_cpu(gfx_hdr->ucode_feature_version)); |
| 124 | } else { |
| 125 | DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) |
| 130 | { |
| 131 | uint16_t version_major = le16_to_cpu(hdr->header_version_major); |
| 132 | uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); |
| 133 | |
| 134 | DRM_DEBUG("RLC\n"); |
| 135 | amdgpu_ucode_print_common_hdr(hdr); |
| 136 | |
| 137 | if (version_major == 1) { |
| 138 | const struct rlc_firmware_header_v1_0 *rlc_hdr = |
| 139 | container_of(hdr, struct rlc_firmware_header_v1_0, header); |
| 140 | |
| 141 | DRM_DEBUG("ucode_feature_version: %u\n", |
| 142 | le32_to_cpu(rlc_hdr->ucode_feature_version)); |
| 143 | DRM_DEBUG("save_and_restore_offset: %u\n", |
| 144 | le32_to_cpu(rlc_hdr->save_and_restore_offset)); |
| 145 | DRM_DEBUG("clear_state_descriptor_offset: %u\n", |
| 146 | le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); |
| 147 | DRM_DEBUG("avail_scratch_ram_locations: %u\n", |
| 148 | le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); |
| 149 | DRM_DEBUG("master_pkt_description_offset: %u\n", |
| 150 | le32_to_cpu(rlc_hdr->master_pkt_description_offset)); |
| 151 | } else if (version_major == 2) { |
| 152 | const struct rlc_firmware_header_v2_0 *rlc_hdr = |
| 153 | container_of(hdr, struct rlc_firmware_header_v2_0, header); |
| 154 | const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 = |
| 155 | container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); |
| 156 | const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 = |
| 157 | container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); |
| 158 | const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 = |
| 159 | container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); |
| 160 | const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = |
| 161 | container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); |
| 162 | |
| 163 | switch (version_minor) { |
| 164 | case 0: |
| 165 | /* rlc_hdr v2_0 */ |
| 166 | DRM_DEBUG("ucode_feature_version: %u\n", |
| 167 | le32_to_cpu(rlc_hdr->ucode_feature_version)); |
| 168 | DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); |
| 169 | DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); |
| 170 | DRM_DEBUG("save_and_restore_offset: %u\n", |
| 171 | le32_to_cpu(rlc_hdr->save_and_restore_offset)); |
| 172 | DRM_DEBUG("clear_state_descriptor_offset: %u\n", |
| 173 | le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); |
| 174 | DRM_DEBUG("avail_scratch_ram_locations: %u\n", |
| 175 | le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); |
| 176 | DRM_DEBUG("reg_restore_list_size: %u\n", |
| 177 | le32_to_cpu(rlc_hdr->reg_restore_list_size)); |
| 178 | DRM_DEBUG("reg_list_format_start: %u\n", |
| 179 | le32_to_cpu(rlc_hdr->reg_list_format_start)); |
| 180 | DRM_DEBUG("reg_list_format_separate_start: %u\n", |
| 181 | le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); |
| 182 | DRM_DEBUG("starting_offsets_start: %u\n", |
| 183 | le32_to_cpu(rlc_hdr->starting_offsets_start)); |
| 184 | DRM_DEBUG("reg_list_format_size_bytes: %u\n", |
| 185 | le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); |
| 186 | DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", |
| 187 | le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); |
| 188 | DRM_DEBUG("reg_list_size_bytes: %u\n", |
| 189 | le32_to_cpu(rlc_hdr->reg_list_size_bytes)); |
| 190 | DRM_DEBUG("reg_list_array_offset_bytes: %u\n", |
| 191 | le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); |
| 192 | DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", |
| 193 | le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); |
| 194 | DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", |
| 195 | le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); |
| 196 | DRM_DEBUG("reg_list_separate_size_bytes: %u\n", |
| 197 | le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); |
| 198 | DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", |
| 199 | le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); |
| 200 | break; |
| 201 | case 1: |
| 202 | /* rlc_hdr v2_1 */ |
| 203 | DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", |
| 204 | le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length)); |
| 205 | DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", |
| 206 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver)); |
| 207 | DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", |
| 208 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver)); |
| 209 | DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", |
| 210 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes)); |
| 211 | DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", |
| 212 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes)); |
| 213 | DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", |
| 214 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver)); |
| 215 | DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", |
| 216 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver)); |
| 217 | DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", |
| 218 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes)); |
| 219 | DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", |
| 220 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes)); |
| 221 | DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", |
| 222 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver)); |
| 223 | DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", |
| 224 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver)); |
| 225 | DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", |
| 226 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes)); |
| 227 | DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", |
| 228 | le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes)); |
| 229 | break; |
| 230 | case 2: |
| 231 | /* rlc_hdr v2_2 */ |
| 232 | DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", |
| 233 | le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes)); |
| 234 | DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", |
| 235 | le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes)); |
| 236 | DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", |
| 237 | le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes)); |
| 238 | DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", |
| 239 | le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes)); |
| 240 | break; |
| 241 | case 3: |
| 242 | /* rlc_hdr v2_3 */ |
| 243 | DRM_DEBUG("rlcp_ucode_version: %u\n", |
| 244 | le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version)); |
| 245 | DRM_DEBUG("rlcp_ucode_feature_version: %u\n", |
| 246 | le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version)); |
| 247 | DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", |
| 248 | le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes)); |
| 249 | DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", |
| 250 | le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes)); |
| 251 | DRM_DEBUG("rlcv_ucode_version: %u\n", |
| 252 | le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version)); |
| 253 | DRM_DEBUG("rlcv_ucode_feature_version: %u\n", |
| 254 | le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version)); |
| 255 | DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", |
| 256 | le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes)); |
| 257 | DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", |
| 258 | le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes)); |
| 259 | break; |
| 260 | case 4: |
| 261 | /* rlc_hdr v2_4 */ |
| 262 | DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", |
| 263 | le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes)); |
| 264 | DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", |
| 265 | le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes)); |
| 266 | DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", |
| 267 | le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes)); |
| 268 | DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", |
| 269 | le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes)); |
| 270 | DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", |
| 271 | le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes)); |
| 272 | DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", |
| 273 | le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes)); |
| 274 | DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", |
| 275 | le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes)); |
| 276 | DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", |
| 277 | le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes)); |
| 278 | DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", |
| 279 | le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes)); |
| 280 | DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", |
| 281 | le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); |
| 282 | break; |
| 283 | default: |
| 284 | DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); |
| 285 | break; |
| 286 | } |
| 287 | } else { |
| 288 | DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); |
| 289 | } |
| 290 | } |
| 291 | |
| 292 | void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) |
| 293 | { |
| 294 | uint16_t version_major = le16_to_cpu(hdr->header_version_major); |
| 295 | uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); |
| 296 | |
| 297 | DRM_DEBUG("SDMA\n"); |
| 298 | amdgpu_ucode_print_common_hdr(hdr); |
| 299 | |
| 300 | if (version_major == 1) { |
| 301 | const struct sdma_firmware_header_v1_0 *sdma_hdr = |
| 302 | container_of(hdr, struct sdma_firmware_header_v1_0, header); |
| 303 | |
| 304 | DRM_DEBUG("ucode_feature_version: %u\n", |
| 305 | le32_to_cpu(sdma_hdr->ucode_feature_version)); |
| 306 | DRM_DEBUG("ucode_change_version: %u\n", |
| 307 | le32_to_cpu(sdma_hdr->ucode_change_version)); |
| 308 | DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); |
| 309 | DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); |
| 310 | if (version_minor >= 1) { |
| 311 | const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = |
| 312 | container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); |
| 313 | DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); |
| 314 | } |
| 315 | } else if (version_major == 2) { |
| 316 | const struct sdma_firmware_header_v2_0 *sdma_hdr = |
| 317 | container_of(hdr, struct sdma_firmware_header_v2_0, header); |
| 318 | |
| 319 | DRM_DEBUG("ucode_feature_version: %u\n", |
| 320 | le32_to_cpu(sdma_hdr->ucode_feature_version)); |
| 321 | DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); |
| 322 | DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); |
| 323 | DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); |
| 324 | DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); |
| 325 | DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); |
| 326 | } else { |
| 327 | DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", |
| 328 | version_major, version_minor); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) |
| 333 | { |
| 334 | uint16_t version_major = le16_to_cpu(hdr->header_version_major); |
| 335 | uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); |
| 336 | uint32_t fw_index; |
| 337 | const struct psp_fw_bin_desc *desc; |
| 338 | |
| 339 | DRM_DEBUG("PSP\n"); |
| 340 | amdgpu_ucode_print_common_hdr(hdr); |
| 341 | |
| 342 | if (version_major == 1) { |
| 343 | const struct psp_firmware_header_v1_0 *psp_hdr = |
| 344 | container_of(hdr, struct psp_firmware_header_v1_0, header); |
| 345 | |
| 346 | DRM_DEBUG("ucode_feature_version: %u\n", |
| 347 | le32_to_cpu(psp_hdr->sos.fw_version)); |
| 348 | DRM_DEBUG("sos_offset_bytes: %u\n", |
| 349 | le32_to_cpu(psp_hdr->sos.offset_bytes)); |
| 350 | DRM_DEBUG("sos_size_bytes: %u\n", |
| 351 | le32_to_cpu(psp_hdr->sos.size_bytes)); |
| 352 | if (version_minor == 1) { |
| 353 | const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = |
| 354 | container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); |
| 355 | DRM_DEBUG("toc_header_version: %u\n", |
| 356 | le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); |
| 357 | DRM_DEBUG("toc_offset_bytes: %u\n", |
| 358 | le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); |
| 359 | DRM_DEBUG("toc_size_bytes: %u\n", |
| 360 | le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); |
| 361 | DRM_DEBUG("kdb_header_version: %u\n", |
| 362 | le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); |
| 363 | DRM_DEBUG("kdb_offset_bytes: %u\n", |
| 364 | le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); |
| 365 | DRM_DEBUG("kdb_size_bytes: %u\n", |
| 366 | le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); |
| 367 | } |
| 368 | if (version_minor == 2) { |
| 369 | const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = |
| 370 | container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); |
| 371 | DRM_DEBUG("kdb_header_version: %u\n", |
| 372 | le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); |
| 373 | DRM_DEBUG("kdb_offset_bytes: %u\n", |
| 374 | le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); |
| 375 | DRM_DEBUG("kdb_size_bytes: %u\n", |
| 376 | le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); |
| 377 | } |
| 378 | if (version_minor == 3) { |
| 379 | const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = |
| 380 | container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); |
| 381 | const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = |
| 382 | container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); |
| 383 | DRM_DEBUG("toc_header_version: %u\n", |
| 384 | le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); |
| 385 | DRM_DEBUG("toc_offset_bytes: %u\n", |
| 386 | le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); |
| 387 | DRM_DEBUG("toc_size_bytes: %u\n", |
| 388 | le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); |
| 389 | DRM_DEBUG("kdb_header_version: %u\n", |
| 390 | le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); |
| 391 | DRM_DEBUG("kdb_offset_bytes: %u\n", |
| 392 | le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); |
| 393 | DRM_DEBUG("kdb_size_bytes: %u\n", |
| 394 | le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); |
| 395 | DRM_DEBUG("spl_header_version: %u\n", |
| 396 | le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); |
| 397 | DRM_DEBUG("spl_offset_bytes: %u\n", |
| 398 | le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); |
| 399 | DRM_DEBUG("spl_size_bytes: %u\n", |
| 400 | le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); |
| 401 | } |
| 402 | } else if (version_major == 2) { |
| 403 | const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 = |
| 404 | container_of(hdr, struct psp_firmware_header_v2_0, header); |
| 405 | for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) { |
| 406 | desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]); |
| 407 | switch (desc->fw_type) { |
| 408 | case PSP_FW_TYPE_PSP_SOS: |
| 409 | DRM_DEBUG("psp_sos_version: %u\n", |
| 410 | le32_to_cpu(desc->fw_version)); |
| 411 | DRM_DEBUG("psp_sos_size_bytes: %u\n", |
| 412 | le32_to_cpu(desc->size_bytes)); |
| 413 | break; |
| 414 | case PSP_FW_TYPE_PSP_SYS_DRV: |
| 415 | DRM_DEBUG("psp_sys_drv_version: %u\n", |
| 416 | le32_to_cpu(desc->fw_version)); |
| 417 | DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", |
| 418 | le32_to_cpu(desc->size_bytes)); |
| 419 | break; |
| 420 | case PSP_FW_TYPE_PSP_KDB: |
| 421 | DRM_DEBUG("psp_kdb_version: %u\n", |
| 422 | le32_to_cpu(desc->fw_version)); |
| 423 | DRM_DEBUG("psp_kdb_size_bytes: %u\n", |
| 424 | le32_to_cpu(desc->size_bytes)); |
| 425 | break; |
| 426 | case PSP_FW_TYPE_PSP_TOC: |
| 427 | DRM_DEBUG("psp_toc_version: %u\n", |
| 428 | le32_to_cpu(desc->fw_version)); |
| 429 | DRM_DEBUG("psp_toc_size_bytes: %u\n", |
| 430 | le32_to_cpu(desc->size_bytes)); |
| 431 | break; |
| 432 | case PSP_FW_TYPE_PSP_SPL: |
| 433 | DRM_DEBUG("psp_spl_version: %u\n", |
| 434 | le32_to_cpu(desc->fw_version)); |
| 435 | DRM_DEBUG("psp_spl_size_bytes: %u\n", |
| 436 | le32_to_cpu(desc->size_bytes)); |
| 437 | break; |
| 438 | case PSP_FW_TYPE_PSP_RL: |
| 439 | DRM_DEBUG("psp_rl_version: %u\n", |
| 440 | le32_to_cpu(desc->fw_version)); |
| 441 | DRM_DEBUG("psp_rl_size_bytes: %u\n", |
| 442 | le32_to_cpu(desc->size_bytes)); |
| 443 | break; |
| 444 | case PSP_FW_TYPE_PSP_SOC_DRV: |
| 445 | DRM_DEBUG("psp_soc_drv_version: %u\n", |
| 446 | le32_to_cpu(desc->fw_version)); |
| 447 | DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", |
| 448 | le32_to_cpu(desc->size_bytes)); |
| 449 | break; |
| 450 | case PSP_FW_TYPE_PSP_INTF_DRV: |
| 451 | DRM_DEBUG("psp_intf_drv_version: %u\n", |
| 452 | le32_to_cpu(desc->fw_version)); |
| 453 | DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", |
| 454 | le32_to_cpu(desc->size_bytes)); |
| 455 | break; |
| 456 | case PSP_FW_TYPE_PSP_DBG_DRV: |
| 457 | DRM_DEBUG("psp_dbg_drv_version: %u\n", |
| 458 | le32_to_cpu(desc->fw_version)); |
| 459 | DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", |
| 460 | le32_to_cpu(desc->size_bytes)); |
| 461 | break; |
| 462 | case PSP_FW_TYPE_PSP_RAS_DRV: |
| 463 | DRM_DEBUG("psp_ras_drv_version: %u\n", |
| 464 | le32_to_cpu(desc->fw_version)); |
| 465 | DRM_DEBUG("psp_ras_drv_size_bytes: %u\n", |
| 466 | le32_to_cpu(desc->size_bytes)); |
| 467 | break; |
| 468 | default: |
| 469 | DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); |
| 470 | break; |
| 471 | } |
| 472 | } |
| 473 | } else { |
| 474 | DRM_ERROR("Unknown PSP ucode version: %u.%u\n", |
| 475 | version_major, version_minor); |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) |
| 480 | { |
| 481 | uint16_t version_major = le16_to_cpu(hdr->header_version_major); |
| 482 | uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); |
| 483 | |
| 484 | DRM_DEBUG("GPU_INFO\n"); |
| 485 | amdgpu_ucode_print_common_hdr(hdr); |
| 486 | |
| 487 | if (version_major == 1) { |
| 488 | const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = |
| 489 | container_of(hdr, struct gpu_info_firmware_header_v1_0, header); |
| 490 | |
| 491 | DRM_DEBUG("version_major: %u\n", |
| 492 | le16_to_cpu(gpu_info_hdr->version_major)); |
| 493 | DRM_DEBUG("version_minor: %u\n", |
| 494 | le16_to_cpu(gpu_info_hdr->version_minor)); |
| 495 | } else { |
| 496 | DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | static int amdgpu_ucode_validate(const struct firmware *fw) |
| 501 | { |
| 502 | const struct common_firmware_header *hdr = |
| 503 | (const struct common_firmware_header *)fw->data; |
| 504 | |
| 505 | if (fw->size == le32_to_cpu(hdr->size_bytes)) |
| 506 | return 0; |
| 507 | |
| 508 | return -EINVAL; |
| 509 | } |
| 510 | |
| 511 | bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, |
| 512 | uint16_t hdr_major, uint16_t hdr_minor) |
| 513 | { |
| 514 | if ((hdr->common.header_version_major == hdr_major) && |
| 515 | (hdr->common.header_version_minor == hdr_minor)) |
| 516 | return true; |
| 517 | return false; |
| 518 | } |
| 519 | |
| 520 | enum amdgpu_firmware_load_type |
| 521 | amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) |
| 522 | { |
| 523 | switch (adev->asic_type) { |
| 524 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 525 | case CHIP_TAHITI: |
| 526 | case CHIP_PITCAIRN: |
| 527 | case CHIP_VERDE: |
| 528 | case CHIP_OLAND: |
| 529 | case CHIP_HAINAN: |
| 530 | return AMDGPU_FW_LOAD_DIRECT; |
| 531 | #endif |
| 532 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 533 | case CHIP_BONAIRE: |
| 534 | case CHIP_KAVERI: |
| 535 | case CHIP_KABINI: |
| 536 | case CHIP_HAWAII: |
| 537 | case CHIP_MULLINS: |
| 538 | return AMDGPU_FW_LOAD_DIRECT; |
| 539 | #endif |
| 540 | case CHIP_TOPAZ: |
| 541 | case CHIP_TONGA: |
| 542 | case CHIP_FIJI: |
| 543 | case CHIP_CARRIZO: |
| 544 | case CHIP_STONEY: |
| 545 | case CHIP_POLARIS10: |
| 546 | case CHIP_POLARIS11: |
| 547 | case CHIP_POLARIS12: |
| 548 | case CHIP_VEGAM: |
| 549 | return AMDGPU_FW_LOAD_SMU; |
| 550 | case CHIP_CYAN_SKILLFISH: |
| 551 | if (!(load_type && |
| 552 | adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) |
| 553 | return AMDGPU_FW_LOAD_DIRECT; |
| 554 | else |
| 555 | return AMDGPU_FW_LOAD_PSP; |
| 556 | default: |
| 557 | if (!load_type) |
| 558 | return AMDGPU_FW_LOAD_DIRECT; |
| 559 | else if (load_type == 3) |
| 560 | return AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO; |
| 561 | else |
| 562 | return AMDGPU_FW_LOAD_PSP; |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) |
| 567 | { |
| 568 | switch (ucode_id) { |
| 569 | case AMDGPU_UCODE_ID_SDMA0: |
| 570 | return "SDMA0"; |
| 571 | case AMDGPU_UCODE_ID_SDMA1: |
| 572 | return "SDMA1"; |
| 573 | case AMDGPU_UCODE_ID_SDMA2: |
| 574 | return "SDMA2"; |
| 575 | case AMDGPU_UCODE_ID_SDMA3: |
| 576 | return "SDMA3"; |
| 577 | case AMDGPU_UCODE_ID_SDMA4: |
| 578 | return "SDMA4"; |
| 579 | case AMDGPU_UCODE_ID_SDMA5: |
| 580 | return "SDMA5"; |
| 581 | case AMDGPU_UCODE_ID_SDMA6: |
| 582 | return "SDMA6"; |
| 583 | case AMDGPU_UCODE_ID_SDMA7: |
| 584 | return "SDMA7"; |
| 585 | case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: |
| 586 | return "SDMA_CTX"; |
| 587 | case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: |
| 588 | return "SDMA_CTL"; |
| 589 | case AMDGPU_UCODE_ID_CP_CE: |
| 590 | return "CP_CE"; |
| 591 | case AMDGPU_UCODE_ID_CP_PFP: |
| 592 | return "CP_PFP"; |
| 593 | case AMDGPU_UCODE_ID_CP_ME: |
| 594 | return "CP_ME"; |
| 595 | case AMDGPU_UCODE_ID_CP_MEC1: |
| 596 | return "CP_MEC1"; |
| 597 | case AMDGPU_UCODE_ID_CP_MEC1_JT: |
| 598 | return "CP_MEC1_JT"; |
| 599 | case AMDGPU_UCODE_ID_CP_MEC2: |
| 600 | return "CP_MEC2"; |
| 601 | case AMDGPU_UCODE_ID_CP_MEC2_JT: |
| 602 | return "CP_MEC2_JT"; |
| 603 | case AMDGPU_UCODE_ID_CP_MES: |
| 604 | return "CP_MES"; |
| 605 | case AMDGPU_UCODE_ID_CP_MES_DATA: |
| 606 | return "CP_MES_DATA"; |
| 607 | case AMDGPU_UCODE_ID_CP_MES1: |
| 608 | return "CP_MES_KIQ"; |
| 609 | case AMDGPU_UCODE_ID_CP_MES1_DATA: |
| 610 | return "CP_MES_KIQ_DATA"; |
| 611 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: |
| 612 | return "RLC_RESTORE_LIST_CNTL"; |
| 613 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: |
| 614 | return "RLC_RESTORE_LIST_GPM_MEM"; |
| 615 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: |
| 616 | return "RLC_RESTORE_LIST_SRM_MEM"; |
| 617 | case AMDGPU_UCODE_ID_RLC_IRAM: |
| 618 | return "RLC_IRAM"; |
| 619 | case AMDGPU_UCODE_ID_RLC_DRAM: |
| 620 | return "RLC_DRAM"; |
| 621 | case AMDGPU_UCODE_ID_RLC_G: |
| 622 | return "RLC_G"; |
| 623 | case AMDGPU_UCODE_ID_RLC_P: |
| 624 | return "RLC_P"; |
| 625 | case AMDGPU_UCODE_ID_RLC_V: |
| 626 | return "RLC_V"; |
| 627 | case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: |
| 628 | return "GLOBAL_TAP_DELAYS"; |
| 629 | case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: |
| 630 | return "SE0_TAP_DELAYS"; |
| 631 | case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: |
| 632 | return "SE1_TAP_DELAYS"; |
| 633 | case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: |
| 634 | return "SE2_TAP_DELAYS"; |
| 635 | case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: |
| 636 | return "SE3_TAP_DELAYS"; |
| 637 | case AMDGPU_UCODE_ID_IMU_I: |
| 638 | return "IMU_I"; |
| 639 | case AMDGPU_UCODE_ID_IMU_D: |
| 640 | return "IMU_D"; |
| 641 | case AMDGPU_UCODE_ID_STORAGE: |
| 642 | return "STORAGE"; |
| 643 | case AMDGPU_UCODE_ID_SMC: |
| 644 | return "SMC"; |
| 645 | case AMDGPU_UCODE_ID_PPTABLE: |
| 646 | return "PPTABLE"; |
| 647 | case AMDGPU_UCODE_ID_P2S_TABLE: |
| 648 | return "P2STABLE"; |
| 649 | case AMDGPU_UCODE_ID_UVD: |
| 650 | return "UVD"; |
| 651 | case AMDGPU_UCODE_ID_UVD1: |
| 652 | return "UVD1"; |
| 653 | case AMDGPU_UCODE_ID_VCE: |
| 654 | return "VCE"; |
| 655 | case AMDGPU_UCODE_ID_VCN: |
| 656 | return "VCN"; |
| 657 | case AMDGPU_UCODE_ID_VCN1: |
| 658 | return "VCN1"; |
| 659 | case AMDGPU_UCODE_ID_DMCU_ERAM: |
| 660 | return "DMCU_ERAM"; |
| 661 | case AMDGPU_UCODE_ID_DMCU_INTV: |
| 662 | return "DMCU_INTV"; |
| 663 | case AMDGPU_UCODE_ID_VCN0_RAM: |
| 664 | return "VCN0_RAM"; |
| 665 | case AMDGPU_UCODE_ID_VCN1_RAM: |
| 666 | return "VCN1_RAM"; |
| 667 | case AMDGPU_UCODE_ID_DMCUB: |
| 668 | return "DMCUB"; |
| 669 | case AMDGPU_UCODE_ID_CAP: |
| 670 | return "CAP"; |
| 671 | case AMDGPU_UCODE_ID_VPE_CTX: |
| 672 | return "VPE_CTX"; |
| 673 | case AMDGPU_UCODE_ID_VPE_CTL: |
| 674 | return "VPE_CTL"; |
| 675 | case AMDGPU_UCODE_ID_VPE: |
| 676 | return "VPE"; |
| 677 | case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: |
| 678 | return "UMSCH_MM_UCODE"; |
| 679 | case AMDGPU_UCODE_ID_UMSCH_MM_DATA: |
| 680 | return "UMSCH_MM_DATA"; |
| 681 | case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: |
| 682 | return "UMSCH_MM_CMD_BUFFER"; |
| 683 | case AMDGPU_UCODE_ID_JPEG_RAM: |
| 684 | return "JPEG"; |
| 685 | default: |
| 686 | return "UNKNOWN UCODE"; |
| 687 | } |
| 688 | } |
| 689 | |
| 690 | static inline int amdgpu_ucode_is_valid(uint32_t fw_version) |
| 691 | { |
| 692 | if (!fw_version) |
| 693 | return -EINVAL; |
| 694 | |
| 695 | return 0; |
| 696 | } |
| 697 | |
| 698 | #define FW_VERSION_ATTR(name, mode, field) \ |
| 699 | static ssize_t show_##name(struct device *dev, \ |
| 700 | struct device_attribute *attr, char *buf) \ |
| 701 | { \ |
| 702 | struct drm_device *ddev = dev_get_drvdata(dev); \ |
| 703 | struct amdgpu_device *adev = drm_to_adev(ddev); \ |
| 704 | \ |
| 705 | if (!buf) \ |
| 706 | return amdgpu_ucode_is_valid(adev->field); \ |
| 707 | \ |
| 708 | return sysfs_emit(buf, "0x%08x\n", adev->field); \ |
| 709 | } \ |
| 710 | static DEVICE_ATTR(name, mode, show_##name, NULL) |
| 711 | |
| 712 | FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); |
| 713 | FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); |
| 714 | FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); |
| 715 | FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); |
| 716 | FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); |
| 717 | FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); |
| 718 | FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); |
| 719 | FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); |
| 720 | FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); |
| 721 | FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); |
| 722 | FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); |
| 723 | FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); |
| 724 | FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version); |
| 725 | FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version); |
| 726 | FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version); |
| 727 | FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version); |
| 728 | FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version); |
| 729 | FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); |
| 730 | FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); |
| 731 | FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); |
| 732 | FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); |
| 733 | FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); |
| 734 | FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK); |
| 735 | FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK); |
| 736 | |
| 737 | static struct attribute *fw_attrs[] = { |
| 738 | &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, |
| 739 | &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, |
| 740 | &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, |
| 741 | &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, |
| 742 | &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, |
| 743 | &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, |
| 744 | &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, |
| 745 | &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, |
| 746 | &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, |
| 747 | &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, |
| 748 | &dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr, |
| 749 | &dev_attr_mes_fw_version.attr, &dev_attr_mes_kiq_fw_version.attr, |
| 750 | NULL |
| 751 | }; |
| 752 | |
| 753 | #define to_dev_attr(x) container_of(x, struct device_attribute, attr) |
| 754 | |
| 755 | static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj, |
| 756 | struct attribute *attr, int idx) |
| 757 | { |
| 758 | struct device_attribute *dev_attr = to_dev_attr(attr); |
| 759 | struct device *dev = kobj_to_dev(kobj); |
| 760 | |
| 761 | if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL) |
| 762 | return 0; |
| 763 | |
| 764 | return attr->mode; |
| 765 | } |
| 766 | |
| 767 | static const struct attribute_group fw_attr_group = { |
| 768 | .name = "fw_version", |
| 769 | .attrs = fw_attrs, |
| 770 | .is_visible = amdgpu_ucode_sys_visible |
| 771 | }; |
| 772 | |
| 773 | int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) |
| 774 | { |
| 775 | return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); |
| 776 | } |
| 777 | |
| 778 | void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) |
| 779 | { |
| 780 | sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); |
| 781 | } |
| 782 | |
| 783 | static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, |
| 784 | struct amdgpu_firmware_info *ucode, |
| 785 | uint64_t mc_addr, void *kptr) |
| 786 | { |
| 787 | const struct common_firmware_header *header = NULL; |
| 788 | const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; |
| 789 | const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL; |
| 790 | const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; |
| 791 | const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; |
| 792 | const struct mes_firmware_header_v1_0 *mes_hdr = NULL; |
| 793 | const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL; |
| 794 | const struct imu_firmware_header_v1_0 *imu_hdr = NULL; |
| 795 | const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL; |
| 796 | const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL; |
| 797 | u8 *ucode_addr; |
| 798 | |
| 799 | if (!ucode->fw) |
| 800 | return 0; |
| 801 | |
| 802 | ucode->mc_addr = mc_addr; |
| 803 | ucode->kaddr = kptr; |
| 804 | |
| 805 | if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) |
| 806 | return 0; |
| 807 | |
| 808 | header = (const struct common_firmware_header *)ucode->fw->data; |
| 809 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; |
| 810 | cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data; |
| 811 | dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; |
| 812 | dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; |
| 813 | mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; |
| 814 | sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data; |
| 815 | imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data; |
| 816 | vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data; |
| 817 | umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data; |
| 818 | |
| 819 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
| 820 | switch (ucode->ucode_id) { |
| 821 | case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: |
| 822 | ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); |
| 823 | ucode_addr = (u8 *)ucode->fw->data + |
| 824 | le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes); |
| 825 | break; |
| 826 | case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: |
| 827 | ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); |
| 828 | ucode_addr = (u8 *)ucode->fw->data + |
| 829 | le32_to_cpu(sdma_hdr->ctl_ucode_offset); |
| 830 | break; |
| 831 | case AMDGPU_UCODE_ID_CP_MEC1: |
| 832 | case AMDGPU_UCODE_ID_CP_MEC2: |
| 833 | ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - |
| 834 | le32_to_cpu(cp_hdr->jt_size) * 4; |
| 835 | ucode_addr = (u8 *)ucode->fw->data + |
| 836 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 837 | break; |
| 838 | case AMDGPU_UCODE_ID_CP_MEC1_JT: |
| 839 | case AMDGPU_UCODE_ID_CP_MEC2_JT: |
| 840 | ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; |
| 841 | ucode_addr = (u8 *)ucode->fw->data + |
| 842 | le32_to_cpu(header->ucode_array_offset_bytes) + |
| 843 | le32_to_cpu(cp_hdr->jt_offset) * 4; |
| 844 | break; |
| 845 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: |
| 846 | ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; |
| 847 | ucode_addr = adev->gfx.rlc.save_restore_list_cntl; |
| 848 | break; |
| 849 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: |
| 850 | ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; |
| 851 | ucode_addr = adev->gfx.rlc.save_restore_list_gpm; |
| 852 | break; |
| 853 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: |
| 854 | ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; |
| 855 | ucode_addr = adev->gfx.rlc.save_restore_list_srm; |
| 856 | break; |
| 857 | case AMDGPU_UCODE_ID_RLC_IRAM: |
| 858 | ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; |
| 859 | ucode_addr = adev->gfx.rlc.rlc_iram_ucode; |
| 860 | break; |
| 861 | case AMDGPU_UCODE_ID_RLC_DRAM: |
| 862 | ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; |
| 863 | ucode_addr = adev->gfx.rlc.rlc_dram_ucode; |
| 864 | break; |
| 865 | case AMDGPU_UCODE_ID_RLC_P: |
| 866 | ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes; |
| 867 | ucode_addr = adev->gfx.rlc.rlcp_ucode; |
| 868 | break; |
| 869 | case AMDGPU_UCODE_ID_RLC_V: |
| 870 | ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes; |
| 871 | ucode_addr = adev->gfx.rlc.rlcv_ucode; |
| 872 | break; |
| 873 | case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: |
| 874 | ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes; |
| 875 | ucode_addr = adev->gfx.rlc.global_tap_delays_ucode; |
| 876 | break; |
| 877 | case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: |
| 878 | ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes; |
| 879 | ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode; |
| 880 | break; |
| 881 | case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: |
| 882 | ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes; |
| 883 | ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode; |
| 884 | break; |
| 885 | case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: |
| 886 | ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes; |
| 887 | ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode; |
| 888 | break; |
| 889 | case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: |
| 890 | ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes; |
| 891 | ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode; |
| 892 | break; |
| 893 | case AMDGPU_UCODE_ID_CP_MES: |
| 894 | ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); |
| 895 | ucode_addr = (u8 *)ucode->fw->data + |
| 896 | le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); |
| 897 | break; |
| 898 | case AMDGPU_UCODE_ID_CP_MES_DATA: |
| 899 | ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); |
| 900 | ucode_addr = (u8 *)ucode->fw->data + |
| 901 | le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); |
| 902 | break; |
| 903 | case AMDGPU_UCODE_ID_CP_MES1: |
| 904 | ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); |
| 905 | ucode_addr = (u8 *)ucode->fw->data + |
| 906 | le32_to_cpu(mes_hdr->mes_ucode_offset_bytes); |
| 907 | break; |
| 908 | case AMDGPU_UCODE_ID_CP_MES1_DATA: |
| 909 | ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); |
| 910 | ucode_addr = (u8 *)ucode->fw->data + |
| 911 | le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes); |
| 912 | break; |
| 913 | case AMDGPU_UCODE_ID_DMCU_ERAM: |
| 914 | ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - |
| 915 | le32_to_cpu(dmcu_hdr->intv_size_bytes); |
| 916 | ucode_addr = (u8 *)ucode->fw->data + |
| 917 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 918 | break; |
| 919 | case AMDGPU_UCODE_ID_DMCU_INTV: |
| 920 | ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); |
| 921 | ucode_addr = (u8 *)ucode->fw->data + |
| 922 | le32_to_cpu(header->ucode_array_offset_bytes) + |
| 923 | le32_to_cpu(dmcu_hdr->intv_offset_bytes); |
| 924 | break; |
| 925 | case AMDGPU_UCODE_ID_DMCUB: |
| 926 | ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); |
| 927 | ucode_addr = (u8 *)ucode->fw->data + |
| 928 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 929 | break; |
| 930 | case AMDGPU_UCODE_ID_PPTABLE: |
| 931 | ucode->ucode_size = ucode->fw->size; |
| 932 | ucode_addr = (u8 *)ucode->fw->data; |
| 933 | break; |
| 934 | case AMDGPU_UCODE_ID_P2S_TABLE: |
| 935 | ucode->ucode_size = ucode->fw->size; |
| 936 | ucode_addr = (u8 *)ucode->fw->data; |
| 937 | break; |
| 938 | case AMDGPU_UCODE_ID_IMU_I: |
| 939 | ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); |
| 940 | ucode_addr = (u8 *)ucode->fw->data + |
| 941 | le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes); |
| 942 | break; |
| 943 | case AMDGPU_UCODE_ID_IMU_D: |
| 944 | ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes); |
| 945 | ucode_addr = (u8 *)ucode->fw->data + |
| 946 | le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) + |
| 947 | le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes); |
| 948 | break; |
| 949 | case AMDGPU_UCODE_ID_CP_RS64_PFP: |
| 950 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); |
| 951 | ucode_addr = (u8 *)ucode->fw->data + |
| 952 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 953 | break; |
| 954 | case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: |
| 955 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 956 | ucode_addr = (u8 *)ucode->fw->data + |
| 957 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 958 | break; |
| 959 | case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: |
| 960 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 961 | ucode_addr = (u8 *)ucode->fw->data + |
| 962 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 963 | break; |
| 964 | case AMDGPU_UCODE_ID_CP_RS64_ME: |
| 965 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); |
| 966 | ucode_addr = (u8 *)ucode->fw->data + |
| 967 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 968 | break; |
| 969 | case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: |
| 970 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 971 | ucode_addr = (u8 *)ucode->fw->data + |
| 972 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 973 | break; |
| 974 | case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: |
| 975 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 976 | ucode_addr = (u8 *)ucode->fw->data + |
| 977 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 978 | break; |
| 979 | case AMDGPU_UCODE_ID_CP_RS64_MEC: |
| 980 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); |
| 981 | ucode_addr = (u8 *)ucode->fw->data + |
| 982 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 983 | break; |
| 984 | case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: |
| 985 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 986 | ucode_addr = (u8 *)ucode->fw->data + |
| 987 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 988 | break; |
| 989 | case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: |
| 990 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 991 | ucode_addr = (u8 *)ucode->fw->data + |
| 992 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 993 | break; |
| 994 | case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: |
| 995 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 996 | ucode_addr = (u8 *)ucode->fw->data + |
| 997 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 998 | break; |
| 999 | case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: |
| 1000 | ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); |
| 1001 | ucode_addr = (u8 *)ucode->fw->data + |
| 1002 | le32_to_cpu(cpv2_hdr->data_offset_bytes); |
| 1003 | break; |
| 1004 | case AMDGPU_UCODE_ID_VPE_CTX: |
| 1005 | ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); |
| 1006 | ucode_addr = (u8 *)ucode->fw->data + |
| 1007 | le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); |
| 1008 | break; |
| 1009 | case AMDGPU_UCODE_ID_VPE_CTL: |
| 1010 | ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); |
| 1011 | ucode_addr = (u8 *)ucode->fw->data + |
| 1012 | le32_to_cpu(vpe_hdr->ctl_ucode_offset); |
| 1013 | break; |
| 1014 | case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: |
| 1015 | ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_size_bytes); |
| 1016 | ucode_addr = (u8 *)ucode->fw->data + |
| 1017 | le32_to_cpu(umsch_mm_hdr->header.ucode_array_offset_bytes); |
| 1018 | break; |
| 1019 | case AMDGPU_UCODE_ID_UMSCH_MM_DATA: |
| 1020 | ucode->ucode_size = le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_size_bytes); |
| 1021 | ucode_addr = (u8 *)ucode->fw->data + |
| 1022 | le32_to_cpu(umsch_mm_hdr->umsch_mm_ucode_data_offset_bytes); |
| 1023 | break; |
| 1024 | default: |
| 1025 | ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); |
| 1026 | ucode_addr = (u8 *)ucode->fw->data + |
| 1027 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 1028 | break; |
| 1029 | } |
| 1030 | } else { |
| 1031 | ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); |
| 1032 | ucode_addr = (u8 *)ucode->fw->data + |
| 1033 | le32_to_cpu(header->ucode_array_offset_bytes); |
| 1034 | } |
| 1035 | |
| 1036 | memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size); |
| 1037 | |
| 1038 | return 0; |
| 1039 | } |
| 1040 | |
| 1041 | static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, |
| 1042 | uint64_t mc_addr, void *kptr) |
| 1043 | { |
| 1044 | const struct gfx_firmware_header_v1_0 *header = NULL; |
| 1045 | const struct common_firmware_header *comm_hdr = NULL; |
| 1046 | uint8_t *src_addr = NULL; |
| 1047 | uint8_t *dst_addr = NULL; |
| 1048 | |
| 1049 | if (!ucode->fw) |
| 1050 | return 0; |
| 1051 | |
| 1052 | comm_hdr = (const struct common_firmware_header *)ucode->fw->data; |
| 1053 | header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; |
| 1054 | dst_addr = ucode->kaddr + |
| 1055 | ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), |
| 1056 | PAGE_SIZE); |
| 1057 | src_addr = (uint8_t *)ucode->fw->data + |
| 1058 | le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + |
| 1059 | (le32_to_cpu(header->jt_offset) * 4); |
| 1060 | memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); |
| 1061 | |
| 1062 | return 0; |
| 1063 | } |
| 1064 | |
| 1065 | int amdgpu_ucode_create_bo(struct amdgpu_device *adev) |
| 1066 | { |
| 1067 | if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) && |
| 1068 | (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) { |
| 1069 | amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, |
| 1070 | (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? |
| 1071 | AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, |
| 1072 | &adev->firmware.fw_buf, |
| 1073 | &adev->firmware.fw_buf_mc, |
| 1074 | &adev->firmware.fw_buf_ptr); |
| 1075 | if (!adev->firmware.fw_buf) { |
| 1076 | dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); |
| 1077 | return -ENOMEM; |
| 1078 | } else if (amdgpu_sriov_vf(adev)) { |
| 1079 | memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); |
| 1080 | } |
| 1081 | } |
| 1082 | return 0; |
| 1083 | } |
| 1084 | |
| 1085 | void amdgpu_ucode_free_bo(struct amdgpu_device *adev) |
| 1086 | { |
| 1087 | amdgpu_bo_free_kernel(&adev->firmware.fw_buf, |
| 1088 | &adev->firmware.fw_buf_mc, |
| 1089 | &adev->firmware.fw_buf_ptr); |
| 1090 | } |
| 1091 | |
| 1092 | int amdgpu_ucode_init_bo(struct amdgpu_device *adev) |
| 1093 | { |
| 1094 | uint64_t fw_offset = 0; |
| 1095 | int i; |
| 1096 | struct amdgpu_firmware_info *ucode = NULL; |
| 1097 | |
| 1098 | /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ |
| 1099 | if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend)) |
| 1100 | return 0; |
| 1101 | /* |
| 1102 | * if SMU loaded firmware, it needn't add SMC, UVD, and VCE |
| 1103 | * ucode info here |
| 1104 | */ |
| 1105 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 1106 | if (amdgpu_sriov_vf(adev)) |
| 1107 | adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; |
| 1108 | else |
| 1109 | adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; |
| 1110 | } else { |
| 1111 | adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; |
| 1112 | } |
| 1113 | |
| 1114 | for (i = 0; i < adev->firmware.max_ucodes; i++) { |
| 1115 | ucode = &adev->firmware.ucode[i]; |
| 1116 | if (ucode->fw) { |
| 1117 | amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, |
| 1118 | adev->firmware.fw_buf_ptr + fw_offset); |
| 1119 | if (i == AMDGPU_UCODE_ID_CP_MEC1 && |
| 1120 | adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 1121 | const struct gfx_firmware_header_v1_0 *cp_hdr; |
| 1122 | |
| 1123 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; |
| 1124 | amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, |
| 1125 | adev->firmware.fw_buf_ptr + fw_offset); |
| 1126 | fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); |
| 1127 | } |
| 1128 | fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); |
| 1129 | } |
| 1130 | } |
| 1131 | return 0; |
| 1132 | } |
| 1133 | |
| 1134 | static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type) |
| 1135 | { |
| 1136 | if (block_type == MP0_HWIP) { |
| 1137 | switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { |
| 1138 | case IP_VERSION(9, 0, 0): |
| 1139 | switch (adev->asic_type) { |
| 1140 | case CHIP_VEGA10: |
| 1141 | return "vega10"; |
| 1142 | case CHIP_VEGA12: |
| 1143 | return "vega12"; |
| 1144 | default: |
| 1145 | return NULL; |
| 1146 | } |
| 1147 | case IP_VERSION(10, 0, 0): |
| 1148 | case IP_VERSION(10, 0, 1): |
| 1149 | if (adev->asic_type == CHIP_RAVEN) { |
| 1150 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
| 1151 | return "raven2"; |
| 1152 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
| 1153 | return "picasso"; |
| 1154 | return "raven"; |
| 1155 | } |
| 1156 | break; |
| 1157 | case IP_VERSION(11, 0, 0): |
| 1158 | return "navi10"; |
| 1159 | case IP_VERSION(11, 0, 2): |
| 1160 | return "vega20"; |
| 1161 | case IP_VERSION(11, 0, 3): |
| 1162 | return "renoir"; |
| 1163 | case IP_VERSION(11, 0, 4): |
| 1164 | return "arcturus"; |
| 1165 | case IP_VERSION(11, 0, 5): |
| 1166 | return "navi14"; |
| 1167 | case IP_VERSION(11, 0, 7): |
| 1168 | return "sienna_cichlid"; |
| 1169 | case IP_VERSION(11, 0, 9): |
| 1170 | return "navi12"; |
| 1171 | case IP_VERSION(11, 0, 11): |
| 1172 | return "navy_flounder"; |
| 1173 | case IP_VERSION(11, 0, 12): |
| 1174 | return "dimgrey_cavefish"; |
| 1175 | case IP_VERSION(11, 0, 13): |
| 1176 | return "beige_goby"; |
| 1177 | case IP_VERSION(11, 5, 0): |
| 1178 | return "vangogh"; |
| 1179 | case IP_VERSION(12, 0, 1): |
| 1180 | return "green_sardine"; |
| 1181 | case IP_VERSION(13, 0, 2): |
| 1182 | return "aldebaran"; |
| 1183 | case IP_VERSION(13, 0, 1): |
| 1184 | case IP_VERSION(13, 0, 3): |
| 1185 | return "yellow_carp"; |
| 1186 | } |
| 1187 | } else if (block_type == MP1_HWIP) { |
| 1188 | switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { |
| 1189 | case IP_VERSION(9, 0, 0): |
| 1190 | case IP_VERSION(10, 0, 0): |
| 1191 | case IP_VERSION(10, 0, 1): |
| 1192 | case IP_VERSION(11, 0, 2): |
| 1193 | if (adev->asic_type == CHIP_ARCTURUS) |
| 1194 | return "arcturus_smc"; |
| 1195 | return NULL; |
| 1196 | case IP_VERSION(11, 0, 0): |
| 1197 | return "navi10_smc"; |
| 1198 | case IP_VERSION(11, 0, 5): |
| 1199 | return "navi14_smc"; |
| 1200 | case IP_VERSION(11, 0, 9): |
| 1201 | return "navi12_smc"; |
| 1202 | case IP_VERSION(11, 0, 7): |
| 1203 | return "sienna_cichlid_smc"; |
| 1204 | case IP_VERSION(11, 0, 11): |
| 1205 | return "navy_flounder_smc"; |
| 1206 | case IP_VERSION(11, 0, 12): |
| 1207 | return "dimgrey_cavefish_smc"; |
| 1208 | case IP_VERSION(11, 0, 13): |
| 1209 | return "beige_goby_smc"; |
| 1210 | case IP_VERSION(13, 0, 2): |
| 1211 | return "aldebaran_smc"; |
| 1212 | } |
| 1213 | } else if (block_type == SDMA0_HWIP) { |
| 1214 | switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { |
| 1215 | case IP_VERSION(4, 0, 0): |
| 1216 | return "vega10_sdma"; |
| 1217 | case IP_VERSION(4, 0, 1): |
| 1218 | return "vega12_sdma"; |
| 1219 | case IP_VERSION(4, 1, 0): |
| 1220 | case IP_VERSION(4, 1, 1): |
| 1221 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
| 1222 | return "raven2_sdma"; |
| 1223 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
| 1224 | return "picasso_sdma"; |
| 1225 | return "raven_sdma"; |
| 1226 | case IP_VERSION(4, 1, 2): |
| 1227 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
| 1228 | return "renoir_sdma"; |
| 1229 | return "green_sardine_sdma"; |
| 1230 | case IP_VERSION(4, 2, 0): |
| 1231 | return "vega20_sdma"; |
| 1232 | case IP_VERSION(4, 2, 2): |
| 1233 | return "arcturus_sdma"; |
| 1234 | case IP_VERSION(4, 4, 0): |
| 1235 | return "aldebaran_sdma"; |
| 1236 | case IP_VERSION(5, 0, 0): |
| 1237 | return "navi10_sdma"; |
| 1238 | case IP_VERSION(5, 0, 1): |
| 1239 | return "cyan_skillfish2_sdma"; |
| 1240 | case IP_VERSION(5, 0, 2): |
| 1241 | return "navi14_sdma"; |
| 1242 | case IP_VERSION(5, 0, 5): |
| 1243 | return "navi12_sdma"; |
| 1244 | case IP_VERSION(5, 2, 0): |
| 1245 | return "sienna_cichlid_sdma"; |
| 1246 | case IP_VERSION(5, 2, 2): |
| 1247 | return "navy_flounder_sdma"; |
| 1248 | case IP_VERSION(5, 2, 4): |
| 1249 | return "dimgrey_cavefish_sdma"; |
| 1250 | case IP_VERSION(5, 2, 5): |
| 1251 | return "beige_goby_sdma"; |
| 1252 | case IP_VERSION(5, 2, 3): |
| 1253 | return "yellow_carp_sdma"; |
| 1254 | case IP_VERSION(5, 2, 1): |
| 1255 | return "vangogh_sdma"; |
| 1256 | } |
| 1257 | } else if (block_type == UVD_HWIP) { |
| 1258 | switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { |
| 1259 | case IP_VERSION(1, 0, 0): |
| 1260 | case IP_VERSION(1, 0, 1): |
| 1261 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
| 1262 | return "raven2_vcn"; |
| 1263 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
| 1264 | return "picasso_vcn"; |
| 1265 | return "raven_vcn"; |
| 1266 | case IP_VERSION(2, 5, 0): |
| 1267 | return "arcturus_vcn"; |
| 1268 | case IP_VERSION(2, 2, 0): |
| 1269 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
| 1270 | return "renoir_vcn"; |
| 1271 | return "green_sardine_vcn"; |
| 1272 | case IP_VERSION(2, 6, 0): |
| 1273 | return "aldebaran_vcn"; |
| 1274 | case IP_VERSION(2, 0, 0): |
| 1275 | return "navi10_vcn"; |
| 1276 | case IP_VERSION(2, 0, 2): |
| 1277 | if (adev->asic_type == CHIP_NAVI12) |
| 1278 | return "navi12_vcn"; |
| 1279 | return "navi14_vcn"; |
| 1280 | case IP_VERSION(3, 0, 0): |
| 1281 | case IP_VERSION(3, 0, 64): |
| 1282 | case IP_VERSION(3, 0, 192): |
| 1283 | if (amdgpu_ip_version(adev, GC_HWIP, 0) == |
| 1284 | IP_VERSION(10, 3, 0)) |
| 1285 | return "sienna_cichlid_vcn"; |
| 1286 | return "navy_flounder_vcn"; |
| 1287 | case IP_VERSION(3, 0, 2): |
| 1288 | return "vangogh_vcn"; |
| 1289 | case IP_VERSION(3, 0, 16): |
| 1290 | return "dimgrey_cavefish_vcn"; |
| 1291 | case IP_VERSION(3, 0, 33): |
| 1292 | return "beige_goby_vcn"; |
| 1293 | case IP_VERSION(3, 1, 1): |
| 1294 | return "yellow_carp_vcn"; |
| 1295 | } |
| 1296 | } else if (block_type == GC_HWIP) { |
| 1297 | switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { |
| 1298 | case IP_VERSION(9, 0, 1): |
| 1299 | return "vega10"; |
| 1300 | case IP_VERSION(9, 2, 1): |
| 1301 | return "vega12"; |
| 1302 | case IP_VERSION(9, 4, 0): |
| 1303 | return "vega20"; |
| 1304 | case IP_VERSION(9, 2, 2): |
| 1305 | case IP_VERSION(9, 1, 0): |
| 1306 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
| 1307 | return "raven2"; |
| 1308 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
| 1309 | return "picasso"; |
| 1310 | return "raven"; |
| 1311 | case IP_VERSION(9, 4, 1): |
| 1312 | return "arcturus"; |
| 1313 | case IP_VERSION(9, 3, 0): |
| 1314 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
| 1315 | return "renoir"; |
| 1316 | return "green_sardine"; |
| 1317 | case IP_VERSION(9, 4, 2): |
| 1318 | return "aldebaran"; |
| 1319 | case IP_VERSION(10, 1, 10): |
| 1320 | return "navi10"; |
| 1321 | case IP_VERSION(10, 1, 1): |
| 1322 | return "navi14"; |
| 1323 | case IP_VERSION(10, 1, 2): |
| 1324 | return "navi12"; |
| 1325 | case IP_VERSION(10, 3, 0): |
| 1326 | return "sienna_cichlid"; |
| 1327 | case IP_VERSION(10, 3, 2): |
| 1328 | return "navy_flounder"; |
| 1329 | case IP_VERSION(10, 3, 1): |
| 1330 | return "vangogh"; |
| 1331 | case IP_VERSION(10, 3, 4): |
| 1332 | return "dimgrey_cavefish"; |
| 1333 | case IP_VERSION(10, 3, 5): |
| 1334 | return "beige_goby"; |
| 1335 | case IP_VERSION(10, 3, 3): |
| 1336 | return "yellow_carp"; |
| 1337 | case IP_VERSION(10, 1, 3): |
| 1338 | case IP_VERSION(10, 1, 4): |
| 1339 | return "cyan_skillfish2"; |
| 1340 | } |
| 1341 | } |
| 1342 | return NULL; |
| 1343 | } |
| 1344 | |
| 1345 | void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) |
| 1346 | { |
| 1347 | int maj, min, rev; |
| 1348 | char *ip_name; |
| 1349 | const char *legacy; |
| 1350 | uint32_t version = amdgpu_ip_version(adev, block_type, 0); |
| 1351 | |
| 1352 | legacy = amdgpu_ucode_legacy_naming(adev, block_type); |
| 1353 | if (legacy) { |
| 1354 | snprintf(ucode_prefix, len, "%s", legacy); |
| 1355 | return; |
| 1356 | } |
| 1357 | |
| 1358 | switch (block_type) { |
| 1359 | case GC_HWIP: |
| 1360 | ip_name = "gc"; |
| 1361 | break; |
| 1362 | case SDMA0_HWIP: |
| 1363 | ip_name = "sdma"; |
| 1364 | break; |
| 1365 | case MP0_HWIP: |
| 1366 | ip_name = "psp"; |
| 1367 | break; |
| 1368 | case MP1_HWIP: |
| 1369 | ip_name = "smu"; |
| 1370 | break; |
| 1371 | case UVD_HWIP: |
| 1372 | ip_name = "vcn"; |
| 1373 | break; |
| 1374 | case VPE_HWIP: |
| 1375 | ip_name = "vpe"; |
| 1376 | break; |
| 1377 | default: |
| 1378 | BUG(); |
| 1379 | } |
| 1380 | |
| 1381 | maj = IP_VERSION_MAJ(version); |
| 1382 | min = IP_VERSION_MIN(version); |
| 1383 | rev = IP_VERSION_REV(version); |
| 1384 | |
| 1385 | snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); |
| 1386 | } |
| 1387 | |
| 1388 | /* |
| 1389 | * amdgpu_ucode_request - Fetch and validate amdgpu microcode |
| 1390 | * |
| 1391 | * @adev: amdgpu device |
| 1392 | * @fw: pointer to load firmware to |
| 1393 | * @fw_name: firmware to load |
| 1394 | * |
| 1395 | * This is a helper that will use request_firmware and amdgpu_ucode_validate |
| 1396 | * to load and run basic validation on firmware. If the load fails, remap |
| 1397 | * the error code to -ENODEV, so that early_init functions will fail to load. |
| 1398 | */ |
| 1399 | int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, |
| 1400 | const char *fw_name) |
| 1401 | { |
| 1402 | int err = request_firmware(fw, fw_name, adev->dev); |
| 1403 | |
| 1404 | if (err) |
| 1405 | return -ENODEV; |
| 1406 | |
| 1407 | err = amdgpu_ucode_validate(*fw); |
| 1408 | if (err) { |
| 1409 | dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name); |
| 1410 | release_firmware(*fw); |
| 1411 | *fw = NULL; |
| 1412 | } |
| 1413 | |
| 1414 | return err; |
| 1415 | } |
| 1416 | |
| 1417 | /* |
| 1418 | * amdgpu_ucode_release - Release firmware microcode |
| 1419 | * |
| 1420 | * @fw: pointer to firmware to release |
| 1421 | */ |
| 1422 | void amdgpu_ucode_release(const struct firmware **fw) |
| 1423 | { |
| 1424 | release_firmware(*fw); |
| 1425 | *fw = NULL; |
| 1426 | } |