| 1 | /* |
| 2 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include <drm/amdgpu_drm.h> |
| 26 | #include <drm/drm_drv.h> |
| 27 | #include <drm/drm_gem.h> |
| 28 | #include <drm/drm_vblank.h> |
| 29 | #include <drm/drm_managed.h> |
| 30 | #include "amdgpu_drv.h" |
| 31 | |
| 32 | #include <drm/drm_pciids.h> |
| 33 | #include <linux/console.h> |
| 34 | #include <linux/module.h> |
| 35 | #include <linux/pm_runtime.h> |
| 36 | #include <linux/vga_switcheroo.h> |
| 37 | #include <drm/drm_probe_helper.h> |
| 38 | #include <linux/mmu_notifier.h> |
| 39 | |
| 40 | #include "amdgpu.h" |
| 41 | #include "amdgpu_irq.h" |
| 42 | #include "amdgpu_dma_buf.h" |
| 43 | |
| 44 | #include "amdgpu_amdkfd.h" |
| 45 | |
| 46 | #include "amdgpu_ras.h" |
| 47 | |
| 48 | /* |
| 49 | * KMS wrapper. |
| 50 | * - 3.0.0 - initial driver |
| 51 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
| 52 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same |
| 53 | * at the end of IBs. |
| 54 | * - 3.3.0 - Add VM support for UVD on supported hardware. |
| 55 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. |
| 56 | * - 3.5.0 - Add support for new UVD_NO_OP register. |
| 57 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. |
| 58 | * - 3.7.0 - Add support for VCE clock list packet |
| 59 | * - 3.8.0 - Add support raster config init in the kernel |
| 60 | * - 3.9.0 - Add support for memory query info about VRAM and GTT. |
| 61 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags |
| 62 | * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). |
| 63 | * - 3.12.0 - Add query for double offchip LDS buffers |
| 64 | * - 3.13.0 - Add PRT support |
| 65 | * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality |
| 66 | * - 3.15.0 - Export more gpu info for gfx9 |
| 67 | * - 3.16.0 - Add reserved vmid support |
| 68 | * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. |
| 69 | * - 3.18.0 - Export gpu always on cu bitmap |
| 70 | * - 3.19.0 - Add support for UVD MJPEG decode |
| 71 | * - 3.20.0 - Add support for local BOs |
| 72 | * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl |
| 73 | * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl |
| 74 | * - 3.23.0 - Add query for VRAM lost counter |
| 75 | * - 3.24.0 - Add high priority compute support for gfx9 |
| 76 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). |
| 77 | * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. |
| 78 | * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. |
| 79 | * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES |
| 80 | * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID |
| 81 | * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. |
| 82 | * - 3.31.0 - Add support for per-flip tiling attribute changes with DC |
| 83 | * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. |
| 84 | * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. |
| 85 | * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches |
| 86 | * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask |
| 87 | * - 3.36.0 - Allow reading more status registers on si/cik |
| 88 | * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness |
| 89 | * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC |
| 90 | * - 3.39.0 - DMABUF implicit sync does a full pipeline sync |
| 91 | * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ |
| 92 | */ |
| 93 | #define KMS_DRIVER_MAJOR 3 |
| 94 | #define KMS_DRIVER_MINOR 40 |
| 95 | #define KMS_DRIVER_PATCHLEVEL 0 |
| 96 | |
| 97 | int amdgpu_vram_limit = 0; |
| 98 | int amdgpu_vis_vram_limit = 0; |
| 99 | int amdgpu_gart_size = -1; /* auto */ |
| 100 | int amdgpu_gtt_size = -1; /* auto */ |
| 101 | int amdgpu_moverate = -1; /* auto */ |
| 102 | int amdgpu_benchmarking = 0; |
| 103 | int amdgpu_testing = 0; |
| 104 | int amdgpu_audio = -1; |
| 105 | int amdgpu_disp_priority = 0; |
| 106 | int amdgpu_hw_i2c = 0; |
| 107 | int amdgpu_pcie_gen2 = -1; |
| 108 | int amdgpu_msi = -1; |
| 109 | char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; |
| 110 | int amdgpu_dpm = -1; |
| 111 | int amdgpu_fw_load_type = -1; |
| 112 | int amdgpu_aspm = -1; |
| 113 | int amdgpu_runtime_pm = -1; |
| 114 | uint amdgpu_ip_block_mask = 0xffffffff; |
| 115 | int amdgpu_bapm = -1; |
| 116 | int amdgpu_deep_color = 0; |
| 117 | int amdgpu_vm_size = -1; |
| 118 | int amdgpu_vm_fragment_size = -1; |
| 119 | int amdgpu_vm_block_size = -1; |
| 120 | int amdgpu_vm_fault_stop = 0; |
| 121 | int amdgpu_vm_debug = 0; |
| 122 | int amdgpu_vm_update_mode = -1; |
| 123 | int amdgpu_exp_hw_support = 0; |
| 124 | int amdgpu_dc = -1; |
| 125 | int amdgpu_sched_jobs = 32; |
| 126 | int amdgpu_sched_hw_submission = 2; |
| 127 | uint amdgpu_pcie_gen_cap = 0; |
| 128 | uint amdgpu_pcie_lane_cap = 0; |
| 129 | uint amdgpu_cg_mask = 0xffffffff; |
| 130 | uint amdgpu_pg_mask = 0xffffffff; |
| 131 | uint amdgpu_sdma_phase_quantum = 32; |
| 132 | char *amdgpu_disable_cu = NULL; |
| 133 | char *amdgpu_virtual_display = NULL; |
| 134 | /* OverDrive(bit 14) disabled by default*/ |
| 135 | uint amdgpu_pp_feature_mask = 0xffffbfff; |
| 136 | uint amdgpu_force_long_training = 0; |
| 137 | int amdgpu_job_hang_limit = 0; |
| 138 | int amdgpu_lbpw = -1; |
| 139 | int amdgpu_compute_multipipe = -1; |
| 140 | int amdgpu_gpu_recovery = -1; /* auto */ |
| 141 | int amdgpu_emu_mode = 0; |
| 142 | uint amdgpu_smu_memory_pool_size = 0; |
| 143 | /* FBC (bit 0) disabled by default*/ |
| 144 | uint amdgpu_dc_feature_mask = 0; |
| 145 | uint amdgpu_dc_debug_mask = 0; |
| 146 | int amdgpu_async_gfx_ring = 1; |
| 147 | int amdgpu_mcbp = 0; |
| 148 | int amdgpu_discovery = -1; |
| 149 | int amdgpu_mes = 0; |
| 150 | int amdgpu_noretry = -1; |
| 151 | int amdgpu_force_asic_type = -1; |
| 152 | int amdgpu_tmz = 0; |
| 153 | int amdgpu_reset_method = -1; /* auto */ |
| 154 | int amdgpu_num_kcq = -1; |
| 155 | |
| 156 | struct amdgpu_mgpu_info mgpu_info = { |
| 157 | .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), |
| 158 | }; |
| 159 | int amdgpu_ras_enable = -1; |
| 160 | uint amdgpu_ras_mask = 0xffffffff; |
| 161 | int amdgpu_bad_page_threshold = -1; |
| 162 | |
| 163 | /** |
| 164 | * DOC: vramlimit (int) |
| 165 | * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). |
| 166 | */ |
| 167 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); |
| 168 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); |
| 169 | |
| 170 | /** |
| 171 | * DOC: vis_vramlimit (int) |
| 172 | * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). |
| 173 | */ |
| 174 | MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); |
| 175 | module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); |
| 176 | |
| 177 | /** |
| 178 | * DOC: gartsize (uint) |
| 179 | * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). |
| 180 | */ |
| 181 | MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); |
| 182 | module_param_named(gartsize, amdgpu_gart_size, uint, 0600); |
| 183 | |
| 184 | /** |
| 185 | * DOC: gttsize (int) |
| 186 | * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, |
| 187 | * otherwise 3/4 RAM size). |
| 188 | */ |
| 189 | MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); |
| 190 | module_param_named(gttsize, amdgpu_gtt_size, int, 0600); |
| 191 | |
| 192 | /** |
| 193 | * DOC: moverate (int) |
| 194 | * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). |
| 195 | */ |
| 196 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); |
| 197 | module_param_named(moverate, amdgpu_moverate, int, 0600); |
| 198 | |
| 199 | /** |
| 200 | * DOC: benchmark (int) |
| 201 | * Run benchmarks. The default is 0 (Skip benchmarks). |
| 202 | */ |
| 203 | MODULE_PARM_DESC(benchmark, "Run benchmark"); |
| 204 | module_param_named(benchmark, amdgpu_benchmarking, int, 0444); |
| 205 | |
| 206 | /** |
| 207 | * DOC: test (int) |
| 208 | * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). |
| 209 | */ |
| 210 | MODULE_PARM_DESC(test, "Run tests"); |
| 211 | module_param_named(test, amdgpu_testing, int, 0444); |
| 212 | |
| 213 | /** |
| 214 | * DOC: audio (int) |
| 215 | * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. |
| 216 | */ |
| 217 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); |
| 218 | module_param_named(audio, amdgpu_audio, int, 0444); |
| 219 | |
| 220 | /** |
| 221 | * DOC: disp_priority (int) |
| 222 | * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). |
| 223 | */ |
| 224 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
| 225 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); |
| 226 | |
| 227 | /** |
| 228 | * DOC: hw_i2c (int) |
| 229 | * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). |
| 230 | */ |
| 231 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
| 232 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); |
| 233 | |
| 234 | /** |
| 235 | * DOC: pcie_gen2 (int) |
| 236 | * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). |
| 237 | */ |
| 238 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
| 239 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); |
| 240 | |
| 241 | /** |
| 242 | * DOC: msi (int) |
| 243 | * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). |
| 244 | */ |
| 245 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
| 246 | module_param_named(msi, amdgpu_msi, int, 0444); |
| 247 | |
| 248 | /** |
| 249 | * DOC: lockup_timeout (string) |
| 250 | * Set GPU scheduler timeout value in ms. |
| 251 | * |
| 252 | * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or |
| 253 | * multiple values specified. 0 and negative values are invalidated. They will be adjusted |
| 254 | * to the default timeout. |
| 255 | * |
| 256 | * - With one value specified, the setting will apply to all non-compute jobs. |
| 257 | * - With multiple values specified, the first one will be for GFX. |
| 258 | * The second one is for Compute. The third and fourth ones are |
| 259 | * for SDMA and Video. |
| 260 | * |
| 261 | * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) |
| 262 | * jobs is 10000. And there is no timeout enforced on compute jobs. |
| 263 | */ |
| 264 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " |
| 265 | "for passthrough or sriov, 10000 for all jobs." |
| 266 | " 0: keep default value. negative: infinity timeout), " |
| 267 | "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " |
| 268 | "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); |
| 269 | module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); |
| 270 | |
| 271 | /** |
| 272 | * DOC: dpm (int) |
| 273 | * Override for dynamic power management setting |
| 274 | * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) |
| 275 | * The default is -1 (auto). |
| 276 | */ |
| 277 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); |
| 278 | module_param_named(dpm, amdgpu_dpm, int, 0444); |
| 279 | |
| 280 | /** |
| 281 | * DOC: fw_load_type (int) |
| 282 | * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). |
| 283 | */ |
| 284 | MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); |
| 285 | module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); |
| 286 | |
| 287 | /** |
| 288 | * DOC: aspm (int) |
| 289 | * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). |
| 290 | */ |
| 291 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); |
| 292 | module_param_named(aspm, amdgpu_aspm, int, 0444); |
| 293 | |
| 294 | /** |
| 295 | * DOC: runpm (int) |
| 296 | * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down |
| 297 | * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. |
| 298 | */ |
| 299 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); |
| 300 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); |
| 301 | |
| 302 | /** |
| 303 | * DOC: ip_block_mask (uint) |
| 304 | * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). |
| 305 | * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have |
| 306 | * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in |
| 307 | * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). |
| 308 | */ |
| 309 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); |
| 310 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); |
| 311 | |
| 312 | /** |
| 313 | * DOC: bapm (int) |
| 314 | * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. |
| 315 | * The default -1 (auto, enabled) |
| 316 | */ |
| 317 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); |
| 318 | module_param_named(bapm, amdgpu_bapm, int, 0444); |
| 319 | |
| 320 | /** |
| 321 | * DOC: deep_color (int) |
| 322 | * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). |
| 323 | */ |
| 324 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); |
| 325 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); |
| 326 | |
| 327 | /** |
| 328 | * DOC: vm_size (int) |
| 329 | * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). |
| 330 | */ |
| 331 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
| 332 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
| 333 | |
| 334 | /** |
| 335 | * DOC: vm_fragment_size (int) |
| 336 | * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). |
| 337 | */ |
| 338 | MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); |
| 339 | module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); |
| 340 | |
| 341 | /** |
| 342 | * DOC: vm_block_size (int) |
| 343 | * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). |
| 344 | */ |
| 345 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); |
| 346 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); |
| 347 | |
| 348 | /** |
| 349 | * DOC: vm_fault_stop (int) |
| 350 | * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). |
| 351 | */ |
| 352 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
| 353 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); |
| 354 | |
| 355 | /** |
| 356 | * DOC: vm_debug (int) |
| 357 | * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). |
| 358 | */ |
| 359 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
| 360 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); |
| 361 | |
| 362 | /** |
| 363 | * DOC: vm_update_mode (int) |
| 364 | * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default |
| 365 | * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). |
| 366 | */ |
| 367 | MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); |
| 368 | module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); |
| 369 | |
| 370 | /** |
| 371 | * DOC: exp_hw_support (int) |
| 372 | * Enable experimental hw support (1 = enable). The default is 0 (disabled). |
| 373 | */ |
| 374 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
| 375 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); |
| 376 | |
| 377 | /** |
| 378 | * DOC: dc (int) |
| 379 | * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). |
| 380 | */ |
| 381 | MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); |
| 382 | module_param_named(dc, amdgpu_dc, int, 0444); |
| 383 | |
| 384 | /** |
| 385 | * DOC: sched_jobs (int) |
| 386 | * Override the max number of jobs supported in the sw queue. The default is 32. |
| 387 | */ |
| 388 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
| 389 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
| 390 | |
| 391 | /** |
| 392 | * DOC: sched_hw_submission (int) |
| 393 | * Override the max number of HW submissions. The default is 2. |
| 394 | */ |
| 395 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
| 396 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); |
| 397 | |
| 398 | /** |
| 399 | * DOC: ppfeaturemask (hexint) |
| 400 | * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. |
| 401 | * The default is the current set of stable power features. |
| 402 | */ |
| 403 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); |
| 404 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); |
| 405 | |
| 406 | /** |
| 407 | * DOC: forcelongtraining (uint) |
| 408 | * Force long memory training in resume. |
| 409 | * The default is zero, indicates short training in resume. |
| 410 | */ |
| 411 | MODULE_PARM_DESC(forcelongtraining, "force memory long training"); |
| 412 | module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); |
| 413 | |
| 414 | /** |
| 415 | * DOC: pcie_gen_cap (uint) |
| 416 | * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. |
| 417 | * The default is 0 (automatic for each asic). |
| 418 | */ |
| 419 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
| 420 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); |
| 421 | |
| 422 | /** |
| 423 | * DOC: pcie_lane_cap (uint) |
| 424 | * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. |
| 425 | * The default is 0 (automatic for each asic). |
| 426 | */ |
| 427 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); |
| 428 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); |
| 429 | |
| 430 | /** |
| 431 | * DOC: cg_mask (uint) |
| 432 | * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in |
| 433 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). |
| 434 | */ |
| 435 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); |
| 436 | module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); |
| 437 | |
| 438 | /** |
| 439 | * DOC: pg_mask (uint) |
| 440 | * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in |
| 441 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). |
| 442 | */ |
| 443 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); |
| 444 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); |
| 445 | |
| 446 | /** |
| 447 | * DOC: sdma_phase_quantum (uint) |
| 448 | * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. |
| 449 | */ |
| 450 | MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); |
| 451 | module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); |
| 452 | |
| 453 | /** |
| 454 | * DOC: disable_cu (charp) |
| 455 | * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. |
| 456 | */ |
| 457 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); |
| 458 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); |
| 459 | |
| 460 | /** |
| 461 | * DOC: virtual_display (charp) |
| 462 | * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards |
| 463 | * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of |
| 464 | * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci |
| 465 | * device at 26:00.0. The default is NULL. |
| 466 | */ |
| 467 | MODULE_PARM_DESC(virtual_display, |
| 468 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); |
| 469 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); |
| 470 | |
| 471 | /** |
| 472 | * DOC: job_hang_limit (int) |
| 473 | * Set how much time allow a job hang and not drop it. The default is 0. |
| 474 | */ |
| 475 | MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); |
| 476 | module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); |
| 477 | |
| 478 | /** |
| 479 | * DOC: lbpw (int) |
| 480 | * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). |
| 481 | */ |
| 482 | MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); |
| 483 | module_param_named(lbpw, amdgpu_lbpw, int, 0444); |
| 484 | |
| 485 | MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); |
| 486 | module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); |
| 487 | |
| 488 | /** |
| 489 | * DOC: gpu_recovery (int) |
| 490 | * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). |
| 491 | */ |
| 492 | MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); |
| 493 | module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); |
| 494 | |
| 495 | /** |
| 496 | * DOC: emu_mode (int) |
| 497 | * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). |
| 498 | */ |
| 499 | MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); |
| 500 | module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); |
| 501 | |
| 502 | /** |
| 503 | * DOC: ras_enable (int) |
| 504 | * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) |
| 505 | */ |
| 506 | MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); |
| 507 | module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); |
| 508 | |
| 509 | /** |
| 510 | * DOC: ras_mask (uint) |
| 511 | * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 |
| 512 | * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |
| 513 | */ |
| 514 | MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); |
| 515 | module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); |
| 516 | |
| 517 | /** |
| 518 | * DOC: si_support (int) |
| 519 | * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, |
| 520 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, |
| 521 | * otherwise using amdgpu driver. |
| 522 | */ |
| 523 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 524 | |
| 525 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) |
| 526 | int amdgpu_si_support = 0; |
| 527 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); |
| 528 | #else |
| 529 | int amdgpu_si_support = 1; |
| 530 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); |
| 531 | #endif |
| 532 | |
| 533 | module_param_named(si_support, amdgpu_si_support, int, 0444); |
| 534 | #endif |
| 535 | |
| 536 | /** |
| 537 | * DOC: cik_support (int) |
| 538 | * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, |
| 539 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, |
| 540 | * otherwise using amdgpu driver. |
| 541 | */ |
| 542 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 543 | |
| 544 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) |
| 545 | int amdgpu_cik_support = 0; |
| 546 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); |
| 547 | #else |
| 548 | int amdgpu_cik_support = 1; |
| 549 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); |
| 550 | #endif |
| 551 | |
| 552 | module_param_named(cik_support, amdgpu_cik_support, int, 0444); |
| 553 | #endif |
| 554 | |
| 555 | /** |
| 556 | * DOC: smu_memory_pool_size (uint) |
| 557 | * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. |
| 558 | * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). |
| 559 | */ |
| 560 | MODULE_PARM_DESC(smu_memory_pool_size, |
| 561 | "reserve gtt for smu debug usage, 0 = disable," |
| 562 | "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); |
| 563 | module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); |
| 564 | |
| 565 | /** |
| 566 | * DOC: async_gfx_ring (int) |
| 567 | * It is used to enable gfx rings that could be configured with different prioritites or equal priorities |
| 568 | */ |
| 569 | MODULE_PARM_DESC(async_gfx_ring, |
| 570 | "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); |
| 571 | module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); |
| 572 | |
| 573 | /** |
| 574 | * DOC: mcbp (int) |
| 575 | * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) |
| 576 | */ |
| 577 | MODULE_PARM_DESC(mcbp, |
| 578 | "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); |
| 579 | module_param_named(mcbp, amdgpu_mcbp, int, 0444); |
| 580 | |
| 581 | /** |
| 582 | * DOC: discovery (int) |
| 583 | * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. |
| 584 | * (-1 = auto (default), 0 = disabled, 1 = enabled) |
| 585 | */ |
| 586 | MODULE_PARM_DESC(discovery, |
| 587 | "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); |
| 588 | module_param_named(discovery, amdgpu_discovery, int, 0444); |
| 589 | |
| 590 | /** |
| 591 | * DOC: mes (int) |
| 592 | * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. |
| 593 | * (0 = disabled (default), 1 = enabled) |
| 594 | */ |
| 595 | MODULE_PARM_DESC(mes, |
| 596 | "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); |
| 597 | module_param_named(mes, amdgpu_mes, int, 0444); |
| 598 | |
| 599 | /** |
| 600 | * DOC: noretry (int) |
| 601 | * Disable retry faults in the GPU memory controller. |
| 602 | * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) |
| 603 | */ |
| 604 | MODULE_PARM_DESC(noretry, |
| 605 | "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); |
| 606 | module_param_named(noretry, amdgpu_noretry, int, 0644); |
| 607 | |
| 608 | /** |
| 609 | * DOC: force_asic_type (int) |
| 610 | * A non negative value used to specify the asic type for all supported GPUs. |
| 611 | */ |
| 612 | MODULE_PARM_DESC(force_asic_type, |
| 613 | "A non negative value used to specify the asic type for all supported GPUs"); |
| 614 | module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); |
| 615 | |
| 616 | |
| 617 | |
| 618 | #ifdef CONFIG_HSA_AMD |
| 619 | /** |
| 620 | * DOC: sched_policy (int) |
| 621 | * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. |
| 622 | * Setting 1 disables over-subscription. Setting 2 disables HWS and statically |
| 623 | * assigns queues to HQDs. |
| 624 | */ |
| 625 | int sched_policy = KFD_SCHED_POLICY_HWS; |
| 626 | module_param(sched_policy, int, 0444); |
| 627 | MODULE_PARM_DESC(sched_policy, |
| 628 | "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); |
| 629 | |
| 630 | /** |
| 631 | * DOC: hws_max_conc_proc (int) |
| 632 | * Maximum number of processes that HWS can schedule concurrently. The maximum is the |
| 633 | * number of VMIDs assigned to the HWS, which is also the default. |
| 634 | */ |
| 635 | int hws_max_conc_proc = 8; |
| 636 | module_param(hws_max_conc_proc, int, 0444); |
| 637 | MODULE_PARM_DESC(hws_max_conc_proc, |
| 638 | "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); |
| 639 | |
| 640 | /** |
| 641 | * DOC: cwsr_enable (int) |
| 642 | * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in |
| 643 | * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 |
| 644 | * disables it. |
| 645 | */ |
| 646 | int cwsr_enable = 1; |
| 647 | module_param(cwsr_enable, int, 0444); |
| 648 | MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); |
| 649 | |
| 650 | /** |
| 651 | * DOC: max_num_of_queues_per_device (int) |
| 652 | * Maximum number of queues per device. Valid setting is between 1 and 4096. Default |
| 653 | * is 4096. |
| 654 | */ |
| 655 | int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; |
| 656 | module_param(max_num_of_queues_per_device, int, 0444); |
| 657 | MODULE_PARM_DESC(max_num_of_queues_per_device, |
| 658 | "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); |
| 659 | |
| 660 | /** |
| 661 | * DOC: send_sigterm (int) |
| 662 | * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm |
| 663 | * but just print errors on dmesg. Setting 1 enables sending sigterm. |
| 664 | */ |
| 665 | int send_sigterm; |
| 666 | module_param(send_sigterm, int, 0444); |
| 667 | MODULE_PARM_DESC(send_sigterm, |
| 668 | "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); |
| 669 | |
| 670 | /** |
| 671 | * DOC: debug_largebar (int) |
| 672 | * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar |
| 673 | * system. This limits the VRAM size reported to ROCm applications to the visible |
| 674 | * size, usually 256MB. |
| 675 | * Default value is 0, diabled. |
| 676 | */ |
| 677 | int debug_largebar; |
| 678 | module_param(debug_largebar, int, 0444); |
| 679 | MODULE_PARM_DESC(debug_largebar, |
| 680 | "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); |
| 681 | |
| 682 | /** |
| 683 | * DOC: ignore_crat (int) |
| 684 | * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT |
| 685 | * table to get information about AMD APUs. This option can serve as a workaround on |
| 686 | * systems with a broken CRAT table. |
| 687 | * |
| 688 | * Default is auto (according to asic type, iommu_v2, and crat table, to decide |
| 689 | * whehter use CRAT) |
| 690 | */ |
| 691 | int ignore_crat; |
| 692 | module_param(ignore_crat, int, 0444); |
| 693 | MODULE_PARM_DESC(ignore_crat, |
| 694 | "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); |
| 695 | |
| 696 | /** |
| 697 | * DOC: halt_if_hws_hang (int) |
| 698 | * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. |
| 699 | * Setting 1 enables halt on hang. |
| 700 | */ |
| 701 | int halt_if_hws_hang; |
| 702 | module_param(halt_if_hws_hang, int, 0644); |
| 703 | MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); |
| 704 | |
| 705 | /** |
| 706 | * DOC: hws_gws_support(bool) |
| 707 | * Assume that HWS supports GWS barriers regardless of what firmware version |
| 708 | * check says. Default value: false (rely on MEC2 firmware version check). |
| 709 | */ |
| 710 | bool hws_gws_support; |
| 711 | module_param(hws_gws_support, bool, 0444); |
| 712 | MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); |
| 713 | |
| 714 | /** |
| 715 | * DOC: queue_preemption_timeout_ms (int) |
| 716 | * queue preemption timeout in ms (1 = Minimum, 9000 = default) |
| 717 | */ |
| 718 | int queue_preemption_timeout_ms = 9000; |
| 719 | module_param(queue_preemption_timeout_ms, int, 0644); |
| 720 | MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); |
| 721 | |
| 722 | /** |
| 723 | * DOC: debug_evictions(bool) |
| 724 | * Enable extra debug messages to help determine the cause of evictions |
| 725 | */ |
| 726 | bool debug_evictions; |
| 727 | module_param(debug_evictions, bool, 0644); |
| 728 | MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); |
| 729 | |
| 730 | /** |
| 731 | * DOC: no_system_mem_limit(bool) |
| 732 | * Disable system memory limit, to support multiple process shared memory |
| 733 | */ |
| 734 | bool no_system_mem_limit; |
| 735 | module_param(no_system_mem_limit, bool, 0644); |
| 736 | MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); |
| 737 | |
| 738 | #endif |
| 739 | |
| 740 | /** |
| 741 | * DOC: dcfeaturemask (uint) |
| 742 | * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. |
| 743 | * The default is the current set of stable display features. |
| 744 | */ |
| 745 | MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); |
| 746 | module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); |
| 747 | |
| 748 | /** |
| 749 | * DOC: dcdebugmask (uint) |
| 750 | * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. |
| 751 | */ |
| 752 | MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); |
| 753 | module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); |
| 754 | |
| 755 | /** |
| 756 | * DOC: abmlevel (uint) |
| 757 | * Override the default ABM (Adaptive Backlight Management) level used for DC |
| 758 | * enabled hardware. Requires DMCU to be supported and loaded. |
| 759 | * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by |
| 760 | * default. Values 1-4 control the maximum allowable brightness reduction via |
| 761 | * the ABM algorithm, with 1 being the least reduction and 4 being the most |
| 762 | * reduction. |
| 763 | * |
| 764 | * Defaults to 0, or disabled. Userspace can still override this level later |
| 765 | * after boot. |
| 766 | */ |
| 767 | uint amdgpu_dm_abm_level = 0; |
| 768 | MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); |
| 769 | module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); |
| 770 | |
| 771 | /** |
| 772 | * DOC: tmz (int) |
| 773 | * Trusted Memory Zone (TMZ) is a method to protect data being written |
| 774 | * to or read from memory. |
| 775 | * |
| 776 | * The default value: 0 (off). TODO: change to auto till it is completed. |
| 777 | */ |
| 778 | MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); |
| 779 | module_param_named(tmz, amdgpu_tmz, int, 0444); |
| 780 | |
| 781 | /** |
| 782 | * DOC: reset_method (int) |
| 783 | * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) |
| 784 | */ |
| 785 | MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)"); |
| 786 | module_param_named(reset_method, amdgpu_reset_method, int, 0444); |
| 787 | |
| 788 | /** |
| 789 | * DOC: bad_page_threshold (int) |
| 790 | * Bad page threshold is to specify the threshold value of faulty pages |
| 791 | * detected by RAS ECC, that may result in GPU entering bad status if total |
| 792 | * faulty pages by ECC exceed threshold value and leave it for user's further |
| 793 | * check. |
| 794 | */ |
| 795 | MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); |
| 796 | module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); |
| 797 | |
| 798 | MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); |
| 799 | module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); |
| 800 | |
| 801 | static const struct pci_device_id pciidlist[] = { |
| 802 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 803 | {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 804 | {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 805 | {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 806 | {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 807 | {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 808 | {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 809 | {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 810 | {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 811 | {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 812 | {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 813 | {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 814 | {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 815 | {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, |
| 816 | {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, |
| 817 | {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, |
| 818 | {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, |
| 819 | {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 820 | {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 821 | {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 822 | {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 823 | {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 824 | {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 825 | {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 826 | {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 827 | {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, |
| 828 | {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 829 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 830 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 831 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 832 | {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 833 | {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 834 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 835 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 836 | {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, |
| 837 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, |
| 838 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, |
| 839 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, |
| 840 | {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 841 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 842 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 843 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 844 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, |
| 845 | {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 846 | {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 847 | {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 848 | {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 849 | {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 850 | {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 851 | {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 852 | {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 853 | {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 854 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 855 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 856 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 857 | {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 858 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 859 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 860 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 861 | {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 862 | {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 863 | {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 864 | {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 865 | {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 866 | {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 867 | {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 868 | {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, |
| 869 | {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 870 | {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 871 | {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 872 | {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 873 | {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 874 | {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 875 | #endif |
| 876 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 877 | /* Kaveri */ |
| 878 | {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 879 | {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 880 | {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 881 | {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 882 | {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 883 | {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 884 | {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 885 | {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 886 | {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 887 | {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 888 | {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 889 | {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 890 | {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 891 | {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 892 | {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 893 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 894 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 895 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 896 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 897 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 898 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 899 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 900 | /* Bonaire */ |
| 901 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 902 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 903 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 904 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 905 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 906 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 907 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 908 | {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 909 | {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 910 | {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 911 | {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
| 912 | /* Hawaii */ |
| 913 | {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 914 | {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 915 | {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 916 | {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 917 | {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 918 | {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 919 | {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 920 | {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 921 | {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 922 | {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 923 | {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 924 | {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, |
| 925 | /* Kabini */ |
| 926 | {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 927 | {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 928 | {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 929 | {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 930 | {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 931 | {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 932 | {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 933 | {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 934 | {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 935 | {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 936 | {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 937 | {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 938 | {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 939 | {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 940 | {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 941 | {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 942 | /* mullins */ |
| 943 | {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 944 | {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 945 | {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 946 | {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 947 | {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 948 | {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 949 | {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 950 | {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 951 | {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 952 | {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 953 | {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 954 | {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 955 | {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 956 | {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 957 | {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 958 | {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 959 | #endif |
| 960 | /* topaz */ |
| 961 | {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
| 962 | {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
| 963 | {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
| 964 | {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
| 965 | {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
| 966 | /* tonga */ |
| 967 | {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 968 | {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 969 | {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 970 | {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 971 | {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 972 | {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 973 | {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 974 | {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 975 | {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
| 976 | /* fiji */ |
| 977 | {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, |
| 978 | {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, |
| 979 | /* carrizo */ |
| 980 | {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 981 | {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 982 | {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 983 | {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 984 | {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 985 | /* stoney */ |
| 986 | {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, |
| 987 | /* Polaris11 */ |
| 988 | {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 989 | {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 990 | {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 991 | {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 992 | {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 993 | {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 994 | {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 995 | {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 996 | {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
| 997 | /* Polaris10 */ |
| 998 | {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 999 | {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1000 | {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1001 | {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1002 | {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1003 | {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1004 | {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1005 | {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1006 | {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1007 | {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1008 | {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1009 | {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1010 | {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
| 1011 | /* Polaris12 */ |
| 1012 | {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1013 | {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1014 | {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1015 | {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1016 | {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1017 | {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1018 | {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1019 | {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
| 1020 | /* VEGAM */ |
| 1021 | {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, |
| 1022 | {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, |
| 1023 | {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, |
| 1024 | /* Vega 10 */ |
| 1025 | {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1026 | {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1027 | {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1028 | {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1029 | {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1030 | {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1031 | {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1032 | {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1033 | {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1034 | {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1035 | {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1036 | {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1037 | {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1038 | {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1039 | {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
| 1040 | /* Vega 12 */ |
| 1041 | {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, |
| 1042 | {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, |
| 1043 | {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, |
| 1044 | {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, |
| 1045 | {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, |
| 1046 | /* Vega 20 */ |
| 1047 | {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
| 1048 | {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
| 1049 | {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
| 1050 | {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
| 1051 | {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
| 1052 | {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
| 1053 | {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
| 1054 | /* Raven */ |
| 1055 | {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
| 1056 | {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
| 1057 | /* Arcturus */ |
| 1058 | {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, |
| 1059 | {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, |
| 1060 | {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, |
| 1061 | {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, |
| 1062 | /* Navi10 */ |
| 1063 | {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
| 1064 | {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
| 1065 | {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
| 1066 | {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
| 1067 | {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
| 1068 | {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
| 1069 | {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
| 1070 | /* Navi14 */ |
| 1071 | {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, |
| 1072 | {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, |
| 1073 | {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, |
| 1074 | {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, |
| 1075 | |
| 1076 | /* Renoir */ |
| 1077 | {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| 1078 | |
| 1079 | /* Navi12 */ |
| 1080 | {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, |
| 1081 | {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, |
| 1082 | |
| 1083 | /* Sienna_Cichlid */ |
| 1084 | {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
| 1085 | {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
| 1086 | {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
| 1087 | {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
| 1088 | {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
| 1089 | {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
| 1090 | |
| 1091 | {0, 0, 0} |
| 1092 | }; |
| 1093 | |
| 1094 | MODULE_DEVICE_TABLE(pci, pciidlist); |
| 1095 | |
| 1096 | static struct drm_driver kms_driver; |
| 1097 | |
| 1098 | static int amdgpu_pci_probe(struct pci_dev *pdev, |
| 1099 | const struct pci_device_id *ent) |
| 1100 | { |
| 1101 | struct drm_device *ddev; |
| 1102 | struct amdgpu_device *adev; |
| 1103 | unsigned long flags = ent->driver_data; |
| 1104 | int ret, retry = 0; |
| 1105 | bool supports_atomic = false; |
| 1106 | |
| 1107 | if (!amdgpu_virtual_display && |
| 1108 | amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) |
| 1109 | supports_atomic = true; |
| 1110 | |
| 1111 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
| 1112 | DRM_INFO("This hardware requires experimental hardware support.\n" |
| 1113 | "See modparam exp_hw_support\n"); |
| 1114 | return -ENODEV; |
| 1115 | } |
| 1116 | |
| 1117 | /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, |
| 1118 | * however, SME requires an indirect IOMMU mapping because the encryption |
| 1119 | * bit is beyond the DMA mask of the chip. |
| 1120 | */ |
| 1121 | if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { |
| 1122 | dev_info(&pdev->dev, |
| 1123 | "SME is not compatible with RAVEN\n"); |
| 1124 | return -ENOTSUPP; |
| 1125 | } |
| 1126 | |
| 1127 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 1128 | if (!amdgpu_si_support) { |
| 1129 | switch (flags & AMD_ASIC_MASK) { |
| 1130 | case CHIP_TAHITI: |
| 1131 | case CHIP_PITCAIRN: |
| 1132 | case CHIP_VERDE: |
| 1133 | case CHIP_OLAND: |
| 1134 | case CHIP_HAINAN: |
| 1135 | dev_info(&pdev->dev, |
| 1136 | "SI support provided by radeon.\n"); |
| 1137 | dev_info(&pdev->dev, |
| 1138 | "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" |
| 1139 | ); |
| 1140 | return -ENODEV; |
| 1141 | } |
| 1142 | } |
| 1143 | #endif |
| 1144 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 1145 | if (!amdgpu_cik_support) { |
| 1146 | switch (flags & AMD_ASIC_MASK) { |
| 1147 | case CHIP_KAVERI: |
| 1148 | case CHIP_BONAIRE: |
| 1149 | case CHIP_HAWAII: |
| 1150 | case CHIP_KABINI: |
| 1151 | case CHIP_MULLINS: |
| 1152 | dev_info(&pdev->dev, |
| 1153 | "CIK support provided by radeon.\n"); |
| 1154 | dev_info(&pdev->dev, |
| 1155 | "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" |
| 1156 | ); |
| 1157 | return -ENODEV; |
| 1158 | } |
| 1159 | } |
| 1160 | #endif |
| 1161 | |
| 1162 | /* Get rid of things like offb */ |
| 1163 | ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); |
| 1164 | if (ret) |
| 1165 | return ret; |
| 1166 | |
| 1167 | adev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*adev), ddev); |
| 1168 | if (IS_ERR(adev)) |
| 1169 | return PTR_ERR(adev); |
| 1170 | |
| 1171 | adev->dev = &pdev->dev; |
| 1172 | adev->pdev = pdev; |
| 1173 | ddev = adev_to_drm(adev); |
| 1174 | |
| 1175 | if (!supports_atomic) |
| 1176 | ddev->driver_features &= ~DRIVER_ATOMIC; |
| 1177 | |
| 1178 | ret = pci_enable_device(pdev); |
| 1179 | if (ret) |
| 1180 | return ret; |
| 1181 | |
| 1182 | ddev->pdev = pdev; |
| 1183 | pci_set_drvdata(pdev, ddev); |
| 1184 | |
| 1185 | ret = amdgpu_driver_load_kms(adev, ent->driver_data); |
| 1186 | if (ret) |
| 1187 | goto err_pci; |
| 1188 | |
| 1189 | retry_init: |
| 1190 | ret = drm_dev_register(ddev, ent->driver_data); |
| 1191 | if (ret == -EAGAIN && ++retry <= 3) { |
| 1192 | DRM_INFO("retry init %d\n", retry); |
| 1193 | /* Don't request EX mode too frequently which is attacking */ |
| 1194 | msleep(5000); |
| 1195 | goto retry_init; |
| 1196 | } else if (ret) { |
| 1197 | goto err_pci; |
| 1198 | } |
| 1199 | |
| 1200 | ret = amdgpu_debugfs_init(adev); |
| 1201 | if (ret) |
| 1202 | DRM_ERROR("Creating debugfs files failed (%d).\n", ret); |
| 1203 | |
| 1204 | return 0; |
| 1205 | |
| 1206 | err_pci: |
| 1207 | pci_disable_device(pdev); |
| 1208 | return ret; |
| 1209 | } |
| 1210 | |
| 1211 | static void |
| 1212 | amdgpu_pci_remove(struct pci_dev *pdev) |
| 1213 | { |
| 1214 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1215 | |
| 1216 | #ifdef MODULE |
| 1217 | if (THIS_MODULE->state != MODULE_STATE_GOING) |
| 1218 | #endif |
| 1219 | DRM_ERROR("Hotplug removal is not supported\n"); |
| 1220 | drm_dev_unplug(dev); |
| 1221 | amdgpu_driver_unload_kms(dev); |
| 1222 | pci_disable_device(pdev); |
| 1223 | pci_set_drvdata(pdev, NULL); |
| 1224 | } |
| 1225 | |
| 1226 | static void |
| 1227 | amdgpu_pci_shutdown(struct pci_dev *pdev) |
| 1228 | { |
| 1229 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1230 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1231 | |
| 1232 | if (amdgpu_ras_intr_triggered()) |
| 1233 | return; |
| 1234 | |
| 1235 | /* if we are running in a VM, make sure the device |
| 1236 | * torn down properly on reboot/shutdown. |
| 1237 | * unfortunately we can't detect certain |
| 1238 | * hypervisors so just do this all the time. |
| 1239 | */ |
| 1240 | if (!amdgpu_passthrough(adev)) |
| 1241 | adev->mp1_state = PP_MP1_STATE_UNLOAD; |
| 1242 | amdgpu_device_ip_suspend(adev); |
| 1243 | adev->mp1_state = PP_MP1_STATE_NONE; |
| 1244 | } |
| 1245 | |
| 1246 | static int amdgpu_pmops_suspend(struct device *dev) |
| 1247 | { |
| 1248 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 1249 | |
| 1250 | return amdgpu_device_suspend(drm_dev, true); |
| 1251 | } |
| 1252 | |
| 1253 | static int amdgpu_pmops_resume(struct device *dev) |
| 1254 | { |
| 1255 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 1256 | |
| 1257 | return amdgpu_device_resume(drm_dev, true); |
| 1258 | } |
| 1259 | |
| 1260 | static int amdgpu_pmops_freeze(struct device *dev) |
| 1261 | { |
| 1262 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 1263 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 1264 | int r; |
| 1265 | |
| 1266 | adev->in_hibernate = true; |
| 1267 | r = amdgpu_device_suspend(drm_dev, true); |
| 1268 | adev->in_hibernate = false; |
| 1269 | if (r) |
| 1270 | return r; |
| 1271 | return amdgpu_asic_reset(adev); |
| 1272 | } |
| 1273 | |
| 1274 | static int amdgpu_pmops_thaw(struct device *dev) |
| 1275 | { |
| 1276 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 1277 | |
| 1278 | return amdgpu_device_resume(drm_dev, true); |
| 1279 | } |
| 1280 | |
| 1281 | static int amdgpu_pmops_poweroff(struct device *dev) |
| 1282 | { |
| 1283 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 1284 | |
| 1285 | return amdgpu_device_suspend(drm_dev, true); |
| 1286 | } |
| 1287 | |
| 1288 | static int amdgpu_pmops_restore(struct device *dev) |
| 1289 | { |
| 1290 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 1291 | |
| 1292 | return amdgpu_device_resume(drm_dev, true); |
| 1293 | } |
| 1294 | |
| 1295 | static int amdgpu_pmops_runtime_suspend(struct device *dev) |
| 1296 | { |
| 1297 | struct pci_dev *pdev = to_pci_dev(dev); |
| 1298 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 1299 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 1300 | int ret, i; |
| 1301 | |
| 1302 | if (!adev->runpm) { |
| 1303 | pm_runtime_forbid(dev); |
| 1304 | return -EBUSY; |
| 1305 | } |
| 1306 | |
| 1307 | /* wait for all rings to drain before suspending */ |
| 1308 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { |
| 1309 | struct amdgpu_ring *ring = adev->rings[i]; |
| 1310 | if (ring && ring->sched.ready) { |
| 1311 | ret = amdgpu_fence_wait_empty(ring); |
| 1312 | if (ret) |
| 1313 | return -EBUSY; |
| 1314 | } |
| 1315 | } |
| 1316 | |
| 1317 | adev->in_runpm = true; |
| 1318 | if (amdgpu_device_supports_boco(drm_dev)) |
| 1319 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
| 1320 | drm_kms_helper_poll_disable(drm_dev); |
| 1321 | |
| 1322 | ret = amdgpu_device_suspend(drm_dev, false); |
| 1323 | if (ret) |
| 1324 | return ret; |
| 1325 | |
| 1326 | if (amdgpu_device_supports_boco(drm_dev)) { |
| 1327 | /* Only need to handle PCI state in the driver for ATPX |
| 1328 | * PCI core handles it for _PR3. |
| 1329 | */ |
| 1330 | if (amdgpu_is_atpx_hybrid()) { |
| 1331 | pci_ignore_hotplug(pdev); |
| 1332 | } else { |
| 1333 | amdgpu_device_cache_pci_state(pdev); |
| 1334 | pci_disable_device(pdev); |
| 1335 | pci_ignore_hotplug(pdev); |
| 1336 | pci_set_power_state(pdev, PCI_D3cold); |
| 1337 | } |
| 1338 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
| 1339 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
| 1340 | amdgpu_device_baco_enter(drm_dev); |
| 1341 | } |
| 1342 | |
| 1343 | return 0; |
| 1344 | } |
| 1345 | |
| 1346 | static int amdgpu_pmops_runtime_resume(struct device *dev) |
| 1347 | { |
| 1348 | struct pci_dev *pdev = to_pci_dev(dev); |
| 1349 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 1350 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 1351 | int ret; |
| 1352 | |
| 1353 | if (!adev->runpm) |
| 1354 | return -EINVAL; |
| 1355 | |
| 1356 | if (amdgpu_device_supports_boco(drm_dev)) { |
| 1357 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
| 1358 | |
| 1359 | /* Only need to handle PCI state in the driver for ATPX |
| 1360 | * PCI core handles it for _PR3. |
| 1361 | */ |
| 1362 | if (amdgpu_is_atpx_hybrid()) { |
| 1363 | pci_set_master(pdev); |
| 1364 | } else { |
| 1365 | pci_set_power_state(pdev, PCI_D0); |
| 1366 | amdgpu_device_load_pci_state(pdev); |
| 1367 | ret = pci_enable_device(pdev); |
| 1368 | if (ret) |
| 1369 | return ret; |
| 1370 | pci_set_master(pdev); |
| 1371 | } |
| 1372 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
| 1373 | amdgpu_device_baco_exit(drm_dev); |
| 1374 | } |
| 1375 | ret = amdgpu_device_resume(drm_dev, false); |
| 1376 | drm_kms_helper_poll_enable(drm_dev); |
| 1377 | if (amdgpu_device_supports_boco(drm_dev)) |
| 1378 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
| 1379 | adev->in_runpm = false; |
| 1380 | return 0; |
| 1381 | } |
| 1382 | |
| 1383 | static int amdgpu_pmops_runtime_idle(struct device *dev) |
| 1384 | { |
| 1385 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 1386 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 1387 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ |
| 1388 | int ret = 1; |
| 1389 | |
| 1390 | if (!adev->runpm) { |
| 1391 | pm_runtime_forbid(dev); |
| 1392 | return -EBUSY; |
| 1393 | } |
| 1394 | |
| 1395 | if (amdgpu_device_has_dc_support(adev)) { |
| 1396 | struct drm_crtc *crtc; |
| 1397 | |
| 1398 | drm_modeset_lock_all(drm_dev); |
| 1399 | |
| 1400 | drm_for_each_crtc(crtc, drm_dev) { |
| 1401 | if (crtc->state->active) { |
| 1402 | ret = -EBUSY; |
| 1403 | break; |
| 1404 | } |
| 1405 | } |
| 1406 | |
| 1407 | drm_modeset_unlock_all(drm_dev); |
| 1408 | |
| 1409 | } else { |
| 1410 | struct drm_connector *list_connector; |
| 1411 | struct drm_connector_list_iter iter; |
| 1412 | |
| 1413 | mutex_lock(&drm_dev->mode_config.mutex); |
| 1414 | drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); |
| 1415 | |
| 1416 | drm_connector_list_iter_begin(drm_dev, &iter); |
| 1417 | drm_for_each_connector_iter(list_connector, &iter) { |
| 1418 | if (list_connector->dpms == DRM_MODE_DPMS_ON) { |
| 1419 | ret = -EBUSY; |
| 1420 | break; |
| 1421 | } |
| 1422 | } |
| 1423 | |
| 1424 | drm_connector_list_iter_end(&iter); |
| 1425 | |
| 1426 | drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); |
| 1427 | mutex_unlock(&drm_dev->mode_config.mutex); |
| 1428 | } |
| 1429 | |
| 1430 | if (ret == -EBUSY) |
| 1431 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); |
| 1432 | |
| 1433 | pm_runtime_mark_last_busy(dev); |
| 1434 | pm_runtime_autosuspend(dev); |
| 1435 | return ret; |
| 1436 | } |
| 1437 | |
| 1438 | long amdgpu_drm_ioctl(struct file *filp, |
| 1439 | unsigned int cmd, unsigned long arg) |
| 1440 | { |
| 1441 | struct drm_file *file_priv = filp->private_data; |
| 1442 | struct drm_device *dev; |
| 1443 | long ret; |
| 1444 | dev = file_priv->minor->dev; |
| 1445 | ret = pm_runtime_get_sync(dev->dev); |
| 1446 | if (ret < 0) |
| 1447 | goto out; |
| 1448 | |
| 1449 | ret = drm_ioctl(filp, cmd, arg); |
| 1450 | |
| 1451 | pm_runtime_mark_last_busy(dev->dev); |
| 1452 | out: |
| 1453 | pm_runtime_put_autosuspend(dev->dev); |
| 1454 | return ret; |
| 1455 | } |
| 1456 | |
| 1457 | static const struct dev_pm_ops amdgpu_pm_ops = { |
| 1458 | .suspend = amdgpu_pmops_suspend, |
| 1459 | .resume = amdgpu_pmops_resume, |
| 1460 | .freeze = amdgpu_pmops_freeze, |
| 1461 | .thaw = amdgpu_pmops_thaw, |
| 1462 | .poweroff = amdgpu_pmops_poweroff, |
| 1463 | .restore = amdgpu_pmops_restore, |
| 1464 | .runtime_suspend = amdgpu_pmops_runtime_suspend, |
| 1465 | .runtime_resume = amdgpu_pmops_runtime_resume, |
| 1466 | .runtime_idle = amdgpu_pmops_runtime_idle, |
| 1467 | }; |
| 1468 | |
| 1469 | static int amdgpu_flush(struct file *f, fl_owner_t id) |
| 1470 | { |
| 1471 | struct drm_file *file_priv = f->private_data; |
| 1472 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
| 1473 | long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; |
| 1474 | |
| 1475 | timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); |
| 1476 | timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); |
| 1477 | |
| 1478 | return timeout >= 0 ? 0 : timeout; |
| 1479 | } |
| 1480 | |
| 1481 | static const struct file_operations amdgpu_driver_kms_fops = { |
| 1482 | .owner = THIS_MODULE, |
| 1483 | .open = drm_open, |
| 1484 | .flush = amdgpu_flush, |
| 1485 | .release = drm_release, |
| 1486 | .unlocked_ioctl = amdgpu_drm_ioctl, |
| 1487 | .mmap = amdgpu_mmap, |
| 1488 | .poll = drm_poll, |
| 1489 | .read = drm_read, |
| 1490 | #ifdef CONFIG_COMPAT |
| 1491 | .compat_ioctl = amdgpu_kms_compat_ioctl, |
| 1492 | #endif |
| 1493 | }; |
| 1494 | |
| 1495 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) |
| 1496 | { |
| 1497 | struct drm_file *file; |
| 1498 | |
| 1499 | if (!filp) |
| 1500 | return -EINVAL; |
| 1501 | |
| 1502 | if (filp->f_op != &amdgpu_driver_kms_fops) { |
| 1503 | return -EINVAL; |
| 1504 | } |
| 1505 | |
| 1506 | file = filp->private_data; |
| 1507 | *fpriv = file->driver_priv; |
| 1508 | return 0; |
| 1509 | } |
| 1510 | |
| 1511 | static struct drm_driver kms_driver = { |
| 1512 | .driver_features = |
| 1513 | DRIVER_ATOMIC | |
| 1514 | DRIVER_GEM | |
| 1515 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | |
| 1516 | DRIVER_SYNCOBJ_TIMELINE, |
| 1517 | .open = amdgpu_driver_open_kms, |
| 1518 | .postclose = amdgpu_driver_postclose_kms, |
| 1519 | .lastclose = amdgpu_driver_lastclose_kms, |
| 1520 | .irq_handler = amdgpu_irq_handler, |
| 1521 | .ioctls = amdgpu_ioctls_kms, |
| 1522 | .gem_free_object_unlocked = amdgpu_gem_object_free, |
| 1523 | .gem_open_object = amdgpu_gem_object_open, |
| 1524 | .gem_close_object = amdgpu_gem_object_close, |
| 1525 | .dumb_create = amdgpu_mode_dumb_create, |
| 1526 | .dumb_map_offset = amdgpu_mode_dumb_mmap, |
| 1527 | .fops = &amdgpu_driver_kms_fops, |
| 1528 | |
| 1529 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1530 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1531 | .gem_prime_export = amdgpu_gem_prime_export, |
| 1532 | .gem_prime_import = amdgpu_gem_prime_import, |
| 1533 | .gem_prime_vmap = amdgpu_gem_prime_vmap, |
| 1534 | .gem_prime_vunmap = amdgpu_gem_prime_vunmap, |
| 1535 | .gem_prime_mmap = amdgpu_gem_prime_mmap, |
| 1536 | |
| 1537 | .name = DRIVER_NAME, |
| 1538 | .desc = DRIVER_DESC, |
| 1539 | .date = DRIVER_DATE, |
| 1540 | .major = KMS_DRIVER_MAJOR, |
| 1541 | .minor = KMS_DRIVER_MINOR, |
| 1542 | .patchlevel = KMS_DRIVER_PATCHLEVEL, |
| 1543 | }; |
| 1544 | |
| 1545 | static struct pci_error_handlers amdgpu_pci_err_handler = { |
| 1546 | .error_detected = amdgpu_pci_error_detected, |
| 1547 | .mmio_enabled = amdgpu_pci_mmio_enabled, |
| 1548 | .slot_reset = amdgpu_pci_slot_reset, |
| 1549 | .resume = amdgpu_pci_resume, |
| 1550 | }; |
| 1551 | |
| 1552 | static struct pci_driver amdgpu_kms_pci_driver = { |
| 1553 | .name = DRIVER_NAME, |
| 1554 | .id_table = pciidlist, |
| 1555 | .probe = amdgpu_pci_probe, |
| 1556 | .remove = amdgpu_pci_remove, |
| 1557 | .shutdown = amdgpu_pci_shutdown, |
| 1558 | .driver.pm = &amdgpu_pm_ops, |
| 1559 | .err_handler = &amdgpu_pci_err_handler, |
| 1560 | }; |
| 1561 | |
| 1562 | static int __init amdgpu_init(void) |
| 1563 | { |
| 1564 | int r; |
| 1565 | |
| 1566 | if (vgacon_text_force()) { |
| 1567 | DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); |
| 1568 | return -EINVAL; |
| 1569 | } |
| 1570 | |
| 1571 | r = amdgpu_sync_init(); |
| 1572 | if (r) |
| 1573 | goto error_sync; |
| 1574 | |
| 1575 | r = amdgpu_fence_slab_init(); |
| 1576 | if (r) |
| 1577 | goto error_fence; |
| 1578 | |
| 1579 | DRM_INFO("amdgpu kernel modesetting enabled.\n"); |
| 1580 | kms_driver.num_ioctls = amdgpu_max_kms_ioctl; |
| 1581 | amdgpu_register_atpx_handler(); |
| 1582 | |
| 1583 | /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ |
| 1584 | amdgpu_amdkfd_init(); |
| 1585 | |
| 1586 | /* let modprobe override vga console setting */ |
| 1587 | return pci_register_driver(&amdgpu_kms_pci_driver); |
| 1588 | |
| 1589 | error_fence: |
| 1590 | amdgpu_sync_fini(); |
| 1591 | |
| 1592 | error_sync: |
| 1593 | return r; |
| 1594 | } |
| 1595 | |
| 1596 | static void __exit amdgpu_exit(void) |
| 1597 | { |
| 1598 | amdgpu_amdkfd_fini(); |
| 1599 | pci_unregister_driver(&amdgpu_kms_pci_driver); |
| 1600 | amdgpu_unregister_atpx_handler(); |
| 1601 | amdgpu_sync_fini(); |
| 1602 | amdgpu_fence_slab_fini(); |
| 1603 | mmu_notifier_synchronize(); |
| 1604 | } |
| 1605 | |
| 1606 | module_init(amdgpu_init); |
| 1607 | module_exit(amdgpu_exit); |
| 1608 | |
| 1609 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 1610 | MODULE_DESCRIPTION(DRIVER_DESC); |
| 1611 | MODULE_LICENSE("GPL and additional rights"); |