| 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __AMDGPU_H__ |
| 29 | #define __AMDGPU_H__ |
| 30 | |
| 31 | #include "amdgpu_ctx.h" |
| 32 | |
| 33 | #include <linux/atomic.h> |
| 34 | #include <linux/wait.h> |
| 35 | #include <linux/list.h> |
| 36 | #include <linux/kref.h> |
| 37 | #include <linux/rbtree.h> |
| 38 | #include <linux/hashtable.h> |
| 39 | #include <linux/dma-fence.h> |
| 40 | |
| 41 | #include <drm/ttm/ttm_bo_api.h> |
| 42 | #include <drm/ttm/ttm_bo_driver.h> |
| 43 | #include <drm/ttm/ttm_placement.h> |
| 44 | #include <drm/ttm/ttm_module.h> |
| 45 | #include <drm/ttm/ttm_execbuf_util.h> |
| 46 | |
| 47 | #include <drm/amdgpu_drm.h> |
| 48 | #include <drm/drm_gem.h> |
| 49 | #include <drm/drm_ioctl.h> |
| 50 | #include <drm/gpu_scheduler.h> |
| 51 | |
| 52 | #include <kgd_kfd_interface.h> |
| 53 | #include "dm_pp_interface.h" |
| 54 | #include "kgd_pp_interface.h" |
| 55 | |
| 56 | #include "amd_shared.h" |
| 57 | #include "amdgpu_mode.h" |
| 58 | #include "amdgpu_ih.h" |
| 59 | #include "amdgpu_irq.h" |
| 60 | #include "amdgpu_ucode.h" |
| 61 | #include "amdgpu_ttm.h" |
| 62 | #include "amdgpu_psp.h" |
| 63 | #include "amdgpu_gds.h" |
| 64 | #include "amdgpu_sync.h" |
| 65 | #include "amdgpu_ring.h" |
| 66 | #include "amdgpu_vm.h" |
| 67 | #include "amdgpu_dpm.h" |
| 68 | #include "amdgpu_acp.h" |
| 69 | #include "amdgpu_uvd.h" |
| 70 | #include "amdgpu_vce.h" |
| 71 | #include "amdgpu_vcn.h" |
| 72 | #include "amdgpu_mn.h" |
| 73 | #include "amdgpu_gmc.h" |
| 74 | #include "amdgpu_gfx.h" |
| 75 | #include "amdgpu_sdma.h" |
| 76 | #include "amdgpu_dm.h" |
| 77 | #include "amdgpu_virt.h" |
| 78 | #include "amdgpu_csa.h" |
| 79 | #include "amdgpu_gart.h" |
| 80 | #include "amdgpu_debugfs.h" |
| 81 | #include "amdgpu_job.h" |
| 82 | #include "amdgpu_bo_list.h" |
| 83 | #include "amdgpu_gem.h" |
| 84 | #include "amdgpu_doorbell.h" |
| 85 | #include "amdgpu_amdkfd.h" |
| 86 | #include "amdgpu_smu.h" |
| 87 | #include "amdgpu_discovery.h" |
| 88 | #include "amdgpu_mes.h" |
| 89 | |
| 90 | #define MAX_GPU_INSTANCE 16 |
| 91 | |
| 92 | struct amdgpu_gpu_instance |
| 93 | { |
| 94 | struct amdgpu_device *adev; |
| 95 | int mgpu_fan_enabled; |
| 96 | }; |
| 97 | |
| 98 | struct amdgpu_mgpu_info |
| 99 | { |
| 100 | struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; |
| 101 | struct mutex mutex; |
| 102 | uint32_t num_gpu; |
| 103 | uint32_t num_dgpu; |
| 104 | uint32_t num_apu; |
| 105 | }; |
| 106 | |
| 107 | /* |
| 108 | * Modules parameters. |
| 109 | */ |
| 110 | extern int amdgpu_modeset; |
| 111 | extern int amdgpu_vram_limit; |
| 112 | extern int amdgpu_vis_vram_limit; |
| 113 | extern int amdgpu_gart_size; |
| 114 | extern int amdgpu_gtt_size; |
| 115 | extern int amdgpu_moverate; |
| 116 | extern int amdgpu_benchmarking; |
| 117 | extern int amdgpu_testing; |
| 118 | extern int amdgpu_audio; |
| 119 | extern int amdgpu_disp_priority; |
| 120 | extern int amdgpu_hw_i2c; |
| 121 | extern int amdgpu_pcie_gen2; |
| 122 | extern int amdgpu_msi; |
| 123 | extern int amdgpu_dpm; |
| 124 | extern int amdgpu_fw_load_type; |
| 125 | extern int amdgpu_aspm; |
| 126 | extern int amdgpu_runtime_pm; |
| 127 | extern uint amdgpu_ip_block_mask; |
| 128 | extern int amdgpu_bapm; |
| 129 | extern int amdgpu_deep_color; |
| 130 | extern int amdgpu_vm_size; |
| 131 | extern int amdgpu_vm_block_size; |
| 132 | extern int amdgpu_vm_fragment_size; |
| 133 | extern int amdgpu_vm_fault_stop; |
| 134 | extern int amdgpu_vm_debug; |
| 135 | extern int amdgpu_vm_update_mode; |
| 136 | extern int amdgpu_dc; |
| 137 | extern int amdgpu_sched_jobs; |
| 138 | extern int amdgpu_sched_hw_submission; |
| 139 | extern uint amdgpu_pcie_gen_cap; |
| 140 | extern uint amdgpu_pcie_lane_cap; |
| 141 | extern uint amdgpu_cg_mask; |
| 142 | extern uint amdgpu_pg_mask; |
| 143 | extern uint amdgpu_sdma_phase_quantum; |
| 144 | extern char *amdgpu_disable_cu; |
| 145 | extern char *amdgpu_virtual_display; |
| 146 | extern uint amdgpu_pp_feature_mask; |
| 147 | extern int amdgpu_ngg; |
| 148 | extern int amdgpu_prim_buf_per_se; |
| 149 | extern int amdgpu_pos_buf_per_se; |
| 150 | extern int amdgpu_cntl_sb_buf_per_se; |
| 151 | extern int amdgpu_param_buf_per_se; |
| 152 | extern int amdgpu_job_hang_limit; |
| 153 | extern int amdgpu_lbpw; |
| 154 | extern int amdgpu_compute_multipipe; |
| 155 | extern int amdgpu_gpu_recovery; |
| 156 | extern int amdgpu_emu_mode; |
| 157 | extern uint amdgpu_smu_memory_pool_size; |
| 158 | extern uint amdgpu_dc_feature_mask; |
| 159 | extern uint amdgpu_dm_abm_level; |
| 160 | extern struct amdgpu_mgpu_info mgpu_info; |
| 161 | extern int amdgpu_ras_enable; |
| 162 | extern uint amdgpu_ras_mask; |
| 163 | extern int amdgpu_async_gfx_ring; |
| 164 | extern int amdgpu_mcbp; |
| 165 | extern int amdgpu_discovery; |
| 166 | extern int amdgpu_mes; |
| 167 | extern int amdgpu_noretry; |
| 168 | |
| 169 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 170 | extern int amdgpu_si_support; |
| 171 | #endif |
| 172 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 173 | extern int amdgpu_cik_support; |
| 174 | #endif |
| 175 | |
| 176 | #define AMDGPU_VM_MAX_NUM_CTX 4096 |
| 177 | #define AMDGPU_SG_THRESHOLD (256*1024*1024) |
| 178 | #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ |
| 179 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
| 180 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 181 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
| 182 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ |
| 183 | #define AMDGPU_IB_POOL_SIZE 16 |
| 184 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 |
| 185 | #define AMDGPUFB_CONN_LIMIT 4 |
| 186 | #define AMDGPU_BIOS_NUM_SCRATCH 16 |
| 187 | |
| 188 | /* hard reset data */ |
| 189 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b |
| 190 | |
| 191 | /* reset flags */ |
| 192 | #define AMDGPU_RESET_GFX (1 << 0) |
| 193 | #define AMDGPU_RESET_COMPUTE (1 << 1) |
| 194 | #define AMDGPU_RESET_DMA (1 << 2) |
| 195 | #define AMDGPU_RESET_CP (1 << 3) |
| 196 | #define AMDGPU_RESET_GRBM (1 << 4) |
| 197 | #define AMDGPU_RESET_DMA1 (1 << 5) |
| 198 | #define AMDGPU_RESET_RLC (1 << 6) |
| 199 | #define AMDGPU_RESET_SEM (1 << 7) |
| 200 | #define AMDGPU_RESET_IH (1 << 8) |
| 201 | #define AMDGPU_RESET_VMC (1 << 9) |
| 202 | #define AMDGPU_RESET_MC (1 << 10) |
| 203 | #define AMDGPU_RESET_DISPLAY (1 << 11) |
| 204 | #define AMDGPU_RESET_UVD (1 << 12) |
| 205 | #define AMDGPU_RESET_VCE (1 << 13) |
| 206 | #define AMDGPU_RESET_VCE1 (1 << 14) |
| 207 | |
| 208 | /* max cursor sizes (in pixels) */ |
| 209 | #define CIK_CURSOR_WIDTH 128 |
| 210 | #define CIK_CURSOR_HEIGHT 128 |
| 211 | |
| 212 | struct amdgpu_device; |
| 213 | struct amdgpu_ib; |
| 214 | struct amdgpu_cs_parser; |
| 215 | struct amdgpu_job; |
| 216 | struct amdgpu_irq_src; |
| 217 | struct amdgpu_fpriv; |
| 218 | struct amdgpu_bo_va_mapping; |
| 219 | struct amdgpu_atif; |
| 220 | struct kfd_vm_fault_info; |
| 221 | |
| 222 | enum amdgpu_cp_irq { |
| 223 | AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, |
| 224 | AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, |
| 225 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, |
| 226 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, |
| 227 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, |
| 228 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, |
| 229 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, |
| 230 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, |
| 231 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, |
| 232 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, |
| 233 | |
| 234 | AMDGPU_CP_IRQ_LAST |
| 235 | }; |
| 236 | |
| 237 | enum amdgpu_thermal_irq { |
| 238 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, |
| 239 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, |
| 240 | |
| 241 | AMDGPU_THERMAL_IRQ_LAST |
| 242 | }; |
| 243 | |
| 244 | enum amdgpu_kiq_irq { |
| 245 | AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, |
| 246 | AMDGPU_CP_KIQ_IRQ_LAST |
| 247 | }; |
| 248 | |
| 249 | #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ |
| 250 | #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ |
| 251 | #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ |
| 252 | |
| 253 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
| 254 | enum amd_ip_block_type block_type, |
| 255 | enum amd_clockgating_state state); |
| 256 | int amdgpu_device_ip_set_powergating_state(void *dev, |
| 257 | enum amd_ip_block_type block_type, |
| 258 | enum amd_powergating_state state); |
| 259 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
| 260 | u32 *flags); |
| 261 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
| 262 | enum amd_ip_block_type block_type); |
| 263 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
| 264 | enum amd_ip_block_type block_type); |
| 265 | |
| 266 | #define AMDGPU_MAX_IP_NUM 16 |
| 267 | |
| 268 | struct amdgpu_ip_block_status { |
| 269 | bool valid; |
| 270 | bool sw; |
| 271 | bool hw; |
| 272 | bool late_initialized; |
| 273 | bool hang; |
| 274 | }; |
| 275 | |
| 276 | struct amdgpu_ip_block_version { |
| 277 | const enum amd_ip_block_type type; |
| 278 | const u32 major; |
| 279 | const u32 minor; |
| 280 | const u32 rev; |
| 281 | const struct amd_ip_funcs *funcs; |
| 282 | }; |
| 283 | |
| 284 | struct amdgpu_ip_block { |
| 285 | struct amdgpu_ip_block_status status; |
| 286 | const struct amdgpu_ip_block_version *version; |
| 287 | }; |
| 288 | |
| 289 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
| 290 | enum amd_ip_block_type type, |
| 291 | u32 major, u32 minor); |
| 292 | |
| 293 | struct amdgpu_ip_block * |
| 294 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, |
| 295 | enum amd_ip_block_type type); |
| 296 | |
| 297 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
| 298 | const struct amdgpu_ip_block_version *ip_block_version); |
| 299 | |
| 300 | /* |
| 301 | * BIOS. |
| 302 | */ |
| 303 | bool amdgpu_get_bios(struct amdgpu_device *adev); |
| 304 | bool amdgpu_read_bios(struct amdgpu_device *adev); |
| 305 | |
| 306 | /* |
| 307 | * Clocks |
| 308 | */ |
| 309 | |
| 310 | #define AMDGPU_MAX_PPLL 3 |
| 311 | |
| 312 | struct amdgpu_clock { |
| 313 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; |
| 314 | struct amdgpu_pll spll; |
| 315 | struct amdgpu_pll mpll; |
| 316 | /* 10 Khz units */ |
| 317 | uint32_t default_mclk; |
| 318 | uint32_t default_sclk; |
| 319 | uint32_t default_dispclk; |
| 320 | uint32_t current_dispclk; |
| 321 | uint32_t dp_extclk; |
| 322 | uint32_t max_pixel_clock; |
| 323 | }; |
| 324 | |
| 325 | /* sub-allocation manager, it has to be protected by another lock. |
| 326 | * By conception this is an helper for other part of the driver |
| 327 | * like the indirect buffer or semaphore, which both have their |
| 328 | * locking. |
| 329 | * |
| 330 | * Principe is simple, we keep a list of sub allocation in offset |
| 331 | * order (first entry has offset == 0, last entry has the highest |
| 332 | * offset). |
| 333 | * |
| 334 | * When allocating new object we first check if there is room at |
| 335 | * the end total_size - (last_object_offset + last_object_size) >= |
| 336 | * alloc_size. If so we allocate new object there. |
| 337 | * |
| 338 | * When there is not enough room at the end, we start waiting for |
| 339 | * each sub object until we reach object_offset+object_size >= |
| 340 | * alloc_size, this object then become the sub object we return. |
| 341 | * |
| 342 | * Alignment can't be bigger than page size. |
| 343 | * |
| 344 | * Hole are not considered for allocation to keep things simple. |
| 345 | * Assumption is that there won't be hole (all object on same |
| 346 | * alignment). |
| 347 | */ |
| 348 | |
| 349 | #define AMDGPU_SA_NUM_FENCE_LISTS 32 |
| 350 | |
| 351 | struct amdgpu_sa_manager { |
| 352 | wait_queue_head_t wq; |
| 353 | struct amdgpu_bo *bo; |
| 354 | struct list_head *hole; |
| 355 | struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; |
| 356 | struct list_head olist; |
| 357 | unsigned size; |
| 358 | uint64_t gpu_addr; |
| 359 | void *cpu_ptr; |
| 360 | uint32_t domain; |
| 361 | uint32_t align; |
| 362 | }; |
| 363 | |
| 364 | /* sub-allocation buffer */ |
| 365 | struct amdgpu_sa_bo { |
| 366 | struct list_head olist; |
| 367 | struct list_head flist; |
| 368 | struct amdgpu_sa_manager *manager; |
| 369 | unsigned soffset; |
| 370 | unsigned eoffset; |
| 371 | struct dma_fence *fence; |
| 372 | }; |
| 373 | |
| 374 | int amdgpu_fence_slab_init(void); |
| 375 | void amdgpu_fence_slab_fini(void); |
| 376 | |
| 377 | /* |
| 378 | * IRQS. |
| 379 | */ |
| 380 | |
| 381 | struct amdgpu_flip_work { |
| 382 | struct delayed_work flip_work; |
| 383 | struct work_struct unpin_work; |
| 384 | struct amdgpu_device *adev; |
| 385 | int crtc_id; |
| 386 | u32 target_vblank; |
| 387 | uint64_t base; |
| 388 | struct drm_pending_vblank_event *event; |
| 389 | struct amdgpu_bo *old_abo; |
| 390 | struct dma_fence *excl; |
| 391 | unsigned shared_count; |
| 392 | struct dma_fence **shared; |
| 393 | struct dma_fence_cb cb; |
| 394 | bool async; |
| 395 | }; |
| 396 | |
| 397 | |
| 398 | /* |
| 399 | * CP & rings. |
| 400 | */ |
| 401 | |
| 402 | struct amdgpu_ib { |
| 403 | struct amdgpu_sa_bo *sa_bo; |
| 404 | uint32_t length_dw; |
| 405 | uint64_t gpu_addr; |
| 406 | uint32_t *ptr; |
| 407 | uint32_t flags; |
| 408 | }; |
| 409 | |
| 410 | extern const struct drm_sched_backend_ops amdgpu_sched_ops; |
| 411 | |
| 412 | /* |
| 413 | * file private structure |
| 414 | */ |
| 415 | |
| 416 | struct amdgpu_fpriv { |
| 417 | struct amdgpu_vm vm; |
| 418 | struct amdgpu_bo_va *prt_va; |
| 419 | struct amdgpu_bo_va *csa_va; |
| 420 | struct mutex bo_list_lock; |
| 421 | struct idr bo_list_handles; |
| 422 | struct amdgpu_ctx_mgr ctx_mgr; |
| 423 | }; |
| 424 | |
| 425 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); |
| 426 | int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev); |
| 427 | |
| 428 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 429 | unsigned size, struct amdgpu_ib *ib); |
| 430 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, |
| 431 | struct dma_fence *f); |
| 432 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, |
| 433 | struct amdgpu_ib *ibs, struct amdgpu_job *job, |
| 434 | struct dma_fence **f); |
| 435 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
| 436 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); |
| 437 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); |
| 438 | |
| 439 | /* |
| 440 | * CS. |
| 441 | */ |
| 442 | struct amdgpu_cs_chunk { |
| 443 | uint32_t chunk_id; |
| 444 | uint32_t length_dw; |
| 445 | void *kdata; |
| 446 | }; |
| 447 | |
| 448 | struct amdgpu_cs_post_dep { |
| 449 | struct drm_syncobj *syncobj; |
| 450 | struct dma_fence_chain *chain; |
| 451 | u64 point; |
| 452 | }; |
| 453 | |
| 454 | struct amdgpu_cs_parser { |
| 455 | struct amdgpu_device *adev; |
| 456 | struct drm_file *filp; |
| 457 | struct amdgpu_ctx *ctx; |
| 458 | |
| 459 | /* chunks */ |
| 460 | unsigned nchunks; |
| 461 | struct amdgpu_cs_chunk *chunks; |
| 462 | |
| 463 | /* scheduler job object */ |
| 464 | struct amdgpu_job *job; |
| 465 | struct drm_sched_entity *entity; |
| 466 | |
| 467 | /* buffer objects */ |
| 468 | struct ww_acquire_ctx ticket; |
| 469 | struct amdgpu_bo_list *bo_list; |
| 470 | struct amdgpu_mn *mn; |
| 471 | struct amdgpu_bo_list_entry vm_pd; |
| 472 | struct list_head validated; |
| 473 | struct dma_fence *fence; |
| 474 | uint64_t bytes_moved_threshold; |
| 475 | uint64_t bytes_moved_vis_threshold; |
| 476 | uint64_t bytes_moved; |
| 477 | uint64_t bytes_moved_vis; |
| 478 | struct amdgpu_bo_list_entry *evictable; |
| 479 | |
| 480 | /* user fence */ |
| 481 | struct amdgpu_bo_list_entry uf_entry; |
| 482 | |
| 483 | unsigned num_post_deps; |
| 484 | struct amdgpu_cs_post_dep *post_deps; |
| 485 | }; |
| 486 | |
| 487 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, |
| 488 | uint32_t ib_idx, int idx) |
| 489 | { |
| 490 | return p->job->ibs[ib_idx].ptr[idx]; |
| 491 | } |
| 492 | |
| 493 | static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, |
| 494 | uint32_t ib_idx, int idx, |
| 495 | uint32_t value) |
| 496 | { |
| 497 | p->job->ibs[ib_idx].ptr[idx] = value; |
| 498 | } |
| 499 | |
| 500 | /* |
| 501 | * Writeback |
| 502 | */ |
| 503 | #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ |
| 504 | |
| 505 | struct amdgpu_wb { |
| 506 | struct amdgpu_bo *wb_obj; |
| 507 | volatile uint32_t *wb; |
| 508 | uint64_t gpu_addr; |
| 509 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ |
| 510 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; |
| 511 | }; |
| 512 | |
| 513 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); |
| 514 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); |
| 515 | |
| 516 | /* |
| 517 | * Benchmarking |
| 518 | */ |
| 519 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); |
| 520 | |
| 521 | |
| 522 | /* |
| 523 | * Testing |
| 524 | */ |
| 525 | void amdgpu_test_moves(struct amdgpu_device *adev); |
| 526 | |
| 527 | /* |
| 528 | * ASIC specific register table accessible by UMD |
| 529 | */ |
| 530 | struct amdgpu_allowed_register_entry { |
| 531 | uint32_t reg_offset; |
| 532 | bool grbm_indexed; |
| 533 | }; |
| 534 | |
| 535 | /* |
| 536 | * ASIC specific functions. |
| 537 | */ |
| 538 | struct amdgpu_asic_funcs { |
| 539 | bool (*read_disabled_bios)(struct amdgpu_device *adev); |
| 540 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
| 541 | u8 *bios, u32 length_bytes); |
| 542 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
| 543 | u32 sh_num, u32 reg_offset, u32 *value); |
| 544 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); |
| 545 | int (*reset)(struct amdgpu_device *adev); |
| 546 | /* get the reference clock */ |
| 547 | u32 (*get_xclk)(struct amdgpu_device *adev); |
| 548 | /* MM block clocks */ |
| 549 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); |
| 550 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); |
| 551 | /* static power management */ |
| 552 | int (*get_pcie_lanes)(struct amdgpu_device *adev); |
| 553 | void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); |
| 554 | /* get config memsize register */ |
| 555 | u32 (*get_config_memsize)(struct amdgpu_device *adev); |
| 556 | /* flush hdp write queue */ |
| 557 | void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
| 558 | /* invalidate hdp read cache */ |
| 559 | void (*invalidate_hdp)(struct amdgpu_device *adev, |
| 560 | struct amdgpu_ring *ring); |
| 561 | /* check if the asic needs a full reset of if soft reset will work */ |
| 562 | bool (*need_full_reset)(struct amdgpu_device *adev); |
| 563 | /* initialize doorbell layout for specific asic*/ |
| 564 | void (*init_doorbell_index)(struct amdgpu_device *adev); |
| 565 | /* PCIe bandwidth usage */ |
| 566 | void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, |
| 567 | uint64_t *count1); |
| 568 | /* do we need to reset the asic at init time (e.g., kexec) */ |
| 569 | bool (*need_reset_on_init)(struct amdgpu_device *adev); |
| 570 | /* PCIe replay counter */ |
| 571 | uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); |
| 572 | }; |
| 573 | |
| 574 | /* |
| 575 | * IOCTL. |
| 576 | */ |
| 577 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, |
| 578 | struct drm_file *filp); |
| 579 | |
| 580 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
| 581 | int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, |
| 582 | struct drm_file *filp); |
| 583 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
| 584 | int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, |
| 585 | struct drm_file *filp); |
| 586 | |
| 587 | /* VRAM scratch page for HDP bug, default vram page */ |
| 588 | struct amdgpu_vram_scratch { |
| 589 | struct amdgpu_bo *robj; |
| 590 | volatile uint32_t *ptr; |
| 591 | u64 gpu_addr; |
| 592 | }; |
| 593 | |
| 594 | /* |
| 595 | * ACPI |
| 596 | */ |
| 597 | struct amdgpu_atcs_functions { |
| 598 | bool get_ext_state; |
| 599 | bool pcie_perf_req; |
| 600 | bool pcie_dev_rdy; |
| 601 | bool pcie_bus_width; |
| 602 | }; |
| 603 | |
| 604 | struct amdgpu_atcs { |
| 605 | struct amdgpu_atcs_functions functions; |
| 606 | }; |
| 607 | |
| 608 | /* |
| 609 | * Firmware VRAM reservation |
| 610 | */ |
| 611 | struct amdgpu_fw_vram_usage { |
| 612 | u64 start_offset; |
| 613 | u64 size; |
| 614 | struct amdgpu_bo *reserved_bo; |
| 615 | void *va; |
| 616 | }; |
| 617 | |
| 618 | /* |
| 619 | * CGS |
| 620 | */ |
| 621 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); |
| 622 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); |
| 623 | |
| 624 | /* |
| 625 | * Core structure, functions and helpers. |
| 626 | */ |
| 627 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); |
| 628 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); |
| 629 | |
| 630 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); |
| 631 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); |
| 632 | |
| 633 | |
| 634 | /* |
| 635 | * amdgpu nbio functions |
| 636 | * |
| 637 | */ |
| 638 | struct nbio_hdp_flush_reg { |
| 639 | u32 ref_and_mask_cp0; |
| 640 | u32 ref_and_mask_cp1; |
| 641 | u32 ref_and_mask_cp2; |
| 642 | u32 ref_and_mask_cp3; |
| 643 | u32 ref_and_mask_cp4; |
| 644 | u32 ref_and_mask_cp5; |
| 645 | u32 ref_and_mask_cp6; |
| 646 | u32 ref_and_mask_cp7; |
| 647 | u32 ref_and_mask_cp8; |
| 648 | u32 ref_and_mask_cp9; |
| 649 | u32 ref_and_mask_sdma0; |
| 650 | u32 ref_and_mask_sdma1; |
| 651 | u32 ref_and_mask_sdma2; |
| 652 | u32 ref_and_mask_sdma3; |
| 653 | u32 ref_and_mask_sdma4; |
| 654 | u32 ref_and_mask_sdma5; |
| 655 | u32 ref_and_mask_sdma6; |
| 656 | u32 ref_and_mask_sdma7; |
| 657 | }; |
| 658 | |
| 659 | struct amdgpu_mmio_remap { |
| 660 | u32 reg_offset; |
| 661 | resource_size_t bus_addr; |
| 662 | }; |
| 663 | |
| 664 | struct amdgpu_nbio_funcs { |
| 665 | const struct nbio_hdp_flush_reg *hdp_flush_reg; |
| 666 | u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); |
| 667 | u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); |
| 668 | u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); |
| 669 | u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); |
| 670 | u32 (*get_rev_id)(struct amdgpu_device *adev); |
| 671 | void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); |
| 672 | void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
| 673 | u32 (*get_memsize)(struct amdgpu_device *adev); |
| 674 | void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, |
| 675 | bool use_doorbell, int doorbell_index, int doorbell_size); |
| 676 | void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell, |
| 677 | int doorbell_index, int instance); |
| 678 | void (*enable_doorbell_aperture)(struct amdgpu_device *adev, |
| 679 | bool enable); |
| 680 | void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, |
| 681 | bool enable); |
| 682 | void (*ih_doorbell_range)(struct amdgpu_device *adev, |
| 683 | bool use_doorbell, int doorbell_index); |
| 684 | void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, |
| 685 | bool enable); |
| 686 | void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, |
| 687 | bool enable); |
| 688 | void (*get_clockgating_state)(struct amdgpu_device *adev, |
| 689 | u32 *flags); |
| 690 | void (*ih_control)(struct amdgpu_device *adev); |
| 691 | void (*init_registers)(struct amdgpu_device *adev); |
| 692 | void (*detect_hw_virt)(struct amdgpu_device *adev); |
| 693 | void (*remap_hdp_registers)(struct amdgpu_device *adev); |
| 694 | }; |
| 695 | |
| 696 | struct amdgpu_df_funcs { |
| 697 | void (*sw_init)(struct amdgpu_device *adev); |
| 698 | void (*enable_broadcast_mode)(struct amdgpu_device *adev, |
| 699 | bool enable); |
| 700 | u32 (*get_fb_channel_number)(struct amdgpu_device *adev); |
| 701 | u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); |
| 702 | void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, |
| 703 | bool enable); |
| 704 | void (*get_clockgating_state)(struct amdgpu_device *adev, |
| 705 | u32 *flags); |
| 706 | void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, |
| 707 | bool enable); |
| 708 | int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, |
| 709 | int is_enable); |
| 710 | int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, |
| 711 | int is_disable); |
| 712 | void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, |
| 713 | uint64_t *count); |
| 714 | uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); |
| 715 | void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, |
| 716 | uint32_t ficadl_val, uint32_t ficadh_val); |
| 717 | }; |
| 718 | /* Define the HW IP blocks will be used in driver , add more if necessary */ |
| 719 | enum amd_hw_ip_block_type { |
| 720 | GC_HWIP = 1, |
| 721 | HDP_HWIP, |
| 722 | SDMA0_HWIP, |
| 723 | SDMA1_HWIP, |
| 724 | SDMA2_HWIP, |
| 725 | SDMA3_HWIP, |
| 726 | SDMA4_HWIP, |
| 727 | SDMA5_HWIP, |
| 728 | SDMA6_HWIP, |
| 729 | SDMA7_HWIP, |
| 730 | MMHUB_HWIP, |
| 731 | ATHUB_HWIP, |
| 732 | NBIO_HWIP, |
| 733 | MP0_HWIP, |
| 734 | MP1_HWIP, |
| 735 | UVD_HWIP, |
| 736 | VCN_HWIP = UVD_HWIP, |
| 737 | VCE_HWIP, |
| 738 | DF_HWIP, |
| 739 | DCE_HWIP, |
| 740 | OSSSYS_HWIP, |
| 741 | SMUIO_HWIP, |
| 742 | PWR_HWIP, |
| 743 | NBIF_HWIP, |
| 744 | THM_HWIP, |
| 745 | CLK_HWIP, |
| 746 | MAX_HWIP |
| 747 | }; |
| 748 | |
| 749 | #define HWIP_MAX_INSTANCE 8 |
| 750 | |
| 751 | struct amd_powerplay { |
| 752 | void *pp_handle; |
| 753 | const struct amd_pm_funcs *pp_funcs; |
| 754 | }; |
| 755 | |
| 756 | #define AMDGPU_RESET_MAGIC_NUM 64 |
| 757 | #define AMDGPU_MAX_DF_PERFMONS 4 |
| 758 | struct amdgpu_device { |
| 759 | struct device *dev; |
| 760 | struct drm_device *ddev; |
| 761 | struct pci_dev *pdev; |
| 762 | |
| 763 | #ifdef CONFIG_DRM_AMD_ACP |
| 764 | struct amdgpu_acp acp; |
| 765 | #endif |
| 766 | |
| 767 | /* ASIC */ |
| 768 | enum amd_asic_type asic_type; |
| 769 | uint32_t family; |
| 770 | uint32_t rev_id; |
| 771 | uint32_t external_rev_id; |
| 772 | unsigned long flags; |
| 773 | int usec_timeout; |
| 774 | const struct amdgpu_asic_funcs *asic_funcs; |
| 775 | bool shutdown; |
| 776 | bool need_dma32; |
| 777 | bool need_swiotlb; |
| 778 | bool accel_working; |
| 779 | struct notifier_block acpi_nb; |
| 780 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; |
| 781 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
| 782 | unsigned debugfs_count; |
| 783 | #if defined(CONFIG_DEBUG_FS) |
| 784 | struct dentry *debugfs_preempt; |
| 785 | struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
| 786 | #endif |
| 787 | struct amdgpu_atif *atif; |
| 788 | struct amdgpu_atcs atcs; |
| 789 | struct mutex srbm_mutex; |
| 790 | /* GRBM index mutex. Protects concurrent access to GRBM index */ |
| 791 | struct mutex grbm_idx_mutex; |
| 792 | struct dev_pm_domain vga_pm_domain; |
| 793 | bool have_disp_power_ref; |
| 794 | bool have_atomics_support; |
| 795 | |
| 796 | /* BIOS */ |
| 797 | bool is_atom_fw; |
| 798 | uint8_t *bios; |
| 799 | uint32_t bios_size; |
| 800 | struct amdgpu_bo *stolen_vga_memory; |
| 801 | uint32_t bios_scratch_reg_offset; |
| 802 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; |
| 803 | |
| 804 | /* Register/doorbell mmio */ |
| 805 | resource_size_t rmmio_base; |
| 806 | resource_size_t rmmio_size; |
| 807 | void __iomem *rmmio; |
| 808 | /* protects concurrent MM_INDEX/DATA based register access */ |
| 809 | spinlock_t mmio_idx_lock; |
| 810 | struct amdgpu_mmio_remap rmmio_remap; |
| 811 | /* protects concurrent SMC based register access */ |
| 812 | spinlock_t smc_idx_lock; |
| 813 | amdgpu_rreg_t smc_rreg; |
| 814 | amdgpu_wreg_t smc_wreg; |
| 815 | /* protects concurrent PCIE register access */ |
| 816 | spinlock_t pcie_idx_lock; |
| 817 | amdgpu_rreg_t pcie_rreg; |
| 818 | amdgpu_wreg_t pcie_wreg; |
| 819 | amdgpu_rreg_t pciep_rreg; |
| 820 | amdgpu_wreg_t pciep_wreg; |
| 821 | /* protects concurrent UVD register access */ |
| 822 | spinlock_t uvd_ctx_idx_lock; |
| 823 | amdgpu_rreg_t uvd_ctx_rreg; |
| 824 | amdgpu_wreg_t uvd_ctx_wreg; |
| 825 | /* protects concurrent DIDT register access */ |
| 826 | spinlock_t didt_idx_lock; |
| 827 | amdgpu_rreg_t didt_rreg; |
| 828 | amdgpu_wreg_t didt_wreg; |
| 829 | /* protects concurrent gc_cac register access */ |
| 830 | spinlock_t gc_cac_idx_lock; |
| 831 | amdgpu_rreg_t gc_cac_rreg; |
| 832 | amdgpu_wreg_t gc_cac_wreg; |
| 833 | /* protects concurrent se_cac register access */ |
| 834 | spinlock_t se_cac_idx_lock; |
| 835 | amdgpu_rreg_t se_cac_rreg; |
| 836 | amdgpu_wreg_t se_cac_wreg; |
| 837 | /* protects concurrent ENDPOINT (audio) register access */ |
| 838 | spinlock_t audio_endpt_idx_lock; |
| 839 | amdgpu_block_rreg_t audio_endpt_rreg; |
| 840 | amdgpu_block_wreg_t audio_endpt_wreg; |
| 841 | void __iomem *rio_mem; |
| 842 | resource_size_t rio_mem_size; |
| 843 | struct amdgpu_doorbell doorbell; |
| 844 | |
| 845 | /* clock/pll info */ |
| 846 | struct amdgpu_clock clock; |
| 847 | |
| 848 | /* MC */ |
| 849 | struct amdgpu_gmc gmc; |
| 850 | struct amdgpu_gart gart; |
| 851 | dma_addr_t dummy_page_addr; |
| 852 | struct amdgpu_vm_manager vm_manager; |
| 853 | struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; |
| 854 | unsigned num_vmhubs; |
| 855 | |
| 856 | /* memory management */ |
| 857 | struct amdgpu_mman mman; |
| 858 | struct amdgpu_vram_scratch vram_scratch; |
| 859 | struct amdgpu_wb wb; |
| 860 | atomic64_t num_bytes_moved; |
| 861 | atomic64_t num_evictions; |
| 862 | atomic64_t num_vram_cpu_page_faults; |
| 863 | atomic_t gpu_reset_counter; |
| 864 | atomic_t vram_lost_counter; |
| 865 | |
| 866 | /* data for buffer migration throttling */ |
| 867 | struct { |
| 868 | spinlock_t lock; |
| 869 | s64 last_update_us; |
| 870 | s64 accum_us; /* accumulated microseconds */ |
| 871 | s64 accum_us_vis; /* for visible VRAM */ |
| 872 | u32 log2_max_MBps; |
| 873 | } mm_stats; |
| 874 | |
| 875 | /* display */ |
| 876 | bool enable_virtual_display; |
| 877 | struct amdgpu_mode_info mode_info; |
| 878 | /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ |
| 879 | struct work_struct hotplug_work; |
| 880 | struct amdgpu_irq_src crtc_irq; |
| 881 | struct amdgpu_irq_src vupdate_irq; |
| 882 | struct amdgpu_irq_src pageflip_irq; |
| 883 | struct amdgpu_irq_src hpd_irq; |
| 884 | |
| 885 | /* rings */ |
| 886 | u64 fence_context; |
| 887 | unsigned num_rings; |
| 888 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; |
| 889 | bool ib_pool_ready; |
| 890 | struct amdgpu_sa_manager ring_tmp_bo; |
| 891 | |
| 892 | /* interrupts */ |
| 893 | struct amdgpu_irq irq; |
| 894 | |
| 895 | /* powerplay */ |
| 896 | struct amd_powerplay powerplay; |
| 897 | bool pp_force_state_enabled; |
| 898 | |
| 899 | /* smu */ |
| 900 | struct smu_context smu; |
| 901 | |
| 902 | /* dpm */ |
| 903 | struct amdgpu_pm pm; |
| 904 | u32 cg_flags; |
| 905 | u32 pg_flags; |
| 906 | |
| 907 | /* gfx */ |
| 908 | struct amdgpu_gfx gfx; |
| 909 | |
| 910 | /* sdma */ |
| 911 | struct amdgpu_sdma sdma; |
| 912 | |
| 913 | /* uvd */ |
| 914 | struct amdgpu_uvd uvd; |
| 915 | |
| 916 | /* vce */ |
| 917 | struct amdgpu_vce vce; |
| 918 | |
| 919 | /* vcn */ |
| 920 | struct amdgpu_vcn vcn; |
| 921 | |
| 922 | /* firmwares */ |
| 923 | struct amdgpu_firmware firmware; |
| 924 | |
| 925 | /* PSP */ |
| 926 | struct psp_context psp; |
| 927 | |
| 928 | /* GDS */ |
| 929 | struct amdgpu_gds gds; |
| 930 | |
| 931 | /* KFD */ |
| 932 | struct amdgpu_kfd_dev kfd; |
| 933 | |
| 934 | /* display related functionality */ |
| 935 | struct amdgpu_display_manager dm; |
| 936 | |
| 937 | /* discovery */ |
| 938 | uint8_t *discovery; |
| 939 | |
| 940 | /* mes */ |
| 941 | bool enable_mes; |
| 942 | struct amdgpu_mes mes; |
| 943 | |
| 944 | struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; |
| 945 | int num_ip_blocks; |
| 946 | struct mutex mn_lock; |
| 947 | DECLARE_HASHTABLE(mn_hash, 7); |
| 948 | |
| 949 | /* tracking pinned memory */ |
| 950 | atomic64_t vram_pin_size; |
| 951 | atomic64_t visible_pin_size; |
| 952 | atomic64_t gart_pin_size; |
| 953 | |
| 954 | /* soc15 register offset based on ip, instance and segment */ |
| 955 | uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; |
| 956 | |
| 957 | const struct amdgpu_nbio_funcs *nbio_funcs; |
| 958 | const struct amdgpu_df_funcs *df_funcs; |
| 959 | |
| 960 | /* delayed work_func for deferring clockgating during resume */ |
| 961 | struct delayed_work delayed_init_work; |
| 962 | |
| 963 | struct amdgpu_virt virt; |
| 964 | /* firmware VRAM reservation */ |
| 965 | struct amdgpu_fw_vram_usage fw_vram_usage; |
| 966 | |
| 967 | /* link all shadow bo */ |
| 968 | struct list_head shadow_list; |
| 969 | struct mutex shadow_list_lock; |
| 970 | /* keep an lru list of rings by HW IP */ |
| 971 | struct list_head ring_lru_list; |
| 972 | spinlock_t ring_lru_list_lock; |
| 973 | |
| 974 | /* record hw reset is performed */ |
| 975 | bool has_hw_reset; |
| 976 | u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; |
| 977 | |
| 978 | /* s3/s4 mask */ |
| 979 | bool in_suspend; |
| 980 | |
| 981 | /* record last mm index being written through WREG32*/ |
| 982 | unsigned long last_mm_index; |
| 983 | bool in_gpu_reset; |
| 984 | struct mutex lock_reset; |
| 985 | struct amdgpu_doorbell_index doorbell_index; |
| 986 | |
| 987 | int asic_reset_res; |
| 988 | struct work_struct xgmi_reset_work; |
| 989 | |
| 990 | bool in_baco_reset; |
| 991 | |
| 992 | long gfx_timeout; |
| 993 | long sdma_timeout; |
| 994 | long video_timeout; |
| 995 | long compute_timeout; |
| 996 | |
| 997 | uint64_t unique_id; |
| 998 | uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; |
| 999 | }; |
| 1000 | |
| 1001 | static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) |
| 1002 | { |
| 1003 | return container_of(bdev, struct amdgpu_device, mman.bdev); |
| 1004 | } |
| 1005 | |
| 1006 | int amdgpu_device_init(struct amdgpu_device *adev, |
| 1007 | struct drm_device *ddev, |
| 1008 | struct pci_dev *pdev, |
| 1009 | uint32_t flags); |
| 1010 | void amdgpu_device_fini(struct amdgpu_device *adev); |
| 1011 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); |
| 1012 | |
| 1013 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
| 1014 | uint32_t acc_flags); |
| 1015 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
| 1016 | uint32_t acc_flags); |
| 1017 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); |
| 1018 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); |
| 1019 | |
| 1020 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); |
| 1021 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); |
| 1022 | |
| 1023 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); |
| 1024 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); |
| 1025 | |
| 1026 | int emu_soc_asic_init(struct amdgpu_device *adev); |
| 1027 | |
| 1028 | /* |
| 1029 | * Registers read & write functions. |
| 1030 | */ |
| 1031 | |
| 1032 | #define AMDGPU_REGS_IDX (1<<0) |
| 1033 | #define AMDGPU_REGS_NO_KIQ (1<<1) |
| 1034 | |
| 1035 | #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) |
| 1036 | #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) |
| 1037 | |
| 1038 | #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) |
| 1039 | #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) |
| 1040 | |
| 1041 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) |
| 1042 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) |
| 1043 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) |
| 1044 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) |
| 1045 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) |
| 1046 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1047 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1048 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) |
| 1049 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) |
| 1050 | #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) |
| 1051 | #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) |
| 1052 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) |
| 1053 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) |
| 1054 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) |
| 1055 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) |
| 1056 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) |
| 1057 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) |
| 1058 | #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) |
| 1059 | #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) |
| 1060 | #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) |
| 1061 | #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) |
| 1062 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) |
| 1063 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) |
| 1064 | #define WREG32_P(reg, val, mask) \ |
| 1065 | do { \ |
| 1066 | uint32_t tmp_ = RREG32(reg); \ |
| 1067 | tmp_ &= (mask); \ |
| 1068 | tmp_ |= ((val) & ~(mask)); \ |
| 1069 | WREG32(reg, tmp_); \ |
| 1070 | } while (0) |
| 1071 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
| 1072 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
| 1073 | #define WREG32_PLL_P(reg, val, mask) \ |
| 1074 | do { \ |
| 1075 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 1076 | tmp_ &= (mask); \ |
| 1077 | tmp_ |= ((val) & ~(mask)); \ |
| 1078 | WREG32_PLL(reg, tmp_); \ |
| 1079 | } while (0) |
| 1080 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) |
| 1081 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) |
| 1082 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) |
| 1083 | |
| 1084 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT |
| 1085 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK |
| 1086 | |
| 1087 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ |
| 1088 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ |
| 1089 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) |
| 1090 | |
| 1091 | #define REG_GET_FIELD(value, reg, field) \ |
| 1092 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) |
| 1093 | |
| 1094 | #define WREG32_FIELD(reg, field, val) \ |
| 1095 | WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) |
| 1096 | |
| 1097 | #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ |
| 1098 | WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) |
| 1099 | |
| 1100 | /* |
| 1101 | * BIOS helpers. |
| 1102 | */ |
| 1103 | #define RBIOS8(i) (adev->bios[i]) |
| 1104 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 1105 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 1106 | |
| 1107 | /* |
| 1108 | * ASICs macro. |
| 1109 | */ |
| 1110 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) |
| 1111 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) |
| 1112 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) |
| 1113 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) |
| 1114 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) |
| 1115 | #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) |
| 1116 | #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) |
| 1117 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) |
| 1118 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) |
| 1119 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
| 1120 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
| 1121 | #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) |
| 1122 | #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) |
| 1123 | #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) |
| 1124 | #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) |
| 1125 | #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) |
| 1126 | #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) |
| 1127 | #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) |
| 1128 | #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) |
| 1129 | |
| 1130 | /* Common functions */ |
| 1131 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); |
| 1132 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
| 1133 | struct amdgpu_job* job); |
| 1134 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); |
| 1135 | bool amdgpu_device_need_post(struct amdgpu_device *adev); |
| 1136 | |
| 1137 | void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, |
| 1138 | u64 num_vis_bytes); |
| 1139 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); |
| 1140 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
| 1141 | const u32 *registers, |
| 1142 | const u32 array_size); |
| 1143 | |
| 1144 | bool amdgpu_device_is_px(struct drm_device *dev); |
| 1145 | bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, |
| 1146 | struct amdgpu_device *peer_adev); |
| 1147 | |
| 1148 | /* atpx handler */ |
| 1149 | #if defined(CONFIG_VGA_SWITCHEROO) |
| 1150 | void amdgpu_register_atpx_handler(void); |
| 1151 | void amdgpu_unregister_atpx_handler(void); |
| 1152 | bool amdgpu_has_atpx_dgpu_power_cntl(void); |
| 1153 | bool amdgpu_is_atpx_hybrid(void); |
| 1154 | bool amdgpu_atpx_dgpu_req_power_for_displays(void); |
| 1155 | bool amdgpu_has_atpx(void); |
| 1156 | #else |
| 1157 | static inline void amdgpu_register_atpx_handler(void) {} |
| 1158 | static inline void amdgpu_unregister_atpx_handler(void) {} |
| 1159 | static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } |
| 1160 | static inline bool amdgpu_is_atpx_hybrid(void) { return false; } |
| 1161 | static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } |
| 1162 | static inline bool amdgpu_has_atpx(void) { return false; } |
| 1163 | #endif |
| 1164 | |
| 1165 | #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) |
| 1166 | void *amdgpu_atpx_get_dhandle(void); |
| 1167 | #else |
| 1168 | static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } |
| 1169 | #endif |
| 1170 | |
| 1171 | /* |
| 1172 | * KMS |
| 1173 | */ |
| 1174 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; |
| 1175 | extern const int amdgpu_max_kms_ioctl; |
| 1176 | |
| 1177 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); |
| 1178 | void amdgpu_driver_unload_kms(struct drm_device *dev); |
| 1179 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); |
| 1180 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); |
| 1181 | void amdgpu_driver_postclose_kms(struct drm_device *dev, |
| 1182 | struct drm_file *file_priv); |
| 1183 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev); |
| 1184 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); |
| 1185 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); |
| 1186 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
| 1187 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); |
| 1188 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); |
| 1189 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
| 1190 | unsigned long arg); |
| 1191 | |
| 1192 | /* |
| 1193 | * functions used by amdgpu_encoder.c |
| 1194 | */ |
| 1195 | struct amdgpu_afmt_acr { |
| 1196 | u32 clock; |
| 1197 | |
| 1198 | int n_32khz; |
| 1199 | int cts_32khz; |
| 1200 | |
| 1201 | int n_44_1khz; |
| 1202 | int cts_44_1khz; |
| 1203 | |
| 1204 | int n_48khz; |
| 1205 | int cts_48khz; |
| 1206 | |
| 1207 | }; |
| 1208 | |
| 1209 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); |
| 1210 | |
| 1211 | /* amdgpu_acpi.c */ |
| 1212 | #if defined(CONFIG_ACPI) |
| 1213 | int amdgpu_acpi_init(struct amdgpu_device *adev); |
| 1214 | void amdgpu_acpi_fini(struct amdgpu_device *adev); |
| 1215 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); |
| 1216 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, |
| 1217 | u8 perf_req, bool advertise); |
| 1218 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); |
| 1219 | |
| 1220 | void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, |
| 1221 | struct amdgpu_dm_backlight_caps *caps); |
| 1222 | #else |
| 1223 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } |
| 1224 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } |
| 1225 | #endif |
| 1226 | |
| 1227 | int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, |
| 1228 | uint64_t addr, struct amdgpu_bo **bo, |
| 1229 | struct amdgpu_bo_va_mapping **mapping); |
| 1230 | |
| 1231 | #if defined(CONFIG_DRM_AMD_DC) |
| 1232 | int amdgpu_dm_display_resume(struct amdgpu_device *adev ); |
| 1233 | #else |
| 1234 | static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } |
| 1235 | #endif |
| 1236 | |
| 1237 | |
| 1238 | void amdgpu_register_gpu_instance(struct amdgpu_device *adev); |
| 1239 | void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); |
| 1240 | |
| 1241 | #include "amdgpu_object.h" |
| 1242 | |
| 1243 | /* used by df_v3_6.c and amdgpu_pmu.c */ |
| 1244 | #define AMDGPU_PMU_ATTR(_name, _object) \ |
| 1245 | static ssize_t \ |
| 1246 | _name##_show(struct device *dev, \ |
| 1247 | struct device_attribute *attr, \ |
| 1248 | char *page) \ |
| 1249 | { \ |
| 1250 | BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ |
| 1251 | return sprintf(page, _object "\n"); \ |
| 1252 | } \ |
| 1253 | \ |
| 1254 | static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) |
| 1255 | |
| 1256 | #endif |
| 1257 | |