[linux-block.git] / drivers / gpio / gpio-stmpe.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/bitops.h>
#include <linux/cleanup.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mfd/stmpe.h>
#include <linux/property.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string_choices.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

enum { LSB, CSB, MSB };

#define CACHE_NR_REGS	3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS	(24 / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct mutex irq_lock;
	u32 norequest_mask;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which + (offset / 8)];
	u8 mask = BIT(offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_get_direction(struct gpio_chip *chip,
				    unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	if (ret & mask)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & BIT(offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
}

static const struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.get_direction		= stmpe_gpio_get_direction,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.request		= stmpe_gpio_request,
	.can_sleep		= true,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801 ||
	    stmpe_gpio->stmpe->partnum == STMPE1600)
		return 0;

	if (type & IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
		[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
		[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
		[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
		[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
		[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
		[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
		[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
		[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
		[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
	};
	int ret, i, j;

	/*
	 * STMPE1600: to be able to get IRQ from pins,
	 * a read must be done on GPMR register, or a write in
	 * GPSR or GPCR registers
	 */
	if (stmpe->partnum == STMPE1600) {
		ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
		if (ret < 0) {
			dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret);
			goto err;
		}
		ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
		if (ret < 0) {
			dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret);
			goto err;
		}
	}

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 and STMPE1600 don't have RE and FE registers */
		if ((stmpe->partnum == STMPE801 ||
		     stmpe->partnum == STMPE1600) &&
		     (i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
		}
	}

err:
	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	gpiochip_disable_irq(gc, offset);
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	gpiochip_enable_irq(gc, offset);
	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static void stmpe_dbg_show_one(struct seq_file *s,
			       struct gpio_chip *gc,
			       unsigned offset, unsigned gpio)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	bool val = !!stmpe_gpio_get(gc, offset);
	u8 bank = offset / 8;
	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
	u8 mask = BIT(offset % 8);
	int ret;
	u8 dir;

	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
	if (IS_ERR(label))
		return;

	ret = stmpe_reg_read(stmpe, dir_reg);
	if (ret < 0)
		return;
	dir = !!(ret & mask);

	if (dir) {
		seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
			   gpio, label ?: "(none)", str_hi_lo(val));
	} else {
		u8 edge_det_reg;
		u8 rise_reg;
		u8 fall_reg;
		u8 irqen_reg;

		static const char * const edge_det_values[] = {
			"edge-inactive",
			"edge-asserted",
			"not-supported"
		};
		static const char * const rise_values[] = {
			"no-rising-edge-detection",
			"rising-edge-detection",
			"not-supported"
		};
		static const char * const fall_values[] = {
			"no-falling-edge-detection",
			"falling-edge-detection",
			"not-supported"
		};
		#define NOT_SUPPORTED_IDX 2
		u8 edge_det = NOT_SUPPORTED_IDX;
		u8 rise = NOT_SUPPORTED_IDX;
		u8 fall = NOT_SUPPORTED_IDX;
		bool irqen;

		switch (stmpe->partnum) {
		case STMPE610:
		case STMPE811:
		case STMPE1601:
		case STMPE2401:
		case STMPE2403:
			edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
			ret = stmpe_reg_read(stmpe, edge_det_reg);
			if (ret < 0)
				return;
			edge_det = !!(ret & mask);
			fallthrough;
		case STMPE1801:
			rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
			fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];

			ret = stmpe_reg_read(stmpe, rise_reg);
			if (ret < 0)
				return;
			rise = !!(ret & mask);
			ret = stmpe_reg_read(stmpe, fall_reg);
			if (ret < 0)
				return;
			fall = !!(ret & mask);
			fallthrough;
		case STMPE801:
		case STMPE1600:
			irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
			break;

		default:
			return;
		}

		ret = stmpe_reg_read(stmpe, irqen_reg);
		if (ret < 0)
			return;
		irqen = !!(ret & mask);

		seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
			   gpio, label ?: "(none)",
			   str_hi_lo(val),
			   edge_det_values[edge_det],
			   irqen ? "IRQ-enabled" : "IRQ-disabled",
			   rise_values[rise],
			   fall_values[fall]);
	}
}

static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
	unsigned i;
	unsigned gpio = gc->base;

	for (i = 0; i < gc->ngpio; i++, gpio++) {
		stmpe_dbg_show_one(s, gc, i, gpio);
		seq_putc(s, '\n');
	}
}

static const struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
	.flags			= IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

#define MAX_GPIOS 24

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
	int ret;
	int i;

	/*
	 * the stmpe_block_read() call below, imposes to set statmsbreg
	 * with the register located at the lowest address. As STMPE1600
	 * variant is the only one which respect registers address's order
	 * (LSB regs located at lowest address than MSB ones) whereas all
	 * the others have a registers layout with MSB located before the
	 * LSB regs.
	 */
	if (stmpe->partnum == STMPE1600)
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	else
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
			   num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
							 line);

			handle_nested_irq(child_irq);
			stat &= ~BIT(bit);
		}

		/*
		 * interrupt status register write has no effect on
		 * 801/1801/1600, bits are cleared when read.
		 * Edge detect register is not present on 801/1600/1801
		 */
		if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
		    stmpe->partnum != STMPE1801) {
			stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
			stmpe_reg_write(stmpe,
					stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
					status[i]);
		}
	}

	return IRQ_HANDLED;
}

static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
				      unsigned long *valid_mask,
				      unsigned int ngpios)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int i;

	if (!stmpe_gpio->norequest_mask)
		return;

	/* Forbid unused lines to be mapped as IRQs */
	for (i = 0; i < sizeof(u32); i++) {
		if (stmpe_gpio->norequest_mask & BIT(i))
			clear_bit(i, valid_mask);
	}
}

static void stmpe_gpio_disable(void *stmpe)
{
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct stmpe *stmpe = dev_get_drvdata(dev->parent);
	struct stmpe_gpio *stmpe_gpio;
	int ret, irq;

	if (stmpe->num_gpios > MAX_GPIOS) {
		dev_err(dev, "Need to increase maximum GPIO number\n");
		return -EINVAL;
	}

	stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.parent = dev;
	stmpe_gpio->chip.base = -1;

	if (IS_ENABLED(CONFIG_DEBUG_FS))
                stmpe_gpio->chip.dbg_show = stmpe_dbg_show;

	device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
	if (ret)
		return ret;

	irq = platform_get_irq(pdev, 0);
	if (irq > 0) {
		struct gpio_irq_chip *girq;

		ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
						IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
		if (ret)
			return dev_err_probe(dev, ret, "unable to register IRQ handler\n");

		girq = &stmpe_gpio->chip.irq;
		gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
		/* This will let us handle the parent IRQ in the driver */
		girq->parent_handler = NULL;
		girq->num_parents = 0;
		girq->parents = NULL;
		girq->default_type = IRQ_TYPE_NONE;
		girq->handler = handle_simple_irq;
		girq->threaded = true;
		girq->init_valid_mask = stmpe_init_irq_valid_mask;
	}

	return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
}

static struct platform_driver stmpe_gpio_driver = {
	.driver = {
		.suppress_bind_attrs	= true,
		.name			= "stmpe-gpio",
	},
	.probe		= stmpe_gpio_probe,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);
Commit	Line	Data
	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Copyright (C) ST-Ericsson SA 2010
	4	*
	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
	8	#include <linux/bitops.h>
	9	#include <linux/cleanup.h>
	10	#include <linux/gpio/driver.h>
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/mfd/stmpe.h>
	14	#include <linux/property.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/seq_file.h>
	17	#include <linux/slab.h>
	18	#include <linux/string_choices.h>
	19
	20	/*
	21	* These registers are modified under the irq bus lock and cached to avoid
	22	* unnecessary writes in bus_sync_unlock.
	23	*/
	24	enum { REG_RE, REG_FE, REG_IE };
	25
	26	enum { LSB, CSB, MSB };
	27
	28	#define CACHE_NR_REGS 3
	29	/* No variant has more than 24 GPIOs */
	30	#define CACHE_NR_BANKS (24 / 8)
	31
	32	struct stmpe_gpio {
	33	struct gpio_chip chip;
	34	struct stmpe *stmpe;
	35	struct mutex irq_lock;
	36	u32 norequest_mask;
	37	/* Caches of interrupt control registers for bus_lock */
	38	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	39	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	40	};
	41
	42	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
	43	{
	44	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	45	struct stmpe *stmpe = stmpe_gpio->stmpe;
	46	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
	47	u8 mask = BIT(offset % 8);
	48	int ret;
	49
	50	ret = stmpe_reg_read(stmpe, reg);
	51	if (ret < 0)
	52	return ret;
	53
	54	return !!(ret & mask);
	55	}
	56
	57	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	58	{
	59	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	60	struct stmpe *stmpe = stmpe_gpio->stmpe;
	61	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	62	u8 reg = stmpe->regs[which + (offset / 8)];
	63	u8 mask = BIT(offset % 8);
	64
	65	/*
	66	* Some variants have single register for gpio set/clear functionality.
	67	* For them we need to write 0 to clear and 1 to set.
	68	*/
	69	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	70	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	71	else
	72	stmpe_reg_write(stmpe, reg, mask);
	73	}
	74
	75	static int stmpe_gpio_get_direction(struct gpio_chip *chip,
	76	unsigned offset)
	77	{
	78	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	79	struct stmpe *stmpe = stmpe_gpio->stmpe;
	80	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	81	u8 mask = BIT(offset % 8);
	82	int ret;
	83
	84	ret = stmpe_reg_read(stmpe, reg);
	85	if (ret < 0)
	86	return ret;
	87
	88	if (ret & mask)
	89	return GPIO_LINE_DIRECTION_OUT;
	90
	91	return GPIO_LINE_DIRECTION_IN;
	92	}
	93
	94	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	95	unsigned offset, int val)
	96	{
	97	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	98	struct stmpe *stmpe = stmpe_gpio->stmpe;
	99	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	100	u8 mask = BIT(offset % 8);
	101
	102	stmpe_gpio_set(chip, offset, val);
	103
	104	return stmpe_set_bits(stmpe, reg, mask, mask);
	105	}
	106
	107	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	108	unsigned offset)
	109	{
	110	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	111	struct stmpe *stmpe = stmpe_gpio->stmpe;
	112	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	113	u8 mask = BIT(offset % 8);
	114
	115	return stmpe_set_bits(stmpe, reg, mask, 0);
	116	}
	117
	118	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
	119	{
	120	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	121	struct stmpe *stmpe = stmpe_gpio->stmpe;
	122
	123	if (stmpe_gpio->norequest_mask & BIT(offset))
	124	return -EINVAL;
	125
	126	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
	127	}
	128
	129	static const struct gpio_chip template_chip = {
	130	.label = "stmpe",
	131	.owner = THIS_MODULE,
	132	.get_direction = stmpe_gpio_get_direction,
	133	.direction_input = stmpe_gpio_direction_input,
	134	.get = stmpe_gpio_get,
	135	.direction_output = stmpe_gpio_direction_output,
	136	.set = stmpe_gpio_set,
	137	.request = stmpe_gpio_request,
	138	.can_sleep = true,
	139	};
	140
	141	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
	142	{
	143	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	144	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	145	int offset = d->hwirq;
	146	int regoffset = offset / 8;
	147	int mask = BIT(offset % 8);
	148
	149	if (type & IRQ_TYPE_LEVEL_LOW \|\| type & IRQ_TYPE_LEVEL_HIGH)
	150	return -EINVAL;
	151
	152	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	153	if (stmpe_gpio->stmpe->partnum == STMPE801 \|\|
	154	stmpe_gpio->stmpe->partnum == STMPE1600)
	155	return 0;
	156
	157	if (type & IRQ_TYPE_EDGE_RISING)
	158	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	159	else
	160	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	161
	162	if (type & IRQ_TYPE_EDGE_FALLING)
	163	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	164	else
	165	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	166
	167	return 0;
	168	}
	169
	170	static void stmpe_gpio_irq_lock(struct irq_data *d)
	171	{
	172	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	173	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	174
	175	mutex_lock(&stmpe_gpio->irq_lock);
	176	}
	177
	178	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
	179	{
	180	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	181	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	182	struct stmpe *stmpe = stmpe_gpio->stmpe;
	183	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	184	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
	185	[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
	186	[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
	187	[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
	188	[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
	189	[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
	190	[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
	191	[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
	192	[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
	193	[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
	194	};
	195	int ret, i, j;
	196
	197	/*
	198	* STMPE1600: to be able to get IRQ from pins,
	199	* a read must be done on GPMR register, or a write in
	200	* GPSR or GPCR registers
	201	*/
	202	if (stmpe->partnum == STMPE1600) {
	203	ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
	204	if (ret < 0) {
	205	dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret);
	206	goto err;
	207	}
	208	ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
	209	if (ret < 0) {
	210	dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret);
	211	goto err;
	212	}
	213	}
	214
	215	for (i = 0; i < CACHE_NR_REGS; i++) {
	216	/* STMPE801 and STMPE1600 don't have RE and FE registers */
	217	if ((stmpe->partnum == STMPE801 \|\|
	218	stmpe->partnum == STMPE1600) &&
	219	(i != REG_IE))
	220	continue;
	221
	222	for (j = 0; j < num_banks; j++) {
	223	u8 old = stmpe_gpio->oldregs[i][j];
	224	u8 new = stmpe_gpio->regs[i][j];
	225
	226	if (new == old)
	227	continue;
	228
	229	stmpe_gpio->oldregs[i][j] = new;
	230	stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
	231	}
	232	}
	233
	234	err:
	235	mutex_unlock(&stmpe_gpio->irq_lock);
	236	}
	237
	238	static void stmpe_gpio_irq_mask(struct irq_data *d)
	239	{
	240	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	241	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	242	int offset = d->hwirq;
	243	int regoffset = offset / 8;
	244	int mask = BIT(offset % 8);
	245
	246	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	247	gpiochip_disable_irq(gc, offset);
	248	}
	249
	250	static void stmpe_gpio_irq_unmask(struct irq_data *d)
	251	{
	252	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	253	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	254	int offset = d->hwirq;
	255	int regoffset = offset / 8;
	256	int mask = BIT(offset % 8);
	257
	258	gpiochip_enable_irq(gc, offset);
	259	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	260	}
	261
	262	static void stmpe_dbg_show_one(struct seq_file *s,
	263	struct gpio_chip *gc,
	264	unsigned offset, unsigned gpio)
	265	{
	266	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	267	struct stmpe *stmpe = stmpe_gpio->stmpe;
	268	bool val = !!stmpe_gpio_get(gc, offset);
	269	u8 bank = offset / 8;
	270	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
	271	u8 mask = BIT(offset % 8);
	272	int ret;
	273	u8 dir;
	274
	275	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
	276	if (IS_ERR(label))
	277	return;
	278
	279	ret = stmpe_reg_read(stmpe, dir_reg);
	280	if (ret < 0)
	281	return;
	282	dir = !!(ret & mask);
	283
	284	if (dir) {
	285	seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
	286	gpio, label ?: "(none)", str_hi_lo(val));
	287	} else {
	288	u8 edge_det_reg;
	289	u8 rise_reg;
	290	u8 fall_reg;
	291	u8 irqen_reg;
	292
	293	static const char * const edge_det_values[] = {
	294	"edge-inactive",
	295	"edge-asserted",
	296	"not-supported"
	297	};
	298	static const char * const rise_values[] = {
	299	"no-rising-edge-detection",
	300	"rising-edge-detection",
	301	"not-supported"
	302	};
	303	static const char * const fall_values[] = {
	304	"no-falling-edge-detection",
	305	"falling-edge-detection",
	306	"not-supported"
	307	};
	308	#define NOT_SUPPORTED_IDX 2
	309	u8 edge_det = NOT_SUPPORTED_IDX;
	310	u8 rise = NOT_SUPPORTED_IDX;
	311	u8 fall = NOT_SUPPORTED_IDX;
	312	bool irqen;
	313
	314	switch (stmpe->partnum) {
	315	case STMPE610:
	316	case STMPE811:
	317	case STMPE1601:
	318	case STMPE2401:
	319	case STMPE2403:
	320	edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
	321	ret = stmpe_reg_read(stmpe, edge_det_reg);
	322	if (ret < 0)
	323	return;
	324	edge_det = !!(ret & mask);
	325	fallthrough;
	326	case STMPE1801:
	327	rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
	328	fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
	329
	330	ret = stmpe_reg_read(stmpe, rise_reg);
	331	if (ret < 0)
	332	return;
	333	rise = !!(ret & mask);
	334	ret = stmpe_reg_read(stmpe, fall_reg);
	335	if (ret < 0)
	336	return;
	337	fall = !!(ret & mask);
	338	fallthrough;
	339	case STMPE801:
	340	case STMPE1600:
	341	irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
	342	break;
	343
	344	default:
	345	return;
	346	}
	347
	348	ret = stmpe_reg_read(stmpe, irqen_reg);
	349	if (ret < 0)
	350	return;
	351	irqen = !!(ret & mask);
	352
	353	seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
	354	gpio, label ?: "(none)",
	355	str_hi_lo(val),
	356	edge_det_values[edge_det],
	357	irqen ? "IRQ-enabled" : "IRQ-disabled",
	358	rise_values[rise],
	359	fall_values[fall]);
	360	}
	361	}
	362
	363	static void stmpe_dbg_show(struct seq_file s, struct gpio_chip gc)
	364	{
	365	unsigned i;
	366	unsigned gpio = gc->base;
	367
	368	for (i = 0; i < gc->ngpio; i++, gpio++) {
	369	stmpe_dbg_show_one(s, gc, i, gpio);
	370	seq_putc(s, '\n');
	371	}
	372	}
	373
	374	static const struct irq_chip stmpe_gpio_irq_chip = {
	375	.name = "stmpe-gpio",
	376	.irq_bus_lock = stmpe_gpio_irq_lock,
	377	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	378	.irq_mask = stmpe_gpio_irq_mask,
	379	.irq_unmask = stmpe_gpio_irq_unmask,
	380	.irq_set_type = stmpe_gpio_irq_set_type,
	381	.flags = IRQCHIP_IMMUTABLE,
	382	GPIOCHIP_IRQ_RESOURCE_HELPERS,
	383	};
	384
	385	#define MAX_GPIOS 24
	386
	387	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	388	{
	389	struct stmpe_gpio *stmpe_gpio = dev;
	390	struct stmpe *stmpe = stmpe_gpio->stmpe;
	391	u8 statmsbreg;
	392	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	393	u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
	394	int ret;
	395	int i;
	396
	397	/*
	398	* the stmpe_block_read() call below, imposes to set statmsbreg
	399	* with the register located at the lowest address. As STMPE1600
	400	* variant is the only one which respect registers address's order
	401	* (LSB regs located at lowest address than MSB ones) whereas all
	402	* the others have a registers layout with MSB located before the
	403	* LSB regs.
	404	*/
	405	if (stmpe->partnum == STMPE1600)
	406	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	407	else
	408	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	409
	410	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	411	if (ret < 0)
	412	return IRQ_NONE;
	413
	414	for (i = 0; i < num_banks; i++) {
	415	int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
	416	num_banks - i - 1;
	417	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	418	unsigned int stat = status[i];
	419
	420	stat &= enabled;
	421	if (!stat)
	422	continue;
	423
	424	while (stat) {
	425	int bit = __ffs(stat);
	426	int line = bank * 8 + bit;
	427	int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
	428	line);
	429
	430	handle_nested_irq(child_irq);
	431	stat &= ~BIT(bit);
	432	}
	433
	434	/*
	435	* interrupt status register write has no effect on
	436	* 801/1801/1600, bits are cleared when read.
	437	* Edge detect register is not present on 801/1600/1801
	438	*/
	439	if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
	440	stmpe->partnum != STMPE1801) {
	441	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
	442	stmpe_reg_write(stmpe,
	443	stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
	444	status[i]);
	445	}
	446	}
	447
	448	return IRQ_HANDLED;
	449	}
	450
	451	static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
	452	unsigned long *valid_mask,
	453	unsigned int ngpios)
	454	{
	455	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	456	int i;
	457
	458	if (!stmpe_gpio->norequest_mask)
	459	return;
	460
	461	/* Forbid unused lines to be mapped as IRQs */
	462	for (i = 0; i < sizeof(u32); i++) {
	463	if (stmpe_gpio->norequest_mask & BIT(i))
	464	clear_bit(i, valid_mask);
	465	}
	466	}
	467
	468	static void stmpe_gpio_disable(void *stmpe)
	469	{
	470	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	471	}
	472
	473	static int stmpe_gpio_probe(struct platform_device *pdev)
	474	{
	475	struct device *dev = &pdev->dev;
	476	struct stmpe *stmpe = dev_get_drvdata(dev->parent);
	477	struct stmpe_gpio *stmpe_gpio;
	478	int ret, irq;
	479
	480	if (stmpe->num_gpios > MAX_GPIOS) {
	481	dev_err(dev, "Need to increase maximum GPIO number\n");
	482	return -EINVAL;
	483	}
	484
	485	stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
	486	if (!stmpe_gpio)
	487	return -ENOMEM;
	488
	489	mutex_init(&stmpe_gpio->irq_lock);
	490
	491	stmpe_gpio->stmpe = stmpe;
	492	stmpe_gpio->chip = template_chip;
	493	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	494	stmpe_gpio->chip.parent = dev;
	495	stmpe_gpio->chip.base = -1;
	496
	497	if (IS_ENABLED(CONFIG_DEBUG_FS))
	498	stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
	499
	500	device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);
	501
	502	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	503	if (ret)
	504	return ret;
	505
	506	ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
	507	if (ret)
	508	return ret;
	509
	510	irq = platform_get_irq(pdev, 0);
	511	if (irq > 0) {
	512	struct gpio_irq_chip *girq;
	513
	514	ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
	515	IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
	516	if (ret)
	517	return dev_err_probe(dev, ret, "unable to register IRQ handler\n");
	518
	519	girq = &stmpe_gpio->chip.irq;
	520	gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
	521	/* This will let us handle the parent IRQ in the driver */
	522	girq->parent_handler = NULL;
	523	girq->num_parents = 0;
	524	girq->parents = NULL;
	525	girq->default_type = IRQ_TYPE_NONE;
	526	girq->handler = handle_simple_irq;
	527	girq->threaded = true;
	528	girq->init_valid_mask = stmpe_init_irq_valid_mask;
	529	}
	530
	531	return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
	532	}
	533
	534	static struct platform_driver stmpe_gpio_driver = {
	535	.driver = {
	536	.suppress_bind_attrs = true,
	537	.name = "stmpe-gpio",
	538	},
	539	.probe = stmpe_gpio_probe,
	540	};
	541
	542	static int __init stmpe_gpio_init(void)
	543	{
	544	return platform_driver_register(&stmpe_gpio_driver);
	545	}
	546	subsys_initcall(stmpe_gpio_init);