[linux-2.6-block.git] / drivers / gpio / gpio-davinci.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006-2007 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/gpio/driver.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/spinlock.h>
#include <linux/pm_runtime.h>

#define MAX_REGS_BANKS 5
#define MAX_INT_PER_BANK 32

struct davinci_gpio_regs {
	u32	dir;
	u32	out_data;
	u32	set_data;
	u32	clr_data;
	u32	in_data;
	u32	set_rising;
	u32	clr_rising;
	u32	set_falling;
	u32	clr_falling;
	u32	intstat;
};

typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);

#define BINTEN	0x8 /* GPIO Interrupt Per-Bank Enable Register */

static void __iomem *gpio_base;
static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};

struct davinci_gpio_irq_data {
	void __iomem			*regs;
	struct davinci_gpio_controller	*chip;
	int				bank_num;
};

struct davinci_gpio_controller {
	struct gpio_chip	chip;
	struct irq_domain	*irq_domain;
	/* Serialize access to GPIO registers */
	spinlock_t		lock;
	void __iomem		*regs[MAX_REGS_BANKS];
	int			gpio_unbanked;
	int			irqs[MAX_INT_PER_BANK];
	struct davinci_gpio_regs context[MAX_REGS_BANKS];
	u32			binten_context;
};

static inline u32 __gpio_mask(unsigned gpio)
{
	return 1 << (gpio % 32);
}

static int davinci_gpio_irq_setup(struct platform_device *pdev);

/*--------------------------------------------------------------------------*/

/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
			unsigned offset, bool out, int value)
{
	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	struct davinci_gpio_regs __iomem *g;
	unsigned long flags;
	u32 temp;
	int bank = offset / 32;
	u32 mask = __gpio_mask(offset);

	g = d->regs[bank];
	spin_lock_irqsave(&d->lock, flags);
	temp = readl_relaxed(&g->dir);
	if (out) {
		temp &= ~mask;
		writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
	} else {
		temp |= mask;
	}
	writel_relaxed(temp, &g->dir);
	spin_unlock_irqrestore(&d->lock, flags);

	return 0;
}

static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
	return __davinci_direction(chip, offset, false, 0);
}

static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
	return __davinci_direction(chip, offset, true, value);
}

/*
 * Read the pin's value (works even if it's set up as output);
 * returns zero/nonzero.
 *
 * Note that changes are synched to the GPIO clock, so reading values back
 * right after you've set them may give old values.
 */
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	struct davinci_gpio_regs __iomem *g;
	int bank = offset / 32;

	g = d->regs[bank];

	return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
}

/*
 * Assuming the pin is muxed as a gpio output, set its output value.
 */
static int
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	struct davinci_gpio_regs __iomem *g;
	int bank = offset / 32;

	g = d->regs[bank];

	writel_relaxed(__gpio_mask(offset),
		       value ? &g->set_data : &g->clr_data);

	return 0;
}

static int davinci_gpio_probe(struct platform_device *pdev)
{
	int bank, i, ret = 0;
	unsigned int ngpio, nbank, nirq, gpio_unbanked;
	struct davinci_gpio_controller *chips;
	struct device *dev = &pdev->dev;

	/*
	 * The gpio banks conceptually expose a segmented bitmap,
	 * and "ngpio" is one more than the largest zero-based
	 * bit index that's valid.
	 */
	ret = device_property_read_u32(dev, "ti,ngpio", &ngpio);
	if (ret)
		return dev_err_probe(dev, ret, "Failed to get the number of GPIOs\n");
	if (ngpio == 0)
		return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n");

	/*
	 * If there are unbanked interrupts then the number of
	 * interrupts is equal to number of gpios else all are banked so
	 * number of interrupts is equal to number of banks(each with 16 gpios)
	 */
	ret = device_property_read_u32(dev, "ti,davinci-gpio-unbanked",
				       &gpio_unbanked);
	if (ret)
		return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs property\n");

	if (gpio_unbanked)
		nirq = gpio_unbanked;
	else
		nirq = DIV_ROUND_UP(ngpio, 16);

	if (nirq > MAX_INT_PER_BANK) {
		dev_err(dev, "Too many IRQs!\n");
		return -EINVAL;
	}

	chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
	if (!chips)
		return -ENOMEM;

	gpio_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(gpio_base))
		return PTR_ERR(gpio_base);

	for (i = 0; i < nirq; i++) {
		chips->irqs[i] = platform_get_irq(pdev, i);
		if (chips->irqs[i] < 0)
			return chips->irqs[i];
	}

	chips->chip.label = dev_name(dev);

	chips->chip.direction_input = davinci_direction_in;
	chips->chip.get = davinci_gpio_get;
	chips->chip.direction_output = davinci_direction_out;
	chips->chip.set_rv = davinci_gpio_set;

	chips->chip.ngpio = ngpio;
	chips->chip.base = -1;

#ifdef CONFIG_OF_GPIO
	chips->chip.parent = dev;
	chips->chip.request = gpiochip_generic_request;
	chips->chip.free = gpiochip_generic_free;
#endif
	spin_lock_init(&chips->lock);

	chips->gpio_unbanked = gpio_unbanked;

	nbank = DIV_ROUND_UP(ngpio, 32);
	for (bank = 0; bank < nbank; bank++)
		chips->regs[bank] = gpio_base + offset_array[bank];

	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, chips);
	ret = davinci_gpio_irq_setup(pdev);
	if (ret)
		return ret;

	return 0;
}

/*--------------------------------------------------------------------------*/
/*
 * We expect irqs will normally be set up as input pins, but they can also be
 * used as output pins ... which is convenient for testing.
 *
 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 * to their GPIOBNK0 irq, with a bit less overhead.
 *
 * All those INTC hookups (direct, plus several IRQ banks) can also
 * serve as EDMA event triggers.
 */

static void gpio_irq_mask(struct irq_data *d)
{
	struct davinci_gpio_controller *chips = irq_data_get_irq_chip_data(d);
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32];
	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);

	writel_relaxed(mask, &g->clr_falling);
	writel_relaxed(mask, &g->clr_rising);

	gpiochip_disable_irq(&chips->chip, hwirq);
}

static void gpio_irq_unmask(struct irq_data *d)
{
	struct davinci_gpio_controller *chips = irq_data_get_irq_chip_data(d);
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32];
	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
	unsigned status = irqd_get_trigger_type(d);

	gpiochip_enable_irq(&chips->chip, hwirq);

	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
	if (!status)
		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;

	if (status & IRQ_TYPE_EDGE_FALLING)
		writel_relaxed(mask, &g->set_falling);
	if (status & IRQ_TYPE_EDGE_RISING)
		writel_relaxed(mask, &g->set_rising);
}

static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{
	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	return 0;
}

static const struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.irq_unmask	= gpio_irq_unmask,
	.irq_mask	= gpio_irq_mask,
	.irq_set_type	= gpio_irq_type,
	.flags		= IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void gpio_irq_handler(struct irq_desc *desc)
{
	struct davinci_gpio_regs __iomem *g;
	u32 mask = 0xffff;
	int bank_num;
	struct davinci_gpio_controller *d;
	struct davinci_gpio_irq_data *irqdata;

	irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
	bank_num = irqdata->bank_num;
	g = irqdata->regs;
	d = irqdata->chip;

	/* we only care about one bank */
	if ((bank_num % 2) == 1)
		mask <<= 16;

	/* temporarily mask (level sensitive) parent IRQ */
	chained_irq_enter(irq_desc_get_chip(desc), desc);
	while (1) {
		u32		status;
		int		bit;
		irq_hw_number_t hw_irq;

		/* ack any irqs */
		status = readl_relaxed(&g->intstat) & mask;
		if (!status)
			break;
		writel_relaxed(status, &g->intstat);

		/* now demux them to the right lowlevel handler */

		while (status) {
			bit = __ffs(status);
			status &= ~BIT(bit);
			/* Max number of gpios per controller is 144 so
			 * hw_irq will be in [0..143]
			 */
			hw_irq = (bank_num / 2) * 32 + bit;

			generic_handle_domain_irq(d->irq_domain, hw_irq);
		}
	}
	chained_irq_exit(irq_desc_get_chip(desc), desc);
	/* now it may re-trigger */
}

static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = gpiochip_get_data(chip);

	if (d->irq_domain)
		return irq_create_mapping(d->irq_domain, offset);
	else
		return -ENXIO;
}

static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = gpiochip_get_data(chip);

	/*
	 * NOTE:  we assume for now that only irqs in the first gpio_chip
	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	 */
	if (offset < d->gpio_unbanked)
		return d->irqs[offset];
	else
		return -ENODEV;
}

static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
{
	struct davinci_gpio_controller *d;
	struct davinci_gpio_regs __iomem *g;
	u32 mask, i;

	d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
	g = (struct davinci_gpio_regs __iomem *)d->regs[0];
	for (i = 0; i < MAX_INT_PER_BANK; i++)
		if (data->irq == d->irqs[i])
			break;

	if (i == MAX_INT_PER_BANK)
		return -EINVAL;

	mask = __gpio_mask(i);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
		     ? &g->set_falling : &g->clr_falling);
	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
		     ? &g->set_rising : &g->clr_rising);

	return 0;
}

static int
davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
		     irq_hw_number_t hw)
{
	struct davinci_gpio_controller *chips =
				(struct davinci_gpio_controller *)d->host_data;

	irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
				"davinci_gpio");
	irq_set_irq_type(irq, IRQ_TYPE_NONE);
	irq_set_chip_data(irq, (__force void *)chips);
	irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));

	return 0;
}

static const struct irq_domain_ops davinci_gpio_irq_ops = {
	.map = davinci_gpio_irq_map,
	.xlate = irq_domain_xlate_onetwocell,
};

static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
{
	static struct irq_chip_type gpio_unbanked;

	gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));

	return &gpio_unbanked.chip;
};

static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
{
	static struct irq_chip gpio_unbanked;

	gpio_unbanked = *irq_get_chip(irq);
	return &gpio_unbanked;
};

static const struct of_device_id davinci_gpio_ids[];

/*
 * NOTE:  for suspend/resume, probably best to make a platform_device with
 * suspend_late/resume_resume calls hooking into results of the set_wake()
 * calls ... so if no gpios are wakeup events the clock can be disabled,
 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 * (dm6446) can be set appropriately for GPIOV33 pins.
 */

static int davinci_gpio_irq_setup(struct platform_device *pdev)
{
	unsigned	gpio, bank;
	int		irq;
	struct clk	*clk;
	u32		binten = 0;
	unsigned	ngpio;
	struct device *dev = &pdev->dev;
	struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
	struct davinci_gpio_regs __iomem *g;
	struct irq_domain	*irq_domain = NULL;
	struct irq_chip *irq_chip;
	struct davinci_gpio_irq_data *irqdata;
	gpio_get_irq_chip_cb_t gpio_get_irq_chip;

	/*
	 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
	 */
	gpio_get_irq_chip = davinci_gpio_get_irq_chip;
	if (dev->of_node)
		gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)device_get_match_data(dev);

	ngpio = chips->chip.ngpio;

	clk = devm_clk_get_enabled(dev, "gpio");
	if (IS_ERR(clk)) {
		dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
		return PTR_ERR(clk);
	}

	if (!chips->gpio_unbanked) {
		irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
		if (irq < 0) {
			dev_err(dev, "Couldn't allocate IRQ numbers\n");
			return irq;
		}

		irq_domain = irq_domain_create_legacy(of_fwnode_handle(dev->of_node), ngpio, irq, 0,
						      &davinci_gpio_irq_ops, chips);
		if (!irq_domain) {
			dev_err(dev, "Couldn't register an IRQ domain\n");
			return -ENODEV;
		}
	}

	/*
	 * Arrange gpiod_to_irq() support, handling either direct IRQs or
	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
	 * IRQs, while the others use banked IRQs, would need some setup
	 * tweaks to recognize hardware which can do that.
	 */
	chips->chip.to_irq = gpio_to_irq_banked;
	chips->irq_domain = irq_domain;

	/*
	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	 * controller only handling trigger modes.  We currently assume no
	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	 */
	if (chips->gpio_unbanked) {
		/* pass "bank 0" GPIO IRQs to AINTC */
		chips->chip.to_irq = gpio_to_irq_unbanked;

		binten = GENMASK(chips->gpio_unbanked / 16, 0);

		/* AINTC handles mask/unmask; GPIO handles triggering */
		irq = chips->irqs[0];
		irq_chip = gpio_get_irq_chip(irq);
		irq_chip->name = "GPIO-AINTC";
		irq_chip->irq_set_type = gpio_irq_type_unbanked;

		/* default trigger: both edges */
		g = chips->regs[0];
		writel_relaxed(~0, &g->set_falling);
		writel_relaxed(~0, &g->set_rising);

		/* set the direct IRQs up to use that irqchip */
		for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) {
			irq_set_chip(chips->irqs[gpio], irq_chip);
			irq_set_handler_data(chips->irqs[gpio], chips);
			irq_set_status_flags(chips->irqs[gpio],
					     IRQ_TYPE_EDGE_BOTH);
		}

		goto done;
	}

	/*
	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	 * then chain through our own handler.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
		/* disabled by default, enabled only as needed
		 * There are register sets for 32 GPIOs. 2 banks of 16
		 * GPIOs are covered by each set of registers hence divide by 2
		 */
		g = chips->regs[bank / 2];
		writel_relaxed(~0, &g->clr_falling);
		writel_relaxed(~0, &g->clr_rising);

		/*
		 * Each chip handles 32 gpios, and each irq bank consists of 16
		 * gpio irqs. Pass the irq bank's corresponding controller to
		 * the chained irq handler.
		 */
		irqdata = devm_kzalloc(&pdev->dev,
				       sizeof(struct
					      davinci_gpio_irq_data),
					      GFP_KERNEL);
		if (!irqdata)
			return -ENOMEM;

		irqdata->regs = g;
		irqdata->bank_num = bank;
		irqdata->chip = chips;

		irq_set_chained_handler_and_data(chips->irqs[bank],
						 gpio_irq_handler, irqdata);

		binten |= BIT(bank);
	}

done:
	/*
	 * BINTEN -- per-bank interrupt enable. genirq would also let these
	 * bits be set/cleared dynamically.
	 */
	writel_relaxed(binten, gpio_base + BINTEN);

	return 0;
}

static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
				      u32 nbank)
{
	struct davinci_gpio_regs __iomem *g;
	struct davinci_gpio_regs *context;
	u32 bank;
	void __iomem *base;

	base = chips->regs[0] - offset_array[0];
	chips->binten_context = readl_relaxed(base + BINTEN);

	for (bank = 0; bank < nbank; bank++) {
		g = chips->regs[bank];
		context = &chips->context[bank];
		context->dir = readl_relaxed(&g->dir);
		context->set_data = readl_relaxed(&g->set_data);
		context->set_rising = readl_relaxed(&g->set_rising);
		context->set_falling = readl_relaxed(&g->set_falling);
	}

	/* Clear all interrupt status registers */
	writel_relaxed(GENMASK(31, 0), &g->intstat);
}

static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
					 u32 nbank)
{
	struct davinci_gpio_regs __iomem *g;
	struct davinci_gpio_regs *context;
	u32 bank;
	void __iomem *base;

	base = chips->regs[0] - offset_array[0];

	if (readl_relaxed(base + BINTEN) != chips->binten_context)
		writel_relaxed(chips->binten_context, base + BINTEN);

	for (bank = 0; bank < nbank; bank++) {
		g = chips->regs[bank];
		context = &chips->context[bank];
		if (readl_relaxed(&g->dir) != context->dir)
			writel_relaxed(context->dir, &g->dir);
		if (readl_relaxed(&g->set_data) != context->set_data)
			writel_relaxed(context->set_data, &g->set_data);
		if (readl_relaxed(&g->set_rising) != context->set_rising)
			writel_relaxed(context->set_rising, &g->set_rising);
		if (readl_relaxed(&g->set_falling) != context->set_falling)
			writel_relaxed(context->set_falling, &g->set_falling);
	}
}

static int davinci_gpio_suspend(struct device *dev)
{
	struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);

	davinci_gpio_save_context(chips, nbank);

	return 0;
}

static int davinci_gpio_resume(struct device *dev)
{
	struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);

	davinci_gpio_restore_context(chips, nbank);

	return 0;
}

static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
			 davinci_gpio_resume);

static const struct of_device_id davinci_gpio_ids[] = {
	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
	{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, davinci_gpio_ids);

static struct platform_driver davinci_gpio_driver = {
	.probe		= davinci_gpio_probe,
	.driver		= {
		.name		= "davinci_gpio",
		.pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
		.of_match_table	= davinci_gpio_ids,
	},
};

/*
 * GPIO driver registration needs to be done before machine_init functions
 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
 */
static int __init davinci_gpio_drv_reg(void)
{
	return platform_driver_register(&davinci_gpio_driver);
}
postcore_initcall(davinci_gpio_drv_reg);

static void __exit davinci_gpio_exit(void)
{
	platform_driver_unregister(&davinci_gpio_driver);
}
module_exit(davinci_gpio_exit);

MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
MODULE_DESCRIPTION("DAVINCI GPIO driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:gpio-davinci");
Commit	Line	Data
	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* TI DaVinci GPIO Support
	4	*
	5	* Copyright (c) 2006-2007 David Brownell
	6	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	7	*/
	8
	9	#include <linux/gpio/driver.h>
	10	#include <linux/errno.h>
	11	#include <linux/kernel.h>
	12	#include <linux/clk.h>
	13	#include <linux/err.h>
	14	#include <linux/io.h>
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/module.h>
	18	#include <linux/pinctrl/consumer.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/property.h>
	21	#include <linux/irqchip/chained_irq.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/pm_runtime.h>
	24
	25	#define MAX_REGS_BANKS 5
	26	#define MAX_INT_PER_BANK 32
	27
	28	struct davinci_gpio_regs {
	29	u32 dir;
	30	u32 out_data;
	31	u32 set_data;
	32	u32 clr_data;
	33	u32 in_data;
	34	u32 set_rising;
	35	u32 clr_rising;
	36	u32 set_falling;
	37	u32 clr_falling;
	38	u32 intstat;
	39	};
	40
	41	typedef struct irq_chip (gpio_get_irq_chip_cb_t)(unsigned int irq);
	42
	43	#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
	44
	45	static void __iomem *gpio_base;
	46	static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
	47
	48	struct davinci_gpio_irq_data {
	49	void __iomem *regs;
	50	struct davinci_gpio_controller *chip;
	51	int bank_num;
	52	};
	53
	54	struct davinci_gpio_controller {
	55	struct gpio_chip chip;
	56	struct irq_domain *irq_domain;
	57	/* Serialize access to GPIO registers */
	58	spinlock_t lock;
	59	void __iomem *regs[MAX_REGS_BANKS];
	60	int gpio_unbanked;
	61	int irqs[MAX_INT_PER_BANK];
	62	struct davinci_gpio_regs context[MAX_REGS_BANKS];
	63	u32 binten_context;
	64	};
	65
	66	static inline u32 __gpio_mask(unsigned gpio)
	67	{
	68	return 1 << (gpio % 32);
	69	}
	70
	71	static int davinci_gpio_irq_setup(struct platform_device *pdev);
	72
	73	/--------------------------------------------------------------------------/
	74
	75	/* board setup code MUST setup pinmux and enable the GPIO clock. */
	76	static inline int __davinci_direction(struct gpio_chip *chip,
	77	unsigned offset, bool out, int value)
	78	{
	79	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	80	struct davinci_gpio_regs __iomem *g;
	81	unsigned long flags;
	82	u32 temp;
	83	int bank = offset / 32;
	84	u32 mask = __gpio_mask(offset);
	85
	86	g = d->regs[bank];
	87	spin_lock_irqsave(&d->lock, flags);
	88	temp = readl_relaxed(&g->dir);
	89	if (out) {
	90	temp &= ~mask;
	91	writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
	92	} else {
	93	temp \|= mask;
	94	}
	95	writel_relaxed(temp, &g->dir);
	96	spin_unlock_irqrestore(&d->lock, flags);
	97
	98	return 0;
	99	}
	100
	101	static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
	102	{
	103	return __davinci_direction(chip, offset, false, 0);
	104	}
	105
	106	static int
	107	davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
	108	{
	109	return __davinci_direction(chip, offset, true, value);
	110	}
	111
	112	/*
	113	* Read the pin's value (works even if it's set up as output);
	114	* returns zero/nonzero.
	115	*
	116	* Note that changes are synched to the GPIO clock, so reading values back
	117	* right after you've set them may give old values.
	118	*/
	119	static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
	120	{
	121	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	122	struct davinci_gpio_regs __iomem *g;
	123	int bank = offset / 32;
	124
	125	g = d->regs[bank];
	126
	127	return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
	128	}
	129
	130	/*
	131	* Assuming the pin is muxed as a gpio output, set its output value.
	132	*/
	133	static int
	134	davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	135	{
	136	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	137	struct davinci_gpio_regs __iomem *g;
	138	int bank = offset / 32;
	139
	140	g = d->regs[bank];
	141
	142	writel_relaxed(__gpio_mask(offset),
	143	value ? &g->set_data : &g->clr_data);
	144
	145	return 0;
	146	}
	147
	148	static int davinci_gpio_probe(struct platform_device *pdev)
	149	{
	150	int bank, i, ret = 0;
	151	unsigned int ngpio, nbank, nirq, gpio_unbanked;
	152	struct davinci_gpio_controller *chips;
	153	struct device *dev = &pdev->dev;
	154
	155	/*
	156	* The gpio banks conceptually expose a segmented bitmap,
	157	* and "ngpio" is one more than the largest zero-based
	158	* bit index that's valid.
	159	*/
	160	ret = device_property_read_u32(dev, "ti,ngpio", &ngpio);
	161	if (ret)
	162	return dev_err_probe(dev, ret, "Failed to get the number of GPIOs\n");
	163	if (ngpio == 0)
	164	return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n");
	165
	166	/*
	167	* If there are unbanked interrupts then the number of
	168	* interrupts is equal to number of gpios else all are banked so
	169	* number of interrupts is equal to number of banks(each with 16 gpios)
	170	*/
	171	ret = device_property_read_u32(dev, "ti,davinci-gpio-unbanked",
	172	&gpio_unbanked);
	173	if (ret)
	174	return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs property\n");
	175
	176	if (gpio_unbanked)
	177	nirq = gpio_unbanked;
	178	else
	179	nirq = DIV_ROUND_UP(ngpio, 16);
	180
	181	if (nirq > MAX_INT_PER_BANK) {
	182	dev_err(dev, "Too many IRQs!\n");
	183	return -EINVAL;
	184	}
	185
	186	chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
	187	if (!chips)
	188	return -ENOMEM;
	189
	190	gpio_base = devm_platform_ioremap_resource(pdev, 0);
	191	if (IS_ERR(gpio_base))
	192	return PTR_ERR(gpio_base);
	193
	194	for (i = 0; i < nirq; i++) {
	195	chips->irqs[i] = platform_get_irq(pdev, i);
	196	if (chips->irqs[i] < 0)
	197	return chips->irqs[i];
	198	}
	199
	200	chips->chip.label = dev_name(dev);
	201
	202	chips->chip.direction_input = davinci_direction_in;
	203	chips->chip.get = davinci_gpio_get;
	204	chips->chip.direction_output = davinci_direction_out;
	205	chips->chip.set_rv = davinci_gpio_set;
	206
	207	chips->chip.ngpio = ngpio;
	208	chips->chip.base = -1;
	209
	210	#ifdef CONFIG_OF_GPIO
	211	chips->chip.parent = dev;
	212	chips->chip.request = gpiochip_generic_request;
	213	chips->chip.free = gpiochip_generic_free;
	214	#endif
	215	spin_lock_init(&chips->lock);
	216
	217	chips->gpio_unbanked = gpio_unbanked;
	218
	219	nbank = DIV_ROUND_UP(ngpio, 32);
	220	for (bank = 0; bank < nbank; bank++)
	221	chips->regs[bank] = gpio_base + offset_array[bank];
	222
	223	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
	224	if (ret)
	225	return ret;
	226
	227	platform_set_drvdata(pdev, chips);
	228	ret = davinci_gpio_irq_setup(pdev);
	229	if (ret)
	230	return ret;
	231
	232	return 0;
	233	}
	234
	235	/--------------------------------------------------------------------------/
	236	/*
	237	* We expect irqs will normally be set up as input pins, but they can also be
	238	* used as output pins ... which is convenient for testing.
	239	*
	240	* NOTE: The first few GPIOs also have direct INTC hookups in addition
	241	* to their GPIOBNK0 irq, with a bit less overhead.
	242	*
	243	* All those INTC hookups (direct, plus several IRQ banks) can also
	244	* serve as EDMA event triggers.
	245	*/
	246
	247	static void gpio_irq_mask(struct irq_data *d)
	248	{
	249	struct davinci_gpio_controller *chips = irq_data_get_irq_chip_data(d);
	250	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	251	struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32];
	252	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
	253
	254	writel_relaxed(mask, &g->clr_falling);
	255	writel_relaxed(mask, &g->clr_rising);
	256
	257	gpiochip_disable_irq(&chips->chip, hwirq);
	258	}
	259
	260	static void gpio_irq_unmask(struct irq_data *d)
	261	{
	262	struct davinci_gpio_controller *chips = irq_data_get_irq_chip_data(d);
	263	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	264	struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32];
	265	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
	266	unsigned status = irqd_get_trigger_type(d);
	267
	268	gpiochip_enable_irq(&chips->chip, hwirq);
	269
	270	status &= IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	271	if (!status)
	272	status = IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	273
	274	if (status & IRQ_TYPE_EDGE_FALLING)
	275	writel_relaxed(mask, &g->set_falling);
	276	if (status & IRQ_TYPE_EDGE_RISING)
	277	writel_relaxed(mask, &g->set_rising);
	278	}
	279
	280	static int gpio_irq_type(struct irq_data *d, unsigned trigger)
	281	{
	282	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	283	return -EINVAL;
	284
	285	return 0;
	286	}
	287
	288	static const struct irq_chip gpio_irqchip = {
	289	.name = "GPIO",
	290	.irq_unmask = gpio_irq_unmask,
	291	.irq_mask = gpio_irq_mask,
	292	.irq_set_type = gpio_irq_type,
	293	.flags = IRQCHIP_IMMUTABLE \| IRQCHIP_SET_TYPE_MASKED \| IRQCHIP_SKIP_SET_WAKE,
	294	GPIOCHIP_IRQ_RESOURCE_HELPERS,
	295	};
	296
	297	static void gpio_irq_handler(struct irq_desc *desc)
	298	{
	299	struct davinci_gpio_regs __iomem *g;
	300	u32 mask = 0xffff;
	301	int bank_num;
	302	struct davinci_gpio_controller *d;
	303	struct davinci_gpio_irq_data *irqdata;
	304
	305	irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
	306	bank_num = irqdata->bank_num;
	307	g = irqdata->regs;
	308	d = irqdata->chip;
	309
	310	/* we only care about one bank */
	311	if ((bank_num % 2) == 1)
	312	mask <<= 16;
	313
	314	/* temporarily mask (level sensitive) parent IRQ */
	315	chained_irq_enter(irq_desc_get_chip(desc), desc);
	316	while (1) {
	317	u32 status;
	318	int bit;
	319	irq_hw_number_t hw_irq;
	320
	321	/* ack any irqs */
	322	status = readl_relaxed(&g->intstat) & mask;
	323	if (!status)
	324	break;
	325	writel_relaxed(status, &g->intstat);
	326
	327	/* now demux them to the right lowlevel handler */
	328
	329	while (status) {
	330	bit = __ffs(status);
	331	status &= ~BIT(bit);
	332	/* Max number of gpios per controller is 144 so
	333	* hw_irq will be in [0..143]
	334	*/
	335	hw_irq = (bank_num / 2) * 32 + bit;
	336
	337	generic_handle_domain_irq(d->irq_domain, hw_irq);
	338	}
	339	}
	340	chained_irq_exit(irq_desc_get_chip(desc), desc);
	341	/* now it may re-trigger */
	342	}
	343
	344	static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
	345	{
	346	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	347
	348	if (d->irq_domain)
	349	return irq_create_mapping(d->irq_domain, offset);
	350	else
	351	return -ENXIO;
	352	}
	353
	354	static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
	355	{
	356	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
	357
	358	/*
	359	* NOTE: we assume for now that only irqs in the first gpio_chip
	360	* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	361	*/
	362	if (offset < d->gpio_unbanked)
	363	return d->irqs[offset];
	364	else
	365	return -ENODEV;
	366	}
	367
	368	static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
	369	{
	370	struct davinci_gpio_controller *d;
	371	struct davinci_gpio_regs __iomem *g;
	372	u32 mask, i;
	373
	374	d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
	375	g = (struct davinci_gpio_regs __iomem *)d->regs[0];
	376	for (i = 0; i < MAX_INT_PER_BANK; i++)
	377	if (data->irq == d->irqs[i])
	378	break;
	379
	380	if (i == MAX_INT_PER_BANK)
	381	return -EINVAL;
	382
	383	mask = __gpio_mask(i);
	384
	385	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	386	return -EINVAL;
	387
	388	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	389	? &g->set_falling : &g->clr_falling);
	390	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	391	? &g->set_rising : &g->clr_rising);
	392
	393	return 0;
	394	}
	395
	396	static int
	397	davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
	398	irq_hw_number_t hw)
	399	{
	400	struct davinci_gpio_controller *chips =
	401	(struct davinci_gpio_controller *)d->host_data;
	402
	403	irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
	404	"davinci_gpio");
	405	irq_set_irq_type(irq, IRQ_TYPE_NONE);
	406	irq_set_chip_data(irq, (__force void *)chips);
	407	irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
	408
	409	return 0;
	410	}
	411
	412	static const struct irq_domain_ops davinci_gpio_irq_ops = {
	413	.map = davinci_gpio_irq_map,
	414	.xlate = irq_domain_xlate_onetwocell,
	415	};
	416
	417	static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
	418	{
	419	static struct irq_chip_type gpio_unbanked;
	420
	421	gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
	422
	423	return &gpio_unbanked.chip;
	424	};
	425
	426	static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
	427	{
	428	static struct irq_chip gpio_unbanked;
	429
	430	gpio_unbanked = *irq_get_chip(irq);
	431	return &gpio_unbanked;
	432	};
	433
	434	static const struct of_device_id davinci_gpio_ids[];
	435
	436	/*
	437	* NOTE: for suspend/resume, probably best to make a platform_device with
	438	* suspend_late/resume_resume calls hooking into results of the set_wake()
	439	* calls ... so if no gpios are wakeup events the clock can be disabled,
	440	* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
	441	* (dm6446) can be set appropriately for GPIOV33 pins.
	442	*/
	443
	444	static int davinci_gpio_irq_setup(struct platform_device *pdev)
	445	{
	446	unsigned gpio, bank;
	447	int irq;
	448	struct clk *clk;
	449	u32 binten = 0;
	450	unsigned ngpio;
	451	struct device *dev = &pdev->dev;
	452	struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
	453	struct davinci_gpio_regs __iomem *g;
	454	struct irq_domain *irq_domain = NULL;
	455	struct irq_chip *irq_chip;
	456	struct davinci_gpio_irq_data *irqdata;
	457	gpio_get_irq_chip_cb_t gpio_get_irq_chip;
	458
	459	/*
	460	* Use davinci_gpio_get_irq_chip by default to handle non DT cases
	461	*/
	462	gpio_get_irq_chip = davinci_gpio_get_irq_chip;
	463	if (dev->of_node)
	464	gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)device_get_match_data(dev);
	465
	466	ngpio = chips->chip.ngpio;
	467
	468	clk = devm_clk_get_enabled(dev, "gpio");
	469	if (IS_ERR(clk)) {
	470	dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
	471	return PTR_ERR(clk);
	472	}
	473
	474	if (!chips->gpio_unbanked) {
	475	irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
	476	if (irq < 0) {
	477	dev_err(dev, "Couldn't allocate IRQ numbers\n");
	478	return irq;
	479	}
	480
	481	irq_domain = irq_domain_create_legacy(of_fwnode_handle(dev->of_node), ngpio, irq, 0,
	482	&davinci_gpio_irq_ops, chips);
	483	if (!irq_domain) {
	484	dev_err(dev, "Couldn't register an IRQ domain\n");
	485	return -ENODEV;
	486	}
	487	}
	488
	489	/*
	490	* Arrange gpiod_to_irq() support, handling either direct IRQs or
	491	* banked IRQs. Having GPIOs in the first GPIO bank use direct
	492	* IRQs, while the others use banked IRQs, would need some setup
	493	* tweaks to recognize hardware which can do that.
	494	*/
	495	chips->chip.to_irq = gpio_to_irq_banked;
	496	chips->irq_domain = irq_domain;
	497
	498	/*
	499	* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	500	* controller only handling trigger modes. We currently assume no
	501	* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	502	*/
	503	if (chips->gpio_unbanked) {
	504	/* pass "bank 0" GPIO IRQs to AINTC */
	505	chips->chip.to_irq = gpio_to_irq_unbanked;
	506
	507	binten = GENMASK(chips->gpio_unbanked / 16, 0);
	508
	509	/* AINTC handles mask/unmask; GPIO handles triggering */
	510	irq = chips->irqs[0];
	511	irq_chip = gpio_get_irq_chip(irq);
	512	irq_chip->name = "GPIO-AINTC";
	513	irq_chip->irq_set_type = gpio_irq_type_unbanked;
	514
	515	/* default trigger: both edges */
	516	g = chips->regs[0];
	517	writel_relaxed(~0, &g->set_falling);
	518	writel_relaxed(~0, &g->set_rising);
	519
	520	/* set the direct IRQs up to use that irqchip */
	521	for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) {
	522	irq_set_chip(chips->irqs[gpio], irq_chip);
	523	irq_set_handler_data(chips->irqs[gpio], chips);
	524	irq_set_status_flags(chips->irqs[gpio],
	525	IRQ_TYPE_EDGE_BOTH);
	526	}
	527
	528	goto done;
	529	}
	530
	531	/*
	532	* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	533	* then chain through our own handler.
	534	*/
	535	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
	536	/* disabled by default, enabled only as needed
	537	* There are register sets for 32 GPIOs. 2 banks of 16
	538	* GPIOs are covered by each set of registers hence divide by 2
	539	*/
	540	g = chips->regs[bank / 2];
	541	writel_relaxed(~0, &g->clr_falling);
	542	writel_relaxed(~0, &g->clr_rising);
	543
	544	/*
	545	* Each chip handles 32 gpios, and each irq bank consists of 16
	546	* gpio irqs. Pass the irq bank's corresponding controller to
	547	* the chained irq handler.
	548	*/
	549	irqdata = devm_kzalloc(&pdev->dev,
	550	sizeof(struct
	551	davinci_gpio_irq_data),
	552	GFP_KERNEL);
	553	if (!irqdata)
	554	return -ENOMEM;
	555
	556	irqdata->regs = g;
	557	irqdata->bank_num = bank;
	558	irqdata->chip = chips;
	559
	560	irq_set_chained_handler_and_data(chips->irqs[bank],
	561	gpio_irq_handler, irqdata);
	562
	563	binten \|= BIT(bank);
	564	}
	565
	566	done:
	567	/*
	568	* BINTEN -- per-bank interrupt enable. genirq would also let these
	569	* bits be set/cleared dynamically.
	570	*/
	571	writel_relaxed(binten, gpio_base + BINTEN);
	572
	573	return 0;
	574	}
	575
	576	static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
	577	u32 nbank)
	578	{
	579	struct davinci_gpio_regs __iomem *g;
	580	struct davinci_gpio_regs *context;
	581	u32 bank;
	582	void __iomem *base;
	583
	584	base = chips->regs[0] - offset_array[0];
	585	chips->binten_context = readl_relaxed(base + BINTEN);
	586
	587	for (bank = 0; bank < nbank; bank++) {
	588	g = chips->regs[bank];
	589	context = &chips->context[bank];
	590	context->dir = readl_relaxed(&g->dir);
	591	context->set_data = readl_relaxed(&g->set_data);
	592	context->set_rising = readl_relaxed(&g->set_rising);
	593	context->set_falling = readl_relaxed(&g->set_falling);
	594	}
	595
	596	/* Clear all interrupt status registers */
	597	writel_relaxed(GENMASK(31, 0), &g->intstat);
	598	}
	599
	600	static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
	601	u32 nbank)
	602	{
	603	struct davinci_gpio_regs __iomem *g;
	604	struct davinci_gpio_regs *context;
	605	u32 bank;
	606	void __iomem *base;
	607
	608	base = chips->regs[0] - offset_array[0];
	609
	610	if (readl_relaxed(base + BINTEN) != chips->binten_context)
	611	writel_relaxed(chips->binten_context, base + BINTEN);
	612
	613	for (bank = 0; bank < nbank; bank++) {
	614	g = chips->regs[bank];
	615	context = &chips->context[bank];
	616	if (readl_relaxed(&g->dir) != context->dir)
	617	writel_relaxed(context->dir, &g->dir);
	618	if (readl_relaxed(&g->set_data) != context->set_data)
	619	writel_relaxed(context->set_data, &g->set_data);
	620	if (readl_relaxed(&g->set_rising) != context->set_rising)
	621	writel_relaxed(context->set_rising, &g->set_rising);
	622	if (readl_relaxed(&g->set_falling) != context->set_falling)
	623	writel_relaxed(context->set_falling, &g->set_falling);
	624	}
	625	}
	626
	627	static int davinci_gpio_suspend(struct device *dev)
	628	{
	629	struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
	630	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);
	631
	632	davinci_gpio_save_context(chips, nbank);
	633
	634	return 0;
	635	}
	636
	637	static int davinci_gpio_resume(struct device *dev)
	638	{
	639	struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
	640	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);
	641
	642	davinci_gpio_restore_context(chips, nbank);
	643
	644	return 0;
	645	}
	646
	647	static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
	648	davinci_gpio_resume);
	649
	650	static const struct of_device_id davinci_gpio_ids[] = {
	651	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
	652	{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
	653	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
	654	{ /* sentinel */ },
	655	};
	656	MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
	657
	658	static struct platform_driver davinci_gpio_driver = {
	659	.probe = davinci_gpio_probe,
	660	.driver = {
	661	.name = "davinci_gpio",
	662	.pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
	663	.of_match_table = davinci_gpio_ids,
	664	},
	665	};
	666
	667	/*
	668	* GPIO driver registration needs to be done before machine_init functions
	669	* access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
	670	*/
	671	static int __init davinci_gpio_drv_reg(void)
	672	{
	673	return platform_driver_register(&davinci_gpio_driver);
	674	}
	675	postcore_initcall(davinci_gpio_drv_reg);
	676
	677	static void __exit davinci_gpio_exit(void)
	678	{
	679	platform_driver_unregister(&davinci_gpio_driver);
	680	}
	681	module_exit(davinci_gpio_exit);
	682
	683	MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
	684	MODULE_DESCRIPTION("DAVINCI GPIO driver");
	685	MODULE_LICENSE("GPL");
	686	MODULE_ALIAS("platform:gpio-davinci");