[linux-block.git] / drivers / clocksource / timer-riscv.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2012 Regents of the University of California
 * Copyright (C) 2017 SiFive
 *
 * All RISC-V systems have a timer attached to every hart.  These timers can
 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
 * setup events, or directly accessed using MMIO registers.
 */

#define pr_fmt(fmt) "riscv-timer: " fmt

#include <linux/acpi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/sched_clock.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/limits.h>
#include <clocksource/timer-riscv.h>
#include <asm/smp.h>
#include <asm/cpufeature.h>
#include <asm/sbi.h>
#include <asm/timex.h>

static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
static bool riscv_timer_cannot_wake_cpu;

static void riscv_clock_event_stop(void)
{
	if (static_branch_likely(&riscv_sstc_available)) {
		csr_write(CSR_STIMECMP, ULONG_MAX);
		if (IS_ENABLED(CONFIG_32BIT))
			csr_write(CSR_STIMECMPH, ULONG_MAX);
	} else {
		sbi_set_timer(U64_MAX);
	}
}

static int riscv_clock_next_event(unsigned long delta,
		struct clock_event_device *ce)
{
	u64 next_tval = get_cycles64() + delta;

	if (static_branch_likely(&riscv_sstc_available)) {
#if defined(CONFIG_32BIT)
		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
		csr_write(CSR_STIMECMPH, next_tval >> 32);
#else
		csr_write(CSR_STIMECMP, next_tval);
#endif
	} else
		sbi_set_timer(next_tval);

	return 0;
}

static int riscv_clock_shutdown(struct clock_event_device *evt)
{
	riscv_clock_event_stop();
	return 0;
}

static unsigned int riscv_clock_event_irq;
static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
	.name			= "riscv_timer_clockevent",
	.features		= CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 100,
	.set_next_event		= riscv_clock_next_event,
	.set_state_shutdown	= riscv_clock_shutdown,
};

/*
 * It is guaranteed that all the timers across all the harts are synchronized
 * within one tick of each other, so while this could technically go
 * backwards when hopping between CPUs, practically it won't happen.
 */
static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
{
	return get_cycles64();
}

static u64 notrace riscv_sched_clock(void)
{
	return get_cycles64();
}

static struct clocksource riscv_clocksource = {
	.name		= "riscv_clocksource",
	.rating		= 400,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.read		= riscv_clocksource_rdtime,
#if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
	.vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
#else
	.vdso_clock_mode = VDSO_CLOCKMODE_NONE,
#endif
};

static int riscv_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);

	ce->cpumask = cpumask_of(cpu);
	ce->irq = riscv_clock_event_irq;
	if (riscv_timer_cannot_wake_cpu)
		ce->features |= CLOCK_EVT_FEAT_C3STOP;
	if (static_branch_likely(&riscv_sstc_available))
		ce->rating = 450;
	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);

	enable_percpu_irq(riscv_clock_event_irq,
			  irq_get_trigger_type(riscv_clock_event_irq));
	return 0;
}

static int riscv_timer_dying_cpu(unsigned int cpu)
{
	disable_percpu_irq(riscv_clock_event_irq);
	return 0;
}

void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
{
	*mult = riscv_clocksource.mult;
	*shift = riscv_clocksource.shift;
}
EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);

/* called directly from the low-level interrupt handler */
static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);

	riscv_clock_event_stop();
	evdev->event_handler(evdev);

	return IRQ_HANDLED;
}

static int __init riscv_timer_init_common(void)
{
	int error;
	struct irq_domain *domain;
	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();

	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
	if (!domain) {
		pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
		       intc_fwnode);
		return -ENODEV;
	}

	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
	if (!riscv_clock_event_irq) {
		pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
		return -ENODEV;
	}

	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
	if (error) {
		pr_err("RISCV timer registration failed [%d]\n", error);
		return error;
	}

	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);

	error = request_percpu_irq(riscv_clock_event_irq,
				    riscv_timer_interrupt,
				    "riscv-timer", &riscv_clock_event);
	if (error) {
		pr_err("registering percpu irq failed [%d]\n", error);
		return error;
	}

	if (riscv_isa_extension_available(NULL, SSTC)) {
		pr_info("Timer interrupt in S-mode is available via sstc extension\n");
		static_branch_enable(&riscv_sstc_available);
	}

	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
			 "clockevents/riscv/timer:starting",
			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
	if (error)
		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
		       error);

	return error;
}

static int __init riscv_timer_init_dt(struct device_node *n)
{
	int cpuid, error;
	unsigned long hartid;
	struct device_node *child;

	error = riscv_of_processor_hartid(n, &hartid);
	if (error < 0) {
		pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
			n, hartid);
		return error;
	}

	cpuid = riscv_hartid_to_cpuid(hartid);
	if (cpuid < 0) {
		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
		return cpuid;
	}

	if (cpuid != smp_processor_id())
		return 0;

	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
	if (child) {
		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
					"riscv,timer-cannot-wake-cpu");
		of_node_put(child);
	}

	return riscv_timer_init_common();
}

TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);

#ifdef CONFIG_ACPI
static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
{
	struct acpi_table_rhct *rhct = (struct acpi_table_rhct *)table;

	riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU;

	return riscv_timer_init_common();
}

TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);

#endif
Commit	Line	Data
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2012 Regents of the University of California
	4	* Copyright (C) 2017 SiFive
	5	*
	6	* All RISC-V systems have a timer attached to every hart. These timers can
	7	* either be read from the "time" and "timeh" CSRs, and can use the SBI to
	8	* setup events, or directly accessed using MMIO registers.
	9	*/
	10
	11	#define pr_fmt(fmt) "riscv-timer: " fmt
	12
	13	#include <linux/acpi.h>
	14	#include <linux/clocksource.h>
	15	#include <linux/clockchips.h>
	16	#include <linux/cpu.h>
	17	#include <linux/delay.h>
	18	#include <linux/irq.h>
	19	#include <linux/irqdomain.h>
	20	#include <linux/module.h>
	21	#include <linux/sched_clock.h>
	22	#include <linux/io-64-nonatomic-lo-hi.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/limits.h>
	26	#include <clocksource/timer-riscv.h>
	27	#include <asm/smp.h>
	28	#include <asm/cpufeature.h>
	29	#include <asm/sbi.h>
	30	#include <asm/timex.h>
	31
	32	static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
	33	static bool riscv_timer_cannot_wake_cpu;
	34
	35	static void riscv_clock_event_stop(void)
	36	{
	37	if (static_branch_likely(&riscv_sstc_available)) {
	38	csr_write(CSR_STIMECMP, ULONG_MAX);
	39	if (IS_ENABLED(CONFIG_32BIT))
	40	csr_write(CSR_STIMECMPH, ULONG_MAX);
	41	} else {
	42	sbi_set_timer(U64_MAX);
	43	}
	44	}
	45
	46	static int riscv_clock_next_event(unsigned long delta,
	47	struct clock_event_device *ce)
	48	{
	49	u64 next_tval = get_cycles64() + delta;
	50
	51	if (static_branch_likely(&riscv_sstc_available)) {
	52	#if defined(CONFIG_32BIT)
	53	csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
	54	csr_write(CSR_STIMECMPH, next_tval >> 32);
	55	#else
	56	csr_write(CSR_STIMECMP, next_tval);
	57	#endif
	58	} else
	59	sbi_set_timer(next_tval);
	60
	61	return 0;
	62	}
	63
	64	static int riscv_clock_shutdown(struct clock_event_device *evt)
	65	{
	66	riscv_clock_event_stop();
	67	return 0;
	68	}
	69
	70	static unsigned int riscv_clock_event_irq;
	71	static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
	72	.name = "riscv_timer_clockevent",
	73	.features = CLOCK_EVT_FEAT_ONESHOT,
	74	.rating = 100,
	75	.set_next_event = riscv_clock_next_event,
	76	.set_state_shutdown = riscv_clock_shutdown,
	77	};
	78
	79	/*
	80	* It is guaranteed that all the timers across all the harts are synchronized
	81	* within one tick of each other, so while this could technically go
	82	* backwards when hopping between CPUs, practically it won't happen.
	83	*/
	84	static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
	85	{
	86	return get_cycles64();
	87	}
	88
	89	static u64 notrace riscv_sched_clock(void)
	90	{
	91	return get_cycles64();
	92	}
	93
	94	static struct clocksource riscv_clocksource = {
	95	.name = "riscv_clocksource",
	96	.rating = 400,
	97	.mask = CLOCKSOURCE_MASK(64),
	98	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	99	.read = riscv_clocksource_rdtime,
	100	#if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
	101	.vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
	102	#else
	103	.vdso_clock_mode = VDSO_CLOCKMODE_NONE,
	104	#endif
	105	};
	106
	107	static int riscv_timer_starting_cpu(unsigned int cpu)
	108	{
	109	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
	110
	111	ce->cpumask = cpumask_of(cpu);
	112	ce->irq = riscv_clock_event_irq;
	113	if (riscv_timer_cannot_wake_cpu)
	114	ce->features \|= CLOCK_EVT_FEAT_C3STOP;
	115	if (static_branch_likely(&riscv_sstc_available))
	116	ce->rating = 450;
	117	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
	118
	119	enable_percpu_irq(riscv_clock_event_irq,
	120	irq_get_trigger_type(riscv_clock_event_irq));
	121	return 0;
	122	}
	123
	124	static int riscv_timer_dying_cpu(unsigned int cpu)
	125	{
	126	disable_percpu_irq(riscv_clock_event_irq);
	127	return 0;
	128	}
	129
	130	void riscv_cs_get_mult_shift(u32 mult, u32 shift)
	131	{
	132	*mult = riscv_clocksource.mult;
	133	*shift = riscv_clocksource.shift;
	134	}
	135	EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
	136
	137	/* called directly from the low-level interrupt handler */
	138	static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
	139	{
	140	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
	141
	142	riscv_clock_event_stop();
	143	evdev->event_handler(evdev);
	144
	145	return IRQ_HANDLED;
	146	}
	147
	148	static int __init riscv_timer_init_common(void)
	149	{
	150	int error;
	151	struct irq_domain *domain;
	152	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
	153
	154	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
	155	if (!domain) {
	156	pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
	157	intc_fwnode);
	158	return -ENODEV;
	159	}
	160
	161	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
	162	if (!riscv_clock_event_irq) {
	163	pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
	164	return -ENODEV;
	165	}
	166
	167	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
	168	if (error) {
	169	pr_err("RISCV timer registration failed [%d]\n", error);
	170	return error;
	171	}
	172
	173	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
	174
	175	error = request_percpu_irq(riscv_clock_event_irq,
	176	riscv_timer_interrupt,
	177	"riscv-timer", &riscv_clock_event);
	178	if (error) {
	179	pr_err("registering percpu irq failed [%d]\n", error);
	180	return error;
	181	}
	182
	183	if (riscv_isa_extension_available(NULL, SSTC)) {
	184	pr_info("Timer interrupt in S-mode is available via sstc extension\n");
	185	static_branch_enable(&riscv_sstc_available);
	186	}
	187
	188	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
	189	"clockevents/riscv/timer:starting",
	190	riscv_timer_starting_cpu, riscv_timer_dying_cpu);
	191	if (error)
	192	pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
	193	error);
	194
	195	return error;
	196	}
	197
	198	static int __init riscv_timer_init_dt(struct device_node *n)
	199	{
	200	int cpuid, error;
	201	unsigned long hartid;
	202	struct device_node *child;
	203
	204	error = riscv_of_processor_hartid(n, &hartid);
	205	if (error < 0) {
	206	pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
	207	n, hartid);
	208	return error;
	209	}
	210
	211	cpuid = riscv_hartid_to_cpuid(hartid);
	212	if (cpuid < 0) {
	213	pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
	214	return cpuid;
	215	}
	216
	217	if (cpuid != smp_processor_id())
	218	return 0;
	219
	220	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
	221	if (child) {
	222	riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
	223	"riscv,timer-cannot-wake-cpu");
	224	of_node_put(child);
	225	}
	226
	227	return riscv_timer_init_common();
	228	}
	229
	230	TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
	231
	232	#ifdef CONFIG_ACPI
	233	static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
	234	{
	235	struct acpi_table_rhct rhct = (struct acpi_table_rhct )table;
	236
	237	riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU;
	238
	239	return riscv_timer_init_common();
	240	}
	241
	242	TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);
	243
	244	#endif