[linux-2.6-block.git] / drivers / clocksource / arc_timer.c

/*
 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
 * programmed to go from @count to @limit and optionally interrupt.
 * We've designated TIMER0 for clockevents and TIMER1 for clocksource
 *
 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
 * which are suitable for UP and SMP based clocksources respectively
 */

#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>

#include <soc/arc/timers.h>
#include <soc/arc/mcip.h>


static unsigned long arc_timer_freq;

static int noinline arc_get_timer_clk(struct device_node *node)
{
	struct clk *clk;
	int ret;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("timer missing clk\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Couldn't enable parent clk\n");
		return ret;
	}

	arc_timer_freq = clk_get_rate(clk);

	return 0;
}

/********** Clock Source Device *********/

#ifdef CONFIG_ARC_TIMERS_64BIT

static u64 arc_read_gfrc(struct clocksource *cs)
{
	unsigned long flags;
	u32 l, h;

	/*
	 * From a programming model pov, there seems to be just one instance of
	 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's
	 * an instance PER ARC CORE (not per cluster), and there are dedicated
	 * hardware decode logic (per core) inside ARConnect to handle
	 * simultaneous read/write accesses from cores via those two registers.
	 * So several concurrent commands to ARConnect are OK if they are
	 * trying to access two different sub-components (like GFRC,
	 * inter-core interrupt, etc...). HW also supports simultaneously
	 * accessing GFRC by multiple cores.
	 * That's why it is safe to disable hard interrupts on the local CPU
	 * before access to GFRC instead of taking global MCIP spinlock
	 * defined in arch/arc/kernel/mcip.c
	 */
	local_irq_save(flags);

	__mcip_cmd(CMD_GFRC_READ_LO, 0);
	l = read_aux_reg(ARC_REG_MCIP_READBACK);

	__mcip_cmd(CMD_GFRC_READ_HI, 0);
	h = read_aux_reg(ARC_REG_MCIP_READBACK);

	local_irq_restore(flags);

	return (((u64)h) << 32) | l;
}

static struct clocksource arc_counter_gfrc = {
	.name   = "ARConnect GFRC",
	.rating = 400,
	.read   = arc_read_gfrc,
	.mask   = CLOCKSOURCE_MASK(64),
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init arc_cs_setup_gfrc(struct device_node *node)
{
	struct mcip_bcr mp;
	int ret;

	READ_BCR(ARC_REG_MCIP_BCR, mp);
	if (!mp.gfrc) {
		pr_warn("Global-64-bit-Ctr clocksource not detected\n");
		return -ENXIO;
	}

	ret = arc_get_timer_clk(node);
	if (ret)
		return ret;

	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
}
TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);

#define AUX_RTC_CTRL	0x103
#define AUX_RTC_LOW	0x104
#define AUX_RTC_HIGH	0x105

static u64 arc_read_rtc(struct clocksource *cs)
{
	unsigned long status;
	u32 l, h;

	/*
	 * hardware has an internal state machine which tracks readout of
	 * low/high and updates the CTRL.status if
	 *  - interrupt/exception taken between the two reads
	 *  - high increments after low has been read
	 */
	do {
		l = read_aux_reg(AUX_RTC_LOW);
		h = read_aux_reg(AUX_RTC_HIGH);
		status = read_aux_reg(AUX_RTC_CTRL);
	} while (!(status & _BITUL(31)));

	return (((u64)h) << 32) | l;
}

static struct clocksource arc_counter_rtc = {
	.name   = "ARCv2 RTC",
	.rating = 350,
	.read   = arc_read_rtc,
	.mask   = CLOCKSOURCE_MASK(64),
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init arc_cs_setup_rtc(struct device_node *node)
{
	struct bcr_timer timer;
	int ret;

	READ_BCR(ARC_REG_TIMERS_BCR, timer);
	if (!timer.rtc) {
		pr_warn("Local-64-bit-Ctr clocksource not detected\n");
		return -ENXIO;
	}

	/* Local to CPU hence not usable in SMP */
	if (IS_ENABLED(CONFIG_SMP)) {
		pr_warn("Local-64-bit-Ctr not usable in SMP\n");
		return -EINVAL;
	}

	ret = arc_get_timer_clk(node);
	if (ret)
		return ret;

	write_aux_reg(AUX_RTC_CTRL, 1);

	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
}
TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);

#endif

/*
 * 32bit TIMER1 to keep counting monotonically and wraparound
 */

static u64 arc_read_timer1(struct clocksource *cs)
{
	return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
}

static struct clocksource arc_counter_timer1 = {
	.name   = "ARC Timer1",
	.rating = 300,
	.read   = arc_read_timer1,
	.mask   = CLOCKSOURCE_MASK(32),
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init arc_cs_setup_timer1(struct device_node *node)
{
	int ret;

	/* Local to CPU hence not usable in SMP */
	if (IS_ENABLED(CONFIG_SMP))
		return -EINVAL;

	ret = arc_get_timer_clk(node);
	if (ret)
		return ret;

	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);

	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
}

/********** Clock Event Device *********/

static int arc_timer_irq;

/*
 * Arm the timer to interrupt after @cycles
 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
 */
static void arc_timer_event_setup(unsigned int cycles)
{
	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
	write_aux_reg(ARC_REG_TIMER0_CNT, 0);	/* start from 0 */

	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
}


static int arc_clkevent_set_next_event(unsigned long delta,
				       struct clock_event_device *dev)
{
	arc_timer_event_setup(delta);
	return 0;
}

static int arc_clkevent_set_periodic(struct clock_event_device *dev)
{
	/*
	 * At X Hz, 1 sec = 1000ms -> X cycles;
	 *		      10ms -> X / 100 cycles
	 */
	arc_timer_event_setup(arc_timer_freq / HZ);
	return 0;
}

static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
	.name			= "ARC Timer0",
	.features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_PERIODIC,
	.rating			= 300,
	.set_next_event		= arc_clkevent_set_next_event,
	.set_state_periodic	= arc_clkevent_set_periodic,
};

static irqreturn_t timer_irq_handler(int irq, void *dev_id)
{
	/*
	 * Note that generic IRQ core could have passed @evt for @dev_id if
	 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
	 */
	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	int irq_reenable = clockevent_state_periodic(evt);

	/*
	 * 1. ACK the interrupt
	 *    - For ARC700, any write to CTRL reg ACKs it, so just rewrite
	 *      Count when [N]ot [H]alted bit.
	 *    - For HS3x, it is a bit subtle. On taken count-down interrupt,
	 *      IP bit [3] is set, which needs to be cleared for ACK'ing.
	 *      The write below can only update the other two bits, hence
	 *      explicitly clears IP bit
	 * 2. Re-arm interrupt if periodic by writing to IE bit [0]
	 */
	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}


static int arc_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);

	evt->cpumask = cpumask_of(smp_processor_id());

	clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
	enable_percpu_irq(arc_timer_irq, 0);
	return 0;
}

static int arc_timer_dying_cpu(unsigned int cpu)
{
	disable_percpu_irq(arc_timer_irq);
	return 0;
}

/*
 * clockevent setup for boot CPU
 */
static int __init arc_clockevent_setup(struct device_node *node)
{
	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	int ret;

	arc_timer_irq = irq_of_parse_and_map(node, 0);
	if (arc_timer_irq <= 0) {
		pr_err("clockevent: missing irq\n");
		return -EINVAL;
	}

	ret = arc_get_timer_clk(node);
	if (ret) {
		pr_err("clockevent: missing clk\n");
		return ret;
	}

	/* Needs apriori irq_set_percpu_devid() done in intc map function */
	ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
				 "Timer0 (per-cpu-tick)", evt);
	if (ret) {
		pr_err("clockevent: unable to request irq\n");
		return ret;
	}

	ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
				"clockevents/arc/timer:starting",
				arc_timer_starting_cpu,
				arc_timer_dying_cpu);
	if (ret) {
		pr_err("Failed to setup hotplug state\n");
		return ret;
	}
	return 0;
}

static int __init arc_of_timer_init(struct device_node *np)
{
	static int init_count = 0;
	int ret;

	if (!init_count) {
		init_count = 1;
		ret = arc_clockevent_setup(np);
	} else {
		ret = arc_cs_setup_timer1(np);
	}

	return ret;
}
TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
Commit	Line	Data
	1	/*
	2	* Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
	3	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9
	10	/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
	11	* programmed to go from @count to @limit and optionally interrupt.
	12	* We've designated TIMER0 for clockevents and TIMER1 for clocksource
	13	*
	14	* ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
	15	* which are suitable for UP and SMP based clocksources respectively
	16	*/
	17
	18	#include <linux/interrupt.h>
	19	#include <linux/clk.h>
	20	#include <linux/clk-provider.h>
	21	#include <linux/clocksource.h>
	22	#include <linux/clockchips.h>
	23	#include <linux/cpu.h>
	24	#include <linux/of.h>
	25	#include <linux/of_irq.h>
	26
	27	#include <soc/arc/timers.h>
	28	#include <soc/arc/mcip.h>
	29
	30
	31	static unsigned long arc_timer_freq;
	32
	33	static int noinline arc_get_timer_clk(struct device_node *node)
	34	{
	35	struct clk *clk;
	36	int ret;
	37
	38	clk = of_clk_get(node, 0);
	39	if (IS_ERR(clk)) {
	40	pr_err("timer missing clk\n");
	41	return PTR_ERR(clk);
	42	}
	43
	44	ret = clk_prepare_enable(clk);
	45	if (ret) {
	46	pr_err("Couldn't enable parent clk\n");
	47	return ret;
	48	}
	49
	50	arc_timer_freq = clk_get_rate(clk);
	51
	52	return 0;
	53	}
	54
	55	/******** Clock Source Device *******/
	56
	57	#ifdef CONFIG_ARC_TIMERS_64BIT
	58
	59	static u64 arc_read_gfrc(struct clocksource *cs)
	60	{
	61	unsigned long flags;
	62	u32 l, h;
	63
	64	/*
	65	* From a programming model pov, there seems to be just one instance of
	66	* MCIP_CMD/MCIP_READBACK however micro-architecturally there's
	67	* an instance PER ARC CORE (not per cluster), and there are dedicated
	68	* hardware decode logic (per core) inside ARConnect to handle
	69	* simultaneous read/write accesses from cores via those two registers.
	70	* So several concurrent commands to ARConnect are OK if they are
	71	* trying to access two different sub-components (like GFRC,
	72	* inter-core interrupt, etc...). HW also supports simultaneously
	73	* accessing GFRC by multiple cores.
	74	* That's why it is safe to disable hard interrupts on the local CPU
	75	* before access to GFRC instead of taking global MCIP spinlock
	76	* defined in arch/arc/kernel/mcip.c
	77	*/
	78	local_irq_save(flags);
	79
	80	__mcip_cmd(CMD_GFRC_READ_LO, 0);
	81	l = read_aux_reg(ARC_REG_MCIP_READBACK);
	82
	83	__mcip_cmd(CMD_GFRC_READ_HI, 0);
	84	h = read_aux_reg(ARC_REG_MCIP_READBACK);
	85
	86	local_irq_restore(flags);
	87
	88	return (((u64)h) << 32) \| l;
	89	}
	90
	91	static struct clocksource arc_counter_gfrc = {
	92	.name = "ARConnect GFRC",
	93	.rating = 400,
	94	.read = arc_read_gfrc,
	95	.mask = CLOCKSOURCE_MASK(64),
	96	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	97	};
	98
	99	static int __init arc_cs_setup_gfrc(struct device_node *node)
	100	{
	101	struct mcip_bcr mp;
	102	int ret;
	103
	104	READ_BCR(ARC_REG_MCIP_BCR, mp);
	105	if (!mp.gfrc) {
	106	pr_warn("Global-64-bit-Ctr clocksource not detected\n");
	107	return -ENXIO;
	108	}
	109
	110	ret = arc_get_timer_clk(node);
	111	if (ret)
	112	return ret;
	113
	114	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
	115	}
	116	TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
	117
	118	#define AUX_RTC_CTRL 0x103
	119	#define AUX_RTC_LOW 0x104
	120	#define AUX_RTC_HIGH 0x105
	121
	122	static u64 arc_read_rtc(struct clocksource *cs)
	123	{
	124	unsigned long status;
	125	u32 l, h;
	126
	127	/*
	128	* hardware has an internal state machine which tracks readout of
	129	* low/high and updates the CTRL.status if
	130	* - interrupt/exception taken between the two reads
	131	* - high increments after low has been read
	132	*/
	133	do {
	134	l = read_aux_reg(AUX_RTC_LOW);
	135	h = read_aux_reg(AUX_RTC_HIGH);
	136	status = read_aux_reg(AUX_RTC_CTRL);
	137	} while (!(status & _BITUL(31)));
	138
	139	return (((u64)h) << 32) \| l;
	140	}
	141
	142	static struct clocksource arc_counter_rtc = {
	143	.name = "ARCv2 RTC",
	144	.rating = 350,
	145	.read = arc_read_rtc,
	146	.mask = CLOCKSOURCE_MASK(64),
	147	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	148	};
	149
	150	static int __init arc_cs_setup_rtc(struct device_node *node)
	151	{
	152	struct bcr_timer timer;
	153	int ret;
	154
	155	READ_BCR(ARC_REG_TIMERS_BCR, timer);
	156	if (!timer.rtc) {
	157	pr_warn("Local-64-bit-Ctr clocksource not detected\n");
	158	return -ENXIO;
	159	}
	160
	161	/* Local to CPU hence not usable in SMP */
	162	if (IS_ENABLED(CONFIG_SMP)) {
	163	pr_warn("Local-64-bit-Ctr not usable in SMP\n");
	164	return -EINVAL;
	165	}
	166
	167	ret = arc_get_timer_clk(node);
	168	if (ret)
	169	return ret;
	170
	171	write_aux_reg(AUX_RTC_CTRL, 1);
	172
	173	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
	174	}
	175	TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
	176
	177	#endif
	178
	179	/*
	180	* 32bit TIMER1 to keep counting monotonically and wraparound
	181	*/
	182
	183	static u64 arc_read_timer1(struct clocksource *cs)
	184	{
	185	return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
	186	}
	187
	188	static struct clocksource arc_counter_timer1 = {
	189	.name = "ARC Timer1",
	190	.rating = 300,
	191	.read = arc_read_timer1,
	192	.mask = CLOCKSOURCE_MASK(32),
	193	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	194	};
	195
	196	static int __init arc_cs_setup_timer1(struct device_node *node)
	197	{
	198	int ret;
	199
	200	/* Local to CPU hence not usable in SMP */
	201	if (IS_ENABLED(CONFIG_SMP))
	202	return -EINVAL;
	203
	204	ret = arc_get_timer_clk(node);
	205	if (ret)
	206	return ret;
	207
	208	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
	209	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
	210	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
	211
	212	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
	213	}
	214
	215	/******** Clock Event Device *******/
	216
	217	static int arc_timer_irq;
	218
	219	/*
	220	* Arm the timer to interrupt after @cycles
	221	* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
	222	*/
	223	static void arc_timer_event_setup(unsigned int cycles)
	224	{
	225	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
	226	write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
	227
	228	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE \| TIMER_CTRL_NH);
	229	}
	230
	231
	232	static int arc_clkevent_set_next_event(unsigned long delta,
	233	struct clock_event_device *dev)
	234	{
	235	arc_timer_event_setup(delta);
	236	return 0;
	237	}
	238
	239	static int arc_clkevent_set_periodic(struct clock_event_device *dev)
	240	{
	241	/*
	242	* At X Hz, 1 sec = 1000ms -> X cycles;
	243	* 10ms -> X / 100 cycles
	244	*/
	245	arc_timer_event_setup(arc_timer_freq / HZ);
	246	return 0;
	247	}
	248
	249	static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
	250	.name = "ARC Timer0",
	251	.features = CLOCK_EVT_FEAT_ONESHOT \|
	252	CLOCK_EVT_FEAT_PERIODIC,
	253	.rating = 300,
	254	.set_next_event = arc_clkevent_set_next_event,
	255	.set_state_periodic = arc_clkevent_set_periodic,
	256	};
	257
	258	static irqreturn_t timer_irq_handler(int irq, void *dev_id)
	259	{
	260	/*
	261	* Note that generic IRQ core could have passed @evt for @dev_id if
	262	* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
	263	*/
	264	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	265	int irq_reenable = clockevent_state_periodic(evt);
	266
	267	/*
	268	* 1. ACK the interrupt
	269	* - For ARC700, any write to CTRL reg ACKs it, so just rewrite
	270	* Count when [N]ot [H]alted bit.
	271	* - For HS3x, it is a bit subtle. On taken count-down interrupt,
	272	* IP bit [3] is set, which needs to be cleared for ACK'ing.
	273	* The write below can only update the other two bits, hence
	274	* explicitly clears IP bit
	275	* 2. Re-arm interrupt if periodic by writing to IE bit [0]
	276	*/
	277	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable \| TIMER_CTRL_NH);
	278
	279	evt->event_handler(evt);
	280
	281	return IRQ_HANDLED;
	282	}
	283
	284
	285	static int arc_timer_starting_cpu(unsigned int cpu)
	286	{
	287	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	288
	289	evt->cpumask = cpumask_of(smp_processor_id());
	290
	291	clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
	292	enable_percpu_irq(arc_timer_irq, 0);
	293	return 0;
	294	}
	295
	296	static int arc_timer_dying_cpu(unsigned int cpu)
	297	{
	298	disable_percpu_irq(arc_timer_irq);
	299	return 0;
	300	}
	301
	302	/*
	303	* clockevent setup for boot CPU
	304	*/
	305	static int __init arc_clockevent_setup(struct device_node *node)
	306	{
	307	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	308	int ret;
	309
	310	arc_timer_irq = irq_of_parse_and_map(node, 0);
	311	if (arc_timer_irq <= 0) {
	312	pr_err("clockevent: missing irq\n");
	313	return -EINVAL;
	314	}
	315
	316	ret = arc_get_timer_clk(node);
	317	if (ret) {
	318	pr_err("clockevent: missing clk\n");
	319	return ret;
	320	}
	321
	322	/* Needs apriori irq_set_percpu_devid() done in intc map function */
	323	ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
	324	"Timer0 (per-cpu-tick)", evt);
	325	if (ret) {
	326	pr_err("clockevent: unable to request irq\n");
	327	return ret;
	328	}
	329
	330	ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
	331	"clockevents/arc/timer:starting",
	332	arc_timer_starting_cpu,
	333	arc_timer_dying_cpu);
	334	if (ret) {
	335	pr_err("Failed to setup hotplug state\n");
	336	return ret;
	337	}
	338	return 0;
	339	}
	340
	341	static int __init arc_of_timer_init(struct device_node *np)
	342	{
	343	static int init_count = 0;
	344	int ret;
	345
	346	if (!init_count) {
	347	init_count = 1;
	348	ret = arc_clockevent_setup(np);
	349	} else {
	350	ret = arc_cs_setup_timer1(np);
	351	}
	352
	353	return ret;
	354	}
	355	TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);