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NVMe: Move structures & definitions to header file
[linux-2.6-block.git] / drivers / block / nvme-core.c
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1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
21#include <linux/bitops.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/genhd.h>
27#include <linux/idr.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
32#include <linux/kthread.h>
33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/pci.h>
38#include <linux/poison.h>
39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42
43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
45#define NVME_Q_DEPTH 1024
46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48#define NVME_MINORS 64
49#define ADMIN_TIMEOUT (60 * HZ)
50
51static int nvme_major;
52module_param(nvme_major, int, 0);
53
54static int use_threaded_interrupts;
55module_param(use_threaded_interrupts, int, 0);
56
57static DEFINE_SPINLOCK(dev_list_lock);
58static LIST_HEAD(dev_list);
59static struct task_struct *nvme_thread;
60
61/*
62 * An NVM Express queue. Each device has at least two (one for admin
63 * commands and one for I/O commands).
64 */
65struct nvme_queue {
66 struct device *q_dmadev;
67 struct nvme_dev *dev;
68 spinlock_t q_lock;
69 struct nvme_command *sq_cmds;
70 volatile struct nvme_completion *cqes;
71 dma_addr_t sq_dma_addr;
72 dma_addr_t cq_dma_addr;
73 wait_queue_head_t sq_full;
74 wait_queue_t sq_cong_wait;
75 struct bio_list sq_cong;
76 u32 __iomem *q_db;
77 u16 q_depth;
78 u16 cq_vector;
79 u16 sq_head;
80 u16 sq_tail;
81 u16 cq_head;
82 u16 cq_phase;
83 unsigned long cmdid_data[];
84};
85
86/*
87 * Check we didin't inadvertently grow the command struct
88 */
89static inline void _nvme_check_size(void)
90{
91 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
92 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
93 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
94 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
95 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
96 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
97 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
98 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
99 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
100 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
101}
102
103typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
104 struct nvme_completion *);
105
106struct nvme_cmd_info {
107 nvme_completion_fn fn;
108 void *ctx;
109 unsigned long timeout;
110};
111
112static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
113{
114 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
115}
116
117/**
118 * alloc_cmdid() - Allocate a Command ID
119 * @nvmeq: The queue that will be used for this command
120 * @ctx: A pointer that will be passed to the handler
121 * @handler: The function to call on completion
122 *
123 * Allocate a Command ID for a queue. The data passed in will
124 * be passed to the completion handler. This is implemented by using
125 * the bottom two bits of the ctx pointer to store the handler ID.
126 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
127 * We can change this if it becomes a problem.
128 *
129 * May be called with local interrupts disabled and the q_lock held,
130 * or with interrupts enabled and no locks held.
131 */
132static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
133 nvme_completion_fn handler, unsigned timeout)
134{
135 int depth = nvmeq->q_depth - 1;
136 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
137 int cmdid;
138
139 do {
140 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
141 if (cmdid >= depth)
142 return -EBUSY;
143 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
144
145 info[cmdid].fn = handler;
146 info[cmdid].ctx = ctx;
147 info[cmdid].timeout = jiffies + timeout;
148 return cmdid;
149}
150
151static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
152 nvme_completion_fn handler, unsigned timeout)
153{
154 int cmdid;
155 wait_event_killable(nvmeq->sq_full,
156 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
157 return (cmdid < 0) ? -EINTR : cmdid;
158}
159
160/* Special values must be less than 0x1000 */
161#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
162#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
163#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
164#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
165#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
166
167static void special_completion(struct nvme_dev *dev, void *ctx,
168 struct nvme_completion *cqe)
169{
170 if (ctx == CMD_CTX_CANCELLED)
171 return;
172 if (ctx == CMD_CTX_FLUSH)
173 return;
174 if (ctx == CMD_CTX_COMPLETED) {
175 dev_warn(&dev->pci_dev->dev,
176 "completed id %d twice on queue %d\n",
177 cqe->command_id, le16_to_cpup(&cqe->sq_id));
178 return;
179 }
180 if (ctx == CMD_CTX_INVALID) {
181 dev_warn(&dev->pci_dev->dev,
182 "invalid id %d completed on queue %d\n",
183 cqe->command_id, le16_to_cpup(&cqe->sq_id));
184 return;
185 }
186
187 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
188}
189
190/*
191 * Called with local interrupts disabled and the q_lock held. May not sleep.
192 */
193static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
194 nvme_completion_fn *fn)
195{
196 void *ctx;
197 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
198
199 if (cmdid >= nvmeq->q_depth) {
200 *fn = special_completion;
201 return CMD_CTX_INVALID;
202 }
203 if (fn)
204 *fn = info[cmdid].fn;
205 ctx = info[cmdid].ctx;
206 info[cmdid].fn = special_completion;
207 info[cmdid].ctx = CMD_CTX_COMPLETED;
208 clear_bit(cmdid, nvmeq->cmdid_data);
209 wake_up(&nvmeq->sq_full);
210 return ctx;
211}
212
213static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
214 nvme_completion_fn *fn)
215{
216 void *ctx;
217 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
218 if (fn)
219 *fn = info[cmdid].fn;
220 ctx = info[cmdid].ctx;
221 info[cmdid].fn = special_completion;
222 info[cmdid].ctx = CMD_CTX_CANCELLED;
223 return ctx;
224}
225
226static struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
227{
228 return dev->queues[get_cpu() + 1];
229}
230
231static void put_nvmeq(struct nvme_queue *nvmeq)
232{
233 put_cpu();
234}
235
236/**
237 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
238 * @nvmeq: The queue to use
239 * @cmd: The command to send
240 *
241 * Safe to use from interrupt context
242 */
243static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
244{
245 unsigned long flags;
246 u16 tail;
247 spin_lock_irqsave(&nvmeq->q_lock, flags);
248 tail = nvmeq->sq_tail;
249 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
250 if (++tail == nvmeq->q_depth)
251 tail = 0;
252 writel(tail, nvmeq->q_db);
253 nvmeq->sq_tail = tail;
254 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
255
256 return 0;
257}
258
259static __le64 **iod_list(struct nvme_iod *iod)
260{
261 return ((void *)iod) + iod->offset;
262}
263
264/*
265 * Will slightly overestimate the number of pages needed. This is OK
266 * as it only leads to a small amount of wasted memory for the lifetime of
267 * the I/O.
268 */
269static int nvme_npages(unsigned size)
270{
271 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
272 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
273}
274
275static struct nvme_iod *
276nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
277{
278 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
279 sizeof(__le64 *) * nvme_npages(nbytes) +
280 sizeof(struct scatterlist) * nseg, gfp);
281
282 if (iod) {
283 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
284 iod->npages = -1;
285 iod->length = nbytes;
286 iod->nents = 0;
287 }
288
289 return iod;
290}
291
292static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
293{
294 const int last_prp = PAGE_SIZE / 8 - 1;
295 int i;
296 __le64 **list = iod_list(iod);
297 dma_addr_t prp_dma = iod->first_dma;
298
299 if (iod->npages == 0)
300 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
301 for (i = 0; i < iod->npages; i++) {
302 __le64 *prp_list = list[i];
303 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
304 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
305 prp_dma = next_prp_dma;
306 }
307 kfree(iod);
308}
309
310static void requeue_bio(struct nvme_dev *dev, struct bio *bio)
311{
312 struct nvme_queue *nvmeq = get_nvmeq(dev);
313 if (bio_list_empty(&nvmeq->sq_cong))
314 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
315 bio_list_add(&nvmeq->sq_cong, bio);
316 put_nvmeq(nvmeq);
317 wake_up_process(nvme_thread);
318}
319
320static void bio_completion(struct nvme_dev *dev, void *ctx,
321 struct nvme_completion *cqe)
322{
323 struct nvme_iod *iod = ctx;
324 struct bio *bio = iod->private;
325 u16 status = le16_to_cpup(&cqe->status) >> 1;
326
327 if (iod->nents)
328 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
329 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
330 nvme_free_iod(dev, iod);
331 if (status) {
332 bio_endio(bio, -EIO);
333 } else if (bio->bi_vcnt > bio->bi_idx) {
334 requeue_bio(dev, bio);
335 } else {
336 bio_endio(bio, 0);
337 }
338}
339
340/* length is in bytes. gfp flags indicates whether we may sleep. */
341static int nvme_setup_prps(struct nvme_dev *dev,
342 struct nvme_common_command *cmd, struct nvme_iod *iod,
343 int total_len, gfp_t gfp)
344{
345 struct dma_pool *pool;
346 int length = total_len;
347 struct scatterlist *sg = iod->sg;
348 int dma_len = sg_dma_len(sg);
349 u64 dma_addr = sg_dma_address(sg);
350 int offset = offset_in_page(dma_addr);
351 __le64 *prp_list;
352 __le64 **list = iod_list(iod);
353 dma_addr_t prp_dma;
354 int nprps, i;
355
356 cmd->prp1 = cpu_to_le64(dma_addr);
357 length -= (PAGE_SIZE - offset);
358 if (length <= 0)
359 return total_len;
360
361 dma_len -= (PAGE_SIZE - offset);
362 if (dma_len) {
363 dma_addr += (PAGE_SIZE - offset);
364 } else {
365 sg = sg_next(sg);
366 dma_addr = sg_dma_address(sg);
367 dma_len = sg_dma_len(sg);
368 }
369
370 if (length <= PAGE_SIZE) {
371 cmd->prp2 = cpu_to_le64(dma_addr);
372 return total_len;
373 }
374
375 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
376 if (nprps <= (256 / 8)) {
377 pool = dev->prp_small_pool;
378 iod->npages = 0;
379 } else {
380 pool = dev->prp_page_pool;
381 iod->npages = 1;
382 }
383
384 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
385 if (!prp_list) {
386 cmd->prp2 = cpu_to_le64(dma_addr);
387 iod->npages = -1;
388 return (total_len - length) + PAGE_SIZE;
389 }
390 list[0] = prp_list;
391 iod->first_dma = prp_dma;
392 cmd->prp2 = cpu_to_le64(prp_dma);
393 i = 0;
394 for (;;) {
395 if (i == PAGE_SIZE / 8) {
396 __le64 *old_prp_list = prp_list;
397 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
398 if (!prp_list)
399 return total_len - length;
400 list[iod->npages++] = prp_list;
401 prp_list[0] = old_prp_list[i - 1];
402 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
403 i = 1;
404 }
405 prp_list[i++] = cpu_to_le64(dma_addr);
406 dma_len -= PAGE_SIZE;
407 dma_addr += PAGE_SIZE;
408 length -= PAGE_SIZE;
409 if (length <= 0)
410 break;
411 if (dma_len > 0)
412 continue;
413 BUG_ON(dma_len < 0);
414 sg = sg_next(sg);
415 dma_addr = sg_dma_address(sg);
416 dma_len = sg_dma_len(sg);
417 }
418
419 return total_len;
420}
421
422/* NVMe scatterlists require no holes in the virtual address */
423#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
424 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
425
426static int nvme_map_bio(struct device *dev, struct nvme_iod *iod,
427 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
428{
429 struct bio_vec *bvec, *bvprv = NULL;
430 struct scatterlist *sg = NULL;
431 int i, old_idx, length = 0, nsegs = 0;
432
433 sg_init_table(iod->sg, psegs);
434 old_idx = bio->bi_idx;
435 bio_for_each_segment(bvec, bio, i) {
436 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
437 sg->length += bvec->bv_len;
438 } else {
439 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
440 break;
441 sg = sg ? sg + 1 : iod->sg;
442 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
443 bvec->bv_offset);
444 nsegs++;
445 }
446 length += bvec->bv_len;
447 bvprv = bvec;
448 }
449 bio->bi_idx = i;
450 iod->nents = nsegs;
451 sg_mark_end(sg);
452 if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) {
453 bio->bi_idx = old_idx;
454 return -ENOMEM;
455 }
456 return length;
457}
458
459/*
460 * We reuse the small pool to allocate the 16-byte range here as it is not
461 * worth having a special pool for these or additional cases to handle freeing
462 * the iod.
463 */
464static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
465 struct bio *bio, struct nvme_iod *iod, int cmdid)
466{
467 struct nvme_dsm_range *range;
468 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
469
470 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
471 &iod->first_dma);
472 if (!range)
473 return -ENOMEM;
474
475 iod_list(iod)[0] = (__le64 *)range;
476 iod->npages = 0;
477
478 range->cattr = cpu_to_le32(0);
479 range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift);
480 range->slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
481
482 memset(cmnd, 0, sizeof(*cmnd));
483 cmnd->dsm.opcode = nvme_cmd_dsm;
484 cmnd->dsm.command_id = cmdid;
485 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
486 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
487 cmnd->dsm.nr = 0;
488 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
489
490 if (++nvmeq->sq_tail == nvmeq->q_depth)
491 nvmeq->sq_tail = 0;
492 writel(nvmeq->sq_tail, nvmeq->q_db);
493
494 return 0;
495}
496
497static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
498 int cmdid)
499{
500 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
501
502 memset(cmnd, 0, sizeof(*cmnd));
503 cmnd->common.opcode = nvme_cmd_flush;
504 cmnd->common.command_id = cmdid;
505 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
506
507 if (++nvmeq->sq_tail == nvmeq->q_depth)
508 nvmeq->sq_tail = 0;
509 writel(nvmeq->sq_tail, nvmeq->q_db);
510
511 return 0;
512}
513
514static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
515{
516 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
517 special_completion, NVME_IO_TIMEOUT);
518 if (unlikely(cmdid < 0))
519 return cmdid;
520
521 return nvme_submit_flush(nvmeq, ns, cmdid);
522}
523
524/*
525 * Called with local interrupts disabled and the q_lock held. May not sleep.
526 */
527static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
528 struct bio *bio)
529{
530 struct nvme_command *cmnd;
531 struct nvme_iod *iod;
532 enum dma_data_direction dma_dir;
533 int cmdid, length, result = -ENOMEM;
534 u16 control;
535 u32 dsmgmt;
536 int psegs = bio_phys_segments(ns->queue, bio);
537
538 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
539 result = nvme_submit_flush_data(nvmeq, ns);
540 if (result)
541 return result;
542 }
543
544 iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
545 if (!iod)
546 goto nomem;
547 iod->private = bio;
548
549 result = -EBUSY;
550 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
551 if (unlikely(cmdid < 0))
552 goto free_iod;
553
554 if (bio->bi_rw & REQ_DISCARD) {
555 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
556 if (result)
557 goto free_cmdid;
558 return result;
559 }
560 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
561 return nvme_submit_flush(nvmeq, ns, cmdid);
562
563 control = 0;
564 if (bio->bi_rw & REQ_FUA)
565 control |= NVME_RW_FUA;
566 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
567 control |= NVME_RW_LR;
568
569 dsmgmt = 0;
570 if (bio->bi_rw & REQ_RAHEAD)
571 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
572
573 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
574
575 memset(cmnd, 0, sizeof(*cmnd));
576 if (bio_data_dir(bio)) {
577 cmnd->rw.opcode = nvme_cmd_write;
578 dma_dir = DMA_TO_DEVICE;
579 } else {
580 cmnd->rw.opcode = nvme_cmd_read;
581 dma_dir = DMA_FROM_DEVICE;
582 }
583
584 result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs);
585 if (result < 0)
586 goto free_cmdid;
587 length = result;
588
589 cmnd->rw.command_id = cmdid;
590 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
591 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
592 GFP_ATOMIC);
593 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
594 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
595 cmnd->rw.control = cpu_to_le16(control);
596 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
597
598 bio->bi_sector += length >> 9;
599
600 if (++nvmeq->sq_tail == nvmeq->q_depth)
601 nvmeq->sq_tail = 0;
602 writel(nvmeq->sq_tail, nvmeq->q_db);
603
604 return 0;
605
606 free_cmdid:
607 free_cmdid(nvmeq, cmdid, NULL);
608 free_iod:
609 nvme_free_iod(nvmeq->dev, iod);
610 nomem:
611 return result;
612}
613
614static void nvme_make_request(struct request_queue *q, struct bio *bio)
615{
616 struct nvme_ns *ns = q->queuedata;
617 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
618 int result = -EBUSY;
619
620 spin_lock_irq(&nvmeq->q_lock);
621 if (bio_list_empty(&nvmeq->sq_cong))
622 result = nvme_submit_bio_queue(nvmeq, ns, bio);
623 if (unlikely(result)) {
624 if (bio_list_empty(&nvmeq->sq_cong))
625 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
626 bio_list_add(&nvmeq->sq_cong, bio);
627 }
628
629 spin_unlock_irq(&nvmeq->q_lock);
630 put_nvmeq(nvmeq);
631}
632
633static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
634{
635 u16 head, phase;
636
637 head = nvmeq->cq_head;
638 phase = nvmeq->cq_phase;
639
640 for (;;) {
641 void *ctx;
642 nvme_completion_fn fn;
643 struct nvme_completion cqe = nvmeq->cqes[head];
644 if ((le16_to_cpu(cqe.status) & 1) != phase)
645 break;
646 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
647 if (++head == nvmeq->q_depth) {
648 head = 0;
649 phase = !phase;
650 }
651
652 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
653 fn(nvmeq->dev, ctx, &cqe);
654 }
655
656 /* If the controller ignores the cq head doorbell and continuously
657 * writes to the queue, it is theoretically possible to wrap around
658 * the queue twice and mistakenly return IRQ_NONE. Linux only
659 * requires that 0.1% of your interrupts are handled, so this isn't
660 * a big problem.
661 */
662 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
663 return IRQ_NONE;
664
665 writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
666 nvmeq->cq_head = head;
667 nvmeq->cq_phase = phase;
668
669 return IRQ_HANDLED;
670}
671
672static irqreturn_t nvme_irq(int irq, void *data)
673{
674 irqreturn_t result;
675 struct nvme_queue *nvmeq = data;
676 spin_lock(&nvmeq->q_lock);
677 result = nvme_process_cq(nvmeq);
678 spin_unlock(&nvmeq->q_lock);
679 return result;
680}
681
682static irqreturn_t nvme_irq_check(int irq, void *data)
683{
684 struct nvme_queue *nvmeq = data;
685 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
686 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
687 return IRQ_NONE;
688 return IRQ_WAKE_THREAD;
689}
690
691static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
692{
693 spin_lock_irq(&nvmeq->q_lock);
694 cancel_cmdid(nvmeq, cmdid, NULL);
695 spin_unlock_irq(&nvmeq->q_lock);
696}
697
698struct sync_cmd_info {
699 struct task_struct *task;
700 u32 result;
701 int status;
702};
703
704static void sync_completion(struct nvme_dev *dev, void *ctx,
705 struct nvme_completion *cqe)
706{
707 struct sync_cmd_info *cmdinfo = ctx;
708 cmdinfo->result = le32_to_cpup(&cqe->result);
709 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
710 wake_up_process(cmdinfo->task);
711}
712
713/*
714 * Returns 0 on success. If the result is negative, it's a Linux error code;
715 * if the result is positive, it's an NVM Express status code
716 */
717static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
718 struct nvme_command *cmd, u32 *result, unsigned timeout)
719{
720 int cmdid;
721 struct sync_cmd_info cmdinfo;
722
723 cmdinfo.task = current;
724 cmdinfo.status = -EINTR;
725
726 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
727 timeout);
728 if (cmdid < 0)
729 return cmdid;
730 cmd->common.command_id = cmdid;
731
732 set_current_state(TASK_KILLABLE);
733 nvme_submit_cmd(nvmeq, cmd);
734 schedule();
735
736 if (cmdinfo.status == -EINTR) {
737 nvme_abort_command(nvmeq, cmdid);
738 return -EINTR;
739 }
740
741 if (result)
742 *result = cmdinfo.result;
743
744 return cmdinfo.status;
745}
746
747static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
748 u32 *result)
749{
750 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
751}
752
753static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
754{
755 int status;
756 struct nvme_command c;
757
758 memset(&c, 0, sizeof(c));
759 c.delete_queue.opcode = opcode;
760 c.delete_queue.qid = cpu_to_le16(id);
761
762 status = nvme_submit_admin_cmd(dev, &c, NULL);
763 if (status)
764 return -EIO;
765 return 0;
766}
767
768static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
769 struct nvme_queue *nvmeq)
770{
771 int status;
772 struct nvme_command c;
773 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
774
775 memset(&c, 0, sizeof(c));
776 c.create_cq.opcode = nvme_admin_create_cq;
777 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
778 c.create_cq.cqid = cpu_to_le16(qid);
779 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
780 c.create_cq.cq_flags = cpu_to_le16(flags);
781 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
782
783 status = nvme_submit_admin_cmd(dev, &c, NULL);
784 if (status)
785 return -EIO;
786 return 0;
787}
788
789static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
790 struct nvme_queue *nvmeq)
791{
792 int status;
793 struct nvme_command c;
794 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
795
796 memset(&c, 0, sizeof(c));
797 c.create_sq.opcode = nvme_admin_create_sq;
798 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
799 c.create_sq.sqid = cpu_to_le16(qid);
800 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
801 c.create_sq.sq_flags = cpu_to_le16(flags);
802 c.create_sq.cqid = cpu_to_le16(qid);
803
804 status = nvme_submit_admin_cmd(dev, &c, NULL);
805 if (status)
806 return -EIO;
807 return 0;
808}
809
810static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
811{
812 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
813}
814
815static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
816{
817 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
818}
819
820static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
821 dma_addr_t dma_addr)
822{
823 struct nvme_command c;
824
825 memset(&c, 0, sizeof(c));
826 c.identify.opcode = nvme_admin_identify;
827 c.identify.nsid = cpu_to_le32(nsid);
828 c.identify.prp1 = cpu_to_le64(dma_addr);
829 c.identify.cns = cpu_to_le32(cns);
830
831 return nvme_submit_admin_cmd(dev, &c, NULL);
832}
833
834static int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
835 dma_addr_t dma_addr, u32 *result)
836{
837 struct nvme_command c;
838
839 memset(&c, 0, sizeof(c));
840 c.features.opcode = nvme_admin_get_features;
841 c.features.nsid = cpu_to_le32(nsid);
842 c.features.prp1 = cpu_to_le64(dma_addr);
843 c.features.fid = cpu_to_le32(fid);
844
845 return nvme_submit_admin_cmd(dev, &c, result);
846}
847
848static int nvme_set_features(struct nvme_dev *dev, unsigned fid,
849 unsigned dword11, dma_addr_t dma_addr, u32 *result)
850{
851 struct nvme_command c;
852
853 memset(&c, 0, sizeof(c));
854 c.features.opcode = nvme_admin_set_features;
855 c.features.prp1 = cpu_to_le64(dma_addr);
856 c.features.fid = cpu_to_le32(fid);
857 c.features.dword11 = cpu_to_le32(dword11);
858
859 return nvme_submit_admin_cmd(dev, &c, result);
860}
861
862/**
863 * nvme_cancel_ios - Cancel outstanding I/Os
864 * @queue: The queue to cancel I/Os on
865 * @timeout: True to only cancel I/Os which have timed out
866 */
867static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
868{
869 int depth = nvmeq->q_depth - 1;
870 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
871 unsigned long now = jiffies;
872 int cmdid;
873
874 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
875 void *ctx;
876 nvme_completion_fn fn;
877 static struct nvme_completion cqe = {
878 .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1,
879 };
880
881 if (timeout && !time_after(now, info[cmdid].timeout))
882 continue;
883 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
884 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
885 fn(nvmeq->dev, ctx, &cqe);
886 }
887}
888
889static void nvme_free_queue_mem(struct nvme_queue *nvmeq)
890{
891 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
892 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
893 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
894 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
895 kfree(nvmeq);
896}
897
898static void nvme_free_queue(struct nvme_dev *dev, int qid)
899{
900 struct nvme_queue *nvmeq = dev->queues[qid];
901 int vector = dev->entry[nvmeq->cq_vector].vector;
902
903 spin_lock_irq(&nvmeq->q_lock);
904 nvme_cancel_ios(nvmeq, false);
905 while (bio_list_peek(&nvmeq->sq_cong)) {
906 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
907 bio_endio(bio, -EIO);
908 }
909 spin_unlock_irq(&nvmeq->q_lock);
910
911 irq_set_affinity_hint(vector, NULL);
912 free_irq(vector, nvmeq);
913
914 /* Don't tell the adapter to delete the admin queue */
915 if (qid) {
916 adapter_delete_sq(dev, qid);
917 adapter_delete_cq(dev, qid);
918 }
919
920 nvme_free_queue_mem(nvmeq);
921}
922
923static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
924 int depth, int vector)
925{
926 struct device *dmadev = &dev->pci_dev->dev;
927 unsigned extra = DIV_ROUND_UP(depth, 8) + (depth *
928 sizeof(struct nvme_cmd_info));
929 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
930 if (!nvmeq)
931 return NULL;
932
933 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
934 &nvmeq->cq_dma_addr, GFP_KERNEL);
935 if (!nvmeq->cqes)
936 goto free_nvmeq;
937 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
938
939 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
940 &nvmeq->sq_dma_addr, GFP_KERNEL);
941 if (!nvmeq->sq_cmds)
942 goto free_cqdma;
943
944 nvmeq->q_dmadev = dmadev;
945 nvmeq->dev = dev;
946 spin_lock_init(&nvmeq->q_lock);
947 nvmeq->cq_head = 0;
948 nvmeq->cq_phase = 1;
949 init_waitqueue_head(&nvmeq->sq_full);
950 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
951 bio_list_init(&nvmeq->sq_cong);
952 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
953 nvmeq->q_depth = depth;
954 nvmeq->cq_vector = vector;
955
956 return nvmeq;
957
958 free_cqdma:
959 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
960 nvmeq->cq_dma_addr);
961 free_nvmeq:
962 kfree(nvmeq);
963 return NULL;
964}
965
966static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
967 const char *name)
968{
969 if (use_threaded_interrupts)
970 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
971 nvme_irq_check, nvme_irq,
972 IRQF_DISABLED | IRQF_SHARED,
973 name, nvmeq);
974 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
975 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
976}
977
978static struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, int qid,
979 int cq_size, int vector)
980{
981 int result;
982 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
983
984 if (!nvmeq)
985 return ERR_PTR(-ENOMEM);
986
987 result = adapter_alloc_cq(dev, qid, nvmeq);
988 if (result < 0)
989 goto free_nvmeq;
990
991 result = adapter_alloc_sq(dev, qid, nvmeq);
992 if (result < 0)
993 goto release_cq;
994
995 result = queue_request_irq(dev, nvmeq, "nvme");
996 if (result < 0)
997 goto release_sq;
998
999 return nvmeq;
1000
1001 release_sq:
1002 adapter_delete_sq(dev, qid);
1003 release_cq:
1004 adapter_delete_cq(dev, qid);
1005 free_nvmeq:
1006 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1007 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1008 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1009 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1010 kfree(nvmeq);
1011 return ERR_PTR(result);
1012}
1013
1014static int nvme_configure_admin_queue(struct nvme_dev *dev)
1015{
1016 int result = 0;
1017 u32 aqa;
1018 u64 cap;
1019 unsigned long timeout;
1020 struct nvme_queue *nvmeq;
1021
1022 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1023
1024 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1025 if (!nvmeq)
1026 return -ENOMEM;
1027
1028 aqa = nvmeq->q_depth - 1;
1029 aqa |= aqa << 16;
1030
1031 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1032 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1033 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1034 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1035
1036 writel(0, &dev->bar->cc);
1037 writel(aqa, &dev->bar->aqa);
1038 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1039 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1040 writel(dev->ctrl_config, &dev->bar->cc);
1041
1042 cap = readq(&dev->bar->cap);
1043 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1044 dev->db_stride = NVME_CAP_STRIDE(cap);
1045
1046 while (!result && !(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
1047 msleep(100);
1048 if (fatal_signal_pending(current))
1049 result = -EINTR;
1050 if (time_after(jiffies, timeout)) {
1051 dev_err(&dev->pci_dev->dev,
1052 "Device not ready; aborting initialisation\n");
1053 result = -ENODEV;
1054 }
1055 }
1056
1057 if (result) {
1058 nvme_free_queue_mem(nvmeq);
1059 return result;
1060 }
1061
1062 result = queue_request_irq(dev, nvmeq, "nvme admin");
1063 dev->queues[0] = nvmeq;
1064 return result;
1065}
1066
1067static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1068 unsigned long addr, unsigned length)
1069{
1070 int i, err, count, nents, offset;
1071 struct scatterlist *sg;
1072 struct page **pages;
1073 struct nvme_iod *iod;
1074
1075 if (addr & 3)
1076 return ERR_PTR(-EINVAL);
1077 if (!length)
1078 return ERR_PTR(-EINVAL);
1079
1080 offset = offset_in_page(addr);
1081 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1082 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1083 if (!pages)
1084 return ERR_PTR(-ENOMEM);
1085
1086 err = get_user_pages_fast(addr, count, 1, pages);
1087 if (err < count) {
1088 count = err;
1089 err = -EFAULT;
1090 goto put_pages;
1091 }
1092
1093 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1094 sg = iod->sg;
1095 sg_init_table(sg, count);
1096 for (i = 0; i < count; i++) {
1097 sg_set_page(&sg[i], pages[i],
1098 min_t(int, length, PAGE_SIZE - offset), offset);
1099 length -= (PAGE_SIZE - offset);
1100 offset = 0;
1101 }
1102 sg_mark_end(&sg[i - 1]);
1103 iod->nents = count;
1104
1105 err = -ENOMEM;
1106 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1107 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1108 if (!nents)
1109 goto free_iod;
1110
1111 kfree(pages);
1112 return iod;
1113
1114 free_iod:
1115 kfree(iod);
1116 put_pages:
1117 for (i = 0; i < count; i++)
1118 put_page(pages[i]);
1119 kfree(pages);
1120 return ERR_PTR(err);
1121}
1122
1123static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1124 struct nvme_iod *iod)
1125{
1126 int i;
1127
1128 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1129 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1130
1131 for (i = 0; i < iod->nents; i++)
1132 put_page(sg_page(&iod->sg[i]));
1133}
1134
1135static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1136{
1137 struct nvme_dev *dev = ns->dev;
1138 struct nvme_queue *nvmeq;
1139 struct nvme_user_io io;
1140 struct nvme_command c;
1141 unsigned length;
1142 int status;
1143 struct nvme_iod *iod;
1144
1145 if (copy_from_user(&io, uio, sizeof(io)))
1146 return -EFAULT;
1147 length = (io.nblocks + 1) << ns->lba_shift;
1148
1149 switch (io.opcode) {
1150 case nvme_cmd_write:
1151 case nvme_cmd_read:
1152 case nvme_cmd_compare:
1153 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1154 break;
1155 default:
1156 return -EINVAL;
1157 }
1158
1159 if (IS_ERR(iod))
1160 return PTR_ERR(iod);
1161
1162 memset(&c, 0, sizeof(c));
1163 c.rw.opcode = io.opcode;
1164 c.rw.flags = io.flags;
1165 c.rw.nsid = cpu_to_le32(ns->ns_id);
1166 c.rw.slba = cpu_to_le64(io.slba);
1167 c.rw.length = cpu_to_le16(io.nblocks);
1168 c.rw.control = cpu_to_le16(io.control);
1169 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1170 c.rw.reftag = io.reftag;
1171 c.rw.apptag = io.apptag;
1172 c.rw.appmask = io.appmask;
1173 /* XXX: metadata */
1174 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1175
1176 nvmeq = get_nvmeq(dev);
1177 /*
1178 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1179 * disabled. We may be preempted at any point, and be rescheduled
1180 * to a different CPU. That will cause cacheline bouncing, but no
1181 * additional races since q_lock already protects against other CPUs.
1182 */
1183 put_nvmeq(nvmeq);
1184 if (length != (io.nblocks + 1) << ns->lba_shift)
1185 status = -ENOMEM;
1186 else
1187 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1188
1189 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1190 nvme_free_iod(dev, iod);
1191 return status;
1192}
1193
1194static int nvme_user_admin_cmd(struct nvme_dev *dev,
1195 struct nvme_admin_cmd __user *ucmd)
1196{
1197 struct nvme_admin_cmd cmd;
1198 struct nvme_command c;
1199 int status, length;
1200 struct nvme_iod *uninitialized_var(iod);
1201
1202 if (!capable(CAP_SYS_ADMIN))
1203 return -EACCES;
1204 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1205 return -EFAULT;
1206
1207 memset(&c, 0, sizeof(c));
1208 c.common.opcode = cmd.opcode;
1209 c.common.flags = cmd.flags;
1210 c.common.nsid = cpu_to_le32(cmd.nsid);
1211 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1212 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1213 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1214 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1215 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1216 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1217 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1218 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1219
1220 length = cmd.data_len;
1221 if (cmd.data_len) {
1222 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1223 length);
1224 if (IS_ERR(iod))
1225 return PTR_ERR(iod);
1226 length = nvme_setup_prps(dev, &c.common, iod, length,
1227 GFP_KERNEL);
1228 }
1229
1230 if (length != cmd.data_len)
1231 status = -ENOMEM;
1232 else
1233 status = nvme_submit_admin_cmd(dev, &c, &cmd.result);
1234
1235 if (cmd.data_len) {
1236 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1237 nvme_free_iod(dev, iod);
1238 }
1239
1240 if (!status && copy_to_user(&ucmd->result, &cmd.result,
1241 sizeof(cmd.result)))
1242 status = -EFAULT;
1243
1244 return status;
1245}
1246
1247static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1248 unsigned long arg)
1249{
1250 struct nvme_ns *ns = bdev->bd_disk->private_data;
1251
1252 switch (cmd) {
1253 case NVME_IOCTL_ID:
1254 return ns->ns_id;
1255 case NVME_IOCTL_ADMIN_CMD:
1256 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
1257 case NVME_IOCTL_SUBMIT_IO:
1258 return nvme_submit_io(ns, (void __user *)arg);
1259 default:
1260 return -ENOTTY;
1261 }
1262}
1263
1264static const struct block_device_operations nvme_fops = {
1265 .owner = THIS_MODULE,
1266 .ioctl = nvme_ioctl,
1267 .compat_ioctl = nvme_ioctl,
1268};
1269
1270static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1271{
1272 while (bio_list_peek(&nvmeq->sq_cong)) {
1273 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1274 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1275 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1276 bio_list_add_head(&nvmeq->sq_cong, bio);
1277 break;
1278 }
1279 if (bio_list_empty(&nvmeq->sq_cong))
1280 remove_wait_queue(&nvmeq->sq_full,
1281 &nvmeq->sq_cong_wait);
1282 }
1283}
1284
1285static int nvme_kthread(void *data)
1286{
1287 struct nvme_dev *dev;
1288
1289 while (!kthread_should_stop()) {
1290 __set_current_state(TASK_RUNNING);
1291 spin_lock(&dev_list_lock);
1292 list_for_each_entry(dev, &dev_list, node) {
1293 int i;
1294 for (i = 0; i < dev->queue_count; i++) {
1295 struct nvme_queue *nvmeq = dev->queues[i];
1296 if (!nvmeq)
1297 continue;
1298 spin_lock_irq(&nvmeq->q_lock);
1299 if (nvme_process_cq(nvmeq))
1300 printk("process_cq did something\n");
1301 nvme_cancel_ios(nvmeq, true);
1302 nvme_resubmit_bios(nvmeq);
1303 spin_unlock_irq(&nvmeq->q_lock);
1304 }
1305 }
1306 spin_unlock(&dev_list_lock);
1307 set_current_state(TASK_INTERRUPTIBLE);
1308 schedule_timeout(HZ);
1309 }
1310 return 0;
1311}
1312
1313static DEFINE_IDA(nvme_index_ida);
1314
1315static int nvme_get_ns_idx(void)
1316{
1317 int index, error;
1318
1319 do {
1320 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1321 return -1;
1322
1323 spin_lock(&dev_list_lock);
1324 error = ida_get_new(&nvme_index_ida, &index);
1325 spin_unlock(&dev_list_lock);
1326 } while (error == -EAGAIN);
1327
1328 if (error)
1329 index = -1;
1330 return index;
1331}
1332
1333static void nvme_put_ns_idx(int index)
1334{
1335 spin_lock(&dev_list_lock);
1336 ida_remove(&nvme_index_ida, index);
1337 spin_unlock(&dev_list_lock);
1338}
1339
1340static void nvme_config_discard(struct nvme_ns *ns)
1341{
1342 u32 logical_block_size = queue_logical_block_size(ns->queue);
1343 ns->queue->limits.discard_zeroes_data = 0;
1344 ns->queue->limits.discard_alignment = logical_block_size;
1345 ns->queue->limits.discard_granularity = logical_block_size;
1346 ns->queue->limits.max_discard_sectors = 0xffffffff;
1347 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1348}
1349
1350static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1351 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1352{
1353 struct nvme_ns *ns;
1354 struct gendisk *disk;
1355 int lbaf;
1356
1357 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1358 return NULL;
1359
1360 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1361 if (!ns)
1362 return NULL;
1363 ns->queue = blk_alloc_queue(GFP_KERNEL);
1364 if (!ns->queue)
1365 goto out_free_ns;
1366 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1367 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1368 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1369 blk_queue_make_request(ns->queue, nvme_make_request);
1370 ns->dev = dev;
1371 ns->queue->queuedata = ns;
1372
1373 disk = alloc_disk(NVME_MINORS);
1374 if (!disk)
1375 goto out_free_queue;
1376 ns->ns_id = nsid;
1377 ns->disk = disk;
1378 lbaf = id->flbas & 0xf;
1379 ns->lba_shift = id->lbaf[lbaf].ds;
1380 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1381 if (dev->max_hw_sectors)
1382 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1383
1384 disk->major = nvme_major;
1385 disk->minors = NVME_MINORS;
1386 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1387 disk->fops = &nvme_fops;
1388 disk->private_data = ns;
1389 disk->queue = ns->queue;
1390 disk->driverfs_dev = &dev->pci_dev->dev;
1391 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1392 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1393
1394 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1395 nvme_config_discard(ns);
1396
1397 return ns;
1398
1399 out_free_queue:
1400 blk_cleanup_queue(ns->queue);
1401 out_free_ns:
1402 kfree(ns);
1403 return NULL;
1404}
1405
1406static void nvme_ns_free(struct nvme_ns *ns)
1407{
1408 int index = ns->disk->first_minor / NVME_MINORS;
1409 put_disk(ns->disk);
1410 nvme_put_ns_idx(index);
1411 blk_cleanup_queue(ns->queue);
1412 kfree(ns);
1413}
1414
1415static int set_queue_count(struct nvme_dev *dev, int count)
1416{
1417 int status;
1418 u32 result;
1419 u32 q_count = (count - 1) | ((count - 1) << 16);
1420
1421 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1422 &result);
1423 if (status)
1424 return -EIO;
1425 return min(result & 0xffff, result >> 16) + 1;
1426}
1427
1428static int nvme_setup_io_queues(struct nvme_dev *dev)
1429{
1430 int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
1431
1432 nr_io_queues = num_online_cpus();
1433 result = set_queue_count(dev, nr_io_queues);
1434 if (result < 0)
1435 return result;
1436 if (result < nr_io_queues)
1437 nr_io_queues = result;
1438
1439 /* Deregister the admin queue's interrupt */
1440 free_irq(dev->entry[0].vector, dev->queues[0]);
1441
1442 db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1443 if (db_bar_size > 8192) {
1444 iounmap(dev->bar);
1445 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1446 db_bar_size);
1447 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1448 dev->queues[0]->q_db = dev->dbs;
1449 }
1450
1451 for (i = 0; i < nr_io_queues; i++)
1452 dev->entry[i].entry = i;
1453 for (;;) {
1454 result = pci_enable_msix(dev->pci_dev, dev->entry,
1455 nr_io_queues);
1456 if (result == 0) {
1457 break;
1458 } else if (result > 0) {
1459 nr_io_queues = result;
1460 continue;
1461 } else {
1462 nr_io_queues = 1;
1463 break;
1464 }
1465 }
1466
1467 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1468 /* XXX: handle failure here */
1469
1470 cpu = cpumask_first(cpu_online_mask);
1471 for (i = 0; i < nr_io_queues; i++) {
1472 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1473 cpu = cpumask_next(cpu, cpu_online_mask);
1474 }
1475
1476 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1477 NVME_Q_DEPTH);
1478 for (i = 0; i < nr_io_queues; i++) {
1479 dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i);
1480 if (IS_ERR(dev->queues[i + 1]))
1481 return PTR_ERR(dev->queues[i + 1]);
1482 dev->queue_count++;
1483 }
1484
1485 for (; i < num_possible_cpus(); i++) {
1486 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1487 dev->queues[i + 1] = dev->queues[target + 1];
1488 }
1489
1490 return 0;
1491}
1492
1493static void nvme_free_queues(struct nvme_dev *dev)
1494{
1495 int i;
1496
1497 for (i = dev->queue_count - 1; i >= 0; i--)
1498 nvme_free_queue(dev, i);
1499}
1500
1501static int nvme_dev_add(struct nvme_dev *dev)
1502{
1503 int res, nn, i;
1504 struct nvme_ns *ns, *next;
1505 struct nvme_id_ctrl *ctrl;
1506 struct nvme_id_ns *id_ns;
1507 void *mem;
1508 dma_addr_t dma_addr;
1509
1510 res = nvme_setup_io_queues(dev);
1511 if (res)
1512 return res;
1513
1514 mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1515 GFP_KERNEL);
1516
1517 res = nvme_identify(dev, 0, 1, dma_addr);
1518 if (res) {
1519 res = -EIO;
1520 goto out_free;
1521 }
1522
1523 ctrl = mem;
1524 nn = le32_to_cpup(&ctrl->nn);
1525 dev->oncs = le16_to_cpup(&ctrl->oncs);
1526 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1527 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1528 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1529 if (ctrl->mdts) {
1530 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
1531 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
1532 }
1533
1534 id_ns = mem;
1535 for (i = 1; i <= nn; i++) {
1536 res = nvme_identify(dev, i, 0, dma_addr);
1537 if (res)
1538 continue;
1539
1540 if (id_ns->ncap == 0)
1541 continue;
1542
1543 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1544 dma_addr + 4096, NULL);
1545 if (res)
1546 memset(mem + 4096, 0, 4096);
1547
1548 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1549 if (ns)
1550 list_add_tail(&ns->list, &dev->namespaces);
1551 }
1552 list_for_each_entry(ns, &dev->namespaces, list)
1553 add_disk(ns->disk);
1554
1555 goto out;
1556
1557 out_free:
1558 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1559 list_del(&ns->list);
1560 nvme_ns_free(ns);
1561 }
1562
1563 out:
1564 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1565 return res;
1566}
1567
1568static int nvme_dev_remove(struct nvme_dev *dev)
1569{
1570 struct nvme_ns *ns, *next;
1571
1572 spin_lock(&dev_list_lock);
1573 list_del(&dev->node);
1574 spin_unlock(&dev_list_lock);
1575
1576 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1577 list_del(&ns->list);
1578 del_gendisk(ns->disk);
1579 nvme_ns_free(ns);
1580 }
1581
1582 nvme_free_queues(dev);
1583
1584 return 0;
1585}
1586
1587static int nvme_setup_prp_pools(struct nvme_dev *dev)
1588{
1589 struct device *dmadev = &dev->pci_dev->dev;
1590 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1591 PAGE_SIZE, PAGE_SIZE, 0);
1592 if (!dev->prp_page_pool)
1593 return -ENOMEM;
1594
1595 /* Optimisation for I/Os between 4k and 128k */
1596 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1597 256, 256, 0);
1598 if (!dev->prp_small_pool) {
1599 dma_pool_destroy(dev->prp_page_pool);
1600 return -ENOMEM;
1601 }
1602 return 0;
1603}
1604
1605static void nvme_release_prp_pools(struct nvme_dev *dev)
1606{
1607 dma_pool_destroy(dev->prp_page_pool);
1608 dma_pool_destroy(dev->prp_small_pool);
1609}
1610
1611static DEFINE_IDA(nvme_instance_ida);
1612
1613static int nvme_set_instance(struct nvme_dev *dev)
1614{
1615 int instance, error;
1616
1617 do {
1618 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1619 return -ENODEV;
1620
1621 spin_lock(&dev_list_lock);
1622 error = ida_get_new(&nvme_instance_ida, &instance);
1623 spin_unlock(&dev_list_lock);
1624 } while (error == -EAGAIN);
1625
1626 if (error)
1627 return -ENODEV;
1628
1629 dev->instance = instance;
1630 return 0;
1631}
1632
1633static void nvme_release_instance(struct nvme_dev *dev)
1634{
1635 spin_lock(&dev_list_lock);
1636 ida_remove(&nvme_instance_ida, dev->instance);
1637 spin_unlock(&dev_list_lock);
1638}
1639
1640static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1641{
1642 int bars, result = -ENOMEM;
1643 struct nvme_dev *dev;
1644
1645 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1646 if (!dev)
1647 return -ENOMEM;
1648 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1649 GFP_KERNEL);
1650 if (!dev->entry)
1651 goto free;
1652 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1653 GFP_KERNEL);
1654 if (!dev->queues)
1655 goto free;
1656
1657 if (pci_enable_device_mem(pdev))
1658 goto free;
1659 pci_set_master(pdev);
1660 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1661 if (pci_request_selected_regions(pdev, bars, "nvme"))
1662 goto disable;
1663
1664 INIT_LIST_HEAD(&dev->namespaces);
1665 dev->pci_dev = pdev;
1666 pci_set_drvdata(pdev, dev);
1667 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1668 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1669 result = nvme_set_instance(dev);
1670 if (result)
1671 goto disable;
1672
1673 dev->entry[0].vector = pdev->irq;
1674
1675 result = nvme_setup_prp_pools(dev);
1676 if (result)
1677 goto disable_msix;
1678
1679 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1680 if (!dev->bar) {
1681 result = -ENOMEM;
1682 goto disable_msix;
1683 }
1684
1685 result = nvme_configure_admin_queue(dev);
1686 if (result)
1687 goto unmap;
1688 dev->queue_count++;
1689
1690 spin_lock(&dev_list_lock);
1691 list_add(&dev->node, &dev_list);
1692 spin_unlock(&dev_list_lock);
1693
1694 result = nvme_dev_add(dev);
1695 if (result)
1696 goto delete;
1697
1698 return 0;
1699
1700 delete:
1701 spin_lock(&dev_list_lock);
1702 list_del(&dev->node);
1703 spin_unlock(&dev_list_lock);
1704
1705 nvme_free_queues(dev);
1706 unmap:
1707 iounmap(dev->bar);
1708 disable_msix:
1709 pci_disable_msix(pdev);
1710 nvme_release_instance(dev);
1711 nvme_release_prp_pools(dev);
1712 disable:
1713 pci_disable_device(pdev);
1714 pci_release_regions(pdev);
1715 free:
1716 kfree(dev->queues);
1717 kfree(dev->entry);
1718 kfree(dev);
1719 return result;
1720}
1721
1722static void nvme_remove(struct pci_dev *pdev)
1723{
1724 struct nvme_dev *dev = pci_get_drvdata(pdev);
1725 nvme_dev_remove(dev);
1726 pci_disable_msix(pdev);
1727 iounmap(dev->bar);
1728 nvme_release_instance(dev);
1729 nvme_release_prp_pools(dev);
1730 pci_disable_device(pdev);
1731 pci_release_regions(pdev);
1732 kfree(dev->queues);
1733 kfree(dev->entry);
1734 kfree(dev);
1735}
1736
1737/* These functions are yet to be implemented */
1738#define nvme_error_detected NULL
1739#define nvme_dump_registers NULL
1740#define nvme_link_reset NULL
1741#define nvme_slot_reset NULL
1742#define nvme_error_resume NULL
1743#define nvme_suspend NULL
1744#define nvme_resume NULL
1745
1746static const struct pci_error_handlers nvme_err_handler = {
1747 .error_detected = nvme_error_detected,
1748 .mmio_enabled = nvme_dump_registers,
1749 .link_reset = nvme_link_reset,
1750 .slot_reset = nvme_slot_reset,
1751 .resume = nvme_error_resume,
1752};
1753
1754/* Move to pci_ids.h later */
1755#define PCI_CLASS_STORAGE_EXPRESS 0x010802
1756
1757static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1758 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1759 { 0, }
1760};
1761MODULE_DEVICE_TABLE(pci, nvme_id_table);
1762
1763static struct pci_driver nvme_driver = {
1764 .name = "nvme",
1765 .id_table = nvme_id_table,
1766 .probe = nvme_probe,
1767 .remove = nvme_remove,
1768 .suspend = nvme_suspend,
1769 .resume = nvme_resume,
1770 .err_handler = &nvme_err_handler,
1771};
1772
1773static int __init nvme_init(void)
1774{
1775 int result;
1776
1777 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1778 if (IS_ERR(nvme_thread))
1779 return PTR_ERR(nvme_thread);
1780
1781 result = register_blkdev(nvme_major, "nvme");
1782 if (result < 0)
1783 goto kill_kthread;
1784 else if (result > 0)
1785 nvme_major = result;
1786
1787 result = pci_register_driver(&nvme_driver);
1788 if (result)
1789 goto unregister_blkdev;
1790 return 0;
1791
1792 unregister_blkdev:
1793 unregister_blkdev(nvme_major, "nvme");
1794 kill_kthread:
1795 kthread_stop(nvme_thread);
1796 return result;
1797}
1798
1799static void __exit nvme_exit(void)
1800{
1801 pci_unregister_driver(&nvme_driver);
1802 unregister_blkdev(nvme_major, "nvme");
1803 kthread_stop(nvme_thread);
1804}
1805
1806MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1807MODULE_LICENSE("GPL");
1808MODULE_VERSION("0.8");
1809module_init(nvme_init);
1810module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)