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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6-block.git] / drivers / ata / sata_promise.c
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1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/gfp.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/device.h>
43#include <scsi/scsi.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "sata_promise.h"
48
49#define DRV_NAME "sata_promise"
50#define DRV_VERSION "2.12"
51
52enum {
53 PDC_MAX_PORTS = 4,
54 PDC_MMIO_BAR = 3,
55 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
56
57 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
58 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
59 PDC_FLASH_CTL = 0x44, /* Flash control register */
60 PDC_PCI_CTL = 0x48, /* PCI control/status reg */
61 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
62 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
63 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
64 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
65
66 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
67 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
68 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
69 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
70 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
71 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
72 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
73 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
74 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
75 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
76 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
77 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
78
79 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
80 PDC_SATA_ERROR = 0x04,
81 PDC_PHYMODE4 = 0x14,
82 PDC_LINK_LAYER_ERRORS = 0x6C,
83 PDC_FPDMA_CTLSTAT = 0xD8,
84 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */
85 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */
86
87 /* PDC_FPDMA_CTLSTAT bit definitions */
88 PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
89 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
90 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
91
92 /* PDC_GLOBAL_CTL bit definitions */
93 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
94 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
95 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
96 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
97 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
98 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
99 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
100 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
101 PDC_DRIVE_ERR = (1 << 21), /* drive error */
102 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
103 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
104 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
105 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
106 PDC2_ATA_DMA_CNT_ERR,
107 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
108 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
109 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
110 PDC1_ERR_MASK | PDC2_ERR_MASK,
111
112 board_2037x = 0, /* FastTrak S150 TX2plus */
113 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
114 board_20319 = 2, /* FastTrak S150 TX4 */
115 board_20619 = 3, /* FastTrak TX4000 */
116 board_2057x = 4, /* SATAII150 Tx2plus */
117 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
118 board_40518 = 6, /* SATAII150 Tx4 */
119
120 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
121
122 /* Sequence counter control registers bit definitions */
123 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
124
125 /* Feature register values */
126 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
127 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
128
129 /* Device/Head register values */
130 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
131
132 /* PDC_CTLSTAT bit definitions */
133 PDC_DMA_ENABLE = (1 << 7),
134 PDC_IRQ_DISABLE = (1 << 10),
135 PDC_RESET = (1 << 11), /* HDMA reset */
136
137 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
138 ATA_FLAG_MMIO |
139 ATA_FLAG_PIO_POLLING,
140
141 /* ap->flags bits */
142 PDC_FLAG_GEN_II = (1 << 24),
143 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
144 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
145};
146
147struct pdc_port_priv {
148 u8 *pkt;
149 dma_addr_t pkt_dma;
150};
151
152static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
153static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
154static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
155static int pdc_common_port_start(struct ata_port *ap);
156static int pdc_sata_port_start(struct ata_port *ap);
157static void pdc_qc_prep(struct ata_queued_cmd *qc);
158static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
159static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
160static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
161static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
162static void pdc_irq_clear(struct ata_port *ap);
163static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
164static void pdc_freeze(struct ata_port *ap);
165static void pdc_sata_freeze(struct ata_port *ap);
166static void pdc_thaw(struct ata_port *ap);
167static void pdc_sata_thaw(struct ata_port *ap);
168static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
169 unsigned long deadline);
170static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
171 unsigned long deadline);
172static void pdc_error_handler(struct ata_port *ap);
173static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
174static int pdc_pata_cable_detect(struct ata_port *ap);
175static int pdc_sata_cable_detect(struct ata_port *ap);
176
177static struct scsi_host_template pdc_ata_sht = {
178 ATA_BASE_SHT(DRV_NAME),
179 .sg_tablesize = PDC_MAX_PRD,
180 .dma_boundary = ATA_DMA_BOUNDARY,
181};
182
183static const struct ata_port_operations pdc_common_ops = {
184 .inherits = &ata_sff_port_ops,
185
186 .sff_tf_load = pdc_tf_load_mmio,
187 .sff_exec_command = pdc_exec_command_mmio,
188 .check_atapi_dma = pdc_check_atapi_dma,
189 .qc_prep = pdc_qc_prep,
190 .qc_issue = pdc_qc_issue,
191
192 .sff_irq_clear = pdc_irq_clear,
193 .lost_interrupt = ATA_OP_NULL,
194
195 .post_internal_cmd = pdc_post_internal_cmd,
196 .error_handler = pdc_error_handler,
197};
198
199static struct ata_port_operations pdc_sata_ops = {
200 .inherits = &pdc_common_ops,
201 .cable_detect = pdc_sata_cable_detect,
202 .freeze = pdc_sata_freeze,
203 .thaw = pdc_sata_thaw,
204 .scr_read = pdc_sata_scr_read,
205 .scr_write = pdc_sata_scr_write,
206 .port_start = pdc_sata_port_start,
207 .hardreset = pdc_sata_hardreset,
208};
209
210/* First-generation chips need a more restrictive ->check_atapi_dma op,
211 and ->freeze/thaw that ignore the hotplug controls. */
212static struct ata_port_operations pdc_old_sata_ops = {
213 .inherits = &pdc_sata_ops,
214 .freeze = pdc_freeze,
215 .thaw = pdc_thaw,
216 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
217};
218
219static struct ata_port_operations pdc_pata_ops = {
220 .inherits = &pdc_common_ops,
221 .cable_detect = pdc_pata_cable_detect,
222 .freeze = pdc_freeze,
223 .thaw = pdc_thaw,
224 .port_start = pdc_common_port_start,
225 .softreset = pdc_pata_softreset,
226};
227
228static const struct ata_port_info pdc_port_info[] = {
229 [board_2037x] =
230 {
231 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
232 PDC_FLAG_SATA_PATA,
233 .pio_mask = ATA_PIO4,
234 .mwdma_mask = ATA_MWDMA2,
235 .udma_mask = ATA_UDMA6,
236 .port_ops = &pdc_old_sata_ops,
237 },
238
239 [board_2037x_pata] =
240 {
241 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
242 .pio_mask = ATA_PIO4,
243 .mwdma_mask = ATA_MWDMA2,
244 .udma_mask = ATA_UDMA6,
245 .port_ops = &pdc_pata_ops,
246 },
247
248 [board_20319] =
249 {
250 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
251 PDC_FLAG_4_PORTS,
252 .pio_mask = ATA_PIO4,
253 .mwdma_mask = ATA_MWDMA2,
254 .udma_mask = ATA_UDMA6,
255 .port_ops = &pdc_old_sata_ops,
256 },
257
258 [board_20619] =
259 {
260 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
261 PDC_FLAG_4_PORTS,
262 .pio_mask = ATA_PIO4,
263 .mwdma_mask = ATA_MWDMA2,
264 .udma_mask = ATA_UDMA6,
265 .port_ops = &pdc_pata_ops,
266 },
267
268 [board_2057x] =
269 {
270 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
271 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
272 .pio_mask = ATA_PIO4,
273 .mwdma_mask = ATA_MWDMA2,
274 .udma_mask = ATA_UDMA6,
275 .port_ops = &pdc_sata_ops,
276 },
277
278 [board_2057x_pata] =
279 {
280 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
281 PDC_FLAG_GEN_II,
282 .pio_mask = ATA_PIO4,
283 .mwdma_mask = ATA_MWDMA2,
284 .udma_mask = ATA_UDMA6,
285 .port_ops = &pdc_pata_ops,
286 },
287
288 [board_40518] =
289 {
290 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
291 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
292 .pio_mask = ATA_PIO4,
293 .mwdma_mask = ATA_MWDMA2,
294 .udma_mask = ATA_UDMA6,
295 .port_ops = &pdc_sata_ops,
296 },
297};
298
299static const struct pci_device_id pdc_ata_pci_tbl[] = {
300 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
301 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
302 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
303 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
304 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
305 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
306 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
307 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
308 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
309 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
310
311 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
312 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
313 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
314 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
315 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
316 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
317
318 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
319
320 { } /* terminate list */
321};
322
323static struct pci_driver pdc_ata_pci_driver = {
324 .name = DRV_NAME,
325 .id_table = pdc_ata_pci_tbl,
326 .probe = pdc_ata_init_one,
327 .remove = ata_pci_remove_one,
328};
329
330static int pdc_common_port_start(struct ata_port *ap)
331{
332 struct device *dev = ap->host->dev;
333 struct pdc_port_priv *pp;
334 int rc;
335
336 rc = ata_port_start(ap);
337 if (rc)
338 return rc;
339
340 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
341 if (!pp)
342 return -ENOMEM;
343
344 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
345 if (!pp->pkt)
346 return -ENOMEM;
347
348 ap->private_data = pp;
349
350 return 0;
351}
352
353static int pdc_sata_port_start(struct ata_port *ap)
354{
355 int rc;
356
357 rc = pdc_common_port_start(ap);
358 if (rc)
359 return rc;
360
361 /* fix up PHYMODE4 align timing */
362 if (ap->flags & PDC_FLAG_GEN_II) {
363 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
364 unsigned int tmp;
365
366 tmp = readl(sata_mmio + PDC_PHYMODE4);
367 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
368 writel(tmp, sata_mmio + PDC_PHYMODE4);
369 }
370
371 return 0;
372}
373
374static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
375{
376 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
377 u32 tmp;
378
379 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
380 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
381 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
382
383 /* It's not allowed to write to the entire FPDMA_CTLSTAT register
384 when NCQ is running. So do a byte-sized write to bits 10 and 11. */
385 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
386 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
387}
388
389static void pdc_fpdma_reset(struct ata_port *ap)
390{
391 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
392 u8 tmp;
393
394 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
395 tmp &= 0x7F;
396 tmp |= PDC_FPDMA_CTLSTAT_RESET;
397 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
398 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
399 udelay(100);
400 tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
401 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
402 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
403
404 pdc_fpdma_clear_interrupt_flag(ap);
405}
406
407static void pdc_not_at_command_packet_phase(struct ata_port *ap)
408{
409 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
410 unsigned int i;
411 u32 tmp;
412
413 /* check not at ASIC packet command phase */
414 for (i = 0; i < 100; ++i) {
415 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
416 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
417 if ((tmp & 0xF) != 1)
418 break;
419 udelay(100);
420 }
421}
422
423static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
424{
425 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
426
427 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
428 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
429}
430
431static void pdc_reset_port(struct ata_port *ap)
432{
433 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
434 unsigned int i;
435 u32 tmp;
436
437 if (ap->flags & PDC_FLAG_GEN_II)
438 pdc_not_at_command_packet_phase(ap);
439
440 tmp = readl(ata_ctlstat_mmio);
441 tmp |= PDC_RESET;
442 writel(tmp, ata_ctlstat_mmio);
443
444 for (i = 11; i > 0; i--) {
445 tmp = readl(ata_ctlstat_mmio);
446 if (tmp & PDC_RESET)
447 break;
448
449 udelay(100);
450
451 tmp |= PDC_RESET;
452 writel(tmp, ata_ctlstat_mmio);
453 }
454
455 tmp &= ~PDC_RESET;
456 writel(tmp, ata_ctlstat_mmio);
457 readl(ata_ctlstat_mmio); /* flush */
458
459 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
460 pdc_fpdma_reset(ap);
461 pdc_clear_internal_debug_record_error_register(ap);
462 }
463}
464
465static int pdc_pata_cable_detect(struct ata_port *ap)
466{
467 u8 tmp;
468 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
469
470 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
471 if (tmp & 0x01)
472 return ATA_CBL_PATA40;
473 return ATA_CBL_PATA80;
474}
475
476static int pdc_sata_cable_detect(struct ata_port *ap)
477{
478 return ATA_CBL_SATA;
479}
480
481static int pdc_sata_scr_read(struct ata_link *link,
482 unsigned int sc_reg, u32 *val)
483{
484 if (sc_reg > SCR_CONTROL)
485 return -EINVAL;
486 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
487 return 0;
488}
489
490static int pdc_sata_scr_write(struct ata_link *link,
491 unsigned int sc_reg, u32 val)
492{
493 if (sc_reg > SCR_CONTROL)
494 return -EINVAL;
495 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
496 return 0;
497}
498
499static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
500{
501 struct ata_port *ap = qc->ap;
502 dma_addr_t sg_table = ap->prd_dma;
503 unsigned int cdb_len = qc->dev->cdb_len;
504 u8 *cdb = qc->cdb;
505 struct pdc_port_priv *pp = ap->private_data;
506 u8 *buf = pp->pkt;
507 __le32 *buf32 = (__le32 *) buf;
508 unsigned int dev_sel, feature;
509
510 /* set control bits (byte 0), zero delay seq id (byte 3),
511 * and seq id (byte 2)
512 */
513 switch (qc->tf.protocol) {
514 case ATAPI_PROT_DMA:
515 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
516 buf32[0] = cpu_to_le32(PDC_PKT_READ);
517 else
518 buf32[0] = 0;
519 break;
520 case ATAPI_PROT_NODATA:
521 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
522 break;
523 default:
524 BUG();
525 break;
526 }
527 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
528 buf32[2] = 0; /* no next-packet */
529
530 /* select drive */
531 if (sata_scr_valid(&ap->link))
532 dev_sel = PDC_DEVICE_SATA;
533 else
534 dev_sel = qc->tf.device;
535
536 buf[12] = (1 << 5) | ATA_REG_DEVICE;
537 buf[13] = dev_sel;
538 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
539 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
540
541 buf[16] = (1 << 5) | ATA_REG_NSECT;
542 buf[17] = qc->tf.nsect;
543 buf[18] = (1 << 5) | ATA_REG_LBAL;
544 buf[19] = qc->tf.lbal;
545
546 /* set feature and byte counter registers */
547 if (qc->tf.protocol != ATAPI_PROT_DMA)
548 feature = PDC_FEATURE_ATAPI_PIO;
549 else
550 feature = PDC_FEATURE_ATAPI_DMA;
551
552 buf[20] = (1 << 5) | ATA_REG_FEATURE;
553 buf[21] = feature;
554 buf[22] = (1 << 5) | ATA_REG_BYTEL;
555 buf[23] = qc->tf.lbam;
556 buf[24] = (1 << 5) | ATA_REG_BYTEH;
557 buf[25] = qc->tf.lbah;
558
559 /* send ATAPI packet command 0xA0 */
560 buf[26] = (1 << 5) | ATA_REG_CMD;
561 buf[27] = qc->tf.command;
562
563 /* select drive and check DRQ */
564 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
565 buf[29] = dev_sel;
566
567 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
568 BUG_ON(cdb_len & ~0x1E);
569
570 /* append the CDB as the final part */
571 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
572 memcpy(buf+31, cdb, cdb_len);
573}
574
575/**
576 * pdc_fill_sg - Fill PCI IDE PRD table
577 * @qc: Metadata associated with taskfile to be transferred
578 *
579 * Fill PCI IDE PRD (scatter-gather) table with segments
580 * associated with the current disk command.
581 * Make sure hardware does not choke on it.
582 *
583 * LOCKING:
584 * spin_lock_irqsave(host lock)
585 *
586 */
587static void pdc_fill_sg(struct ata_queued_cmd *qc)
588{
589 struct ata_port *ap = qc->ap;
590 struct scatterlist *sg;
591 const u32 SG_COUNT_ASIC_BUG = 41*4;
592 unsigned int si, idx;
593 u32 len;
594
595 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
596 return;
597
598 idx = 0;
599 for_each_sg(qc->sg, sg, qc->n_elem, si) {
600 u32 addr, offset;
601 u32 sg_len;
602
603 /* determine if physical DMA addr spans 64K boundary.
604 * Note h/w doesn't support 64-bit, so we unconditionally
605 * truncate dma_addr_t to u32.
606 */
607 addr = (u32) sg_dma_address(sg);
608 sg_len = sg_dma_len(sg);
609
610 while (sg_len) {
611 offset = addr & 0xffff;
612 len = sg_len;
613 if ((offset + sg_len) > 0x10000)
614 len = 0x10000 - offset;
615
616 ap->prd[idx].addr = cpu_to_le32(addr);
617 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
618 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
619
620 idx++;
621 sg_len -= len;
622 addr += len;
623 }
624 }
625
626 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
627
628 if (len > SG_COUNT_ASIC_BUG) {
629 u32 addr;
630
631 VPRINTK("Splitting last PRD.\n");
632
633 addr = le32_to_cpu(ap->prd[idx - 1].addr);
634 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
635 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
636
637 addr = addr + len - SG_COUNT_ASIC_BUG;
638 len = SG_COUNT_ASIC_BUG;
639 ap->prd[idx].addr = cpu_to_le32(addr);
640 ap->prd[idx].flags_len = cpu_to_le32(len);
641 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
642
643 idx++;
644 }
645
646 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
647}
648
649static void pdc_qc_prep(struct ata_queued_cmd *qc)
650{
651 struct pdc_port_priv *pp = qc->ap->private_data;
652 unsigned int i;
653
654 VPRINTK("ENTER\n");
655
656 switch (qc->tf.protocol) {
657 case ATA_PROT_DMA:
658 pdc_fill_sg(qc);
659 /*FALLTHROUGH*/
660 case ATA_PROT_NODATA:
661 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
662 qc->dev->devno, pp->pkt);
663 if (qc->tf.flags & ATA_TFLAG_LBA48)
664 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
665 else
666 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
667 pdc_pkt_footer(&qc->tf, pp->pkt, i);
668 break;
669 case ATAPI_PROT_PIO:
670 pdc_fill_sg(qc);
671 break;
672 case ATAPI_PROT_DMA:
673 pdc_fill_sg(qc);
674 /*FALLTHROUGH*/
675 case ATAPI_PROT_NODATA:
676 pdc_atapi_pkt(qc);
677 break;
678 default:
679 break;
680 }
681}
682
683static int pdc_is_sataii_tx4(unsigned long flags)
684{
685 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
686 return (flags & mask) == mask;
687}
688
689static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
690 int is_sataii_tx4)
691{
692 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
693 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
694}
695
696static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
697{
698 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
699}
700
701static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
702{
703 const struct ata_host *host = ap->host;
704 unsigned int nr_ports = pdc_sata_nr_ports(ap);
705 unsigned int i;
706
707 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
708 ;
709 BUG_ON(i >= nr_ports);
710 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
711}
712
713static void pdc_freeze(struct ata_port *ap)
714{
715 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
716 u32 tmp;
717
718 tmp = readl(ata_mmio + PDC_CTLSTAT);
719 tmp |= PDC_IRQ_DISABLE;
720 tmp &= ~PDC_DMA_ENABLE;
721 writel(tmp, ata_mmio + PDC_CTLSTAT);
722 readl(ata_mmio + PDC_CTLSTAT); /* flush */
723}
724
725static void pdc_sata_freeze(struct ata_port *ap)
726{
727 struct ata_host *host = ap->host;
728 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
729 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
730 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
731 u32 hotplug_status;
732
733 /* Disable hotplug events on this port.
734 *
735 * Locking:
736 * 1) hotplug register accesses must be serialised via host->lock
737 * 2) ap->lock == &ap->host->lock
738 * 3) ->freeze() and ->thaw() are called with ap->lock held
739 */
740 hotplug_status = readl(host_mmio + hotplug_offset);
741 hotplug_status |= 0x11 << (ata_no + 16);
742 writel(hotplug_status, host_mmio + hotplug_offset);
743 readl(host_mmio + hotplug_offset); /* flush */
744
745 pdc_freeze(ap);
746}
747
748static void pdc_thaw(struct ata_port *ap)
749{
750 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
751 u32 tmp;
752
753 /* clear IRQ */
754 readl(ata_mmio + PDC_COMMAND);
755
756 /* turn IRQ back on */
757 tmp = readl(ata_mmio + PDC_CTLSTAT);
758 tmp &= ~PDC_IRQ_DISABLE;
759 writel(tmp, ata_mmio + PDC_CTLSTAT);
760 readl(ata_mmio + PDC_CTLSTAT); /* flush */
761}
762
763static void pdc_sata_thaw(struct ata_port *ap)
764{
765 struct ata_host *host = ap->host;
766 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
767 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
768 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
769 u32 hotplug_status;
770
771 pdc_thaw(ap);
772
773 /* Enable hotplug events on this port.
774 * Locking: see pdc_sata_freeze().
775 */
776 hotplug_status = readl(host_mmio + hotplug_offset);
777 hotplug_status |= 0x11 << ata_no;
778 hotplug_status &= ~(0x11 << (ata_no + 16));
779 writel(hotplug_status, host_mmio + hotplug_offset);
780 readl(host_mmio + hotplug_offset); /* flush */
781}
782
783static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
784 unsigned long deadline)
785{
786 pdc_reset_port(link->ap);
787 return ata_sff_softreset(link, class, deadline);
788}
789
790static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
791{
792 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
793 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
794
795 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
796 return (ata_mmio - host_mmio - 0x200) / 0x80;
797}
798
799static void pdc_hard_reset_port(struct ata_port *ap)
800{
801 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
802 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
803 unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
804 u8 tmp;
805
806 spin_lock(&ap->host->lock);
807
808 tmp = readb(pcictl_b1_mmio);
809 tmp &= ~(0x10 << ata_no);
810 writeb(tmp, pcictl_b1_mmio);
811 readb(pcictl_b1_mmio); /* flush */
812 udelay(100);
813 tmp |= (0x10 << ata_no);
814 writeb(tmp, pcictl_b1_mmio);
815 readb(pcictl_b1_mmio); /* flush */
816
817 spin_unlock(&ap->host->lock);
818}
819
820static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
821 unsigned long deadline)
822{
823 if (link->ap->flags & PDC_FLAG_GEN_II)
824 pdc_not_at_command_packet_phase(link->ap);
825 /* hotplug IRQs should have been masked by pdc_sata_freeze() */
826 pdc_hard_reset_port(link->ap);
827 pdc_reset_port(link->ap);
828
829 /* sata_promise can't reliably acquire the first D2H Reg FIS
830 * after hardreset. Do non-waiting hardreset and request
831 * follow-up SRST.
832 */
833 return sata_std_hardreset(link, class, deadline);
834}
835
836static void pdc_error_handler(struct ata_port *ap)
837{
838 if (!(ap->pflags & ATA_PFLAG_FROZEN))
839 pdc_reset_port(ap);
840
841 ata_std_error_handler(ap);
842}
843
844static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
845{
846 struct ata_port *ap = qc->ap;
847
848 /* make DMA engine forget about the failed command */
849 if (qc->flags & ATA_QCFLAG_FAILED)
850 pdc_reset_port(ap);
851}
852
853static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
854 u32 port_status, u32 err_mask)
855{
856 struct ata_eh_info *ehi = &ap->link.eh_info;
857 unsigned int ac_err_mask = 0;
858
859 ata_ehi_clear_desc(ehi);
860 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
861 port_status &= err_mask;
862
863 if (port_status & PDC_DRIVE_ERR)
864 ac_err_mask |= AC_ERR_DEV;
865 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
866 ac_err_mask |= AC_ERR_OTHER;
867 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
868 ac_err_mask |= AC_ERR_ATA_BUS;
869 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
870 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
871 ac_err_mask |= AC_ERR_HOST_BUS;
872
873 if (sata_scr_valid(&ap->link)) {
874 u32 serror;
875
876 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
877 ehi->serror |= serror;
878 }
879
880 qc->err_mask |= ac_err_mask;
881
882 pdc_reset_port(ap);
883
884 ata_port_abort(ap);
885}
886
887static unsigned int pdc_host_intr(struct ata_port *ap,
888 struct ata_queued_cmd *qc)
889{
890 unsigned int handled = 0;
891 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
892 u32 port_status, err_mask;
893
894 err_mask = PDC_ERR_MASK;
895 if (ap->flags & PDC_FLAG_GEN_II)
896 err_mask &= ~PDC1_ERR_MASK;
897 else
898 err_mask &= ~PDC2_ERR_MASK;
899 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
900 if (unlikely(port_status & err_mask)) {
901 pdc_error_intr(ap, qc, port_status, err_mask);
902 return 1;
903 }
904
905 switch (qc->tf.protocol) {
906 case ATA_PROT_DMA:
907 case ATA_PROT_NODATA:
908 case ATAPI_PROT_DMA:
909 case ATAPI_PROT_NODATA:
910 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
911 ata_qc_complete(qc);
912 handled = 1;
913 break;
914 default:
915 ap->stats.idle_irq++;
916 break;
917 }
918
919 return handled;
920}
921
922static void pdc_irq_clear(struct ata_port *ap)
923{
924 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
925
926 readl(ata_mmio + PDC_COMMAND);
927}
928
929static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
930{
931 struct ata_host *host = dev_instance;
932 struct ata_port *ap;
933 u32 mask = 0;
934 unsigned int i, tmp;
935 unsigned int handled = 0;
936 void __iomem *host_mmio;
937 unsigned int hotplug_offset, ata_no;
938 u32 hotplug_status;
939 int is_sataii_tx4;
940
941 VPRINTK("ENTER\n");
942
943 if (!host || !host->iomap[PDC_MMIO_BAR]) {
944 VPRINTK("QUICK EXIT\n");
945 return IRQ_NONE;
946 }
947
948 host_mmio = host->iomap[PDC_MMIO_BAR];
949
950 spin_lock(&host->lock);
951
952 /* read and clear hotplug flags for all ports */
953 if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
954 hotplug_offset = PDC2_SATA_PLUG_CSR;
955 hotplug_status = readl(host_mmio + hotplug_offset);
956 if (hotplug_status & 0xff)
957 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
958 hotplug_status &= 0xff; /* clear uninteresting bits */
959 } else
960 hotplug_status = 0;
961
962 /* reading should also clear interrupts */
963 mask = readl(host_mmio + PDC_INT_SEQMASK);
964
965 if (mask == 0xffffffff && hotplug_status == 0) {
966 VPRINTK("QUICK EXIT 2\n");
967 goto done_irq;
968 }
969
970 mask &= 0xffff; /* only 16 SEQIDs possible */
971 if (mask == 0 && hotplug_status == 0) {
972 VPRINTK("QUICK EXIT 3\n");
973 goto done_irq;
974 }
975
976 writel(mask, host_mmio + PDC_INT_SEQMASK);
977
978 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
979
980 for (i = 0; i < host->n_ports; i++) {
981 VPRINTK("port %u\n", i);
982 ap = host->ports[i];
983
984 /* check for a plug or unplug event */
985 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
986 tmp = hotplug_status & (0x11 << ata_no);
987 if (tmp && ap &&
988 !(ap->flags & ATA_FLAG_DISABLED)) {
989 struct ata_eh_info *ehi = &ap->link.eh_info;
990 ata_ehi_clear_desc(ehi);
991 ata_ehi_hotplugged(ehi);
992 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
993 ata_port_freeze(ap);
994 ++handled;
995 continue;
996 }
997
998 /* check for a packet interrupt */
999 tmp = mask & (1 << (i + 1));
1000 if (tmp && ap &&
1001 !(ap->flags & ATA_FLAG_DISABLED)) {
1002 struct ata_queued_cmd *qc;
1003
1004 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1005 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1006 handled += pdc_host_intr(ap, qc);
1007 }
1008 }
1009
1010 VPRINTK("EXIT\n");
1011
1012done_irq:
1013 spin_unlock(&host->lock);
1014 return IRQ_RETVAL(handled);
1015}
1016
1017static void pdc_packet_start(struct ata_queued_cmd *qc)
1018{
1019 struct ata_port *ap = qc->ap;
1020 struct pdc_port_priv *pp = ap->private_data;
1021 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1022 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1023 unsigned int port_no = ap->port_no;
1024 u8 seq = (u8) (port_no + 1);
1025
1026 VPRINTK("ENTER, ap %p\n", ap);
1027
1028 writel(0x00000001, host_mmio + (seq * 4));
1029 readl(host_mmio + (seq * 4)); /* flush */
1030
1031 pp->pkt[2] = seq;
1032 wmb(); /* flush PRD, pkt writes */
1033 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1034 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1035}
1036
1037static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1038{
1039 switch (qc->tf.protocol) {
1040 case ATAPI_PROT_NODATA:
1041 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1042 break;
1043 /*FALLTHROUGH*/
1044 case ATA_PROT_NODATA:
1045 if (qc->tf.flags & ATA_TFLAG_POLLING)
1046 break;
1047 /*FALLTHROUGH*/
1048 case ATAPI_PROT_DMA:
1049 case ATA_PROT_DMA:
1050 pdc_packet_start(qc);
1051 return 0;
1052 default:
1053 break;
1054 }
1055 return ata_sff_qc_issue(qc);
1056}
1057
1058static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1059{
1060 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1061 ata_sff_tf_load(ap, tf);
1062}
1063
1064static void pdc_exec_command_mmio(struct ata_port *ap,
1065 const struct ata_taskfile *tf)
1066{
1067 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1068 ata_sff_exec_command(ap, tf);
1069}
1070
1071static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1072{
1073 u8 *scsicmd = qc->scsicmd->cmnd;
1074 int pio = 1; /* atapi dma off by default */
1075
1076 /* Whitelist commands that may use DMA. */
1077 switch (scsicmd[0]) {
1078 case WRITE_12:
1079 case WRITE_10:
1080 case WRITE_6:
1081 case READ_12:
1082 case READ_10:
1083 case READ_6:
1084 case 0xad: /* READ_DVD_STRUCTURE */
1085 case 0xbe: /* READ_CD */
1086 pio = 0;
1087 }
1088 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1089 if (scsicmd[0] == WRITE_10) {
1090 unsigned int lba =
1091 (scsicmd[2] << 24) |
1092 (scsicmd[3] << 16) |
1093 (scsicmd[4] << 8) |
1094 scsicmd[5];
1095 if (lba >= 0xFFFF4FA2)
1096 pio = 1;
1097 }
1098 return pio;
1099}
1100
1101static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1102{
1103 /* First generation chips cannot use ATAPI DMA on SATA ports */
1104 return 1;
1105}
1106
1107static void pdc_ata_setup_port(struct ata_port *ap,
1108 void __iomem *base, void __iomem *scr_addr)
1109{
1110 ap->ioaddr.cmd_addr = base;
1111 ap->ioaddr.data_addr = base;
1112 ap->ioaddr.feature_addr =
1113 ap->ioaddr.error_addr = base + 0x4;
1114 ap->ioaddr.nsect_addr = base + 0x8;
1115 ap->ioaddr.lbal_addr = base + 0xc;
1116 ap->ioaddr.lbam_addr = base + 0x10;
1117 ap->ioaddr.lbah_addr = base + 0x14;
1118 ap->ioaddr.device_addr = base + 0x18;
1119 ap->ioaddr.command_addr =
1120 ap->ioaddr.status_addr = base + 0x1c;
1121 ap->ioaddr.altstatus_addr =
1122 ap->ioaddr.ctl_addr = base + 0x38;
1123 ap->ioaddr.scr_addr = scr_addr;
1124}
1125
1126static void pdc_host_init(struct ata_host *host)
1127{
1128 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1129 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1130 int hotplug_offset;
1131 u32 tmp;
1132
1133 if (is_gen2)
1134 hotplug_offset = PDC2_SATA_PLUG_CSR;
1135 else
1136 hotplug_offset = PDC_SATA_PLUG_CSR;
1137
1138 /*
1139 * Except for the hotplug stuff, this is voodoo from the
1140 * Promise driver. Label this entire section
1141 * "TODO: figure out why we do this"
1142 */
1143
1144 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1145 tmp = readl(host_mmio + PDC_FLASH_CTL);
1146 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1147 if (!is_gen2)
1148 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1149 writel(tmp, host_mmio + PDC_FLASH_CTL);
1150
1151 /* clear plug/unplug flags for all ports */
1152 tmp = readl(host_mmio + hotplug_offset);
1153 writel(tmp | 0xff, host_mmio + hotplug_offset);
1154
1155 tmp = readl(host_mmio + hotplug_offset);
1156 if (is_gen2) /* unmask plug/unplug ints */
1157 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1158 else /* mask plug/unplug ints */
1159 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1160
1161 /* don't initialise TBG or SLEW on 2nd generation chips */
1162 if (is_gen2)
1163 return;
1164
1165 /* reduce TBG clock to 133 Mhz. */
1166 tmp = readl(host_mmio + PDC_TBG_MODE);
1167 tmp &= ~0x30000; /* clear bit 17, 16*/
1168 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1169 writel(tmp, host_mmio + PDC_TBG_MODE);
1170
1171 readl(host_mmio + PDC_TBG_MODE); /* flush */
1172 msleep(10);
1173
1174 /* adjust slew rate control register. */
1175 tmp = readl(host_mmio + PDC_SLEW_CTL);
1176 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1177 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1178 writel(tmp, host_mmio + PDC_SLEW_CTL);
1179}
1180
1181static int pdc_ata_init_one(struct pci_dev *pdev,
1182 const struct pci_device_id *ent)
1183{
1184 static int printed_version;
1185 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1186 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1187 struct ata_host *host;
1188 void __iomem *host_mmio;
1189 int n_ports, i, rc;
1190 int is_sataii_tx4;
1191
1192 if (!printed_version++)
1193 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1194
1195 /* enable and acquire resources */
1196 rc = pcim_enable_device(pdev);
1197 if (rc)
1198 return rc;
1199
1200 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1201 if (rc == -EBUSY)
1202 pcim_pin_device(pdev);
1203 if (rc)
1204 return rc;
1205 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1206
1207 /* determine port configuration and setup host */
1208 n_ports = 2;
1209 if (pi->flags & PDC_FLAG_4_PORTS)
1210 n_ports = 4;
1211 for (i = 0; i < n_ports; i++)
1212 ppi[i] = pi;
1213
1214 if (pi->flags & PDC_FLAG_SATA_PATA) {
1215 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1216 if (!(tmp & 0x80))
1217 ppi[n_ports++] = pi + 1;
1218 }
1219
1220 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1221 if (!host) {
1222 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1223 return -ENOMEM;
1224 }
1225 host->iomap = pcim_iomap_table(pdev);
1226
1227 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1228 for (i = 0; i < host->n_ports; i++) {
1229 struct ata_port *ap = host->ports[i];
1230 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1231 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1232 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1233
1234 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1235
1236 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1237 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1238 }
1239
1240 /* initialize adapter */
1241 pdc_host_init(host);
1242
1243 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1244 if (rc)
1245 return rc;
1246 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1247 if (rc)
1248 return rc;
1249
1250 /* start host, request IRQ and attach */
1251 pci_set_master(pdev);
1252 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1253 &pdc_ata_sht);
1254}
1255
1256static int __init pdc_ata_init(void)
1257{
1258 return pci_register_driver(&pdc_ata_pci_driver);
1259}
1260
1261static void __exit pdc_ata_exit(void)
1262{
1263 pci_unregister_driver(&pdc_ata_pci_driver);
1264}
1265
1266MODULE_AUTHOR("Jeff Garzik");
1267MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1268MODULE_LICENSE("GPL");
1269MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1270MODULE_VERSION(DRV_VERSION);
1271
1272module_init(pdc_ata_init);
1273module_exit(pdc_ata_exit);
Linux 6.x block layer and io_uring tree(s)