| 1 | /* |
| 2 | * Intel IO-APIC support for multi-Pentium hosts. |
| 3 | * |
| 4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo |
| 5 | * |
| 6 | * Many thanks to Stig Venaas for trying out countless experimental |
| 7 | * patches and reporting/debugging problems patiently! |
| 8 | * |
| 9 | * (c) 1999, Multiple IO-APIC support, developed by |
| 10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and |
| 11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, |
| 12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> |
| 13 | * and Ingo Molnar <mingo@redhat.com> |
| 14 | * |
| 15 | * Fixes |
| 16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 17 | * thanks to Eric Gilmore |
| 18 | * and Rolf G. Tews |
| 19 | * for testing these extensively |
| 20 | * Paul Diefenbaugh : Added full ACPI support |
| 21 | */ |
| 22 | |
| 23 | #include <linux/mm.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/sched.h> |
| 28 | #include <linux/config.h> |
| 29 | #include <linux/smp_lock.h> |
| 30 | #include <linux/mc146818rtc.h> |
| 31 | #include <linux/acpi.h> |
| 32 | #include <linux/sysdev.h> |
| 33 | #ifdef CONFIG_ACPI |
| 34 | #include <acpi/acpi_bus.h> |
| 35 | #endif |
| 36 | |
| 37 | #include <asm/io.h> |
| 38 | #include <asm/smp.h> |
| 39 | #include <asm/desc.h> |
| 40 | #include <asm/proto.h> |
| 41 | #include <asm/mach_apic.h> |
| 42 | #include <asm/acpi.h> |
| 43 | #include <asm/dma.h> |
| 44 | #include <asm/nmi.h> |
| 45 | |
| 46 | #define __apicdebuginit __init |
| 47 | |
| 48 | int sis_apic_bug; /* not actually supported, dummy for compile */ |
| 49 | |
| 50 | static int no_timer_check; |
| 51 | |
| 52 | int disable_timer_pin_1 __initdata; |
| 53 | |
| 54 | int timer_over_8254 __initdata = 0; |
| 55 | |
| 56 | /* Where if anywhere is the i8259 connect in external int mode */ |
| 57 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; |
| 58 | |
| 59 | static DEFINE_SPINLOCK(ioapic_lock); |
| 60 | static DEFINE_SPINLOCK(vector_lock); |
| 61 | |
| 62 | /* |
| 63 | * # of IRQ routing registers |
| 64 | */ |
| 65 | int nr_ioapic_registers[MAX_IO_APICS]; |
| 66 | |
| 67 | /* |
| 68 | * Rough estimation of how many shared IRQs there are, can |
| 69 | * be changed anytime. |
| 70 | */ |
| 71 | #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS |
| 72 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) |
| 73 | |
| 74 | /* |
| 75 | * This is performance-critical, we want to do it O(1) |
| 76 | * |
| 77 | * the indexing order of this array favors 1:1 mappings |
| 78 | * between pins and IRQs. |
| 79 | */ |
| 80 | |
| 81 | static struct irq_pin_list { |
| 82 | short apic, pin, next; |
| 83 | } irq_2_pin[PIN_MAP_SIZE]; |
| 84 | |
| 85 | int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1}; |
| 86 | #ifdef CONFIG_PCI_MSI |
| 87 | #define vector_to_irq(vector) \ |
| 88 | (platform_legacy_irq(vector) ? vector : vector_irq[vector]) |
| 89 | #else |
| 90 | #define vector_to_irq(vector) (vector) |
| 91 | #endif |
| 92 | |
| 93 | #define __DO_ACTION(R, ACTION, FINAL) \ |
| 94 | \ |
| 95 | { \ |
| 96 | int pin; \ |
| 97 | struct irq_pin_list *entry = irq_2_pin + irq; \ |
| 98 | \ |
| 99 | BUG_ON(irq >= NR_IRQS); \ |
| 100 | for (;;) { \ |
| 101 | unsigned int reg; \ |
| 102 | pin = entry->pin; \ |
| 103 | if (pin == -1) \ |
| 104 | break; \ |
| 105 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ |
| 106 | reg ACTION; \ |
| 107 | io_apic_modify(entry->apic, reg); \ |
| 108 | if (!entry->next) \ |
| 109 | break; \ |
| 110 | entry = irq_2_pin + entry->next; \ |
| 111 | } \ |
| 112 | FINAL; \ |
| 113 | } |
| 114 | |
| 115 | #ifdef CONFIG_SMP |
| 116 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
| 117 | { |
| 118 | unsigned long flags; |
| 119 | unsigned int dest; |
| 120 | cpumask_t tmp; |
| 121 | |
| 122 | cpus_and(tmp, mask, cpu_online_map); |
| 123 | if (cpus_empty(tmp)) |
| 124 | tmp = TARGET_CPUS; |
| 125 | |
| 126 | cpus_and(mask, tmp, CPU_MASK_ALL); |
| 127 | |
| 128 | dest = cpu_mask_to_apicid(mask); |
| 129 | |
| 130 | /* |
| 131 | * Only the high 8 bits are valid. |
| 132 | */ |
| 133 | dest = SET_APIC_LOGICAL_ID(dest); |
| 134 | |
| 135 | spin_lock_irqsave(&ioapic_lock, flags); |
| 136 | __DO_ACTION(1, = dest, ) |
| 137 | set_irq_info(irq, mask); |
| 138 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 139 | } |
| 140 | #endif |
| 141 | |
| 142 | static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF }; |
| 143 | |
| 144 | /* |
| 145 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are |
| 146 | * shared ISA-space IRQs, so we have to support them. We are super |
| 147 | * fast in the common case, and fast for shared ISA-space IRQs. |
| 148 | */ |
| 149 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) |
| 150 | { |
| 151 | static int first_free_entry = NR_IRQS; |
| 152 | struct irq_pin_list *entry = irq_2_pin + irq; |
| 153 | |
| 154 | BUG_ON(irq >= NR_IRQS); |
| 155 | while (entry->next) |
| 156 | entry = irq_2_pin + entry->next; |
| 157 | |
| 158 | if (entry->pin != -1) { |
| 159 | entry->next = first_free_entry; |
| 160 | entry = irq_2_pin + entry->next; |
| 161 | if (++first_free_entry >= PIN_MAP_SIZE) |
| 162 | panic("io_apic.c: ran out of irq_2_pin entries!"); |
| 163 | } |
| 164 | entry->apic = apic; |
| 165 | entry->pin = pin; |
| 166 | } |
| 167 | |
| 168 | |
| 169 | #define DO_ACTION(name,R,ACTION, FINAL) \ |
| 170 | \ |
| 171 | static void name##_IO_APIC_irq (unsigned int irq) \ |
| 172 | __DO_ACTION(R, ACTION, FINAL) |
| 173 | |
| 174 | DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) |
| 175 | /* mask = 1 */ |
| 176 | DO_ACTION( __unmask, 0, &= 0xfffeffff, ) |
| 177 | /* mask = 0 */ |
| 178 | |
| 179 | static void mask_IO_APIC_irq (unsigned int irq) |
| 180 | { |
| 181 | unsigned long flags; |
| 182 | |
| 183 | spin_lock_irqsave(&ioapic_lock, flags); |
| 184 | __mask_IO_APIC_irq(irq); |
| 185 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 186 | } |
| 187 | |
| 188 | static void unmask_IO_APIC_irq (unsigned int irq) |
| 189 | { |
| 190 | unsigned long flags; |
| 191 | |
| 192 | spin_lock_irqsave(&ioapic_lock, flags); |
| 193 | __unmask_IO_APIC_irq(irq); |
| 194 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 195 | } |
| 196 | |
| 197 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
| 198 | { |
| 199 | struct IO_APIC_route_entry entry; |
| 200 | unsigned long flags; |
| 201 | |
| 202 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
| 203 | spin_lock_irqsave(&ioapic_lock, flags); |
| 204 | *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
| 205 | *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
| 206 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 207 | if (entry.delivery_mode == dest_SMI) |
| 208 | return; |
| 209 | /* |
| 210 | * Disable it in the IO-APIC irq-routing table: |
| 211 | */ |
| 212 | memset(&entry, 0, sizeof(entry)); |
| 213 | entry.mask = 1; |
| 214 | spin_lock_irqsave(&ioapic_lock, flags); |
| 215 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0)); |
| 216 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1)); |
| 217 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 218 | } |
| 219 | |
| 220 | static void clear_IO_APIC (void) |
| 221 | { |
| 222 | int apic, pin; |
| 223 | |
| 224 | for (apic = 0; apic < nr_ioapics; apic++) |
| 225 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
| 226 | clear_IO_APIC_pin(apic, pin); |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to |
| 231 | * specific CPU-side IRQs. |
| 232 | */ |
| 233 | |
| 234 | #define MAX_PIRQS 8 |
| 235 | static int pirq_entries [MAX_PIRQS]; |
| 236 | static int pirqs_enabled; |
| 237 | int skip_ioapic_setup; |
| 238 | int ioapic_force; |
| 239 | |
| 240 | /* dummy parsing: see setup.c */ |
| 241 | |
| 242 | static int __init disable_ioapic_setup(char *str) |
| 243 | { |
| 244 | skip_ioapic_setup = 1; |
| 245 | return 1; |
| 246 | } |
| 247 | |
| 248 | static int __init enable_ioapic_setup(char *str) |
| 249 | { |
| 250 | ioapic_force = 1; |
| 251 | skip_ioapic_setup = 0; |
| 252 | return 1; |
| 253 | } |
| 254 | |
| 255 | __setup("noapic", disable_ioapic_setup); |
| 256 | __setup("apic", enable_ioapic_setup); |
| 257 | |
| 258 | static int __init setup_disable_8254_timer(char *s) |
| 259 | { |
| 260 | timer_over_8254 = -1; |
| 261 | return 1; |
| 262 | } |
| 263 | static int __init setup_enable_8254_timer(char *s) |
| 264 | { |
| 265 | timer_over_8254 = 2; |
| 266 | return 1; |
| 267 | } |
| 268 | |
| 269 | __setup("disable_8254_timer", setup_disable_8254_timer); |
| 270 | __setup("enable_8254_timer", setup_enable_8254_timer); |
| 271 | |
| 272 | #include <asm/pci-direct.h> |
| 273 | #include <linux/pci_ids.h> |
| 274 | #include <linux/pci.h> |
| 275 | |
| 276 | |
| 277 | #ifdef CONFIG_ACPI |
| 278 | |
| 279 | static int nvidia_hpet_detected __initdata; |
| 280 | |
| 281 | static int __init nvidia_hpet_check(unsigned long phys, unsigned long size) |
| 282 | { |
| 283 | nvidia_hpet_detected = 1; |
| 284 | return 0; |
| 285 | } |
| 286 | #endif |
| 287 | |
| 288 | /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC |
| 289 | off. Check for an Nvidia or VIA PCI bridge and turn it off. |
| 290 | Use pci direct infrastructure because this runs before the PCI subsystem. |
| 291 | |
| 292 | Can be overwritten with "apic" |
| 293 | |
| 294 | And another hack to disable the IOMMU on VIA chipsets. |
| 295 | |
| 296 | ... and others. Really should move this somewhere else. |
| 297 | |
| 298 | Kludge-O-Rama. */ |
| 299 | void __init check_ioapic(void) |
| 300 | { |
| 301 | int num,slot,func; |
| 302 | /* Poor man's PCI discovery */ |
| 303 | for (num = 0; num < 32; num++) { |
| 304 | for (slot = 0; slot < 32; slot++) { |
| 305 | for (func = 0; func < 8; func++) { |
| 306 | u32 class; |
| 307 | u32 vendor; |
| 308 | u8 type; |
| 309 | class = read_pci_config(num,slot,func, |
| 310 | PCI_CLASS_REVISION); |
| 311 | if (class == 0xffffffff) |
| 312 | break; |
| 313 | |
| 314 | if ((class >> 16) != PCI_CLASS_BRIDGE_PCI) |
| 315 | continue; |
| 316 | |
| 317 | vendor = read_pci_config(num, slot, func, |
| 318 | PCI_VENDOR_ID); |
| 319 | vendor &= 0xffff; |
| 320 | switch (vendor) { |
| 321 | case PCI_VENDOR_ID_VIA: |
| 322 | #ifdef CONFIG_GART_IOMMU |
| 323 | if ((end_pfn > MAX_DMA32_PFN || |
| 324 | force_iommu) && |
| 325 | !iommu_aperture_allowed) { |
| 326 | printk(KERN_INFO |
| 327 | "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n"); |
| 328 | iommu_aperture_disabled = 1; |
| 329 | } |
| 330 | #endif |
| 331 | return; |
| 332 | case PCI_VENDOR_ID_NVIDIA: |
| 333 | #ifdef CONFIG_ACPI |
| 334 | /* |
| 335 | * All timer overrides on Nvidia are |
| 336 | * wrong unless HPET is enabled. |
| 337 | */ |
| 338 | nvidia_hpet_detected = 0; |
| 339 | acpi_table_parse(ACPI_HPET, |
| 340 | nvidia_hpet_check); |
| 341 | if (nvidia_hpet_detected == 0) { |
| 342 | acpi_skip_timer_override = 1; |
| 343 | printk(KERN_INFO "Nvidia board " |
| 344 | "detected. Ignoring ACPI " |
| 345 | "timer override.\n"); |
| 346 | } |
| 347 | #endif |
| 348 | /* RED-PEN skip them on mptables too? */ |
| 349 | return; |
| 350 | |
| 351 | /* This should be actually default, but |
| 352 | for 2.6.16 let's do it for ATI only where |
| 353 | it's really needed. */ |
| 354 | case PCI_VENDOR_ID_ATI: |
| 355 | if (timer_over_8254 == 1) { |
| 356 | timer_over_8254 = 0; |
| 357 | printk(KERN_INFO |
| 358 | "ATI board detected. Disabling timer routing over 8254.\n"); |
| 359 | } |
| 360 | return; |
| 361 | } |
| 362 | |
| 363 | |
| 364 | /* No multi-function device? */ |
| 365 | type = read_pci_config_byte(num,slot,func, |
| 366 | PCI_HEADER_TYPE); |
| 367 | if (!(type & 0x80)) |
| 368 | break; |
| 369 | } |
| 370 | } |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | static int __init ioapic_pirq_setup(char *str) |
| 375 | { |
| 376 | int i, max; |
| 377 | int ints[MAX_PIRQS+1]; |
| 378 | |
| 379 | get_options(str, ARRAY_SIZE(ints), ints); |
| 380 | |
| 381 | for (i = 0; i < MAX_PIRQS; i++) |
| 382 | pirq_entries[i] = -1; |
| 383 | |
| 384 | pirqs_enabled = 1; |
| 385 | apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n"); |
| 386 | max = MAX_PIRQS; |
| 387 | if (ints[0] < MAX_PIRQS) |
| 388 | max = ints[0]; |
| 389 | |
| 390 | for (i = 0; i < max; i++) { |
| 391 | apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); |
| 392 | /* |
| 393 | * PIRQs are mapped upside down, usually. |
| 394 | */ |
| 395 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; |
| 396 | } |
| 397 | return 1; |
| 398 | } |
| 399 | |
| 400 | __setup("pirq=", ioapic_pirq_setup); |
| 401 | |
| 402 | /* |
| 403 | * Find the IRQ entry number of a certain pin. |
| 404 | */ |
| 405 | static int find_irq_entry(int apic, int pin, int type) |
| 406 | { |
| 407 | int i; |
| 408 | |
| 409 | for (i = 0; i < mp_irq_entries; i++) |
| 410 | if (mp_irqs[i].mpc_irqtype == type && |
| 411 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || |
| 412 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && |
| 413 | mp_irqs[i].mpc_dstirq == pin) |
| 414 | return i; |
| 415 | |
| 416 | return -1; |
| 417 | } |
| 418 | |
| 419 | /* |
| 420 | * Find the pin to which IRQ[irq] (ISA) is connected |
| 421 | */ |
| 422 | static int __init find_isa_irq_pin(int irq, int type) |
| 423 | { |
| 424 | int i; |
| 425 | |
| 426 | for (i = 0; i < mp_irq_entries; i++) { |
| 427 | int lbus = mp_irqs[i].mpc_srcbus; |
| 428 | |
| 429 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || |
| 430 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || |
| 431 | mp_bus_id_to_type[lbus] == MP_BUS_MCA) && |
| 432 | (mp_irqs[i].mpc_irqtype == type) && |
| 433 | (mp_irqs[i].mpc_srcbusirq == irq)) |
| 434 | |
| 435 | return mp_irqs[i].mpc_dstirq; |
| 436 | } |
| 437 | return -1; |
| 438 | } |
| 439 | |
| 440 | static int __init find_isa_irq_apic(int irq, int type) |
| 441 | { |
| 442 | int i; |
| 443 | |
| 444 | for (i = 0; i < mp_irq_entries; i++) { |
| 445 | int lbus = mp_irqs[i].mpc_srcbus; |
| 446 | |
| 447 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || |
| 448 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || |
| 449 | mp_bus_id_to_type[lbus] == MP_BUS_MCA) && |
| 450 | (mp_irqs[i].mpc_irqtype == type) && |
| 451 | (mp_irqs[i].mpc_srcbusirq == irq)) |
| 452 | break; |
| 453 | } |
| 454 | if (i < mp_irq_entries) { |
| 455 | int apic; |
| 456 | for(apic = 0; apic < nr_ioapics; apic++) { |
| 457 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) |
| 458 | return apic; |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | return -1; |
| 463 | } |
| 464 | |
| 465 | /* |
| 466 | * Find a specific PCI IRQ entry. |
| 467 | * Not an __init, possibly needed by modules |
| 468 | */ |
| 469 | static int pin_2_irq(int idx, int apic, int pin); |
| 470 | |
| 471 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
| 472 | { |
| 473 | int apic, i, best_guess = -1; |
| 474 | |
| 475 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
| 476 | bus, slot, pin); |
| 477 | if (mp_bus_id_to_pci_bus[bus] == -1) { |
| 478 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
| 479 | return -1; |
| 480 | } |
| 481 | for (i = 0; i < mp_irq_entries; i++) { |
| 482 | int lbus = mp_irqs[i].mpc_srcbus; |
| 483 | |
| 484 | for (apic = 0; apic < nr_ioapics; apic++) |
| 485 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || |
| 486 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) |
| 487 | break; |
| 488 | |
| 489 | if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && |
| 490 | !mp_irqs[i].mpc_irqtype && |
| 491 | (bus == lbus) && |
| 492 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { |
| 493 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); |
| 494 | |
| 495 | if (!(apic || IO_APIC_IRQ(irq))) |
| 496 | continue; |
| 497 | |
| 498 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) |
| 499 | return irq; |
| 500 | /* |
| 501 | * Use the first all-but-pin matching entry as a |
| 502 | * best-guess fuzzy result for broken mptables. |
| 503 | */ |
| 504 | if (best_guess < 0) |
| 505 | best_guess = irq; |
| 506 | } |
| 507 | } |
| 508 | BUG_ON(best_guess >= NR_IRQS); |
| 509 | return best_guess; |
| 510 | } |
| 511 | |
| 512 | /* |
| 513 | * EISA Edge/Level control register, ELCR |
| 514 | */ |
| 515 | static int EISA_ELCR(unsigned int irq) |
| 516 | { |
| 517 | if (irq < 16) { |
| 518 | unsigned int port = 0x4d0 + (irq >> 3); |
| 519 | return (inb(port) >> (irq & 7)) & 1; |
| 520 | } |
| 521 | apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq); |
| 522 | return 0; |
| 523 | } |
| 524 | |
| 525 | /* EISA interrupts are always polarity zero and can be edge or level |
| 526 | * trigger depending on the ELCR value. If an interrupt is listed as |
| 527 | * EISA conforming in the MP table, that means its trigger type must |
| 528 | * be read in from the ELCR */ |
| 529 | |
| 530 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) |
| 531 | #define default_EISA_polarity(idx) (0) |
| 532 | |
| 533 | /* ISA interrupts are always polarity zero edge triggered, |
| 534 | * when listed as conforming in the MP table. */ |
| 535 | |
| 536 | #define default_ISA_trigger(idx) (0) |
| 537 | #define default_ISA_polarity(idx) (0) |
| 538 | |
| 539 | /* PCI interrupts are always polarity one level triggered, |
| 540 | * when listed as conforming in the MP table. */ |
| 541 | |
| 542 | #define default_PCI_trigger(idx) (1) |
| 543 | #define default_PCI_polarity(idx) (1) |
| 544 | |
| 545 | /* MCA interrupts are always polarity zero level triggered, |
| 546 | * when listed as conforming in the MP table. */ |
| 547 | |
| 548 | #define default_MCA_trigger(idx) (1) |
| 549 | #define default_MCA_polarity(idx) (0) |
| 550 | |
| 551 | static int __init MPBIOS_polarity(int idx) |
| 552 | { |
| 553 | int bus = mp_irqs[idx].mpc_srcbus; |
| 554 | int polarity; |
| 555 | |
| 556 | /* |
| 557 | * Determine IRQ line polarity (high active or low active): |
| 558 | */ |
| 559 | switch (mp_irqs[idx].mpc_irqflag & 3) |
| 560 | { |
| 561 | case 0: /* conforms, ie. bus-type dependent polarity */ |
| 562 | { |
| 563 | switch (mp_bus_id_to_type[bus]) |
| 564 | { |
| 565 | case MP_BUS_ISA: /* ISA pin */ |
| 566 | { |
| 567 | polarity = default_ISA_polarity(idx); |
| 568 | break; |
| 569 | } |
| 570 | case MP_BUS_EISA: /* EISA pin */ |
| 571 | { |
| 572 | polarity = default_EISA_polarity(idx); |
| 573 | break; |
| 574 | } |
| 575 | case MP_BUS_PCI: /* PCI pin */ |
| 576 | { |
| 577 | polarity = default_PCI_polarity(idx); |
| 578 | break; |
| 579 | } |
| 580 | case MP_BUS_MCA: /* MCA pin */ |
| 581 | { |
| 582 | polarity = default_MCA_polarity(idx); |
| 583 | break; |
| 584 | } |
| 585 | default: |
| 586 | { |
| 587 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 588 | polarity = 1; |
| 589 | break; |
| 590 | } |
| 591 | } |
| 592 | break; |
| 593 | } |
| 594 | case 1: /* high active */ |
| 595 | { |
| 596 | polarity = 0; |
| 597 | break; |
| 598 | } |
| 599 | case 2: /* reserved */ |
| 600 | { |
| 601 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 602 | polarity = 1; |
| 603 | break; |
| 604 | } |
| 605 | case 3: /* low active */ |
| 606 | { |
| 607 | polarity = 1; |
| 608 | break; |
| 609 | } |
| 610 | default: /* invalid */ |
| 611 | { |
| 612 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 613 | polarity = 1; |
| 614 | break; |
| 615 | } |
| 616 | } |
| 617 | return polarity; |
| 618 | } |
| 619 | |
| 620 | static int MPBIOS_trigger(int idx) |
| 621 | { |
| 622 | int bus = mp_irqs[idx].mpc_srcbus; |
| 623 | int trigger; |
| 624 | |
| 625 | /* |
| 626 | * Determine IRQ trigger mode (edge or level sensitive): |
| 627 | */ |
| 628 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) |
| 629 | { |
| 630 | case 0: /* conforms, ie. bus-type dependent */ |
| 631 | { |
| 632 | switch (mp_bus_id_to_type[bus]) |
| 633 | { |
| 634 | case MP_BUS_ISA: /* ISA pin */ |
| 635 | { |
| 636 | trigger = default_ISA_trigger(idx); |
| 637 | break; |
| 638 | } |
| 639 | case MP_BUS_EISA: /* EISA pin */ |
| 640 | { |
| 641 | trigger = default_EISA_trigger(idx); |
| 642 | break; |
| 643 | } |
| 644 | case MP_BUS_PCI: /* PCI pin */ |
| 645 | { |
| 646 | trigger = default_PCI_trigger(idx); |
| 647 | break; |
| 648 | } |
| 649 | case MP_BUS_MCA: /* MCA pin */ |
| 650 | { |
| 651 | trigger = default_MCA_trigger(idx); |
| 652 | break; |
| 653 | } |
| 654 | default: |
| 655 | { |
| 656 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 657 | trigger = 1; |
| 658 | break; |
| 659 | } |
| 660 | } |
| 661 | break; |
| 662 | } |
| 663 | case 1: /* edge */ |
| 664 | { |
| 665 | trigger = 0; |
| 666 | break; |
| 667 | } |
| 668 | case 2: /* reserved */ |
| 669 | { |
| 670 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 671 | trigger = 1; |
| 672 | break; |
| 673 | } |
| 674 | case 3: /* level */ |
| 675 | { |
| 676 | trigger = 1; |
| 677 | break; |
| 678 | } |
| 679 | default: /* invalid */ |
| 680 | { |
| 681 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 682 | trigger = 0; |
| 683 | break; |
| 684 | } |
| 685 | } |
| 686 | return trigger; |
| 687 | } |
| 688 | |
| 689 | static inline int irq_polarity(int idx) |
| 690 | { |
| 691 | return MPBIOS_polarity(idx); |
| 692 | } |
| 693 | |
| 694 | static inline int irq_trigger(int idx) |
| 695 | { |
| 696 | return MPBIOS_trigger(idx); |
| 697 | } |
| 698 | |
| 699 | static int next_irq = 16; |
| 700 | |
| 701 | /* |
| 702 | * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ |
| 703 | * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number |
| 704 | * from ACPI, which can reach 800 in large boxen. |
| 705 | * |
| 706 | * Compact the sparse GSI space into a sequential IRQ series and reuse |
| 707 | * vectors if possible. |
| 708 | */ |
| 709 | int gsi_irq_sharing(int gsi) |
| 710 | { |
| 711 | int i, tries, vector; |
| 712 | |
| 713 | BUG_ON(gsi >= NR_IRQ_VECTORS); |
| 714 | |
| 715 | if (platform_legacy_irq(gsi)) |
| 716 | return gsi; |
| 717 | |
| 718 | if (gsi_2_irq[gsi] != 0xFF) |
| 719 | return (int)gsi_2_irq[gsi]; |
| 720 | |
| 721 | tries = NR_IRQS; |
| 722 | try_again: |
| 723 | vector = assign_irq_vector(gsi); |
| 724 | |
| 725 | /* |
| 726 | * Sharing vectors means sharing IRQs, so scan irq_vectors for previous |
| 727 | * use of vector and if found, return that IRQ. However, we never want |
| 728 | * to share legacy IRQs, which usually have a different trigger mode |
| 729 | * than PCI. |
| 730 | */ |
| 731 | for (i = 0; i < NR_IRQS; i++) |
| 732 | if (IO_APIC_VECTOR(i) == vector) |
| 733 | break; |
| 734 | if (platform_legacy_irq(i)) { |
| 735 | if (--tries >= 0) { |
| 736 | IO_APIC_VECTOR(i) = 0; |
| 737 | goto try_again; |
| 738 | } |
| 739 | panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi); |
| 740 | } |
| 741 | if (i < NR_IRQS) { |
| 742 | gsi_2_irq[gsi] = i; |
| 743 | printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n", |
| 744 | gsi, vector, i); |
| 745 | return i; |
| 746 | } |
| 747 | |
| 748 | i = next_irq++; |
| 749 | BUG_ON(i >= NR_IRQS); |
| 750 | gsi_2_irq[gsi] = i; |
| 751 | IO_APIC_VECTOR(i) = vector; |
| 752 | printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n", |
| 753 | gsi, vector, i); |
| 754 | return i; |
| 755 | } |
| 756 | |
| 757 | static int pin_2_irq(int idx, int apic, int pin) |
| 758 | { |
| 759 | int irq, i; |
| 760 | int bus = mp_irqs[idx].mpc_srcbus; |
| 761 | |
| 762 | /* |
| 763 | * Debugging check, we are in big trouble if this message pops up! |
| 764 | */ |
| 765 | if (mp_irqs[idx].mpc_dstirq != pin) |
| 766 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
| 767 | |
| 768 | switch (mp_bus_id_to_type[bus]) |
| 769 | { |
| 770 | case MP_BUS_ISA: /* ISA pin */ |
| 771 | case MP_BUS_EISA: |
| 772 | case MP_BUS_MCA: |
| 773 | { |
| 774 | irq = mp_irqs[idx].mpc_srcbusirq; |
| 775 | break; |
| 776 | } |
| 777 | case MP_BUS_PCI: /* PCI pin */ |
| 778 | { |
| 779 | /* |
| 780 | * PCI IRQs are mapped in order |
| 781 | */ |
| 782 | i = irq = 0; |
| 783 | while (i < apic) |
| 784 | irq += nr_ioapic_registers[i++]; |
| 785 | irq += pin; |
| 786 | irq = gsi_irq_sharing(irq); |
| 787 | break; |
| 788 | } |
| 789 | default: |
| 790 | { |
| 791 | printk(KERN_ERR "unknown bus type %d.\n",bus); |
| 792 | irq = 0; |
| 793 | break; |
| 794 | } |
| 795 | } |
| 796 | BUG_ON(irq >= NR_IRQS); |
| 797 | |
| 798 | /* |
| 799 | * PCI IRQ command line redirection. Yes, limits are hardcoded. |
| 800 | */ |
| 801 | if ((pin >= 16) && (pin <= 23)) { |
| 802 | if (pirq_entries[pin-16] != -1) { |
| 803 | if (!pirq_entries[pin-16]) { |
| 804 | apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16); |
| 805 | } else { |
| 806 | irq = pirq_entries[pin-16]; |
| 807 | apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n", |
| 808 | pin-16, irq); |
| 809 | } |
| 810 | } |
| 811 | } |
| 812 | BUG_ON(irq >= NR_IRQS); |
| 813 | return irq; |
| 814 | } |
| 815 | |
| 816 | static inline int IO_APIC_irq_trigger(int irq) |
| 817 | { |
| 818 | int apic, idx, pin; |
| 819 | |
| 820 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 821 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
| 822 | idx = find_irq_entry(apic,pin,mp_INT); |
| 823 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) |
| 824 | return irq_trigger(idx); |
| 825 | } |
| 826 | } |
| 827 | /* |
| 828 | * nonexistent IRQs are edge default |
| 829 | */ |
| 830 | return 0; |
| 831 | } |
| 832 | |
| 833 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ |
| 834 | u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
| 835 | |
| 836 | int assign_irq_vector(int irq) |
| 837 | { |
| 838 | static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; |
| 839 | int vector; |
| 840 | |
| 841 | BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS); |
| 842 | |
| 843 | spin_lock(&vector_lock); |
| 844 | |
| 845 | if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) { |
| 846 | spin_unlock(&vector_lock); |
| 847 | return IO_APIC_VECTOR(irq); |
| 848 | } |
| 849 | next: |
| 850 | current_vector += 8; |
| 851 | if (current_vector == IA32_SYSCALL_VECTOR) |
| 852 | goto next; |
| 853 | |
| 854 | if (current_vector >= FIRST_SYSTEM_VECTOR) { |
| 855 | /* If we run out of vectors on large boxen, must share them. */ |
| 856 | offset = (offset + 1) % 8; |
| 857 | current_vector = FIRST_DEVICE_VECTOR + offset; |
| 858 | } |
| 859 | |
| 860 | vector = current_vector; |
| 861 | vector_irq[vector] = irq; |
| 862 | if (irq != AUTO_ASSIGN) |
| 863 | IO_APIC_VECTOR(irq) = vector; |
| 864 | |
| 865 | spin_unlock(&vector_lock); |
| 866 | |
| 867 | return vector; |
| 868 | } |
| 869 | |
| 870 | extern void (*interrupt[NR_IRQS])(void); |
| 871 | static struct hw_interrupt_type ioapic_level_type; |
| 872 | static struct hw_interrupt_type ioapic_edge_type; |
| 873 | |
| 874 | #define IOAPIC_AUTO -1 |
| 875 | #define IOAPIC_EDGE 0 |
| 876 | #define IOAPIC_LEVEL 1 |
| 877 | |
| 878 | static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
| 879 | { |
| 880 | unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; |
| 881 | |
| 882 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
| 883 | trigger == IOAPIC_LEVEL) |
| 884 | irq_desc[idx].handler = &ioapic_level_type; |
| 885 | else |
| 886 | irq_desc[idx].handler = &ioapic_edge_type; |
| 887 | set_intr_gate(vector, interrupt[idx]); |
| 888 | } |
| 889 | |
| 890 | static void __init setup_IO_APIC_irqs(void) |
| 891 | { |
| 892 | struct IO_APIC_route_entry entry; |
| 893 | int apic, pin, idx, irq, first_notcon = 1, vector; |
| 894 | unsigned long flags; |
| 895 | |
| 896 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); |
| 897 | |
| 898 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 899 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
| 900 | |
| 901 | /* |
| 902 | * add it to the IO-APIC irq-routing table: |
| 903 | */ |
| 904 | memset(&entry,0,sizeof(entry)); |
| 905 | |
| 906 | entry.delivery_mode = INT_DELIVERY_MODE; |
| 907 | entry.dest_mode = INT_DEST_MODE; |
| 908 | entry.mask = 0; /* enable IRQ */ |
| 909 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
| 910 | |
| 911 | idx = find_irq_entry(apic,pin,mp_INT); |
| 912 | if (idx == -1) { |
| 913 | if (first_notcon) { |
| 914 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin); |
| 915 | first_notcon = 0; |
| 916 | } else |
| 917 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin); |
| 918 | continue; |
| 919 | } |
| 920 | |
| 921 | entry.trigger = irq_trigger(idx); |
| 922 | entry.polarity = irq_polarity(idx); |
| 923 | |
| 924 | if (irq_trigger(idx)) { |
| 925 | entry.trigger = 1; |
| 926 | entry.mask = 1; |
| 927 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
| 928 | } |
| 929 | |
| 930 | irq = pin_2_irq(idx, apic, pin); |
| 931 | add_pin_to_irq(irq, apic, pin); |
| 932 | |
| 933 | if (!apic && !IO_APIC_IRQ(irq)) |
| 934 | continue; |
| 935 | |
| 936 | if (IO_APIC_IRQ(irq)) { |
| 937 | vector = assign_irq_vector(irq); |
| 938 | entry.vector = vector; |
| 939 | |
| 940 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); |
| 941 | if (!apic && (irq < 16)) |
| 942 | disable_8259A_irq(irq); |
| 943 | } |
| 944 | spin_lock_irqsave(&ioapic_lock, flags); |
| 945 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
| 946 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); |
| 947 | set_native_irq_info(irq, TARGET_CPUS); |
| 948 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 949 | } |
| 950 | } |
| 951 | |
| 952 | if (!first_notcon) |
| 953 | apic_printk(APIC_VERBOSE," not connected.\n"); |
| 954 | } |
| 955 | |
| 956 | /* |
| 957 | * Set up the 8259A-master output pin as broadcast to all |
| 958 | * CPUs. |
| 959 | */ |
| 960 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
| 961 | { |
| 962 | struct IO_APIC_route_entry entry; |
| 963 | unsigned long flags; |
| 964 | |
| 965 | memset(&entry,0,sizeof(entry)); |
| 966 | |
| 967 | disable_8259A_irq(0); |
| 968 | |
| 969 | /* mask LVT0 */ |
| 970 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
| 971 | |
| 972 | /* |
| 973 | * We use logical delivery to get the timer IRQ |
| 974 | * to the first CPU. |
| 975 | */ |
| 976 | entry.dest_mode = INT_DEST_MODE; |
| 977 | entry.mask = 0; /* unmask IRQ now */ |
| 978 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
| 979 | entry.delivery_mode = INT_DELIVERY_MODE; |
| 980 | entry.polarity = 0; |
| 981 | entry.trigger = 0; |
| 982 | entry.vector = vector; |
| 983 | |
| 984 | /* |
| 985 | * The timer IRQ doesn't have to know that behind the |
| 986 | * scene we have a 8259A-master in AEOI mode ... |
| 987 | */ |
| 988 | irq_desc[0].handler = &ioapic_edge_type; |
| 989 | |
| 990 | /* |
| 991 | * Add it to the IO-APIC irq-routing table: |
| 992 | */ |
| 993 | spin_lock_irqsave(&ioapic_lock, flags); |
| 994 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
| 995 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); |
| 996 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 997 | |
| 998 | enable_8259A_irq(0); |
| 999 | } |
| 1000 | |
| 1001 | void __init UNEXPECTED_IO_APIC(void) |
| 1002 | { |
| 1003 | } |
| 1004 | |
| 1005 | void __apicdebuginit print_IO_APIC(void) |
| 1006 | { |
| 1007 | int apic, i; |
| 1008 | union IO_APIC_reg_00 reg_00; |
| 1009 | union IO_APIC_reg_01 reg_01; |
| 1010 | union IO_APIC_reg_02 reg_02; |
| 1011 | unsigned long flags; |
| 1012 | |
| 1013 | if (apic_verbosity == APIC_QUIET) |
| 1014 | return; |
| 1015 | |
| 1016 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
| 1017 | for (i = 0; i < nr_ioapics; i++) |
| 1018 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
| 1019 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); |
| 1020 | |
| 1021 | /* |
| 1022 | * We are a bit conservative about what we expect. We have to |
| 1023 | * know about every hardware change ASAP. |
| 1024 | */ |
| 1025 | printk(KERN_INFO "testing the IO APIC.......................\n"); |
| 1026 | |
| 1027 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 1028 | |
| 1029 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1030 | reg_00.raw = io_apic_read(apic, 0); |
| 1031 | reg_01.raw = io_apic_read(apic, 1); |
| 1032 | if (reg_01.bits.version >= 0x10) |
| 1033 | reg_02.raw = io_apic_read(apic, 2); |
| 1034 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1035 | |
| 1036 | printk("\n"); |
| 1037 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); |
| 1038 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
| 1039 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); |
| 1040 | if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) |
| 1041 | UNEXPECTED_IO_APIC(); |
| 1042 | |
| 1043 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
| 1044 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
| 1045 | if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ |
| 1046 | (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ |
| 1047 | (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ |
| 1048 | (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ |
| 1049 | (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ |
| 1050 | (reg_01.bits.entries != 0x2E) && |
| 1051 | (reg_01.bits.entries != 0x3F) && |
| 1052 | (reg_01.bits.entries != 0x03) |
| 1053 | ) |
| 1054 | UNEXPECTED_IO_APIC(); |
| 1055 | |
| 1056 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); |
| 1057 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); |
| 1058 | if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ |
| 1059 | (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */ |
| 1060 | (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ |
| 1061 | (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ |
| 1062 | (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ |
| 1063 | (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ |
| 1064 | ) |
| 1065 | UNEXPECTED_IO_APIC(); |
| 1066 | if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) |
| 1067 | UNEXPECTED_IO_APIC(); |
| 1068 | |
| 1069 | if (reg_01.bits.version >= 0x10) { |
| 1070 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); |
| 1071 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); |
| 1072 | if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) |
| 1073 | UNEXPECTED_IO_APIC(); |
| 1074 | } |
| 1075 | |
| 1076 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); |
| 1077 | |
| 1078 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" |
| 1079 | " Stat Dest Deli Vect: \n"); |
| 1080 | |
| 1081 | for (i = 0; i <= reg_01.bits.entries; i++) { |
| 1082 | struct IO_APIC_route_entry entry; |
| 1083 | |
| 1084 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1085 | *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); |
| 1086 | *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); |
| 1087 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1088 | |
| 1089 | printk(KERN_DEBUG " %02x %03X %02X ", |
| 1090 | i, |
| 1091 | entry.dest.logical.logical_dest, |
| 1092 | entry.dest.physical.physical_dest |
| 1093 | ); |
| 1094 | |
| 1095 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", |
| 1096 | entry.mask, |
| 1097 | entry.trigger, |
| 1098 | entry.irr, |
| 1099 | entry.polarity, |
| 1100 | entry.delivery_status, |
| 1101 | entry.dest_mode, |
| 1102 | entry.delivery_mode, |
| 1103 | entry.vector |
| 1104 | ); |
| 1105 | } |
| 1106 | } |
| 1107 | if (use_pci_vector()) |
| 1108 | printk(KERN_INFO "Using vector-based indexing\n"); |
| 1109 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
| 1110 | for (i = 0; i < NR_IRQS; i++) { |
| 1111 | struct irq_pin_list *entry = irq_2_pin + i; |
| 1112 | if (entry->pin < 0) |
| 1113 | continue; |
| 1114 | if (use_pci_vector() && !platform_legacy_irq(i)) |
| 1115 | printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i)); |
| 1116 | else |
| 1117 | printk(KERN_DEBUG "IRQ%d ", i); |
| 1118 | for (;;) { |
| 1119 | printk("-> %d:%d", entry->apic, entry->pin); |
| 1120 | if (!entry->next) |
| 1121 | break; |
| 1122 | entry = irq_2_pin + entry->next; |
| 1123 | } |
| 1124 | printk("\n"); |
| 1125 | } |
| 1126 | |
| 1127 | printk(KERN_INFO ".................................... done.\n"); |
| 1128 | |
| 1129 | return; |
| 1130 | } |
| 1131 | |
| 1132 | #if 0 |
| 1133 | |
| 1134 | static __apicdebuginit void print_APIC_bitfield (int base) |
| 1135 | { |
| 1136 | unsigned int v; |
| 1137 | int i, j; |
| 1138 | |
| 1139 | if (apic_verbosity == APIC_QUIET) |
| 1140 | return; |
| 1141 | |
| 1142 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); |
| 1143 | for (i = 0; i < 8; i++) { |
| 1144 | v = apic_read(base + i*0x10); |
| 1145 | for (j = 0; j < 32; j++) { |
| 1146 | if (v & (1<<j)) |
| 1147 | printk("1"); |
| 1148 | else |
| 1149 | printk("0"); |
| 1150 | } |
| 1151 | printk("\n"); |
| 1152 | } |
| 1153 | } |
| 1154 | |
| 1155 | void __apicdebuginit print_local_APIC(void * dummy) |
| 1156 | { |
| 1157 | unsigned int v, ver, maxlvt; |
| 1158 | |
| 1159 | if (apic_verbosity == APIC_QUIET) |
| 1160 | return; |
| 1161 | |
| 1162 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
| 1163 | smp_processor_id(), hard_smp_processor_id()); |
| 1164 | v = apic_read(APIC_ID); |
| 1165 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); |
| 1166 | v = apic_read(APIC_LVR); |
| 1167 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); |
| 1168 | ver = GET_APIC_VERSION(v); |
| 1169 | maxlvt = get_maxlvt(); |
| 1170 | |
| 1171 | v = apic_read(APIC_TASKPRI); |
| 1172 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
| 1173 | |
| 1174 | v = apic_read(APIC_ARBPRI); |
| 1175 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, |
| 1176 | v & APIC_ARBPRI_MASK); |
| 1177 | v = apic_read(APIC_PROCPRI); |
| 1178 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); |
| 1179 | |
| 1180 | v = apic_read(APIC_EOI); |
| 1181 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); |
| 1182 | v = apic_read(APIC_RRR); |
| 1183 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); |
| 1184 | v = apic_read(APIC_LDR); |
| 1185 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); |
| 1186 | v = apic_read(APIC_DFR); |
| 1187 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); |
| 1188 | v = apic_read(APIC_SPIV); |
| 1189 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); |
| 1190 | |
| 1191 | printk(KERN_DEBUG "... APIC ISR field:\n"); |
| 1192 | print_APIC_bitfield(APIC_ISR); |
| 1193 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
| 1194 | print_APIC_bitfield(APIC_TMR); |
| 1195 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
| 1196 | print_APIC_bitfield(APIC_IRR); |
| 1197 | |
| 1198 | v = apic_read(APIC_ESR); |
| 1199 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); |
| 1200 | |
| 1201 | v = apic_read(APIC_ICR); |
| 1202 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); |
| 1203 | v = apic_read(APIC_ICR2); |
| 1204 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); |
| 1205 | |
| 1206 | v = apic_read(APIC_LVTT); |
| 1207 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); |
| 1208 | |
| 1209 | if (maxlvt > 3) { /* PC is LVT#4. */ |
| 1210 | v = apic_read(APIC_LVTPC); |
| 1211 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); |
| 1212 | } |
| 1213 | v = apic_read(APIC_LVT0); |
| 1214 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); |
| 1215 | v = apic_read(APIC_LVT1); |
| 1216 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); |
| 1217 | |
| 1218 | if (maxlvt > 2) { /* ERR is LVT#3. */ |
| 1219 | v = apic_read(APIC_LVTERR); |
| 1220 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); |
| 1221 | } |
| 1222 | |
| 1223 | v = apic_read(APIC_TMICT); |
| 1224 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); |
| 1225 | v = apic_read(APIC_TMCCT); |
| 1226 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); |
| 1227 | v = apic_read(APIC_TDCR); |
| 1228 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); |
| 1229 | printk("\n"); |
| 1230 | } |
| 1231 | |
| 1232 | void print_all_local_APICs (void) |
| 1233 | { |
| 1234 | on_each_cpu(print_local_APIC, NULL, 1, 1); |
| 1235 | } |
| 1236 | |
| 1237 | void __apicdebuginit print_PIC(void) |
| 1238 | { |
| 1239 | unsigned int v; |
| 1240 | unsigned long flags; |
| 1241 | |
| 1242 | if (apic_verbosity == APIC_QUIET) |
| 1243 | return; |
| 1244 | |
| 1245 | printk(KERN_DEBUG "\nprinting PIC contents\n"); |
| 1246 | |
| 1247 | spin_lock_irqsave(&i8259A_lock, flags); |
| 1248 | |
| 1249 | v = inb(0xa1) << 8 | inb(0x21); |
| 1250 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); |
| 1251 | |
| 1252 | v = inb(0xa0) << 8 | inb(0x20); |
| 1253 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); |
| 1254 | |
| 1255 | outb(0x0b,0xa0); |
| 1256 | outb(0x0b,0x20); |
| 1257 | v = inb(0xa0) << 8 | inb(0x20); |
| 1258 | outb(0x0a,0xa0); |
| 1259 | outb(0x0a,0x20); |
| 1260 | |
| 1261 | spin_unlock_irqrestore(&i8259A_lock, flags); |
| 1262 | |
| 1263 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); |
| 1264 | |
| 1265 | v = inb(0x4d1) << 8 | inb(0x4d0); |
| 1266 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); |
| 1267 | } |
| 1268 | |
| 1269 | #endif /* 0 */ |
| 1270 | |
| 1271 | static void __init enable_IO_APIC(void) |
| 1272 | { |
| 1273 | union IO_APIC_reg_01 reg_01; |
| 1274 | int i8259_apic, i8259_pin; |
| 1275 | int i, apic; |
| 1276 | unsigned long flags; |
| 1277 | |
| 1278 | for (i = 0; i < PIN_MAP_SIZE; i++) { |
| 1279 | irq_2_pin[i].pin = -1; |
| 1280 | irq_2_pin[i].next = 0; |
| 1281 | } |
| 1282 | if (!pirqs_enabled) |
| 1283 | for (i = 0; i < MAX_PIRQS; i++) |
| 1284 | pirq_entries[i] = -1; |
| 1285 | |
| 1286 | /* |
| 1287 | * The number of IO-APIC IRQ registers (== #pins): |
| 1288 | */ |
| 1289 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 1290 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1291 | reg_01.raw = io_apic_read(apic, 1); |
| 1292 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1293 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
| 1294 | } |
| 1295 | for(apic = 0; apic < nr_ioapics; apic++) { |
| 1296 | int pin; |
| 1297 | /* See if any of the pins is in ExtINT mode */ |
| 1298 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
| 1299 | struct IO_APIC_route_entry entry; |
| 1300 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1301 | *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
| 1302 | *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
| 1303 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1304 | |
| 1305 | |
| 1306 | /* If the interrupt line is enabled and in ExtInt mode |
| 1307 | * I have found the pin where the i8259 is connected. |
| 1308 | */ |
| 1309 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { |
| 1310 | ioapic_i8259.apic = apic; |
| 1311 | ioapic_i8259.pin = pin; |
| 1312 | goto found_i8259; |
| 1313 | } |
| 1314 | } |
| 1315 | } |
| 1316 | found_i8259: |
| 1317 | /* Look to see what if the MP table has reported the ExtINT */ |
| 1318 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); |
| 1319 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); |
| 1320 | /* Trust the MP table if nothing is setup in the hardware */ |
| 1321 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { |
| 1322 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); |
| 1323 | ioapic_i8259.pin = i8259_pin; |
| 1324 | ioapic_i8259.apic = i8259_apic; |
| 1325 | } |
| 1326 | /* Complain if the MP table and the hardware disagree */ |
| 1327 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && |
| 1328 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) |
| 1329 | { |
| 1330 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); |
| 1331 | } |
| 1332 | |
| 1333 | /* |
| 1334 | * Do not trust the IO-APIC being empty at bootup |
| 1335 | */ |
| 1336 | clear_IO_APIC(); |
| 1337 | } |
| 1338 | |
| 1339 | /* |
| 1340 | * Not an __init, needed by the reboot code |
| 1341 | */ |
| 1342 | void disable_IO_APIC(void) |
| 1343 | { |
| 1344 | /* |
| 1345 | * Clear the IO-APIC before rebooting: |
| 1346 | */ |
| 1347 | clear_IO_APIC(); |
| 1348 | |
| 1349 | /* |
| 1350 | * If the i8259 is routed through an IOAPIC |
| 1351 | * Put that IOAPIC in virtual wire mode |
| 1352 | * so legacy interrupts can be delivered. |
| 1353 | */ |
| 1354 | if (ioapic_i8259.pin != -1) { |
| 1355 | struct IO_APIC_route_entry entry; |
| 1356 | unsigned long flags; |
| 1357 | |
| 1358 | memset(&entry, 0, sizeof(entry)); |
| 1359 | entry.mask = 0; /* Enabled */ |
| 1360 | entry.trigger = 0; /* Edge */ |
| 1361 | entry.irr = 0; |
| 1362 | entry.polarity = 0; /* High */ |
| 1363 | entry.delivery_status = 0; |
| 1364 | entry.dest_mode = 0; /* Physical */ |
| 1365 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
| 1366 | entry.vector = 0; |
| 1367 | entry.dest.physical.physical_dest = |
| 1368 | GET_APIC_ID(apic_read(APIC_ID)); |
| 1369 | |
| 1370 | /* |
| 1371 | * Add it to the IO-APIC irq-routing table: |
| 1372 | */ |
| 1373 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1374 | io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin, |
| 1375 | *(((int *)&entry)+1)); |
| 1376 | io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin, |
| 1377 | *(((int *)&entry)+0)); |
| 1378 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1379 | } |
| 1380 | |
| 1381 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
| 1382 | } |
| 1383 | |
| 1384 | /* |
| 1385 | * function to set the IO-APIC physical IDs based on the |
| 1386 | * values stored in the MPC table. |
| 1387 | * |
| 1388 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 |
| 1389 | */ |
| 1390 | |
| 1391 | static void __init setup_ioapic_ids_from_mpc (void) |
| 1392 | { |
| 1393 | union IO_APIC_reg_00 reg_00; |
| 1394 | int apic; |
| 1395 | int i; |
| 1396 | unsigned char old_id; |
| 1397 | unsigned long flags; |
| 1398 | |
| 1399 | /* |
| 1400 | * Set the IOAPIC ID to the value stored in the MPC table. |
| 1401 | */ |
| 1402 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 1403 | |
| 1404 | /* Read the register 0 value */ |
| 1405 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1406 | reg_00.raw = io_apic_read(apic, 0); |
| 1407 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1408 | |
| 1409 | old_id = mp_ioapics[apic].mpc_apicid; |
| 1410 | |
| 1411 | |
| 1412 | printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid); |
| 1413 | |
| 1414 | |
| 1415 | /* |
| 1416 | * We need to adjust the IRQ routing table |
| 1417 | * if the ID changed. |
| 1418 | */ |
| 1419 | if (old_id != mp_ioapics[apic].mpc_apicid) |
| 1420 | for (i = 0; i < mp_irq_entries; i++) |
| 1421 | if (mp_irqs[i].mpc_dstapic == old_id) |
| 1422 | mp_irqs[i].mpc_dstapic |
| 1423 | = mp_ioapics[apic].mpc_apicid; |
| 1424 | |
| 1425 | /* |
| 1426 | * Read the right value from the MPC table and |
| 1427 | * write it into the ID register. |
| 1428 | */ |
| 1429 | apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...", |
| 1430 | mp_ioapics[apic].mpc_apicid); |
| 1431 | |
| 1432 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; |
| 1433 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1434 | io_apic_write(apic, 0, reg_00.raw); |
| 1435 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1436 | |
| 1437 | /* |
| 1438 | * Sanity check |
| 1439 | */ |
| 1440 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1441 | reg_00.raw = io_apic_read(apic, 0); |
| 1442 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1443 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) |
| 1444 | printk("could not set ID!\n"); |
| 1445 | else |
| 1446 | apic_printk(APIC_VERBOSE," ok.\n"); |
| 1447 | } |
| 1448 | } |
| 1449 | |
| 1450 | /* |
| 1451 | * There is a nasty bug in some older SMP boards, their mptable lies |
| 1452 | * about the timer IRQ. We do the following to work around the situation: |
| 1453 | * |
| 1454 | * - timer IRQ defaults to IO-APIC IRQ |
| 1455 | * - if this function detects that timer IRQs are defunct, then we fall |
| 1456 | * back to ISA timer IRQs |
| 1457 | */ |
| 1458 | static int __init timer_irq_works(void) |
| 1459 | { |
| 1460 | unsigned long t1 = jiffies; |
| 1461 | |
| 1462 | local_irq_enable(); |
| 1463 | /* Let ten ticks pass... */ |
| 1464 | mdelay((10 * 1000) / HZ); |
| 1465 | |
| 1466 | /* |
| 1467 | * Expect a few ticks at least, to be sure some possible |
| 1468 | * glue logic does not lock up after one or two first |
| 1469 | * ticks in a non-ExtINT mode. Also the local APIC |
| 1470 | * might have cached one ExtINT interrupt. Finally, at |
| 1471 | * least one tick may be lost due to delays. |
| 1472 | */ |
| 1473 | |
| 1474 | /* jiffies wrap? */ |
| 1475 | if (jiffies - t1 > 4) |
| 1476 | return 1; |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
| 1480 | /* |
| 1481 | * In the SMP+IOAPIC case it might happen that there are an unspecified |
| 1482 | * number of pending IRQ events unhandled. These cases are very rare, |
| 1483 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much |
| 1484 | * better to do it this way as thus we do not have to be aware of |
| 1485 | * 'pending' interrupts in the IRQ path, except at this point. |
| 1486 | */ |
| 1487 | /* |
| 1488 | * Edge triggered needs to resend any interrupt |
| 1489 | * that was delayed but this is now handled in the device |
| 1490 | * independent code. |
| 1491 | */ |
| 1492 | |
| 1493 | /* |
| 1494 | * Starting up a edge-triggered IO-APIC interrupt is |
| 1495 | * nasty - we need to make sure that we get the edge. |
| 1496 | * If it is already asserted for some reason, we need |
| 1497 | * return 1 to indicate that is was pending. |
| 1498 | * |
| 1499 | * This is not complete - we should be able to fake |
| 1500 | * an edge even if it isn't on the 8259A... |
| 1501 | */ |
| 1502 | |
| 1503 | static unsigned int startup_edge_ioapic_irq(unsigned int irq) |
| 1504 | { |
| 1505 | int was_pending = 0; |
| 1506 | unsigned long flags; |
| 1507 | |
| 1508 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1509 | if (irq < 16) { |
| 1510 | disable_8259A_irq(irq); |
| 1511 | if (i8259A_irq_pending(irq)) |
| 1512 | was_pending = 1; |
| 1513 | } |
| 1514 | __unmask_IO_APIC_irq(irq); |
| 1515 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1516 | |
| 1517 | return was_pending; |
| 1518 | } |
| 1519 | |
| 1520 | /* |
| 1521 | * Once we have recorded IRQ_PENDING already, we can mask the |
| 1522 | * interrupt for real. This prevents IRQ storms from unhandled |
| 1523 | * devices. |
| 1524 | */ |
| 1525 | static void ack_edge_ioapic_irq(unsigned int irq) |
| 1526 | { |
| 1527 | move_irq(irq); |
| 1528 | if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) |
| 1529 | == (IRQ_PENDING | IRQ_DISABLED)) |
| 1530 | mask_IO_APIC_irq(irq); |
| 1531 | ack_APIC_irq(); |
| 1532 | } |
| 1533 | |
| 1534 | /* |
| 1535 | * Level triggered interrupts can just be masked, |
| 1536 | * and shutting down and starting up the interrupt |
| 1537 | * is the same as enabling and disabling them -- except |
| 1538 | * with a startup need to return a "was pending" value. |
| 1539 | * |
| 1540 | * Level triggered interrupts are special because we |
| 1541 | * do not touch any IO-APIC register while handling |
| 1542 | * them. We ack the APIC in the end-IRQ handler, not |
| 1543 | * in the start-IRQ-handler. Protection against reentrance |
| 1544 | * from the same interrupt is still provided, both by the |
| 1545 | * generic IRQ layer and by the fact that an unacked local |
| 1546 | * APIC does not accept IRQs. |
| 1547 | */ |
| 1548 | static unsigned int startup_level_ioapic_irq (unsigned int irq) |
| 1549 | { |
| 1550 | unmask_IO_APIC_irq(irq); |
| 1551 | |
| 1552 | return 0; /* don't check for pending */ |
| 1553 | } |
| 1554 | |
| 1555 | static void end_level_ioapic_irq (unsigned int irq) |
| 1556 | { |
| 1557 | move_irq(irq); |
| 1558 | ack_APIC_irq(); |
| 1559 | } |
| 1560 | |
| 1561 | #ifdef CONFIG_PCI_MSI |
| 1562 | static unsigned int startup_edge_ioapic_vector(unsigned int vector) |
| 1563 | { |
| 1564 | int irq = vector_to_irq(vector); |
| 1565 | |
| 1566 | return startup_edge_ioapic_irq(irq); |
| 1567 | } |
| 1568 | |
| 1569 | static void ack_edge_ioapic_vector(unsigned int vector) |
| 1570 | { |
| 1571 | int irq = vector_to_irq(vector); |
| 1572 | |
| 1573 | move_native_irq(vector); |
| 1574 | ack_edge_ioapic_irq(irq); |
| 1575 | } |
| 1576 | |
| 1577 | static unsigned int startup_level_ioapic_vector (unsigned int vector) |
| 1578 | { |
| 1579 | int irq = vector_to_irq(vector); |
| 1580 | |
| 1581 | return startup_level_ioapic_irq (irq); |
| 1582 | } |
| 1583 | |
| 1584 | static void end_level_ioapic_vector (unsigned int vector) |
| 1585 | { |
| 1586 | int irq = vector_to_irq(vector); |
| 1587 | |
| 1588 | move_native_irq(vector); |
| 1589 | end_level_ioapic_irq(irq); |
| 1590 | } |
| 1591 | |
| 1592 | static void mask_IO_APIC_vector (unsigned int vector) |
| 1593 | { |
| 1594 | int irq = vector_to_irq(vector); |
| 1595 | |
| 1596 | mask_IO_APIC_irq(irq); |
| 1597 | } |
| 1598 | |
| 1599 | static void unmask_IO_APIC_vector (unsigned int vector) |
| 1600 | { |
| 1601 | int irq = vector_to_irq(vector); |
| 1602 | |
| 1603 | unmask_IO_APIC_irq(irq); |
| 1604 | } |
| 1605 | |
| 1606 | #ifdef CONFIG_SMP |
| 1607 | static void set_ioapic_affinity_vector (unsigned int vector, |
| 1608 | cpumask_t cpu_mask) |
| 1609 | { |
| 1610 | int irq = vector_to_irq(vector); |
| 1611 | |
| 1612 | set_native_irq_info(vector, cpu_mask); |
| 1613 | set_ioapic_affinity_irq(irq, cpu_mask); |
| 1614 | } |
| 1615 | #endif // CONFIG_SMP |
| 1616 | #endif // CONFIG_PCI_MSI |
| 1617 | |
| 1618 | /* |
| 1619 | * Level and edge triggered IO-APIC interrupts need different handling, |
| 1620 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be |
| 1621 | * handled with the level-triggered descriptor, but that one has slightly |
| 1622 | * more overhead. Level-triggered interrupts cannot be handled with the |
| 1623 | * edge-triggered handler, without risking IRQ storms and other ugly |
| 1624 | * races. |
| 1625 | */ |
| 1626 | |
| 1627 | static struct hw_interrupt_type ioapic_edge_type __read_mostly = { |
| 1628 | .typename = "IO-APIC-edge", |
| 1629 | .startup = startup_edge_ioapic, |
| 1630 | .shutdown = shutdown_edge_ioapic, |
| 1631 | .enable = enable_edge_ioapic, |
| 1632 | .disable = disable_edge_ioapic, |
| 1633 | .ack = ack_edge_ioapic, |
| 1634 | .end = end_edge_ioapic, |
| 1635 | #ifdef CONFIG_SMP |
| 1636 | .set_affinity = set_ioapic_affinity, |
| 1637 | #endif |
| 1638 | }; |
| 1639 | |
| 1640 | static struct hw_interrupt_type ioapic_level_type __read_mostly = { |
| 1641 | .typename = "IO-APIC-level", |
| 1642 | .startup = startup_level_ioapic, |
| 1643 | .shutdown = shutdown_level_ioapic, |
| 1644 | .enable = enable_level_ioapic, |
| 1645 | .disable = disable_level_ioapic, |
| 1646 | .ack = mask_and_ack_level_ioapic, |
| 1647 | .end = end_level_ioapic, |
| 1648 | #ifdef CONFIG_SMP |
| 1649 | .set_affinity = set_ioapic_affinity, |
| 1650 | #endif |
| 1651 | }; |
| 1652 | |
| 1653 | static inline void init_IO_APIC_traps(void) |
| 1654 | { |
| 1655 | int irq; |
| 1656 | |
| 1657 | /* |
| 1658 | * NOTE! The local APIC isn't very good at handling |
| 1659 | * multiple interrupts at the same interrupt level. |
| 1660 | * As the interrupt level is determined by taking the |
| 1661 | * vector number and shifting that right by 4, we |
| 1662 | * want to spread these out a bit so that they don't |
| 1663 | * all fall in the same interrupt level. |
| 1664 | * |
| 1665 | * Also, we've got to be careful not to trash gate |
| 1666 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
| 1667 | */ |
| 1668 | for (irq = 0; irq < NR_IRQS ; irq++) { |
| 1669 | int tmp = irq; |
| 1670 | if (use_pci_vector()) { |
| 1671 | if (!platform_legacy_irq(tmp)) |
| 1672 | if ((tmp = vector_to_irq(tmp)) == -1) |
| 1673 | continue; |
| 1674 | } |
| 1675 | if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) { |
| 1676 | /* |
| 1677 | * Hmm.. We don't have an entry for this, |
| 1678 | * so default to an old-fashioned 8259 |
| 1679 | * interrupt if we can.. |
| 1680 | */ |
| 1681 | if (irq < 16) |
| 1682 | make_8259A_irq(irq); |
| 1683 | else |
| 1684 | /* Strange. Oh, well.. */ |
| 1685 | irq_desc[irq].handler = &no_irq_type; |
| 1686 | } |
| 1687 | } |
| 1688 | } |
| 1689 | |
| 1690 | static void enable_lapic_irq (unsigned int irq) |
| 1691 | { |
| 1692 | unsigned long v; |
| 1693 | |
| 1694 | v = apic_read(APIC_LVT0); |
| 1695 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
| 1696 | } |
| 1697 | |
| 1698 | static void disable_lapic_irq (unsigned int irq) |
| 1699 | { |
| 1700 | unsigned long v; |
| 1701 | |
| 1702 | v = apic_read(APIC_LVT0); |
| 1703 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
| 1704 | } |
| 1705 | |
| 1706 | static void ack_lapic_irq (unsigned int irq) |
| 1707 | { |
| 1708 | ack_APIC_irq(); |
| 1709 | } |
| 1710 | |
| 1711 | static void end_lapic_irq (unsigned int i) { /* nothing */ } |
| 1712 | |
| 1713 | static struct hw_interrupt_type lapic_irq_type __read_mostly = { |
| 1714 | .typename = "local-APIC-edge", |
| 1715 | .startup = NULL, /* startup_irq() not used for IRQ0 */ |
| 1716 | .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */ |
| 1717 | .enable = enable_lapic_irq, |
| 1718 | .disable = disable_lapic_irq, |
| 1719 | .ack = ack_lapic_irq, |
| 1720 | .end = end_lapic_irq, |
| 1721 | }; |
| 1722 | |
| 1723 | static void setup_nmi (void) |
| 1724 | { |
| 1725 | /* |
| 1726 | * Dirty trick to enable the NMI watchdog ... |
| 1727 | * We put the 8259A master into AEOI mode and |
| 1728 | * unmask on all local APICs LVT0 as NMI. |
| 1729 | * |
| 1730 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') |
| 1731 | * is from Maciej W. Rozycki - so we do not have to EOI from |
| 1732 | * the NMI handler or the timer interrupt. |
| 1733 | */ |
| 1734 | printk(KERN_INFO "activating NMI Watchdog ..."); |
| 1735 | |
| 1736 | enable_NMI_through_LVT0(NULL); |
| 1737 | |
| 1738 | printk(" done.\n"); |
| 1739 | } |
| 1740 | |
| 1741 | /* |
| 1742 | * This looks a bit hackish but it's about the only one way of sending |
| 1743 | * a few INTA cycles to 8259As and any associated glue logic. ICR does |
| 1744 | * not support the ExtINT mode, unfortunately. We need to send these |
| 1745 | * cycles as some i82489DX-based boards have glue logic that keeps the |
| 1746 | * 8259A interrupt line asserted until INTA. --macro |
| 1747 | */ |
| 1748 | static inline void unlock_ExtINT_logic(void) |
| 1749 | { |
| 1750 | int apic, pin, i; |
| 1751 | struct IO_APIC_route_entry entry0, entry1; |
| 1752 | unsigned char save_control, save_freq_select; |
| 1753 | unsigned long flags; |
| 1754 | |
| 1755 | pin = find_isa_irq_pin(8, mp_INT); |
| 1756 | apic = find_isa_irq_apic(8, mp_INT); |
| 1757 | if (pin == -1) |
| 1758 | return; |
| 1759 | |
| 1760 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1761 | *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
| 1762 | *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin); |
| 1763 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1764 | clear_IO_APIC_pin(apic, pin); |
| 1765 | |
| 1766 | memset(&entry1, 0, sizeof(entry1)); |
| 1767 | |
| 1768 | entry1.dest_mode = 0; /* physical delivery */ |
| 1769 | entry1.mask = 0; /* unmask IRQ now */ |
| 1770 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); |
| 1771 | entry1.delivery_mode = dest_ExtINT; |
| 1772 | entry1.polarity = entry0.polarity; |
| 1773 | entry1.trigger = 0; |
| 1774 | entry1.vector = 0; |
| 1775 | |
| 1776 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1777 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); |
| 1778 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); |
| 1779 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1780 | |
| 1781 | save_control = CMOS_READ(RTC_CONTROL); |
| 1782 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); |
| 1783 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, |
| 1784 | RTC_FREQ_SELECT); |
| 1785 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); |
| 1786 | |
| 1787 | i = 100; |
| 1788 | while (i-- > 0) { |
| 1789 | mdelay(10); |
| 1790 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) |
| 1791 | i -= 10; |
| 1792 | } |
| 1793 | |
| 1794 | CMOS_WRITE(save_control, RTC_CONTROL); |
| 1795 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); |
| 1796 | clear_IO_APIC_pin(apic, pin); |
| 1797 | |
| 1798 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1799 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); |
| 1800 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); |
| 1801 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1802 | } |
| 1803 | |
| 1804 | int timer_uses_ioapic_pin_0; |
| 1805 | |
| 1806 | /* |
| 1807 | * This code may look a bit paranoid, but it's supposed to cooperate with |
| 1808 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ |
| 1809 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast |
| 1810 | * fanatically on his truly buggy board. |
| 1811 | * |
| 1812 | * FIXME: really need to revamp this for modern platforms only. |
| 1813 | */ |
| 1814 | static inline void check_timer(void) |
| 1815 | { |
| 1816 | int apic1, pin1, apic2, pin2; |
| 1817 | int vector; |
| 1818 | |
| 1819 | /* |
| 1820 | * get/set the timer IRQ vector: |
| 1821 | */ |
| 1822 | disable_8259A_irq(0); |
| 1823 | vector = assign_irq_vector(0); |
| 1824 | set_intr_gate(vector, interrupt[0]); |
| 1825 | |
| 1826 | /* |
| 1827 | * Subtle, code in do_timer_interrupt() expects an AEOI |
| 1828 | * mode for the 8259A whenever interrupts are routed |
| 1829 | * through I/O APICs. Also IRQ0 has to be enabled in |
| 1830 | * the 8259A which implies the virtual wire has to be |
| 1831 | * disabled in the local APIC. |
| 1832 | */ |
| 1833 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
| 1834 | init_8259A(1); |
| 1835 | if (timer_over_8254 > 0) |
| 1836 | enable_8259A_irq(0); |
| 1837 | |
| 1838 | pin1 = find_isa_irq_pin(0, mp_INT); |
| 1839 | apic1 = find_isa_irq_apic(0, mp_INT); |
| 1840 | pin2 = ioapic_i8259.pin; |
| 1841 | apic2 = ioapic_i8259.apic; |
| 1842 | |
| 1843 | if (pin1 == 0) |
| 1844 | timer_uses_ioapic_pin_0 = 1; |
| 1845 | |
| 1846 | apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
| 1847 | vector, apic1, pin1, apic2, pin2); |
| 1848 | |
| 1849 | if (pin1 != -1) { |
| 1850 | /* |
| 1851 | * Ok, does IRQ0 through the IOAPIC work? |
| 1852 | */ |
| 1853 | unmask_IO_APIC_irq(0); |
| 1854 | if (!no_timer_check && timer_irq_works()) { |
| 1855 | nmi_watchdog_default(); |
| 1856 | if (nmi_watchdog == NMI_IO_APIC) { |
| 1857 | disable_8259A_irq(0); |
| 1858 | setup_nmi(); |
| 1859 | enable_8259A_irq(0); |
| 1860 | } |
| 1861 | if (disable_timer_pin_1 > 0) |
| 1862 | clear_IO_APIC_pin(0, pin1); |
| 1863 | return; |
| 1864 | } |
| 1865 | clear_IO_APIC_pin(apic1, pin1); |
| 1866 | apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not " |
| 1867 | "connected to IO-APIC\n"); |
| 1868 | } |
| 1869 | |
| 1870 | apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) " |
| 1871 | "through the 8259A ... "); |
| 1872 | if (pin2 != -1) { |
| 1873 | apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...", |
| 1874 | apic2, pin2); |
| 1875 | /* |
| 1876 | * legacy devices should be connected to IO APIC #0 |
| 1877 | */ |
| 1878 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
| 1879 | if (timer_irq_works()) { |
| 1880 | apic_printk(APIC_VERBOSE," works.\n"); |
| 1881 | nmi_watchdog_default(); |
| 1882 | if (nmi_watchdog == NMI_IO_APIC) { |
| 1883 | setup_nmi(); |
| 1884 | } |
| 1885 | return; |
| 1886 | } |
| 1887 | /* |
| 1888 | * Cleanup, just in case ... |
| 1889 | */ |
| 1890 | clear_IO_APIC_pin(apic2, pin2); |
| 1891 | } |
| 1892 | apic_printk(APIC_VERBOSE," failed.\n"); |
| 1893 | |
| 1894 | if (nmi_watchdog == NMI_IO_APIC) { |
| 1895 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); |
| 1896 | nmi_watchdog = 0; |
| 1897 | } |
| 1898 | |
| 1899 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); |
| 1900 | |
| 1901 | disable_8259A_irq(0); |
| 1902 | irq_desc[0].handler = &lapic_irq_type; |
| 1903 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
| 1904 | enable_8259A_irq(0); |
| 1905 | |
| 1906 | if (timer_irq_works()) { |
| 1907 | apic_printk(APIC_VERBOSE," works.\n"); |
| 1908 | return; |
| 1909 | } |
| 1910 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
| 1911 | apic_printk(APIC_VERBOSE," failed.\n"); |
| 1912 | |
| 1913 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ..."); |
| 1914 | |
| 1915 | init_8259A(0); |
| 1916 | make_8259A_irq(0); |
| 1917 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
| 1918 | |
| 1919 | unlock_ExtINT_logic(); |
| 1920 | |
| 1921 | if (timer_irq_works()) { |
| 1922 | apic_printk(APIC_VERBOSE," works.\n"); |
| 1923 | return; |
| 1924 | } |
| 1925 | apic_printk(APIC_VERBOSE," failed :(.\n"); |
| 1926 | panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n"); |
| 1927 | } |
| 1928 | |
| 1929 | static int __init notimercheck(char *s) |
| 1930 | { |
| 1931 | no_timer_check = 1; |
| 1932 | return 1; |
| 1933 | } |
| 1934 | __setup("no_timer_check", notimercheck); |
| 1935 | |
| 1936 | /* |
| 1937 | * |
| 1938 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. |
| 1939 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. |
| 1940 | * Linux doesn't really care, as it's not actually used |
| 1941 | * for any interrupt handling anyway. |
| 1942 | */ |
| 1943 | #define PIC_IRQS (1<<2) |
| 1944 | |
| 1945 | void __init setup_IO_APIC(void) |
| 1946 | { |
| 1947 | enable_IO_APIC(); |
| 1948 | |
| 1949 | if (acpi_ioapic) |
| 1950 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ |
| 1951 | else |
| 1952 | io_apic_irqs = ~PIC_IRQS; |
| 1953 | |
| 1954 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
| 1955 | |
| 1956 | /* |
| 1957 | * Set up the IO-APIC IRQ routing table. |
| 1958 | */ |
| 1959 | if (!acpi_ioapic) |
| 1960 | setup_ioapic_ids_from_mpc(); |
| 1961 | sync_Arb_IDs(); |
| 1962 | setup_IO_APIC_irqs(); |
| 1963 | init_IO_APIC_traps(); |
| 1964 | check_timer(); |
| 1965 | if (!acpi_ioapic) |
| 1966 | print_IO_APIC(); |
| 1967 | } |
| 1968 | |
| 1969 | struct sysfs_ioapic_data { |
| 1970 | struct sys_device dev; |
| 1971 | struct IO_APIC_route_entry entry[0]; |
| 1972 | }; |
| 1973 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
| 1974 | |
| 1975 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
| 1976 | { |
| 1977 | struct IO_APIC_route_entry *entry; |
| 1978 | struct sysfs_ioapic_data *data; |
| 1979 | unsigned long flags; |
| 1980 | int i; |
| 1981 | |
| 1982 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
| 1983 | entry = data->entry; |
| 1984 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1985 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { |
| 1986 | *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i); |
| 1987 | *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i); |
| 1988 | } |
| 1989 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1990 | |
| 1991 | return 0; |
| 1992 | } |
| 1993 | |
| 1994 | static int ioapic_resume(struct sys_device *dev) |
| 1995 | { |
| 1996 | struct IO_APIC_route_entry *entry; |
| 1997 | struct sysfs_ioapic_data *data; |
| 1998 | unsigned long flags; |
| 1999 | union IO_APIC_reg_00 reg_00; |
| 2000 | int i; |
| 2001 | |
| 2002 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
| 2003 | entry = data->entry; |
| 2004 | |
| 2005 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2006 | reg_00.raw = io_apic_read(dev->id, 0); |
| 2007 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { |
| 2008 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; |
| 2009 | io_apic_write(dev->id, 0, reg_00.raw); |
| 2010 | } |
| 2011 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) { |
| 2012 | io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1)); |
| 2013 | io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0)); |
| 2014 | } |
| 2015 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2016 | |
| 2017 | return 0; |
| 2018 | } |
| 2019 | |
| 2020 | static struct sysdev_class ioapic_sysdev_class = { |
| 2021 | set_kset_name("ioapic"), |
| 2022 | .suspend = ioapic_suspend, |
| 2023 | .resume = ioapic_resume, |
| 2024 | }; |
| 2025 | |
| 2026 | static int __init ioapic_init_sysfs(void) |
| 2027 | { |
| 2028 | struct sys_device * dev; |
| 2029 | int i, size, error = 0; |
| 2030 | |
| 2031 | error = sysdev_class_register(&ioapic_sysdev_class); |
| 2032 | if (error) |
| 2033 | return error; |
| 2034 | |
| 2035 | for (i = 0; i < nr_ioapics; i++ ) { |
| 2036 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
| 2037 | * sizeof(struct IO_APIC_route_entry); |
| 2038 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); |
| 2039 | if (!mp_ioapic_data[i]) { |
| 2040 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
| 2041 | continue; |
| 2042 | } |
| 2043 | memset(mp_ioapic_data[i], 0, size); |
| 2044 | dev = &mp_ioapic_data[i]->dev; |
| 2045 | dev->id = i; |
| 2046 | dev->cls = &ioapic_sysdev_class; |
| 2047 | error = sysdev_register(dev); |
| 2048 | if (error) { |
| 2049 | kfree(mp_ioapic_data[i]); |
| 2050 | mp_ioapic_data[i] = NULL; |
| 2051 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
| 2052 | continue; |
| 2053 | } |
| 2054 | } |
| 2055 | |
| 2056 | return 0; |
| 2057 | } |
| 2058 | |
| 2059 | device_initcall(ioapic_init_sysfs); |
| 2060 | |
| 2061 | /* -------------------------------------------------------------------------- |
| 2062 | ACPI-based IOAPIC Configuration |
| 2063 | -------------------------------------------------------------------------- */ |
| 2064 | |
| 2065 | #ifdef CONFIG_ACPI |
| 2066 | |
| 2067 | #define IO_APIC_MAX_ID 0xFE |
| 2068 | |
| 2069 | int __init io_apic_get_version (int ioapic) |
| 2070 | { |
| 2071 | union IO_APIC_reg_01 reg_01; |
| 2072 | unsigned long flags; |
| 2073 | |
| 2074 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2075 | reg_01.raw = io_apic_read(ioapic, 1); |
| 2076 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2077 | |
| 2078 | return reg_01.bits.version; |
| 2079 | } |
| 2080 | |
| 2081 | |
| 2082 | int __init io_apic_get_redir_entries (int ioapic) |
| 2083 | { |
| 2084 | union IO_APIC_reg_01 reg_01; |
| 2085 | unsigned long flags; |
| 2086 | |
| 2087 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2088 | reg_01.raw = io_apic_read(ioapic, 1); |
| 2089 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2090 | |
| 2091 | return reg_01.bits.entries; |
| 2092 | } |
| 2093 | |
| 2094 | |
| 2095 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
| 2096 | { |
| 2097 | struct IO_APIC_route_entry entry; |
| 2098 | unsigned long flags; |
| 2099 | |
| 2100 | if (!IO_APIC_IRQ(irq)) { |
| 2101 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
| 2102 | ioapic); |
| 2103 | return -EINVAL; |
| 2104 | } |
| 2105 | |
| 2106 | /* |
| 2107 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. |
| 2108 | * Note that we mask (disable) IRQs now -- these get enabled when the |
| 2109 | * corresponding device driver registers for this IRQ. |
| 2110 | */ |
| 2111 | |
| 2112 | memset(&entry,0,sizeof(entry)); |
| 2113 | |
| 2114 | entry.delivery_mode = INT_DELIVERY_MODE; |
| 2115 | entry.dest_mode = INT_DEST_MODE; |
| 2116 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
| 2117 | entry.trigger = triggering; |
| 2118 | entry.polarity = polarity; |
| 2119 | entry.mask = 1; /* Disabled (masked) */ |
| 2120 | |
| 2121 | irq = gsi_irq_sharing(irq); |
| 2122 | /* |
| 2123 | * IRQs < 16 are already in the irq_2_pin[] map |
| 2124 | */ |
| 2125 | if (irq >= 16) |
| 2126 | add_pin_to_irq(irq, ioapic, pin); |
| 2127 | |
| 2128 | entry.vector = assign_irq_vector(irq); |
| 2129 | |
| 2130 | apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> " |
| 2131 | "IRQ %d Mode:%i Active:%i)\n", ioapic, |
| 2132 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, |
| 2133 | triggering, polarity); |
| 2134 | |
| 2135 | ioapic_register_intr(irq, entry.vector, triggering); |
| 2136 | |
| 2137 | if (!ioapic && (irq < 16)) |
| 2138 | disable_8259A_irq(irq); |
| 2139 | |
| 2140 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2141 | io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1)); |
| 2142 | io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0)); |
| 2143 | set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS); |
| 2144 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2145 | |
| 2146 | return 0; |
| 2147 | } |
| 2148 | |
| 2149 | #endif /* CONFIG_ACPI */ |
| 2150 | |
| 2151 | |
| 2152 | /* |
| 2153 | * This function currently is only a helper for the i386 smp boot process where |
| 2154 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
| 2155 | * so mask in all cases should simply be TARGET_CPUS |
| 2156 | */ |
| 2157 | #ifdef CONFIG_SMP |
| 2158 | void __init setup_ioapic_dest(void) |
| 2159 | { |
| 2160 | int pin, ioapic, irq, irq_entry; |
| 2161 | |
| 2162 | if (skip_ioapic_setup == 1) |
| 2163 | return; |
| 2164 | |
| 2165 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { |
| 2166 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
| 2167 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
| 2168 | if (irq_entry == -1) |
| 2169 | continue; |
| 2170 | irq = pin_2_irq(irq_entry, ioapic, pin); |
| 2171 | set_ioapic_affinity_irq(irq, TARGET_CPUS); |
| 2172 | } |
| 2173 | |
| 2174 | } |
| 2175 | } |
| 2176 | #endif |