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KVM: x86: always stop emulation on page fault
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19#include <linux/kvm_host.h>
20#include "irq.h"
21#include "mmu.h"
22#include "i8254.h"
23#include "tss.h"
24#include "kvm_cache_regs.h"
25#include "x86.h"
26#include "cpuid.h"
27#include "pmu.h"
28#include "hyperv.h"
29
30#include <linux/clocksource.h>
31#include <linux/interrupt.h>
32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
35#include <linux/export.h>
36#include <linux/moduleparam.h>
37#include <linux/mman.h>
38#include <linux/highmem.h>
39#include <linux/iommu.h>
40#include <linux/intel-iommu.h>
41#include <linux/cpufreq.h>
42#include <linux/user-return-notifier.h>
43#include <linux/srcu.h>
44#include <linux/slab.h>
45#include <linux/perf_event.h>
46#include <linux/uaccess.h>
47#include <linux/hash.h>
48#include <linux/pci.h>
49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
53#include <linux/sched/stat.h>
54#include <linux/sched/isolation.h>
55#include <linux/mem_encrypt.h>
56
57#include <trace/events/kvm.h>
58
59#include <asm/debugreg.h>
60#include <asm/msr.h>
61#include <asm/desc.h>
62#include <asm/mce.h>
63#include <linux/kernel_stat.h>
64#include <asm/fpu/internal.h> /* Ugh! */
65#include <asm/pvclock.h>
66#include <asm/div64.h>
67#include <asm/irq_remapping.h>
68#include <asm/mshyperv.h>
69#include <asm/hypervisor.h>
70#include <asm/intel_pt.h>
71#include <clocksource/hyperv_timer.h>
72
73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
76#define MAX_IO_MSRS 256
77#define KVM_MAX_MCE_BANKS 32
78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
80
81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
91#else
92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
93#endif
94
95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
97
98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
100
101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102static void process_nmi(struct kvm_vcpu *vcpu);
103static void enter_smm(struct kvm_vcpu *vcpu);
104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
107
108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109EXPORT_SYMBOL_GPL(kvm_x86_ops);
110
111static bool __read_mostly ignore_msrs = 0;
112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
113
114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
117unsigned int min_timer_period_us = 200;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
123bool __read_mostly kvm_has_tsc_control;
124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125u32 __read_mostly kvm_max_guest_tsc_khz;
126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
133
134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135static u32 __read_mostly tsc_tolerance_ppm = 250;
136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
146
147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
164 u32 msrs[KVM_NR_SHARED_MSRS];
165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
177static struct kvm_shared_msrs __percpu *shared_msrs;
178
179struct kvm_stats_debugfs_item debugfs_entries[] = {
180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
190 { "halt_exits", VCPU_STAT(halt_exits) },
191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
195 { "hypercalls", VCPU_STAT(hypercalls) },
196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
202 { "irq_injections", VCPU_STAT(irq_injections) },
203 { "nmi_injections", VCPU_STAT(nmi_injections) },
204 { "req_event", VCPU_STAT(req_event) },
205 { "l1d_flush", VCPU_STAT(l1d_flush) },
206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
213 { "mmu_unsync", VM_STAT(mmu_unsync) },
214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
215 { "largepages", VM_STAT(lpages) },
216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
218 { NULL }
219};
220
221u64 __read_mostly host_xcr0;
222
223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
227
228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
240 struct kvm_shared_msr_values *values;
241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
258 }
259 }
260}
261
262static void shared_msr_update(unsigned slot, u32 msr)
263{
264 u64 value;
265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
267
268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
282 shared_msrs_global.msrs[slot] = msr;
283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
293 shared_msr_update(i, shared_msrs_global.msrs[i]);
294}
295
296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
297{
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
300 int err;
301
302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
303 return 0;
304 smsr->values[slot].curr = value;
305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
314 return 0;
315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
318static void drop_user_return_notifiers(void)
319{
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
329 return vcpu->arch.apic_base;
330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
345
346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
347 return 1;
348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
360asmlinkage __visible void kvm_spurious_fault(void)
361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
456 unsigned nr, bool has_error, u32 error_code,
457 bool has_payload, unsigned long payload, bool reinject)
458{
459 u32 prev_nr;
460 int class1, class2;
461
462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
465 queue:
466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
529 vcpu->arch.exception.pending = true;
530 vcpu->arch.exception.injected = false;
531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
569{
570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
578
579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
580{
581 ++vcpu->stat.pf_guest;
582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
584 if (vcpu->arch.exception.nested_apf) {
585 vcpu->arch.apf.nested_apf_token = fault->address;
586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
591}
592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
593
594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
595{
596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
598 else
599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
600
601 return fault->nested_page_fault;
602}
603
604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
628{
629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
633}
634EXPORT_SYMBOL_GPL(kvm_require_cpl);
635
636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
646/*
647 * This function will be used to read from the physical memory of the currently
648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
655 struct x86_exception exception;
656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
677static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
678{
679 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
680 rsvd_bits(1, 2);
681}
682
683/*
684 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
685 */
686int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
687{
688 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
689 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
690 int i;
691 int ret;
692 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
693
694 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
695 offset * sizeof(u64), sizeof(pdpte),
696 PFERR_USER_MASK|PFERR_WRITE_MASK);
697 if (ret < 0) {
698 ret = 0;
699 goto out;
700 }
701 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
702 if ((pdpte[i] & PT_PRESENT_MASK) &&
703 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
704 ret = 0;
705 goto out;
706 }
707 }
708 ret = 1;
709
710 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
711 __set_bit(VCPU_EXREG_PDPTR,
712 (unsigned long *)&vcpu->arch.regs_avail);
713 __set_bit(VCPU_EXREG_PDPTR,
714 (unsigned long *)&vcpu->arch.regs_dirty);
715out:
716
717 return ret;
718}
719EXPORT_SYMBOL_GPL(load_pdptrs);
720
721bool pdptrs_changed(struct kvm_vcpu *vcpu)
722{
723 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
724 bool changed = true;
725 int offset;
726 gfn_t gfn;
727 int r;
728
729 if (!is_pae_paging(vcpu))
730 return false;
731
732 if (!test_bit(VCPU_EXREG_PDPTR,
733 (unsigned long *)&vcpu->arch.regs_avail))
734 return true;
735
736 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
737 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
738 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
739 PFERR_USER_MASK | PFERR_WRITE_MASK);
740 if (r < 0)
741 goto out;
742 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
743out:
744
745 return changed;
746}
747EXPORT_SYMBOL_GPL(pdptrs_changed);
748
749int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
750{
751 unsigned long old_cr0 = kvm_read_cr0(vcpu);
752 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
753
754 cr0 |= X86_CR0_ET;
755
756#ifdef CONFIG_X86_64
757 if (cr0 & 0xffffffff00000000UL)
758 return 1;
759#endif
760
761 cr0 &= ~CR0_RESERVED_BITS;
762
763 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
764 return 1;
765
766 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
767 return 1;
768
769 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
770#ifdef CONFIG_X86_64
771 if ((vcpu->arch.efer & EFER_LME)) {
772 int cs_db, cs_l;
773
774 if (!is_pae(vcpu))
775 return 1;
776 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
777 if (cs_l)
778 return 1;
779 } else
780#endif
781 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
782 kvm_read_cr3(vcpu)))
783 return 1;
784 }
785
786 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
787 return 1;
788
789 kvm_x86_ops->set_cr0(vcpu, cr0);
790
791 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
792 kvm_clear_async_pf_completion_queue(vcpu);
793 kvm_async_pf_hash_reset(vcpu);
794 }
795
796 if ((cr0 ^ old_cr0) & update_bits)
797 kvm_mmu_reset_context(vcpu);
798
799 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
800 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
801 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
802 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
803
804 return 0;
805}
806EXPORT_SYMBOL_GPL(kvm_set_cr0);
807
808void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
809{
810 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
811}
812EXPORT_SYMBOL_GPL(kvm_lmsw);
813
814void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
815{
816 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
817 !vcpu->guest_xcr0_loaded) {
818 /* kvm_set_xcr() also depends on this */
819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
821 vcpu->guest_xcr0_loaded = 1;
822 }
823}
824EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
825
826void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
827{
828 if (vcpu->guest_xcr0_loaded) {
829 if (vcpu->arch.xcr0 != host_xcr0)
830 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
831 vcpu->guest_xcr0_loaded = 0;
832 }
833}
834EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
835
836static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
837{
838 u64 xcr0 = xcr;
839 u64 old_xcr0 = vcpu->arch.xcr0;
840 u64 valid_bits;
841
842 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
843 if (index != XCR_XFEATURE_ENABLED_MASK)
844 return 1;
845 if (!(xcr0 & XFEATURE_MASK_FP))
846 return 1;
847 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
848 return 1;
849
850 /*
851 * Do not allow the guest to set bits that we do not support
852 * saving. However, xcr0 bit 0 is always set, even if the
853 * emulated CPU does not support XSAVE (see fx_init).
854 */
855 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
856 if (xcr0 & ~valid_bits)
857 return 1;
858
859 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
860 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
861 return 1;
862
863 if (xcr0 & XFEATURE_MASK_AVX512) {
864 if (!(xcr0 & XFEATURE_MASK_YMM))
865 return 1;
866 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
867 return 1;
868 }
869 vcpu->arch.xcr0 = xcr0;
870
871 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
872 kvm_update_cpuid(vcpu);
873 return 0;
874}
875
876int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
877{
878 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
879 __kvm_set_xcr(vcpu, index, xcr)) {
880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884}
885EXPORT_SYMBOL_GPL(kvm_set_xcr);
886
887int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
888{
889 unsigned long old_cr4 = kvm_read_cr4(vcpu);
890 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
891 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
892
893 if (cr4 & CR4_RESERVED_BITS)
894 return 1;
895
896 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
897 return 1;
898
899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
900 return 1;
901
902 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
903 return 1;
904
905 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
906 return 1;
907
908 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
909 return 1;
910
911 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
912 return 1;
913
914 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
915 return 1;
916
917 if (is_long_mode(vcpu)) {
918 if (!(cr4 & X86_CR4_PAE))
919 return 1;
920 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
921 && ((cr4 ^ old_cr4) & pdptr_bits)
922 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
923 kvm_read_cr3(vcpu)))
924 return 1;
925
926 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
927 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
928 return 1;
929
930 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
931 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
932 return 1;
933 }
934
935 if (kvm_x86_ops->set_cr4(vcpu, cr4))
936 return 1;
937
938 if (((cr4 ^ old_cr4) & pdptr_bits) ||
939 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
940 kvm_mmu_reset_context(vcpu);
941
942 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
943 kvm_update_cpuid(vcpu);
944
945 return 0;
946}
947EXPORT_SYMBOL_GPL(kvm_set_cr4);
948
949int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
950{
951 bool skip_tlb_flush = false;
952#ifdef CONFIG_X86_64
953 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
954
955 if (pcid_enabled) {
956 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
957 cr3 &= ~X86_CR3_PCID_NOFLUSH;
958 }
959#endif
960
961 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
962 if (!skip_tlb_flush) {
963 kvm_mmu_sync_roots(vcpu);
964 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
965 }
966 return 0;
967 }
968
969 if (is_long_mode(vcpu) &&
970 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
971 return 1;
972 else if (is_pae_paging(vcpu) &&
973 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
974 return 1;
975
976 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
977 vcpu->arch.cr3 = cr3;
978 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
979
980 return 0;
981}
982EXPORT_SYMBOL_GPL(kvm_set_cr3);
983
984int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
985{
986 if (cr8 & CR8_RESERVED_BITS)
987 return 1;
988 if (lapic_in_kernel(vcpu))
989 kvm_lapic_set_tpr(vcpu, cr8);
990 else
991 vcpu->arch.cr8 = cr8;
992 return 0;
993}
994EXPORT_SYMBOL_GPL(kvm_set_cr8);
995
996unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
997{
998 if (lapic_in_kernel(vcpu))
999 return kvm_lapic_get_cr8(vcpu);
1000 else
1001 return vcpu->arch.cr8;
1002}
1003EXPORT_SYMBOL_GPL(kvm_get_cr8);
1004
1005static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1006{
1007 int i;
1008
1009 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1010 for (i = 0; i < KVM_NR_DB_REGS; i++)
1011 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1012 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1013 }
1014}
1015
1016static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1017{
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1019 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1020}
1021
1022static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1023{
1024 unsigned long dr7;
1025
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 dr7 = vcpu->arch.guest_debug_dr7;
1028 else
1029 dr7 = vcpu->arch.dr7;
1030 kvm_x86_ops->set_dr7(vcpu, dr7);
1031 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1032 if (dr7 & DR7_BP_EN_MASK)
1033 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1034}
1035
1036static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1037{
1038 u64 fixed = DR6_FIXED_1;
1039
1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1041 fixed |= DR6_RTM;
1042 return fixed;
1043}
1044
1045static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1046{
1047 switch (dr) {
1048 case 0 ... 3:
1049 vcpu->arch.db[dr] = val;
1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1051 vcpu->arch.eff_db[dr] = val;
1052 break;
1053 case 4:
1054 /* fall through */
1055 case 6:
1056 if (val & 0xffffffff00000000ULL)
1057 return -1; /* #GP */
1058 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1059 kvm_update_dr6(vcpu);
1060 break;
1061 case 5:
1062 /* fall through */
1063 default: /* 7 */
1064 if (val & 0xffffffff00000000ULL)
1065 return -1; /* #GP */
1066 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1067 kvm_update_dr7(vcpu);
1068 break;
1069 }
1070
1071 return 0;
1072}
1073
1074int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1075{
1076 if (__kvm_set_dr(vcpu, dr, val)) {
1077 kvm_inject_gp(vcpu, 0);
1078 return 1;
1079 }
1080 return 0;
1081}
1082EXPORT_SYMBOL_GPL(kvm_set_dr);
1083
1084int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1085{
1086 switch (dr) {
1087 case 0 ... 3:
1088 *val = vcpu->arch.db[dr];
1089 break;
1090 case 4:
1091 /* fall through */
1092 case 6:
1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1094 *val = vcpu->arch.dr6;
1095 else
1096 *val = kvm_x86_ops->get_dr6(vcpu);
1097 break;
1098 case 5:
1099 /* fall through */
1100 default: /* 7 */
1101 *val = vcpu->arch.dr7;
1102 break;
1103 }
1104 return 0;
1105}
1106EXPORT_SYMBOL_GPL(kvm_get_dr);
1107
1108bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1109{
1110 u32 ecx = kvm_rcx_read(vcpu);
1111 u64 data;
1112 int err;
1113
1114 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1115 if (err)
1116 return err;
1117 kvm_rax_write(vcpu, (u32)data);
1118 kvm_rdx_write(vcpu, data >> 32);
1119 return err;
1120}
1121EXPORT_SYMBOL_GPL(kvm_rdpmc);
1122
1123/*
1124 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1125 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1126 *
1127 * This list is modified at module load time to reflect the
1128 * capabilities of the host cpu. This capabilities test skips MSRs that are
1129 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1130 * may depend on host virtualization features rather than host cpu features.
1131 */
1132
1133static u32 msrs_to_save[] = {
1134 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1135 MSR_STAR,
1136#ifdef CONFIG_X86_64
1137 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1138#endif
1139 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1140 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1141 MSR_IA32_SPEC_CTRL,
1142 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1143 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1144 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1145 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1146 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1147 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1148};
1149
1150static unsigned num_msrs_to_save;
1151
1152static u32 emulated_msrs[] = {
1153 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1154 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1155 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1156 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1157 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1158 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1159 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1160 HV_X64_MSR_RESET,
1161 HV_X64_MSR_VP_INDEX,
1162 HV_X64_MSR_VP_RUNTIME,
1163 HV_X64_MSR_SCONTROL,
1164 HV_X64_MSR_STIMER0_CONFIG,
1165 HV_X64_MSR_VP_ASSIST_PAGE,
1166 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1167 HV_X64_MSR_TSC_EMULATION_STATUS,
1168
1169 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1170 MSR_KVM_PV_EOI_EN,
1171
1172 MSR_IA32_TSC_ADJUST,
1173 MSR_IA32_TSCDEADLINE,
1174 MSR_IA32_ARCH_CAPABILITIES,
1175 MSR_IA32_MISC_ENABLE,
1176 MSR_IA32_MCG_STATUS,
1177 MSR_IA32_MCG_CTL,
1178 MSR_IA32_MCG_EXT_CTL,
1179 MSR_IA32_SMBASE,
1180 MSR_SMI_COUNT,
1181 MSR_PLATFORM_INFO,
1182 MSR_MISC_FEATURES_ENABLES,
1183 MSR_AMD64_VIRT_SPEC_CTRL,
1184 MSR_IA32_POWER_CTL,
1185
1186 /*
1187 * The following list leaves out MSRs whose values are determined
1188 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1189 * We always support the "true" VMX control MSRs, even if the host
1190 * processor does not, so I am putting these registers here rather
1191 * than in msrs_to_save.
1192 */
1193 MSR_IA32_VMX_BASIC,
1194 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1195 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1196 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1197 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1198 MSR_IA32_VMX_MISC,
1199 MSR_IA32_VMX_CR0_FIXED0,
1200 MSR_IA32_VMX_CR4_FIXED0,
1201 MSR_IA32_VMX_VMCS_ENUM,
1202 MSR_IA32_VMX_PROCBASED_CTLS2,
1203 MSR_IA32_VMX_EPT_VPID_CAP,
1204 MSR_IA32_VMX_VMFUNC,
1205
1206 MSR_K7_HWCR,
1207 MSR_KVM_POLL_CONTROL,
1208};
1209
1210static unsigned num_emulated_msrs;
1211
1212/*
1213 * List of msr numbers which are used to expose MSR-based features that
1214 * can be used by a hypervisor to validate requested CPU features.
1215 */
1216static u32 msr_based_features[] = {
1217 MSR_IA32_VMX_BASIC,
1218 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1219 MSR_IA32_VMX_PINBASED_CTLS,
1220 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1221 MSR_IA32_VMX_PROCBASED_CTLS,
1222 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1223 MSR_IA32_VMX_EXIT_CTLS,
1224 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1225 MSR_IA32_VMX_ENTRY_CTLS,
1226 MSR_IA32_VMX_MISC,
1227 MSR_IA32_VMX_CR0_FIXED0,
1228 MSR_IA32_VMX_CR0_FIXED1,
1229 MSR_IA32_VMX_CR4_FIXED0,
1230 MSR_IA32_VMX_CR4_FIXED1,
1231 MSR_IA32_VMX_VMCS_ENUM,
1232 MSR_IA32_VMX_PROCBASED_CTLS2,
1233 MSR_IA32_VMX_EPT_VPID_CAP,
1234 MSR_IA32_VMX_VMFUNC,
1235
1236 MSR_F10H_DECFG,
1237 MSR_IA32_UCODE_REV,
1238 MSR_IA32_ARCH_CAPABILITIES,
1239};
1240
1241static unsigned int num_msr_based_features;
1242
1243static u64 kvm_get_arch_capabilities(void)
1244{
1245 u64 data = 0;
1246
1247 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1248 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1249
1250 /*
1251 * If we're doing cache flushes (either "always" or "cond")
1252 * we will do one whenever the guest does a vmlaunch/vmresume.
1253 * If an outer hypervisor is doing the cache flush for us
1254 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1255 * capability to the guest too, and if EPT is disabled we're not
1256 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1257 * require a nested hypervisor to do a flush of its own.
1258 */
1259 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1260 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1261
1262 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1263 data |= ARCH_CAP_RDCL_NO;
1264 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1265 data |= ARCH_CAP_SSB_NO;
1266 if (!boot_cpu_has_bug(X86_BUG_MDS))
1267 data |= ARCH_CAP_MDS_NO;
1268
1269 return data;
1270}
1271
1272static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1273{
1274 switch (msr->index) {
1275 case MSR_IA32_ARCH_CAPABILITIES:
1276 msr->data = kvm_get_arch_capabilities();
1277 break;
1278 case MSR_IA32_UCODE_REV:
1279 rdmsrl_safe(msr->index, &msr->data);
1280 break;
1281 default:
1282 if (kvm_x86_ops->get_msr_feature(msr))
1283 return 1;
1284 }
1285 return 0;
1286}
1287
1288static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1289{
1290 struct kvm_msr_entry msr;
1291 int r;
1292
1293 msr.index = index;
1294 r = kvm_get_msr_feature(&msr);
1295 if (r)
1296 return r;
1297
1298 *data = msr.data;
1299
1300 return 0;
1301}
1302
1303static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1304{
1305 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1306 return false;
1307
1308 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1309 return false;
1310
1311 if (efer & (EFER_LME | EFER_LMA) &&
1312 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1313 return false;
1314
1315 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1316 return false;
1317
1318 return true;
1319
1320}
1321bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1322{
1323 if (efer & efer_reserved_bits)
1324 return false;
1325
1326 return __kvm_valid_efer(vcpu, efer);
1327}
1328EXPORT_SYMBOL_GPL(kvm_valid_efer);
1329
1330static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1331{
1332 u64 old_efer = vcpu->arch.efer;
1333 u64 efer = msr_info->data;
1334
1335 if (efer & efer_reserved_bits)
1336 return 1;
1337
1338 if (!msr_info->host_initiated) {
1339 if (!__kvm_valid_efer(vcpu, efer))
1340 return 1;
1341
1342 if (is_paging(vcpu) &&
1343 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1344 return 1;
1345 }
1346
1347 efer &= ~EFER_LMA;
1348 efer |= vcpu->arch.efer & EFER_LMA;
1349
1350 kvm_x86_ops->set_efer(vcpu, efer);
1351
1352 /* Update reserved bits */
1353 if ((efer ^ old_efer) & EFER_NX)
1354 kvm_mmu_reset_context(vcpu);
1355
1356 return 0;
1357}
1358
1359void kvm_enable_efer_bits(u64 mask)
1360{
1361 efer_reserved_bits &= ~mask;
1362}
1363EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1364
1365/*
1366 * Write @data into the MSR specified by @index. Select MSR specific fault
1367 * checks are bypassed if @host_initiated is %true.
1368 * Returns 0 on success, non-0 otherwise.
1369 * Assumes vcpu_load() was already called.
1370 */
1371static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1372 bool host_initiated)
1373{
1374 struct msr_data msr;
1375
1376 switch (index) {
1377 case MSR_FS_BASE:
1378 case MSR_GS_BASE:
1379 case MSR_KERNEL_GS_BASE:
1380 case MSR_CSTAR:
1381 case MSR_LSTAR:
1382 if (is_noncanonical_address(data, vcpu))
1383 return 1;
1384 break;
1385 case MSR_IA32_SYSENTER_EIP:
1386 case MSR_IA32_SYSENTER_ESP:
1387 /*
1388 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1389 * non-canonical address is written on Intel but not on
1390 * AMD (which ignores the top 32-bits, because it does
1391 * not implement 64-bit SYSENTER).
1392 *
1393 * 64-bit code should hence be able to write a non-canonical
1394 * value on AMD. Making the address canonical ensures that
1395 * vmentry does not fail on Intel after writing a non-canonical
1396 * value, and that something deterministic happens if the guest
1397 * invokes 64-bit SYSENTER.
1398 */
1399 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1400 }
1401
1402 msr.data = data;
1403 msr.index = index;
1404 msr.host_initiated = host_initiated;
1405
1406 return kvm_x86_ops->set_msr(vcpu, &msr);
1407}
1408
1409/*
1410 * Read the MSR specified by @index into @data. Select MSR specific fault
1411 * checks are bypassed if @host_initiated is %true.
1412 * Returns 0 on success, non-0 otherwise.
1413 * Assumes vcpu_load() was already called.
1414 */
1415static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1416 bool host_initiated)
1417{
1418 struct msr_data msr;
1419 int ret;
1420
1421 msr.index = index;
1422 msr.host_initiated = host_initiated;
1423
1424 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1425 if (!ret)
1426 *data = msr.data;
1427 return ret;
1428}
1429
1430int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1431{
1432 return __kvm_get_msr(vcpu, index, data, false);
1433}
1434EXPORT_SYMBOL_GPL(kvm_get_msr);
1435
1436int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1437{
1438 return __kvm_set_msr(vcpu, index, data, false);
1439}
1440EXPORT_SYMBOL_GPL(kvm_set_msr);
1441
1442int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1443{
1444 u32 ecx = kvm_rcx_read(vcpu);
1445 u64 data;
1446
1447 if (kvm_get_msr(vcpu, ecx, &data)) {
1448 trace_kvm_msr_read_ex(ecx);
1449 kvm_inject_gp(vcpu, 0);
1450 return 1;
1451 }
1452
1453 trace_kvm_msr_read(ecx, data);
1454
1455 kvm_rax_write(vcpu, data & -1u);
1456 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1457 return kvm_skip_emulated_instruction(vcpu);
1458}
1459EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1460
1461int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1462{
1463 u32 ecx = kvm_rcx_read(vcpu);
1464 u64 data = kvm_read_edx_eax(vcpu);
1465
1466 if (kvm_set_msr(vcpu, ecx, data)) {
1467 trace_kvm_msr_write_ex(ecx, data);
1468 kvm_inject_gp(vcpu, 0);
1469 return 1;
1470 }
1471
1472 trace_kvm_msr_write(ecx, data);
1473 return kvm_skip_emulated_instruction(vcpu);
1474}
1475EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1476
1477/*
1478 * Adapt set_msr() to msr_io()'s calling convention
1479 */
1480static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1481{
1482 return __kvm_get_msr(vcpu, index, data, true);
1483}
1484
1485static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1486{
1487 return __kvm_set_msr(vcpu, index, *data, true);
1488}
1489
1490#ifdef CONFIG_X86_64
1491struct pvclock_gtod_data {
1492 seqcount_t seq;
1493
1494 struct { /* extract of a clocksource struct */
1495 int vclock_mode;
1496 u64 cycle_last;
1497 u64 mask;
1498 u32 mult;
1499 u32 shift;
1500 } clock;
1501
1502 u64 boot_ns;
1503 u64 nsec_base;
1504 u64 wall_time_sec;
1505};
1506
1507static struct pvclock_gtod_data pvclock_gtod_data;
1508
1509static void update_pvclock_gtod(struct timekeeper *tk)
1510{
1511 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1512 u64 boot_ns;
1513
1514 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1515
1516 write_seqcount_begin(&vdata->seq);
1517
1518 /* copy pvclock gtod data */
1519 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1520 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1521 vdata->clock.mask = tk->tkr_mono.mask;
1522 vdata->clock.mult = tk->tkr_mono.mult;
1523 vdata->clock.shift = tk->tkr_mono.shift;
1524
1525 vdata->boot_ns = boot_ns;
1526 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1527
1528 vdata->wall_time_sec = tk->xtime_sec;
1529
1530 write_seqcount_end(&vdata->seq);
1531}
1532#endif
1533
1534void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1535{
1536 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1537 kvm_vcpu_kick(vcpu);
1538}
1539
1540static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1541{
1542 int version;
1543 int r;
1544 struct pvclock_wall_clock wc;
1545 struct timespec64 boot;
1546
1547 if (!wall_clock)
1548 return;
1549
1550 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1551 if (r)
1552 return;
1553
1554 if (version & 1)
1555 ++version; /* first time write, random junk */
1556
1557 ++version;
1558
1559 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1560 return;
1561
1562 /*
1563 * The guest calculates current wall clock time by adding
1564 * system time (updated by kvm_guest_time_update below) to the
1565 * wall clock specified here. guest system time equals host
1566 * system time for us, thus we must fill in host boot time here.
1567 */
1568 getboottime64(&boot);
1569
1570 if (kvm->arch.kvmclock_offset) {
1571 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1572 boot = timespec64_sub(boot, ts);
1573 }
1574 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1575 wc.nsec = boot.tv_nsec;
1576 wc.version = version;
1577
1578 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1579
1580 version++;
1581 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1582}
1583
1584static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1585{
1586 do_shl32_div32(dividend, divisor);
1587 return dividend;
1588}
1589
1590static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1591 s8 *pshift, u32 *pmultiplier)
1592{
1593 uint64_t scaled64;
1594 int32_t shift = 0;
1595 uint64_t tps64;
1596 uint32_t tps32;
1597
1598 tps64 = base_hz;
1599 scaled64 = scaled_hz;
1600 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1601 tps64 >>= 1;
1602 shift--;
1603 }
1604
1605 tps32 = (uint32_t)tps64;
1606 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1607 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1608 scaled64 >>= 1;
1609 else
1610 tps32 <<= 1;
1611 shift++;
1612 }
1613
1614 *pshift = shift;
1615 *pmultiplier = div_frac(scaled64, tps32);
1616}
1617
1618#ifdef CONFIG_X86_64
1619static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1620#endif
1621
1622static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1623static unsigned long max_tsc_khz;
1624
1625static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1626{
1627 u64 v = (u64)khz * (1000000 + ppm);
1628 do_div(v, 1000000);
1629 return v;
1630}
1631
1632static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1633{
1634 u64 ratio;
1635
1636 /* Guest TSC same frequency as host TSC? */
1637 if (!scale) {
1638 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1639 return 0;
1640 }
1641
1642 /* TSC scaling supported? */
1643 if (!kvm_has_tsc_control) {
1644 if (user_tsc_khz > tsc_khz) {
1645 vcpu->arch.tsc_catchup = 1;
1646 vcpu->arch.tsc_always_catchup = 1;
1647 return 0;
1648 } else {
1649 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1650 return -1;
1651 }
1652 }
1653
1654 /* TSC scaling required - calculate ratio */
1655 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1656 user_tsc_khz, tsc_khz);
1657
1658 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1659 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1660 user_tsc_khz);
1661 return -1;
1662 }
1663
1664 vcpu->arch.tsc_scaling_ratio = ratio;
1665 return 0;
1666}
1667
1668static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1669{
1670 u32 thresh_lo, thresh_hi;
1671 int use_scaling = 0;
1672
1673 /* tsc_khz can be zero if TSC calibration fails */
1674 if (user_tsc_khz == 0) {
1675 /* set tsc_scaling_ratio to a safe value */
1676 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1677 return -1;
1678 }
1679
1680 /* Compute a scale to convert nanoseconds in TSC cycles */
1681 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1682 &vcpu->arch.virtual_tsc_shift,
1683 &vcpu->arch.virtual_tsc_mult);
1684 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1685
1686 /*
1687 * Compute the variation in TSC rate which is acceptable
1688 * within the range of tolerance and decide if the
1689 * rate being applied is within that bounds of the hardware
1690 * rate. If so, no scaling or compensation need be done.
1691 */
1692 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1693 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1694 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1695 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1696 use_scaling = 1;
1697 }
1698 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1699}
1700
1701static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1702{
1703 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1704 vcpu->arch.virtual_tsc_mult,
1705 vcpu->arch.virtual_tsc_shift);
1706 tsc += vcpu->arch.this_tsc_write;
1707 return tsc;
1708}
1709
1710static inline int gtod_is_based_on_tsc(int mode)
1711{
1712 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1713}
1714
1715static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1716{
1717#ifdef CONFIG_X86_64
1718 bool vcpus_matched;
1719 struct kvm_arch *ka = &vcpu->kvm->arch;
1720 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1721
1722 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1723 atomic_read(&vcpu->kvm->online_vcpus));
1724
1725 /*
1726 * Once the masterclock is enabled, always perform request in
1727 * order to update it.
1728 *
1729 * In order to enable masterclock, the host clocksource must be TSC
1730 * and the vcpus need to have matched TSCs. When that happens,
1731 * perform request to enable masterclock.
1732 */
1733 if (ka->use_master_clock ||
1734 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1735 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1736
1737 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1738 atomic_read(&vcpu->kvm->online_vcpus),
1739 ka->use_master_clock, gtod->clock.vclock_mode);
1740#endif
1741}
1742
1743static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1744{
1745 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1746 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1747}
1748
1749/*
1750 * Multiply tsc by a fixed point number represented by ratio.
1751 *
1752 * The most significant 64-N bits (mult) of ratio represent the
1753 * integral part of the fixed point number; the remaining N bits
1754 * (frac) represent the fractional part, ie. ratio represents a fixed
1755 * point number (mult + frac * 2^(-N)).
1756 *
1757 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1758 */
1759static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1760{
1761 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1762}
1763
1764u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1765{
1766 u64 _tsc = tsc;
1767 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1768
1769 if (ratio != kvm_default_tsc_scaling_ratio)
1770 _tsc = __scale_tsc(ratio, tsc);
1771
1772 return _tsc;
1773}
1774EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1775
1776static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1777{
1778 u64 tsc;
1779
1780 tsc = kvm_scale_tsc(vcpu, rdtsc());
1781
1782 return target_tsc - tsc;
1783}
1784
1785u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1786{
1787 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1788
1789 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1790}
1791EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1792
1793static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1794{
1795 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1796}
1797
1798static inline bool kvm_check_tsc_unstable(void)
1799{
1800#ifdef CONFIG_X86_64
1801 /*
1802 * TSC is marked unstable when we're running on Hyper-V,
1803 * 'TSC page' clocksource is good.
1804 */
1805 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1806 return false;
1807#endif
1808 return check_tsc_unstable();
1809}
1810
1811void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1812{
1813 struct kvm *kvm = vcpu->kvm;
1814 u64 offset, ns, elapsed;
1815 unsigned long flags;
1816 bool matched;
1817 bool already_matched;
1818 u64 data = msr->data;
1819 bool synchronizing = false;
1820
1821 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1822 offset = kvm_compute_tsc_offset(vcpu, data);
1823 ns = ktime_get_boottime_ns();
1824 elapsed = ns - kvm->arch.last_tsc_nsec;
1825
1826 if (vcpu->arch.virtual_tsc_khz) {
1827 if (data == 0 && msr->host_initiated) {
1828 /*
1829 * detection of vcpu initialization -- need to sync
1830 * with other vCPUs. This particularly helps to keep
1831 * kvm_clock stable after CPU hotplug
1832 */
1833 synchronizing = true;
1834 } else {
1835 u64 tsc_exp = kvm->arch.last_tsc_write +
1836 nsec_to_cycles(vcpu, elapsed);
1837 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1838 /*
1839 * Special case: TSC write with a small delta (1 second)
1840 * of virtual cycle time against real time is
1841 * interpreted as an attempt to synchronize the CPU.
1842 */
1843 synchronizing = data < tsc_exp + tsc_hz &&
1844 data + tsc_hz > tsc_exp;
1845 }
1846 }
1847
1848 /*
1849 * For a reliable TSC, we can match TSC offsets, and for an unstable
1850 * TSC, we add elapsed time in this computation. We could let the
1851 * compensation code attempt to catch up if we fall behind, but
1852 * it's better to try to match offsets from the beginning.
1853 */
1854 if (synchronizing &&
1855 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1856 if (!kvm_check_tsc_unstable()) {
1857 offset = kvm->arch.cur_tsc_offset;
1858 } else {
1859 u64 delta = nsec_to_cycles(vcpu, elapsed);
1860 data += delta;
1861 offset = kvm_compute_tsc_offset(vcpu, data);
1862 }
1863 matched = true;
1864 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1865 } else {
1866 /*
1867 * We split periods of matched TSC writes into generations.
1868 * For each generation, we track the original measured
1869 * nanosecond time, offset, and write, so if TSCs are in
1870 * sync, we can match exact offset, and if not, we can match
1871 * exact software computation in compute_guest_tsc()
1872 *
1873 * These values are tracked in kvm->arch.cur_xxx variables.
1874 */
1875 kvm->arch.cur_tsc_generation++;
1876 kvm->arch.cur_tsc_nsec = ns;
1877 kvm->arch.cur_tsc_write = data;
1878 kvm->arch.cur_tsc_offset = offset;
1879 matched = false;
1880 }
1881
1882 /*
1883 * We also track th most recent recorded KHZ, write and time to
1884 * allow the matching interval to be extended at each write.
1885 */
1886 kvm->arch.last_tsc_nsec = ns;
1887 kvm->arch.last_tsc_write = data;
1888 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1889
1890 vcpu->arch.last_guest_tsc = data;
1891
1892 /* Keep track of which generation this VCPU has synchronized to */
1893 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1894 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1895 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1896
1897 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1898 update_ia32_tsc_adjust_msr(vcpu, offset);
1899
1900 kvm_vcpu_write_tsc_offset(vcpu, offset);
1901 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1902
1903 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1904 if (!matched) {
1905 kvm->arch.nr_vcpus_matched_tsc = 0;
1906 } else if (!already_matched) {
1907 kvm->arch.nr_vcpus_matched_tsc++;
1908 }
1909
1910 kvm_track_tsc_matching(vcpu);
1911 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1912}
1913
1914EXPORT_SYMBOL_GPL(kvm_write_tsc);
1915
1916static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1917 s64 adjustment)
1918{
1919 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1920 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1921}
1922
1923static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1924{
1925 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1926 WARN_ON(adjustment < 0);
1927 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1928 adjust_tsc_offset_guest(vcpu, adjustment);
1929}
1930
1931#ifdef CONFIG_X86_64
1932
1933static u64 read_tsc(void)
1934{
1935 u64 ret = (u64)rdtsc_ordered();
1936 u64 last = pvclock_gtod_data.clock.cycle_last;
1937
1938 if (likely(ret >= last))
1939 return ret;
1940
1941 /*
1942 * GCC likes to generate cmov here, but this branch is extremely
1943 * predictable (it's just a function of time and the likely is
1944 * very likely) and there's a data dependence, so force GCC
1945 * to generate a branch instead. I don't barrier() because
1946 * we don't actually need a barrier, and if this function
1947 * ever gets inlined it will generate worse code.
1948 */
1949 asm volatile ("");
1950 return last;
1951}
1952
1953static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1954{
1955 long v;
1956 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1957 u64 tsc_pg_val;
1958
1959 switch (gtod->clock.vclock_mode) {
1960 case VCLOCK_HVCLOCK:
1961 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1962 tsc_timestamp);
1963 if (tsc_pg_val != U64_MAX) {
1964 /* TSC page valid */
1965 *mode = VCLOCK_HVCLOCK;
1966 v = (tsc_pg_val - gtod->clock.cycle_last) &
1967 gtod->clock.mask;
1968 } else {
1969 /* TSC page invalid */
1970 *mode = VCLOCK_NONE;
1971 }
1972 break;
1973 case VCLOCK_TSC:
1974 *mode = VCLOCK_TSC;
1975 *tsc_timestamp = read_tsc();
1976 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1977 gtod->clock.mask;
1978 break;
1979 default:
1980 *mode = VCLOCK_NONE;
1981 }
1982
1983 if (*mode == VCLOCK_NONE)
1984 *tsc_timestamp = v = 0;
1985
1986 return v * gtod->clock.mult;
1987}
1988
1989static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1990{
1991 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1992 unsigned long seq;
1993 int mode;
1994 u64 ns;
1995
1996 do {
1997 seq = read_seqcount_begin(&gtod->seq);
1998 ns = gtod->nsec_base;
1999 ns += vgettsc(tsc_timestamp, &mode);
2000 ns >>= gtod->clock.shift;
2001 ns += gtod->boot_ns;
2002 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2003 *t = ns;
2004
2005 return mode;
2006}
2007
2008static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2009{
2010 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2011 unsigned long seq;
2012 int mode;
2013 u64 ns;
2014
2015 do {
2016 seq = read_seqcount_begin(&gtod->seq);
2017 ts->tv_sec = gtod->wall_time_sec;
2018 ns = gtod->nsec_base;
2019 ns += vgettsc(tsc_timestamp, &mode);
2020 ns >>= gtod->clock.shift;
2021 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2022
2023 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2024 ts->tv_nsec = ns;
2025
2026 return mode;
2027}
2028
2029/* returns true if host is using TSC based clocksource */
2030static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2031{
2032 /* checked again under seqlock below */
2033 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2034 return false;
2035
2036 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2037 tsc_timestamp));
2038}
2039
2040/* returns true if host is using TSC based clocksource */
2041static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2042 u64 *tsc_timestamp)
2043{
2044 /* checked again under seqlock below */
2045 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2046 return false;
2047
2048 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2049}
2050#endif
2051
2052/*
2053 *
2054 * Assuming a stable TSC across physical CPUS, and a stable TSC
2055 * across virtual CPUs, the following condition is possible.
2056 * Each numbered line represents an event visible to both
2057 * CPUs at the next numbered event.
2058 *
2059 * "timespecX" represents host monotonic time. "tscX" represents
2060 * RDTSC value.
2061 *
2062 * VCPU0 on CPU0 | VCPU1 on CPU1
2063 *
2064 * 1. read timespec0,tsc0
2065 * 2. | timespec1 = timespec0 + N
2066 * | tsc1 = tsc0 + M
2067 * 3. transition to guest | transition to guest
2068 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2069 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2070 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2071 *
2072 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2073 *
2074 * - ret0 < ret1
2075 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2076 * ...
2077 * - 0 < N - M => M < N
2078 *
2079 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2080 * always the case (the difference between two distinct xtime instances
2081 * might be smaller then the difference between corresponding TSC reads,
2082 * when updating guest vcpus pvclock areas).
2083 *
2084 * To avoid that problem, do not allow visibility of distinct
2085 * system_timestamp/tsc_timestamp values simultaneously: use a master
2086 * copy of host monotonic time values. Update that master copy
2087 * in lockstep.
2088 *
2089 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2090 *
2091 */
2092
2093static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2094{
2095#ifdef CONFIG_X86_64
2096 struct kvm_arch *ka = &kvm->arch;
2097 int vclock_mode;
2098 bool host_tsc_clocksource, vcpus_matched;
2099
2100 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2101 atomic_read(&kvm->online_vcpus));
2102
2103 /*
2104 * If the host uses TSC clock, then passthrough TSC as stable
2105 * to the guest.
2106 */
2107 host_tsc_clocksource = kvm_get_time_and_clockread(
2108 &ka->master_kernel_ns,
2109 &ka->master_cycle_now);
2110
2111 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2112 && !ka->backwards_tsc_observed
2113 && !ka->boot_vcpu_runs_old_kvmclock;
2114
2115 if (ka->use_master_clock)
2116 atomic_set(&kvm_guest_has_master_clock, 1);
2117
2118 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2119 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2120 vcpus_matched);
2121#endif
2122}
2123
2124void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2125{
2126 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2127}
2128
2129static void kvm_gen_update_masterclock(struct kvm *kvm)
2130{
2131#ifdef CONFIG_X86_64
2132 int i;
2133 struct kvm_vcpu *vcpu;
2134 struct kvm_arch *ka = &kvm->arch;
2135
2136 spin_lock(&ka->pvclock_gtod_sync_lock);
2137 kvm_make_mclock_inprogress_request(kvm);
2138 /* no guest entries from this point */
2139 pvclock_update_vm_gtod_copy(kvm);
2140
2141 kvm_for_each_vcpu(i, vcpu, kvm)
2142 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2143
2144 /* guest entries allowed */
2145 kvm_for_each_vcpu(i, vcpu, kvm)
2146 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2147
2148 spin_unlock(&ka->pvclock_gtod_sync_lock);
2149#endif
2150}
2151
2152u64 get_kvmclock_ns(struct kvm *kvm)
2153{
2154 struct kvm_arch *ka = &kvm->arch;
2155 struct pvclock_vcpu_time_info hv_clock;
2156 u64 ret;
2157
2158 spin_lock(&ka->pvclock_gtod_sync_lock);
2159 if (!ka->use_master_clock) {
2160 spin_unlock(&ka->pvclock_gtod_sync_lock);
2161 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2162 }
2163
2164 hv_clock.tsc_timestamp = ka->master_cycle_now;
2165 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2166 spin_unlock(&ka->pvclock_gtod_sync_lock);
2167
2168 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2169 get_cpu();
2170
2171 if (__this_cpu_read(cpu_tsc_khz)) {
2172 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2173 &hv_clock.tsc_shift,
2174 &hv_clock.tsc_to_system_mul);
2175 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2176 } else
2177 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2178
2179 put_cpu();
2180
2181 return ret;
2182}
2183
2184static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2185{
2186 struct kvm_vcpu_arch *vcpu = &v->arch;
2187 struct pvclock_vcpu_time_info guest_hv_clock;
2188
2189 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2190 &guest_hv_clock, sizeof(guest_hv_clock))))
2191 return;
2192
2193 /* This VCPU is paused, but it's legal for a guest to read another
2194 * VCPU's kvmclock, so we really have to follow the specification where
2195 * it says that version is odd if data is being modified, and even after
2196 * it is consistent.
2197 *
2198 * Version field updates must be kept separate. This is because
2199 * kvm_write_guest_cached might use a "rep movs" instruction, and
2200 * writes within a string instruction are weakly ordered. So there
2201 * are three writes overall.
2202 *
2203 * As a small optimization, only write the version field in the first
2204 * and third write. The vcpu->pv_time cache is still valid, because the
2205 * version field is the first in the struct.
2206 */
2207 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2208
2209 if (guest_hv_clock.version & 1)
2210 ++guest_hv_clock.version; /* first time write, random junk */
2211
2212 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2213 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2214 &vcpu->hv_clock,
2215 sizeof(vcpu->hv_clock.version));
2216
2217 smp_wmb();
2218
2219 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2220 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2221
2222 if (vcpu->pvclock_set_guest_stopped_request) {
2223 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2224 vcpu->pvclock_set_guest_stopped_request = false;
2225 }
2226
2227 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2228
2229 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2230 &vcpu->hv_clock,
2231 sizeof(vcpu->hv_clock));
2232
2233 smp_wmb();
2234
2235 vcpu->hv_clock.version++;
2236 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2237 &vcpu->hv_clock,
2238 sizeof(vcpu->hv_clock.version));
2239}
2240
2241static int kvm_guest_time_update(struct kvm_vcpu *v)
2242{
2243 unsigned long flags, tgt_tsc_khz;
2244 struct kvm_vcpu_arch *vcpu = &v->arch;
2245 struct kvm_arch *ka = &v->kvm->arch;
2246 s64 kernel_ns;
2247 u64 tsc_timestamp, host_tsc;
2248 u8 pvclock_flags;
2249 bool use_master_clock;
2250
2251 kernel_ns = 0;
2252 host_tsc = 0;
2253
2254 /*
2255 * If the host uses TSC clock, then passthrough TSC as stable
2256 * to the guest.
2257 */
2258 spin_lock(&ka->pvclock_gtod_sync_lock);
2259 use_master_clock = ka->use_master_clock;
2260 if (use_master_clock) {
2261 host_tsc = ka->master_cycle_now;
2262 kernel_ns = ka->master_kernel_ns;
2263 }
2264 spin_unlock(&ka->pvclock_gtod_sync_lock);
2265
2266 /* Keep irq disabled to prevent changes to the clock */
2267 local_irq_save(flags);
2268 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2269 if (unlikely(tgt_tsc_khz == 0)) {
2270 local_irq_restore(flags);
2271 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2272 return 1;
2273 }
2274 if (!use_master_clock) {
2275 host_tsc = rdtsc();
2276 kernel_ns = ktime_get_boottime_ns();
2277 }
2278
2279 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2280
2281 /*
2282 * We may have to catch up the TSC to match elapsed wall clock
2283 * time for two reasons, even if kvmclock is used.
2284 * 1) CPU could have been running below the maximum TSC rate
2285 * 2) Broken TSC compensation resets the base at each VCPU
2286 * entry to avoid unknown leaps of TSC even when running
2287 * again on the same CPU. This may cause apparent elapsed
2288 * time to disappear, and the guest to stand still or run
2289 * very slowly.
2290 */
2291 if (vcpu->tsc_catchup) {
2292 u64 tsc = compute_guest_tsc(v, kernel_ns);
2293 if (tsc > tsc_timestamp) {
2294 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2295 tsc_timestamp = tsc;
2296 }
2297 }
2298
2299 local_irq_restore(flags);
2300
2301 /* With all the info we got, fill in the values */
2302
2303 if (kvm_has_tsc_control)
2304 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2305
2306 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2307 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2308 &vcpu->hv_clock.tsc_shift,
2309 &vcpu->hv_clock.tsc_to_system_mul);
2310 vcpu->hw_tsc_khz = tgt_tsc_khz;
2311 }
2312
2313 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2314 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2315 vcpu->last_guest_tsc = tsc_timestamp;
2316
2317 /* If the host uses TSC clocksource, then it is stable */
2318 pvclock_flags = 0;
2319 if (use_master_clock)
2320 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2321
2322 vcpu->hv_clock.flags = pvclock_flags;
2323
2324 if (vcpu->pv_time_enabled)
2325 kvm_setup_pvclock_page(v);
2326 if (v == kvm_get_vcpu(v->kvm, 0))
2327 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2328 return 0;
2329}
2330
2331/*
2332 * kvmclock updates which are isolated to a given vcpu, such as
2333 * vcpu->cpu migration, should not allow system_timestamp from
2334 * the rest of the vcpus to remain static. Otherwise ntp frequency
2335 * correction applies to one vcpu's system_timestamp but not
2336 * the others.
2337 *
2338 * So in those cases, request a kvmclock update for all vcpus.
2339 * We need to rate-limit these requests though, as they can
2340 * considerably slow guests that have a large number of vcpus.
2341 * The time for a remote vcpu to update its kvmclock is bound
2342 * by the delay we use to rate-limit the updates.
2343 */
2344
2345#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2346
2347static void kvmclock_update_fn(struct work_struct *work)
2348{
2349 int i;
2350 struct delayed_work *dwork = to_delayed_work(work);
2351 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2352 kvmclock_update_work);
2353 struct kvm *kvm = container_of(ka, struct kvm, arch);
2354 struct kvm_vcpu *vcpu;
2355
2356 kvm_for_each_vcpu(i, vcpu, kvm) {
2357 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2358 kvm_vcpu_kick(vcpu);
2359 }
2360}
2361
2362static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2363{
2364 struct kvm *kvm = v->kvm;
2365
2366 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2367 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2368 KVMCLOCK_UPDATE_DELAY);
2369}
2370
2371#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2372
2373static void kvmclock_sync_fn(struct work_struct *work)
2374{
2375 struct delayed_work *dwork = to_delayed_work(work);
2376 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2377 kvmclock_sync_work);
2378 struct kvm *kvm = container_of(ka, struct kvm, arch);
2379
2380 if (!kvmclock_periodic_sync)
2381 return;
2382
2383 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2384 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2385 KVMCLOCK_SYNC_PERIOD);
2386}
2387
2388/*
2389 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2390 */
2391static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2392{
2393 /* McStatusWrEn enabled? */
2394 if (guest_cpuid_is_amd(vcpu))
2395 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2396
2397 return false;
2398}
2399
2400static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2401{
2402 u64 mcg_cap = vcpu->arch.mcg_cap;
2403 unsigned bank_num = mcg_cap & 0xff;
2404 u32 msr = msr_info->index;
2405 u64 data = msr_info->data;
2406
2407 switch (msr) {
2408 case MSR_IA32_MCG_STATUS:
2409 vcpu->arch.mcg_status = data;
2410 break;
2411 case MSR_IA32_MCG_CTL:
2412 if (!(mcg_cap & MCG_CTL_P) &&
2413 (data || !msr_info->host_initiated))
2414 return 1;
2415 if (data != 0 && data != ~(u64)0)
2416 return 1;
2417 vcpu->arch.mcg_ctl = data;
2418 break;
2419 default:
2420 if (msr >= MSR_IA32_MC0_CTL &&
2421 msr < MSR_IA32_MCx_CTL(bank_num)) {
2422 u32 offset = msr - MSR_IA32_MC0_CTL;
2423 /* only 0 or all 1s can be written to IA32_MCi_CTL
2424 * some Linux kernels though clear bit 10 in bank 4 to
2425 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2426 * this to avoid an uncatched #GP in the guest
2427 */
2428 if ((offset & 0x3) == 0 &&
2429 data != 0 && (data | (1 << 10)) != ~(u64)0)
2430 return -1;
2431
2432 /* MCi_STATUS */
2433 if (!msr_info->host_initiated &&
2434 (offset & 0x3) == 1 && data != 0) {
2435 if (!can_set_mci_status(vcpu))
2436 return -1;
2437 }
2438
2439 vcpu->arch.mce_banks[offset] = data;
2440 break;
2441 }
2442 return 1;
2443 }
2444 return 0;
2445}
2446
2447static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2448{
2449 struct kvm *kvm = vcpu->kvm;
2450 int lm = is_long_mode(vcpu);
2451 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2452 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2453 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2454 : kvm->arch.xen_hvm_config.blob_size_32;
2455 u32 page_num = data & ~PAGE_MASK;
2456 u64 page_addr = data & PAGE_MASK;
2457 u8 *page;
2458 int r;
2459
2460 r = -E2BIG;
2461 if (page_num >= blob_size)
2462 goto out;
2463 r = -ENOMEM;
2464 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2465 if (IS_ERR(page)) {
2466 r = PTR_ERR(page);
2467 goto out;
2468 }
2469 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2470 goto out_free;
2471 r = 0;
2472out_free:
2473 kfree(page);
2474out:
2475 return r;
2476}
2477
2478static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2479{
2480 gpa_t gpa = data & ~0x3f;
2481
2482 /* Bits 3:5 are reserved, Should be zero */
2483 if (data & 0x38)
2484 return 1;
2485
2486 vcpu->arch.apf.msr_val = data;
2487
2488 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2489 kvm_clear_async_pf_completion_queue(vcpu);
2490 kvm_async_pf_hash_reset(vcpu);
2491 return 0;
2492 }
2493
2494 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2495 sizeof(u32)))
2496 return 1;
2497
2498 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2499 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2500 kvm_async_pf_wakeup_all(vcpu);
2501 return 0;
2502}
2503
2504static void kvmclock_reset(struct kvm_vcpu *vcpu)
2505{
2506 vcpu->arch.pv_time_enabled = false;
2507}
2508
2509static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2510{
2511 ++vcpu->stat.tlb_flush;
2512 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2513}
2514
2515static void record_steal_time(struct kvm_vcpu *vcpu)
2516{
2517 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2518 return;
2519
2520 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2521 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2522 return;
2523
2524 /*
2525 * Doing a TLB flush here, on the guest's behalf, can avoid
2526 * expensive IPIs.
2527 */
2528 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2529 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
2530 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2531 kvm_vcpu_flush_tlb(vcpu, false);
2532
2533 if (vcpu->arch.st.steal.version & 1)
2534 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2535
2536 vcpu->arch.st.steal.version += 1;
2537
2538 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2539 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2540
2541 smp_wmb();
2542
2543 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2544 vcpu->arch.st.last_steal;
2545 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2546
2547 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2548 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2549
2550 smp_wmb();
2551
2552 vcpu->arch.st.steal.version += 1;
2553
2554 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2555 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2556}
2557
2558int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2559{
2560 bool pr = false;
2561 u32 msr = msr_info->index;
2562 u64 data = msr_info->data;
2563
2564 switch (msr) {
2565 case MSR_AMD64_NB_CFG:
2566 case MSR_IA32_UCODE_WRITE:
2567 case MSR_VM_HSAVE_PA:
2568 case MSR_AMD64_PATCH_LOADER:
2569 case MSR_AMD64_BU_CFG2:
2570 case MSR_AMD64_DC_CFG:
2571 case MSR_F15H_EX_CFG:
2572 break;
2573
2574 case MSR_IA32_UCODE_REV:
2575 if (msr_info->host_initiated)
2576 vcpu->arch.microcode_version = data;
2577 break;
2578 case MSR_IA32_ARCH_CAPABILITIES:
2579 if (!msr_info->host_initiated)
2580 return 1;
2581 vcpu->arch.arch_capabilities = data;
2582 break;
2583 case MSR_EFER:
2584 return set_efer(vcpu, msr_info);
2585 case MSR_K7_HWCR:
2586 data &= ~(u64)0x40; /* ignore flush filter disable */
2587 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2588 data &= ~(u64)0x8; /* ignore TLB cache disable */
2589
2590 /* Handle McStatusWrEn */
2591 if (data == BIT_ULL(18)) {
2592 vcpu->arch.msr_hwcr = data;
2593 } else if (data != 0) {
2594 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2595 data);
2596 return 1;
2597 }
2598 break;
2599 case MSR_FAM10H_MMIO_CONF_BASE:
2600 if (data != 0) {
2601 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2602 "0x%llx\n", data);
2603 return 1;
2604 }
2605 break;
2606 case MSR_IA32_DEBUGCTLMSR:
2607 if (!data) {
2608 /* We support the non-activated case already */
2609 break;
2610 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2611 /* Values other than LBR and BTF are vendor-specific,
2612 thus reserved and should throw a #GP */
2613 return 1;
2614 }
2615 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2616 __func__, data);
2617 break;
2618 case 0x200 ... 0x2ff:
2619 return kvm_mtrr_set_msr(vcpu, msr, data);
2620 case MSR_IA32_APICBASE:
2621 return kvm_set_apic_base(vcpu, msr_info);
2622 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2623 return kvm_x2apic_msr_write(vcpu, msr, data);
2624 case MSR_IA32_TSCDEADLINE:
2625 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2626 break;
2627 case MSR_IA32_TSC_ADJUST:
2628 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2629 if (!msr_info->host_initiated) {
2630 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2631 adjust_tsc_offset_guest(vcpu, adj);
2632 }
2633 vcpu->arch.ia32_tsc_adjust_msr = data;
2634 }
2635 break;
2636 case MSR_IA32_MISC_ENABLE:
2637 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2638 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2639 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2640 return 1;
2641 vcpu->arch.ia32_misc_enable_msr = data;
2642 kvm_update_cpuid(vcpu);
2643 } else {
2644 vcpu->arch.ia32_misc_enable_msr = data;
2645 }
2646 break;
2647 case MSR_IA32_SMBASE:
2648 if (!msr_info->host_initiated)
2649 return 1;
2650 vcpu->arch.smbase = data;
2651 break;
2652 case MSR_IA32_POWER_CTL:
2653 vcpu->arch.msr_ia32_power_ctl = data;
2654 break;
2655 case MSR_IA32_TSC:
2656 kvm_write_tsc(vcpu, msr_info);
2657 break;
2658 case MSR_SMI_COUNT:
2659 if (!msr_info->host_initiated)
2660 return 1;
2661 vcpu->arch.smi_count = data;
2662 break;
2663 case MSR_KVM_WALL_CLOCK_NEW:
2664 case MSR_KVM_WALL_CLOCK:
2665 vcpu->kvm->arch.wall_clock = data;
2666 kvm_write_wall_clock(vcpu->kvm, data);
2667 break;
2668 case MSR_KVM_SYSTEM_TIME_NEW:
2669 case MSR_KVM_SYSTEM_TIME: {
2670 struct kvm_arch *ka = &vcpu->kvm->arch;
2671
2672 kvmclock_reset(vcpu);
2673
2674 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2675 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2676
2677 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2678 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2679
2680 ka->boot_vcpu_runs_old_kvmclock = tmp;
2681 }
2682
2683 vcpu->arch.time = data;
2684 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2685
2686 /* we verify if the enable bit is set... */
2687 if (!(data & 1))
2688 break;
2689
2690 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2691 &vcpu->arch.pv_time, data & ~1ULL,
2692 sizeof(struct pvclock_vcpu_time_info)))
2693 vcpu->arch.pv_time_enabled = false;
2694 else
2695 vcpu->arch.pv_time_enabled = true;
2696
2697 break;
2698 }
2699 case MSR_KVM_ASYNC_PF_EN:
2700 if (kvm_pv_enable_async_pf(vcpu, data))
2701 return 1;
2702 break;
2703 case MSR_KVM_STEAL_TIME:
2704
2705 if (unlikely(!sched_info_on()))
2706 return 1;
2707
2708 if (data & KVM_STEAL_RESERVED_MASK)
2709 return 1;
2710
2711 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2712 data & KVM_STEAL_VALID_BITS,
2713 sizeof(struct kvm_steal_time)))
2714 return 1;
2715
2716 vcpu->arch.st.msr_val = data;
2717
2718 if (!(data & KVM_MSR_ENABLED))
2719 break;
2720
2721 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2722
2723 break;
2724 case MSR_KVM_PV_EOI_EN:
2725 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2726 return 1;
2727 break;
2728
2729 case MSR_KVM_POLL_CONTROL:
2730 /* only enable bit supported */
2731 if (data & (-1ULL << 1))
2732 return 1;
2733
2734 vcpu->arch.msr_kvm_poll_control = data;
2735 break;
2736
2737 case MSR_IA32_MCG_CTL:
2738 case MSR_IA32_MCG_STATUS:
2739 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2740 return set_msr_mce(vcpu, msr_info);
2741
2742 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2743 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2744 pr = true; /* fall through */
2745 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2746 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2747 if (kvm_pmu_is_valid_msr(vcpu, msr))
2748 return kvm_pmu_set_msr(vcpu, msr_info);
2749
2750 if (pr || data != 0)
2751 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2752 "0x%x data 0x%llx\n", msr, data);
2753 break;
2754 case MSR_K7_CLK_CTL:
2755 /*
2756 * Ignore all writes to this no longer documented MSR.
2757 * Writes are only relevant for old K7 processors,
2758 * all pre-dating SVM, but a recommended workaround from
2759 * AMD for these chips. It is possible to specify the
2760 * affected processor models on the command line, hence
2761 * the need to ignore the workaround.
2762 */
2763 break;
2764 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2765 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2766 case HV_X64_MSR_CRASH_CTL:
2767 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2768 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2769 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2770 case HV_X64_MSR_TSC_EMULATION_STATUS:
2771 return kvm_hv_set_msr_common(vcpu, msr, data,
2772 msr_info->host_initiated);
2773 case MSR_IA32_BBL_CR_CTL3:
2774 /* Drop writes to this legacy MSR -- see rdmsr
2775 * counterpart for further detail.
2776 */
2777 if (report_ignored_msrs)
2778 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2779 msr, data);
2780 break;
2781 case MSR_AMD64_OSVW_ID_LENGTH:
2782 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2783 return 1;
2784 vcpu->arch.osvw.length = data;
2785 break;
2786 case MSR_AMD64_OSVW_STATUS:
2787 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2788 return 1;
2789 vcpu->arch.osvw.status = data;
2790 break;
2791 case MSR_PLATFORM_INFO:
2792 if (!msr_info->host_initiated ||
2793 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2794 cpuid_fault_enabled(vcpu)))
2795 return 1;
2796 vcpu->arch.msr_platform_info = data;
2797 break;
2798 case MSR_MISC_FEATURES_ENABLES:
2799 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2800 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2801 !supports_cpuid_fault(vcpu)))
2802 return 1;
2803 vcpu->arch.msr_misc_features_enables = data;
2804 break;
2805 default:
2806 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2807 return xen_hvm_config(vcpu, data);
2808 if (kvm_pmu_is_valid_msr(vcpu, msr))
2809 return kvm_pmu_set_msr(vcpu, msr_info);
2810 if (!ignore_msrs) {
2811 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2812 msr, data);
2813 return 1;
2814 } else {
2815 if (report_ignored_msrs)
2816 vcpu_unimpl(vcpu,
2817 "ignored wrmsr: 0x%x data 0x%llx\n",
2818 msr, data);
2819 break;
2820 }
2821 }
2822 return 0;
2823}
2824EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2825
2826static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2827{
2828 u64 data;
2829 u64 mcg_cap = vcpu->arch.mcg_cap;
2830 unsigned bank_num = mcg_cap & 0xff;
2831
2832 switch (msr) {
2833 case MSR_IA32_P5_MC_ADDR:
2834 case MSR_IA32_P5_MC_TYPE:
2835 data = 0;
2836 break;
2837 case MSR_IA32_MCG_CAP:
2838 data = vcpu->arch.mcg_cap;
2839 break;
2840 case MSR_IA32_MCG_CTL:
2841 if (!(mcg_cap & MCG_CTL_P) && !host)
2842 return 1;
2843 data = vcpu->arch.mcg_ctl;
2844 break;
2845 case MSR_IA32_MCG_STATUS:
2846 data = vcpu->arch.mcg_status;
2847 break;
2848 default:
2849 if (msr >= MSR_IA32_MC0_CTL &&
2850 msr < MSR_IA32_MCx_CTL(bank_num)) {
2851 u32 offset = msr - MSR_IA32_MC0_CTL;
2852 data = vcpu->arch.mce_banks[offset];
2853 break;
2854 }
2855 return 1;
2856 }
2857 *pdata = data;
2858 return 0;
2859}
2860
2861int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2862{
2863 switch (msr_info->index) {
2864 case MSR_IA32_PLATFORM_ID:
2865 case MSR_IA32_EBL_CR_POWERON:
2866 case MSR_IA32_DEBUGCTLMSR:
2867 case MSR_IA32_LASTBRANCHFROMIP:
2868 case MSR_IA32_LASTBRANCHTOIP:
2869 case MSR_IA32_LASTINTFROMIP:
2870 case MSR_IA32_LASTINTTOIP:
2871 case MSR_K8_SYSCFG:
2872 case MSR_K8_TSEG_ADDR:
2873 case MSR_K8_TSEG_MASK:
2874 case MSR_VM_HSAVE_PA:
2875 case MSR_K8_INT_PENDING_MSG:
2876 case MSR_AMD64_NB_CFG:
2877 case MSR_FAM10H_MMIO_CONF_BASE:
2878 case MSR_AMD64_BU_CFG2:
2879 case MSR_IA32_PERF_CTL:
2880 case MSR_AMD64_DC_CFG:
2881 case MSR_F15H_EX_CFG:
2882 msr_info->data = 0;
2883 break;
2884 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2885 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2886 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2887 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2888 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2889 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2890 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2891 msr_info->data = 0;
2892 break;
2893 case MSR_IA32_UCODE_REV:
2894 msr_info->data = vcpu->arch.microcode_version;
2895 break;
2896 case MSR_IA32_ARCH_CAPABILITIES:
2897 if (!msr_info->host_initiated &&
2898 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2899 return 1;
2900 msr_info->data = vcpu->arch.arch_capabilities;
2901 break;
2902 case MSR_IA32_POWER_CTL:
2903 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2904 break;
2905 case MSR_IA32_TSC:
2906 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2907 break;
2908 case MSR_MTRRcap:
2909 case 0x200 ... 0x2ff:
2910 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2911 case 0xcd: /* fsb frequency */
2912 msr_info->data = 3;
2913 break;
2914 /*
2915 * MSR_EBC_FREQUENCY_ID
2916 * Conservative value valid for even the basic CPU models.
2917 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2918 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2919 * and 266MHz for model 3, or 4. Set Core Clock
2920 * Frequency to System Bus Frequency Ratio to 1 (bits
2921 * 31:24) even though these are only valid for CPU
2922 * models > 2, however guests may end up dividing or
2923 * multiplying by zero otherwise.
2924 */
2925 case MSR_EBC_FREQUENCY_ID:
2926 msr_info->data = 1 << 24;
2927 break;
2928 case MSR_IA32_APICBASE:
2929 msr_info->data = kvm_get_apic_base(vcpu);
2930 break;
2931 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2932 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2933 break;
2934 case MSR_IA32_TSCDEADLINE:
2935 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2936 break;
2937 case MSR_IA32_TSC_ADJUST:
2938 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2939 break;
2940 case MSR_IA32_MISC_ENABLE:
2941 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2942 break;
2943 case MSR_IA32_SMBASE:
2944 if (!msr_info->host_initiated)
2945 return 1;
2946 msr_info->data = vcpu->arch.smbase;
2947 break;
2948 case MSR_SMI_COUNT:
2949 msr_info->data = vcpu->arch.smi_count;
2950 break;
2951 case MSR_IA32_PERF_STATUS:
2952 /* TSC increment by tick */
2953 msr_info->data = 1000ULL;
2954 /* CPU multiplier */
2955 msr_info->data |= (((uint64_t)4ULL) << 40);
2956 break;
2957 case MSR_EFER:
2958 msr_info->data = vcpu->arch.efer;
2959 break;
2960 case MSR_KVM_WALL_CLOCK:
2961 case MSR_KVM_WALL_CLOCK_NEW:
2962 msr_info->data = vcpu->kvm->arch.wall_clock;
2963 break;
2964 case MSR_KVM_SYSTEM_TIME:
2965 case MSR_KVM_SYSTEM_TIME_NEW:
2966 msr_info->data = vcpu->arch.time;
2967 break;
2968 case MSR_KVM_ASYNC_PF_EN:
2969 msr_info->data = vcpu->arch.apf.msr_val;
2970 break;
2971 case MSR_KVM_STEAL_TIME:
2972 msr_info->data = vcpu->arch.st.msr_val;
2973 break;
2974 case MSR_KVM_PV_EOI_EN:
2975 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2976 break;
2977 case MSR_KVM_POLL_CONTROL:
2978 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2979 break;
2980 case MSR_IA32_P5_MC_ADDR:
2981 case MSR_IA32_P5_MC_TYPE:
2982 case MSR_IA32_MCG_CAP:
2983 case MSR_IA32_MCG_CTL:
2984 case MSR_IA32_MCG_STATUS:
2985 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2986 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2987 msr_info->host_initiated);
2988 case MSR_K7_CLK_CTL:
2989 /*
2990 * Provide expected ramp-up count for K7. All other
2991 * are set to zero, indicating minimum divisors for
2992 * every field.
2993 *
2994 * This prevents guest kernels on AMD host with CPU
2995 * type 6, model 8 and higher from exploding due to
2996 * the rdmsr failing.
2997 */
2998 msr_info->data = 0x20000000;
2999 break;
3000 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3001 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3002 case HV_X64_MSR_CRASH_CTL:
3003 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3004 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3005 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3006 case HV_X64_MSR_TSC_EMULATION_STATUS:
3007 return kvm_hv_get_msr_common(vcpu,
3008 msr_info->index, &msr_info->data,
3009 msr_info->host_initiated);
3010 break;
3011 case MSR_IA32_BBL_CR_CTL3:
3012 /* This legacy MSR exists but isn't fully documented in current
3013 * silicon. It is however accessed by winxp in very narrow
3014 * scenarios where it sets bit #19, itself documented as
3015 * a "reserved" bit. Best effort attempt to source coherent
3016 * read data here should the balance of the register be
3017 * interpreted by the guest:
3018 *
3019 * L2 cache control register 3: 64GB range, 256KB size,
3020 * enabled, latency 0x1, configured
3021 */
3022 msr_info->data = 0xbe702111;
3023 break;
3024 case MSR_AMD64_OSVW_ID_LENGTH:
3025 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3026 return 1;
3027 msr_info->data = vcpu->arch.osvw.length;
3028 break;
3029 case MSR_AMD64_OSVW_STATUS:
3030 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3031 return 1;
3032 msr_info->data = vcpu->arch.osvw.status;
3033 break;
3034 case MSR_PLATFORM_INFO:
3035 if (!msr_info->host_initiated &&
3036 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3037 return 1;
3038 msr_info->data = vcpu->arch.msr_platform_info;
3039 break;
3040 case MSR_MISC_FEATURES_ENABLES:
3041 msr_info->data = vcpu->arch.msr_misc_features_enables;
3042 break;
3043 case MSR_K7_HWCR:
3044 msr_info->data = vcpu->arch.msr_hwcr;
3045 break;
3046 default:
3047 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3048 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3049 if (!ignore_msrs) {
3050 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3051 msr_info->index);
3052 return 1;
3053 } else {
3054 if (report_ignored_msrs)
3055 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3056 msr_info->index);
3057 msr_info->data = 0;
3058 }
3059 break;
3060 }
3061 return 0;
3062}
3063EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3064
3065/*
3066 * Read or write a bunch of msrs. All parameters are kernel addresses.
3067 *
3068 * @return number of msrs set successfully.
3069 */
3070static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3071 struct kvm_msr_entry *entries,
3072 int (*do_msr)(struct kvm_vcpu *vcpu,
3073 unsigned index, u64 *data))
3074{
3075 int i;
3076
3077 for (i = 0; i < msrs->nmsrs; ++i)
3078 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3079 break;
3080
3081 return i;
3082}
3083
3084/*
3085 * Read or write a bunch of msrs. Parameters are user addresses.
3086 *
3087 * @return number of msrs set successfully.
3088 */
3089static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3090 int (*do_msr)(struct kvm_vcpu *vcpu,
3091 unsigned index, u64 *data),
3092 int writeback)
3093{
3094 struct kvm_msrs msrs;
3095 struct kvm_msr_entry *entries;
3096 int r, n;
3097 unsigned size;
3098
3099 r = -EFAULT;
3100 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3101 goto out;
3102
3103 r = -E2BIG;
3104 if (msrs.nmsrs >= MAX_IO_MSRS)
3105 goto out;
3106
3107 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3108 entries = memdup_user(user_msrs->entries, size);
3109 if (IS_ERR(entries)) {
3110 r = PTR_ERR(entries);
3111 goto out;
3112 }
3113
3114 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3115 if (r < 0)
3116 goto out_free;
3117
3118 r = -EFAULT;
3119 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3120 goto out_free;
3121
3122 r = n;
3123
3124out_free:
3125 kfree(entries);
3126out:
3127 return r;
3128}
3129
3130static inline bool kvm_can_mwait_in_guest(void)
3131{
3132 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3133 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3134 boot_cpu_has(X86_FEATURE_ARAT);
3135}
3136
3137int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3138{
3139 int r = 0;
3140
3141 switch (ext) {
3142 case KVM_CAP_IRQCHIP:
3143 case KVM_CAP_HLT:
3144 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3145 case KVM_CAP_SET_TSS_ADDR:
3146 case KVM_CAP_EXT_CPUID:
3147 case KVM_CAP_EXT_EMUL_CPUID:
3148 case KVM_CAP_CLOCKSOURCE:
3149 case KVM_CAP_PIT:
3150 case KVM_CAP_NOP_IO_DELAY:
3151 case KVM_CAP_MP_STATE:
3152 case KVM_CAP_SYNC_MMU:
3153 case KVM_CAP_USER_NMI:
3154 case KVM_CAP_REINJECT_CONTROL:
3155 case KVM_CAP_IRQ_INJECT_STATUS:
3156 case KVM_CAP_IOEVENTFD:
3157 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3158 case KVM_CAP_PIT2:
3159 case KVM_CAP_PIT_STATE2:
3160 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3161 case KVM_CAP_XEN_HVM:
3162 case KVM_CAP_VCPU_EVENTS:
3163 case KVM_CAP_HYPERV:
3164 case KVM_CAP_HYPERV_VAPIC:
3165 case KVM_CAP_HYPERV_SPIN:
3166 case KVM_CAP_HYPERV_SYNIC:
3167 case KVM_CAP_HYPERV_SYNIC2:
3168 case KVM_CAP_HYPERV_VP_INDEX:
3169 case KVM_CAP_HYPERV_EVENTFD:
3170 case KVM_CAP_HYPERV_TLBFLUSH:
3171 case KVM_CAP_HYPERV_SEND_IPI:
3172 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3173 case KVM_CAP_HYPERV_CPUID:
3174 case KVM_CAP_PCI_SEGMENT:
3175 case KVM_CAP_DEBUGREGS:
3176 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3177 case KVM_CAP_XSAVE:
3178 case KVM_CAP_ASYNC_PF:
3179 case KVM_CAP_GET_TSC_KHZ:
3180 case KVM_CAP_KVMCLOCK_CTRL:
3181 case KVM_CAP_READONLY_MEM:
3182 case KVM_CAP_HYPERV_TIME:
3183 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3184 case KVM_CAP_TSC_DEADLINE_TIMER:
3185 case KVM_CAP_DISABLE_QUIRKS:
3186 case KVM_CAP_SET_BOOT_CPU_ID:
3187 case KVM_CAP_SPLIT_IRQCHIP:
3188 case KVM_CAP_IMMEDIATE_EXIT:
3189 case KVM_CAP_PMU_EVENT_FILTER:
3190 case KVM_CAP_GET_MSR_FEATURES:
3191 case KVM_CAP_MSR_PLATFORM_INFO:
3192 case KVM_CAP_EXCEPTION_PAYLOAD:
3193 r = 1;
3194 break;
3195 case KVM_CAP_SYNC_REGS:
3196 r = KVM_SYNC_X86_VALID_FIELDS;
3197 break;
3198 case KVM_CAP_ADJUST_CLOCK:
3199 r = KVM_CLOCK_TSC_STABLE;
3200 break;
3201 case KVM_CAP_X86_DISABLE_EXITS:
3202 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3203 KVM_X86_DISABLE_EXITS_CSTATE;
3204 if(kvm_can_mwait_in_guest())
3205 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3206 break;
3207 case KVM_CAP_X86_SMM:
3208 /* SMBASE is usually relocated above 1M on modern chipsets,
3209 * and SMM handlers might indeed rely on 4G segment limits,
3210 * so do not report SMM to be available if real mode is
3211 * emulated via vm86 mode. Still, do not go to great lengths
3212 * to avoid userspace's usage of the feature, because it is a
3213 * fringe case that is not enabled except via specific settings
3214 * of the module parameters.
3215 */
3216 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3217 break;
3218 case KVM_CAP_VAPIC:
3219 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3220 break;
3221 case KVM_CAP_NR_VCPUS:
3222 r = KVM_SOFT_MAX_VCPUS;
3223 break;
3224 case KVM_CAP_MAX_VCPUS:
3225 r = KVM_MAX_VCPUS;
3226 break;
3227 case KVM_CAP_MAX_VCPU_ID:
3228 r = KVM_MAX_VCPU_ID;
3229 break;
3230 case KVM_CAP_PV_MMU: /* obsolete */
3231 r = 0;
3232 break;
3233 case KVM_CAP_MCE:
3234 r = KVM_MAX_MCE_BANKS;
3235 break;
3236 case KVM_CAP_XCRS:
3237 r = boot_cpu_has(X86_FEATURE_XSAVE);
3238 break;
3239 case KVM_CAP_TSC_CONTROL:
3240 r = kvm_has_tsc_control;
3241 break;
3242 case KVM_CAP_X2APIC_API:
3243 r = KVM_X2APIC_API_VALID_FLAGS;
3244 break;
3245 case KVM_CAP_NESTED_STATE:
3246 r = kvm_x86_ops->get_nested_state ?
3247 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3248 break;
3249 default:
3250 break;
3251 }
3252 return r;
3253
3254}
3255
3256long kvm_arch_dev_ioctl(struct file *filp,
3257 unsigned int ioctl, unsigned long arg)
3258{
3259 void __user *argp = (void __user *)arg;
3260 long r;
3261
3262 switch (ioctl) {
3263 case KVM_GET_MSR_INDEX_LIST: {
3264 struct kvm_msr_list __user *user_msr_list = argp;
3265 struct kvm_msr_list msr_list;
3266 unsigned n;
3267
3268 r = -EFAULT;
3269 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3270 goto out;
3271 n = msr_list.nmsrs;
3272 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3273 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3274 goto out;
3275 r = -E2BIG;
3276 if (n < msr_list.nmsrs)
3277 goto out;
3278 r = -EFAULT;
3279 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3280 num_msrs_to_save * sizeof(u32)))
3281 goto out;
3282 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3283 &emulated_msrs,
3284 num_emulated_msrs * sizeof(u32)))
3285 goto out;
3286 r = 0;
3287 break;
3288 }
3289 case KVM_GET_SUPPORTED_CPUID:
3290 case KVM_GET_EMULATED_CPUID: {
3291 struct kvm_cpuid2 __user *cpuid_arg = argp;
3292 struct kvm_cpuid2 cpuid;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3296 goto out;
3297
3298 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3299 ioctl);
3300 if (r)
3301 goto out;
3302
3303 r = -EFAULT;
3304 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3305 goto out;
3306 r = 0;
3307 break;
3308 }
3309 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3310 r = -EFAULT;
3311 if (copy_to_user(argp, &kvm_mce_cap_supported,
3312 sizeof(kvm_mce_cap_supported)))
3313 goto out;
3314 r = 0;
3315 break;
3316 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3317 struct kvm_msr_list __user *user_msr_list = argp;
3318 struct kvm_msr_list msr_list;
3319 unsigned int n;
3320
3321 r = -EFAULT;
3322 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3323 goto out;
3324 n = msr_list.nmsrs;
3325 msr_list.nmsrs = num_msr_based_features;
3326 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3327 goto out;
3328 r = -E2BIG;
3329 if (n < msr_list.nmsrs)
3330 goto out;
3331 r = -EFAULT;
3332 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3333 num_msr_based_features * sizeof(u32)))
3334 goto out;
3335 r = 0;
3336 break;
3337 }
3338 case KVM_GET_MSRS:
3339 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3340 break;
3341 }
3342 default:
3343 r = -EINVAL;
3344 }
3345out:
3346 return r;
3347}
3348
3349static void wbinvd_ipi(void *garbage)
3350{
3351 wbinvd();
3352}
3353
3354static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3355{
3356 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3357}
3358
3359void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3360{
3361 /* Address WBINVD may be executed by guest */
3362 if (need_emulate_wbinvd(vcpu)) {
3363 if (kvm_x86_ops->has_wbinvd_exit())
3364 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3365 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3366 smp_call_function_single(vcpu->cpu,
3367 wbinvd_ipi, NULL, 1);
3368 }
3369
3370 kvm_x86_ops->vcpu_load(vcpu, cpu);
3371
3372 fpregs_assert_state_consistent();
3373 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3374 switch_fpu_return();
3375
3376 /* Apply any externally detected TSC adjustments (due to suspend) */
3377 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3378 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3379 vcpu->arch.tsc_offset_adjustment = 0;
3380 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3381 }
3382
3383 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3384 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3385 rdtsc() - vcpu->arch.last_host_tsc;
3386 if (tsc_delta < 0)
3387 mark_tsc_unstable("KVM discovered backwards TSC");
3388
3389 if (kvm_check_tsc_unstable()) {
3390 u64 offset = kvm_compute_tsc_offset(vcpu,
3391 vcpu->arch.last_guest_tsc);
3392 kvm_vcpu_write_tsc_offset(vcpu, offset);
3393 vcpu->arch.tsc_catchup = 1;
3394 }
3395
3396 if (kvm_lapic_hv_timer_in_use(vcpu))
3397 kvm_lapic_restart_hv_timer(vcpu);
3398
3399 /*
3400 * On a host with synchronized TSC, there is no need to update
3401 * kvmclock on vcpu->cpu migration
3402 */
3403 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3404 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3405 if (vcpu->cpu != cpu)
3406 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3407 vcpu->cpu = cpu;
3408 }
3409
3410 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3411}
3412
3413static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3414{
3415 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3416 return;
3417
3418 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3419
3420 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3421 &vcpu->arch.st.steal.preempted,
3422 offsetof(struct kvm_steal_time, preempted),
3423 sizeof(vcpu->arch.st.steal.preempted));
3424}
3425
3426void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3427{
3428 int idx;
3429
3430 if (vcpu->preempted)
3431 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3432
3433 /*
3434 * Disable page faults because we're in atomic context here.
3435 * kvm_write_guest_offset_cached() would call might_fault()
3436 * that relies on pagefault_disable() to tell if there's a
3437 * bug. NOTE: the write to guest memory may not go through if
3438 * during postcopy live migration or if there's heavy guest
3439 * paging.
3440 */
3441 pagefault_disable();
3442 /*
3443 * kvm_memslots() will be called by
3444 * kvm_write_guest_offset_cached() so take the srcu lock.
3445 */
3446 idx = srcu_read_lock(&vcpu->kvm->srcu);
3447 kvm_steal_time_set_preempted(vcpu);
3448 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3449 pagefault_enable();
3450 kvm_x86_ops->vcpu_put(vcpu);
3451 vcpu->arch.last_host_tsc = rdtsc();
3452 /*
3453 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3454 * on every vmexit, but if not, we might have a stale dr6 from the
3455 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3456 */
3457 set_debugreg(0, 6);
3458}
3459
3460static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3461 struct kvm_lapic_state *s)
3462{
3463 if (vcpu->arch.apicv_active)
3464 kvm_x86_ops->sync_pir_to_irr(vcpu);
3465
3466 return kvm_apic_get_state(vcpu, s);
3467}
3468
3469static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3470 struct kvm_lapic_state *s)
3471{
3472 int r;
3473
3474 r = kvm_apic_set_state(vcpu, s);
3475 if (r)
3476 return r;
3477 update_cr8_intercept(vcpu);
3478
3479 return 0;
3480}
3481
3482static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3483{
3484 return (!lapic_in_kernel(vcpu) ||
3485 kvm_apic_accept_pic_intr(vcpu));
3486}
3487
3488/*
3489 * if userspace requested an interrupt window, check that the
3490 * interrupt window is open.
3491 *
3492 * No need to exit to userspace if we already have an interrupt queued.
3493 */
3494static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3495{
3496 return kvm_arch_interrupt_allowed(vcpu) &&
3497 !kvm_cpu_has_interrupt(vcpu) &&
3498 !kvm_event_needs_reinjection(vcpu) &&
3499 kvm_cpu_accept_dm_intr(vcpu);
3500}
3501
3502static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3503 struct kvm_interrupt *irq)
3504{
3505 if (irq->irq >= KVM_NR_INTERRUPTS)
3506 return -EINVAL;
3507
3508 if (!irqchip_in_kernel(vcpu->kvm)) {
3509 kvm_queue_interrupt(vcpu, irq->irq, false);
3510 kvm_make_request(KVM_REQ_EVENT, vcpu);
3511 return 0;
3512 }
3513
3514 /*
3515 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3516 * fail for in-kernel 8259.
3517 */
3518 if (pic_in_kernel(vcpu->kvm))
3519 return -ENXIO;
3520
3521 if (vcpu->arch.pending_external_vector != -1)
3522 return -EEXIST;
3523
3524 vcpu->arch.pending_external_vector = irq->irq;
3525 kvm_make_request(KVM_REQ_EVENT, vcpu);
3526 return 0;
3527}
3528
3529static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3530{
3531 kvm_inject_nmi(vcpu);
3532
3533 return 0;
3534}
3535
3536static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3537{
3538 kvm_make_request(KVM_REQ_SMI, vcpu);
3539
3540 return 0;
3541}
3542
3543static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3544 struct kvm_tpr_access_ctl *tac)
3545{
3546 if (tac->flags)
3547 return -EINVAL;
3548 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3549 return 0;
3550}
3551
3552static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3553 u64 mcg_cap)
3554{
3555 int r;
3556 unsigned bank_num = mcg_cap & 0xff, bank;
3557
3558 r = -EINVAL;
3559 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3560 goto out;
3561 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3562 goto out;
3563 r = 0;
3564 vcpu->arch.mcg_cap = mcg_cap;
3565 /* Init IA32_MCG_CTL to all 1s */
3566 if (mcg_cap & MCG_CTL_P)
3567 vcpu->arch.mcg_ctl = ~(u64)0;
3568 /* Init IA32_MCi_CTL to all 1s */
3569 for (bank = 0; bank < bank_num; bank++)
3570 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3571
3572 kvm_x86_ops->setup_mce(vcpu);
3573out:
3574 return r;
3575}
3576
3577static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3578 struct kvm_x86_mce *mce)
3579{
3580 u64 mcg_cap = vcpu->arch.mcg_cap;
3581 unsigned bank_num = mcg_cap & 0xff;
3582 u64 *banks = vcpu->arch.mce_banks;
3583
3584 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3585 return -EINVAL;
3586 /*
3587 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3588 * reporting is disabled
3589 */
3590 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3591 vcpu->arch.mcg_ctl != ~(u64)0)
3592 return 0;
3593 banks += 4 * mce->bank;
3594 /*
3595 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3596 * reporting is disabled for the bank
3597 */
3598 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3599 return 0;
3600 if (mce->status & MCI_STATUS_UC) {
3601 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3602 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3603 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3604 return 0;
3605 }
3606 if (banks[1] & MCI_STATUS_VAL)
3607 mce->status |= MCI_STATUS_OVER;
3608 banks[2] = mce->addr;
3609 banks[3] = mce->misc;
3610 vcpu->arch.mcg_status = mce->mcg_status;
3611 banks[1] = mce->status;
3612 kvm_queue_exception(vcpu, MC_VECTOR);
3613 } else if (!(banks[1] & MCI_STATUS_VAL)
3614 || !(banks[1] & MCI_STATUS_UC)) {
3615 if (banks[1] & MCI_STATUS_VAL)
3616 mce->status |= MCI_STATUS_OVER;
3617 banks[2] = mce->addr;
3618 banks[3] = mce->misc;
3619 banks[1] = mce->status;
3620 } else
3621 banks[1] |= MCI_STATUS_OVER;
3622 return 0;
3623}
3624
3625static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3626 struct kvm_vcpu_events *events)
3627{
3628 process_nmi(vcpu);
3629
3630 /*
3631 * The API doesn't provide the instruction length for software
3632 * exceptions, so don't report them. As long as the guest RIP
3633 * isn't advanced, we should expect to encounter the exception
3634 * again.
3635 */
3636 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3637 events->exception.injected = 0;
3638 events->exception.pending = 0;
3639 } else {
3640 events->exception.injected = vcpu->arch.exception.injected;
3641 events->exception.pending = vcpu->arch.exception.pending;
3642 /*
3643 * For ABI compatibility, deliberately conflate
3644 * pending and injected exceptions when
3645 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3646 */
3647 if (!vcpu->kvm->arch.exception_payload_enabled)
3648 events->exception.injected |=
3649 vcpu->arch.exception.pending;
3650 }
3651 events->exception.nr = vcpu->arch.exception.nr;
3652 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3653 events->exception.error_code = vcpu->arch.exception.error_code;
3654 events->exception_has_payload = vcpu->arch.exception.has_payload;
3655 events->exception_payload = vcpu->arch.exception.payload;
3656
3657 events->interrupt.injected =
3658 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3659 events->interrupt.nr = vcpu->arch.interrupt.nr;
3660 events->interrupt.soft = 0;
3661 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3662
3663 events->nmi.injected = vcpu->arch.nmi_injected;
3664 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3665 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3666 events->nmi.pad = 0;
3667
3668 events->sipi_vector = 0; /* never valid when reporting to user space */
3669
3670 events->smi.smm = is_smm(vcpu);
3671 events->smi.pending = vcpu->arch.smi_pending;
3672 events->smi.smm_inside_nmi =
3673 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3674 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3675
3676 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3677 | KVM_VCPUEVENT_VALID_SHADOW
3678 | KVM_VCPUEVENT_VALID_SMM);
3679 if (vcpu->kvm->arch.exception_payload_enabled)
3680 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3681
3682 memset(&events->reserved, 0, sizeof(events->reserved));
3683}
3684
3685static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3686
3687static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3688 struct kvm_vcpu_events *events)
3689{
3690 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3691 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3692 | KVM_VCPUEVENT_VALID_SHADOW
3693 | KVM_VCPUEVENT_VALID_SMM
3694 | KVM_VCPUEVENT_VALID_PAYLOAD))
3695 return -EINVAL;
3696
3697 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3698 if (!vcpu->kvm->arch.exception_payload_enabled)
3699 return -EINVAL;
3700 if (events->exception.pending)
3701 events->exception.injected = 0;
3702 else
3703 events->exception_has_payload = 0;
3704 } else {
3705 events->exception.pending = 0;
3706 events->exception_has_payload = 0;
3707 }
3708
3709 if ((events->exception.injected || events->exception.pending) &&
3710 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3711 return -EINVAL;
3712
3713 /* INITs are latched while in SMM */
3714 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3715 (events->smi.smm || events->smi.pending) &&
3716 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3717 return -EINVAL;
3718
3719 process_nmi(vcpu);
3720 vcpu->arch.exception.injected = events->exception.injected;
3721 vcpu->arch.exception.pending = events->exception.pending;
3722 vcpu->arch.exception.nr = events->exception.nr;
3723 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3724 vcpu->arch.exception.error_code = events->exception.error_code;
3725 vcpu->arch.exception.has_payload = events->exception_has_payload;
3726 vcpu->arch.exception.payload = events->exception_payload;
3727
3728 vcpu->arch.interrupt.injected = events->interrupt.injected;
3729 vcpu->arch.interrupt.nr = events->interrupt.nr;
3730 vcpu->arch.interrupt.soft = events->interrupt.soft;
3731 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3732 kvm_x86_ops->set_interrupt_shadow(vcpu,
3733 events->interrupt.shadow);
3734
3735 vcpu->arch.nmi_injected = events->nmi.injected;
3736 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3737 vcpu->arch.nmi_pending = events->nmi.pending;
3738 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3739
3740 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3741 lapic_in_kernel(vcpu))
3742 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3743
3744 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3745 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3746 if (events->smi.smm)
3747 vcpu->arch.hflags |= HF_SMM_MASK;
3748 else
3749 vcpu->arch.hflags &= ~HF_SMM_MASK;
3750 kvm_smm_changed(vcpu);
3751 }
3752
3753 vcpu->arch.smi_pending = events->smi.pending;
3754
3755 if (events->smi.smm) {
3756 if (events->smi.smm_inside_nmi)
3757 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3758 else
3759 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3760 if (lapic_in_kernel(vcpu)) {
3761 if (events->smi.latched_init)
3762 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3763 else
3764 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3765 }
3766 }
3767 }
3768
3769 kvm_make_request(KVM_REQ_EVENT, vcpu);
3770
3771 return 0;
3772}
3773
3774static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3775 struct kvm_debugregs *dbgregs)
3776{
3777 unsigned long val;
3778
3779 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3780 kvm_get_dr(vcpu, 6, &val);
3781 dbgregs->dr6 = val;
3782 dbgregs->dr7 = vcpu->arch.dr7;
3783 dbgregs->flags = 0;
3784 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3785}
3786
3787static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3788 struct kvm_debugregs *dbgregs)
3789{
3790 if (dbgregs->flags)
3791 return -EINVAL;
3792
3793 if (dbgregs->dr6 & ~0xffffffffull)
3794 return -EINVAL;
3795 if (dbgregs->dr7 & ~0xffffffffull)
3796 return -EINVAL;
3797
3798 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3799 kvm_update_dr0123(vcpu);
3800 vcpu->arch.dr6 = dbgregs->dr6;
3801 kvm_update_dr6(vcpu);
3802 vcpu->arch.dr7 = dbgregs->dr7;
3803 kvm_update_dr7(vcpu);
3804
3805 return 0;
3806}
3807
3808#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3809
3810static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3811{
3812 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3813 u64 xstate_bv = xsave->header.xfeatures;
3814 u64 valid;
3815
3816 /*
3817 * Copy legacy XSAVE area, to avoid complications with CPUID
3818 * leaves 0 and 1 in the loop below.
3819 */
3820 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3821
3822 /* Set XSTATE_BV */
3823 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3824 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3825
3826 /*
3827 * Copy each region from the possibly compacted offset to the
3828 * non-compacted offset.
3829 */
3830 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3831 while (valid) {
3832 u64 xfeature_mask = valid & -valid;
3833 int xfeature_nr = fls64(xfeature_mask) - 1;
3834 void *src = get_xsave_addr(xsave, xfeature_nr);
3835
3836 if (src) {
3837 u32 size, offset, ecx, edx;
3838 cpuid_count(XSTATE_CPUID, xfeature_nr,
3839 &size, &offset, &ecx, &edx);
3840 if (xfeature_nr == XFEATURE_PKRU)
3841 memcpy(dest + offset, &vcpu->arch.pkru,
3842 sizeof(vcpu->arch.pkru));
3843 else
3844 memcpy(dest + offset, src, size);
3845
3846 }
3847
3848 valid -= xfeature_mask;
3849 }
3850}
3851
3852static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3853{
3854 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3855 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3856 u64 valid;
3857
3858 /*
3859 * Copy legacy XSAVE area, to avoid complications with CPUID
3860 * leaves 0 and 1 in the loop below.
3861 */
3862 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3863
3864 /* Set XSTATE_BV and possibly XCOMP_BV. */
3865 xsave->header.xfeatures = xstate_bv;
3866 if (boot_cpu_has(X86_FEATURE_XSAVES))
3867 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3868
3869 /*
3870 * Copy each region from the non-compacted offset to the
3871 * possibly compacted offset.
3872 */
3873 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3874 while (valid) {
3875 u64 xfeature_mask = valid & -valid;
3876 int xfeature_nr = fls64(xfeature_mask) - 1;
3877 void *dest = get_xsave_addr(xsave, xfeature_nr);
3878
3879 if (dest) {
3880 u32 size, offset, ecx, edx;
3881 cpuid_count(XSTATE_CPUID, xfeature_nr,
3882 &size, &offset, &ecx, &edx);
3883 if (xfeature_nr == XFEATURE_PKRU)
3884 memcpy(&vcpu->arch.pkru, src + offset,
3885 sizeof(vcpu->arch.pkru));
3886 else
3887 memcpy(dest, src + offset, size);
3888 }
3889
3890 valid -= xfeature_mask;
3891 }
3892}
3893
3894static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3895 struct kvm_xsave *guest_xsave)
3896{
3897 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3898 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3899 fill_xsave((u8 *) guest_xsave->region, vcpu);
3900 } else {
3901 memcpy(guest_xsave->region,
3902 &vcpu->arch.guest_fpu->state.fxsave,
3903 sizeof(struct fxregs_state));
3904 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3905 XFEATURE_MASK_FPSSE;
3906 }
3907}
3908
3909#define XSAVE_MXCSR_OFFSET 24
3910
3911static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3912 struct kvm_xsave *guest_xsave)
3913{
3914 u64 xstate_bv =
3915 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3916 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3917
3918 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3919 /*
3920 * Here we allow setting states that are not present in
3921 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3922 * with old userspace.
3923 */
3924 if (xstate_bv & ~kvm_supported_xcr0() ||
3925 mxcsr & ~mxcsr_feature_mask)
3926 return -EINVAL;
3927 load_xsave(vcpu, (u8 *)guest_xsave->region);
3928 } else {
3929 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3930 mxcsr & ~mxcsr_feature_mask)
3931 return -EINVAL;
3932 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3933 guest_xsave->region, sizeof(struct fxregs_state));
3934 }
3935 return 0;
3936}
3937
3938static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3939 struct kvm_xcrs *guest_xcrs)
3940{
3941 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3942 guest_xcrs->nr_xcrs = 0;
3943 return;
3944 }
3945
3946 guest_xcrs->nr_xcrs = 1;
3947 guest_xcrs->flags = 0;
3948 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3949 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3950}
3951
3952static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3953 struct kvm_xcrs *guest_xcrs)
3954{
3955 int i, r = 0;
3956
3957 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3958 return -EINVAL;
3959
3960 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3961 return -EINVAL;
3962
3963 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3964 /* Only support XCR0 currently */
3965 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3966 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3967 guest_xcrs->xcrs[i].value);
3968 break;
3969 }
3970 if (r)
3971 r = -EINVAL;
3972 return r;
3973}
3974
3975/*
3976 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3977 * stopped by the hypervisor. This function will be called from the host only.
3978 * EINVAL is returned when the host attempts to set the flag for a guest that
3979 * does not support pv clocks.
3980 */
3981static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3982{
3983 if (!vcpu->arch.pv_time_enabled)
3984 return -EINVAL;
3985 vcpu->arch.pvclock_set_guest_stopped_request = true;
3986 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3987 return 0;
3988}
3989
3990static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3991 struct kvm_enable_cap *cap)
3992{
3993 int r;
3994 uint16_t vmcs_version;
3995 void __user *user_ptr;
3996
3997 if (cap->flags)
3998 return -EINVAL;
3999
4000 switch (cap->cap) {
4001 case KVM_CAP_HYPERV_SYNIC2:
4002 if (cap->args[0])
4003 return -EINVAL;
4004 /* fall through */
4005
4006 case KVM_CAP_HYPERV_SYNIC:
4007 if (!irqchip_in_kernel(vcpu->kvm))
4008 return -EINVAL;
4009 return kvm_hv_activate_synic(vcpu, cap->cap ==
4010 KVM_CAP_HYPERV_SYNIC2);
4011 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4012 if (!kvm_x86_ops->nested_enable_evmcs)
4013 return -ENOTTY;
4014 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4015 if (!r) {
4016 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4017 if (copy_to_user(user_ptr, &vmcs_version,
4018 sizeof(vmcs_version)))
4019 r = -EFAULT;
4020 }
4021 return r;
4022
4023 default:
4024 return -EINVAL;
4025 }
4026}
4027
4028long kvm_arch_vcpu_ioctl(struct file *filp,
4029 unsigned int ioctl, unsigned long arg)
4030{
4031 struct kvm_vcpu *vcpu = filp->private_data;
4032 void __user *argp = (void __user *)arg;
4033 int r;
4034 union {
4035 struct kvm_lapic_state *lapic;
4036 struct kvm_xsave *xsave;
4037 struct kvm_xcrs *xcrs;
4038 void *buffer;
4039 } u;
4040
4041 vcpu_load(vcpu);
4042
4043 u.buffer = NULL;
4044 switch (ioctl) {
4045 case KVM_GET_LAPIC: {
4046 r = -EINVAL;
4047 if (!lapic_in_kernel(vcpu))
4048 goto out;
4049 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4050 GFP_KERNEL_ACCOUNT);
4051
4052 r = -ENOMEM;
4053 if (!u.lapic)
4054 goto out;
4055 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4056 if (r)
4057 goto out;
4058 r = -EFAULT;
4059 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4060 goto out;
4061 r = 0;
4062 break;
4063 }
4064 case KVM_SET_LAPIC: {
4065 r = -EINVAL;
4066 if (!lapic_in_kernel(vcpu))
4067 goto out;
4068 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4069 if (IS_ERR(u.lapic)) {
4070 r = PTR_ERR(u.lapic);
4071 goto out_nofree;
4072 }
4073
4074 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4075 break;
4076 }
4077 case KVM_INTERRUPT: {
4078 struct kvm_interrupt irq;
4079
4080 r = -EFAULT;
4081 if (copy_from_user(&irq, argp, sizeof(irq)))
4082 goto out;
4083 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4084 break;
4085 }
4086 case KVM_NMI: {
4087 r = kvm_vcpu_ioctl_nmi(vcpu);
4088 break;
4089 }
4090 case KVM_SMI: {
4091 r = kvm_vcpu_ioctl_smi(vcpu);
4092 break;
4093 }
4094 case KVM_SET_CPUID: {
4095 struct kvm_cpuid __user *cpuid_arg = argp;
4096 struct kvm_cpuid cpuid;
4097
4098 r = -EFAULT;
4099 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4100 goto out;
4101 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4102 break;
4103 }
4104 case KVM_SET_CPUID2: {
4105 struct kvm_cpuid2 __user *cpuid_arg = argp;
4106 struct kvm_cpuid2 cpuid;
4107
4108 r = -EFAULT;
4109 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4110 goto out;
4111 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4112 cpuid_arg->entries);
4113 break;
4114 }
4115 case KVM_GET_CPUID2: {
4116 struct kvm_cpuid2 __user *cpuid_arg = argp;
4117 struct kvm_cpuid2 cpuid;
4118
4119 r = -EFAULT;
4120 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4121 goto out;
4122 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4123 cpuid_arg->entries);
4124 if (r)
4125 goto out;
4126 r = -EFAULT;
4127 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4128 goto out;
4129 r = 0;
4130 break;
4131 }
4132 case KVM_GET_MSRS: {
4133 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4134 r = msr_io(vcpu, argp, do_get_msr, 1);
4135 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4136 break;
4137 }
4138 case KVM_SET_MSRS: {
4139 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4140 r = msr_io(vcpu, argp, do_set_msr, 0);
4141 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4142 break;
4143 }
4144 case KVM_TPR_ACCESS_REPORTING: {
4145 struct kvm_tpr_access_ctl tac;
4146
4147 r = -EFAULT;
4148 if (copy_from_user(&tac, argp, sizeof(tac)))
4149 goto out;
4150 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4151 if (r)
4152 goto out;
4153 r = -EFAULT;
4154 if (copy_to_user(argp, &tac, sizeof(tac)))
4155 goto out;
4156 r = 0;
4157 break;
4158 };
4159 case KVM_SET_VAPIC_ADDR: {
4160 struct kvm_vapic_addr va;
4161 int idx;
4162
4163 r = -EINVAL;
4164 if (!lapic_in_kernel(vcpu))
4165 goto out;
4166 r = -EFAULT;
4167 if (copy_from_user(&va, argp, sizeof(va)))
4168 goto out;
4169 idx = srcu_read_lock(&vcpu->kvm->srcu);
4170 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4171 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4172 break;
4173 }
4174 case KVM_X86_SETUP_MCE: {
4175 u64 mcg_cap;
4176
4177 r = -EFAULT;
4178 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4179 goto out;
4180 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4181 break;
4182 }
4183 case KVM_X86_SET_MCE: {
4184 struct kvm_x86_mce mce;
4185
4186 r = -EFAULT;
4187 if (copy_from_user(&mce, argp, sizeof(mce)))
4188 goto out;
4189 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4190 break;
4191 }
4192 case KVM_GET_VCPU_EVENTS: {
4193 struct kvm_vcpu_events events;
4194
4195 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4196
4197 r = -EFAULT;
4198 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4199 break;
4200 r = 0;
4201 break;
4202 }
4203 case KVM_SET_VCPU_EVENTS: {
4204 struct kvm_vcpu_events events;
4205
4206 r = -EFAULT;
4207 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4208 break;
4209
4210 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4211 break;
4212 }
4213 case KVM_GET_DEBUGREGS: {
4214 struct kvm_debugregs dbgregs;
4215
4216 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4217
4218 r = -EFAULT;
4219 if (copy_to_user(argp, &dbgregs,
4220 sizeof(struct kvm_debugregs)))
4221 break;
4222 r = 0;
4223 break;
4224 }
4225 case KVM_SET_DEBUGREGS: {
4226 struct kvm_debugregs dbgregs;
4227
4228 r = -EFAULT;
4229 if (copy_from_user(&dbgregs, argp,
4230 sizeof(struct kvm_debugregs)))
4231 break;
4232
4233 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4234 break;
4235 }
4236 case KVM_GET_XSAVE: {
4237 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4238 r = -ENOMEM;
4239 if (!u.xsave)
4240 break;
4241
4242 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4243
4244 r = -EFAULT;
4245 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4246 break;
4247 r = 0;
4248 break;
4249 }
4250 case KVM_SET_XSAVE: {
4251 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4252 if (IS_ERR(u.xsave)) {
4253 r = PTR_ERR(u.xsave);
4254 goto out_nofree;
4255 }
4256
4257 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4258 break;
4259 }
4260 case KVM_GET_XCRS: {
4261 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4262 r = -ENOMEM;
4263 if (!u.xcrs)
4264 break;
4265
4266 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4267
4268 r = -EFAULT;
4269 if (copy_to_user(argp, u.xcrs,
4270 sizeof(struct kvm_xcrs)))
4271 break;
4272 r = 0;
4273 break;
4274 }
4275 case KVM_SET_XCRS: {
4276 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4277 if (IS_ERR(u.xcrs)) {
4278 r = PTR_ERR(u.xcrs);
4279 goto out_nofree;
4280 }
4281
4282 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4283 break;
4284 }
4285 case KVM_SET_TSC_KHZ: {
4286 u32 user_tsc_khz;
4287
4288 r = -EINVAL;
4289 user_tsc_khz = (u32)arg;
4290
4291 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4292 goto out;
4293
4294 if (user_tsc_khz == 0)
4295 user_tsc_khz = tsc_khz;
4296
4297 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4298 r = 0;
4299
4300 goto out;
4301 }
4302 case KVM_GET_TSC_KHZ: {
4303 r = vcpu->arch.virtual_tsc_khz;
4304 goto out;
4305 }
4306 case KVM_KVMCLOCK_CTRL: {
4307 r = kvm_set_guest_paused(vcpu);
4308 goto out;
4309 }
4310 case KVM_ENABLE_CAP: {
4311 struct kvm_enable_cap cap;
4312
4313 r = -EFAULT;
4314 if (copy_from_user(&cap, argp, sizeof(cap)))
4315 goto out;
4316 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4317 break;
4318 }
4319 case KVM_GET_NESTED_STATE: {
4320 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4321 u32 user_data_size;
4322
4323 r = -EINVAL;
4324 if (!kvm_x86_ops->get_nested_state)
4325 break;
4326
4327 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4328 r = -EFAULT;
4329 if (get_user(user_data_size, &user_kvm_nested_state->size))
4330 break;
4331
4332 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4333 user_data_size);
4334 if (r < 0)
4335 break;
4336
4337 if (r > user_data_size) {
4338 if (put_user(r, &user_kvm_nested_state->size))
4339 r = -EFAULT;
4340 else
4341 r = -E2BIG;
4342 break;
4343 }
4344
4345 r = 0;
4346 break;
4347 }
4348 case KVM_SET_NESTED_STATE: {
4349 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4350 struct kvm_nested_state kvm_state;
4351
4352 r = -EINVAL;
4353 if (!kvm_x86_ops->set_nested_state)
4354 break;
4355
4356 r = -EFAULT;
4357 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4358 break;
4359
4360 r = -EINVAL;
4361 if (kvm_state.size < sizeof(kvm_state))
4362 break;
4363
4364 if (kvm_state.flags &
4365 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4366 | KVM_STATE_NESTED_EVMCS))
4367 break;
4368
4369 /* nested_run_pending implies guest_mode. */
4370 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4371 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4372 break;
4373
4374 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4375 break;
4376 }
4377 case KVM_GET_SUPPORTED_HV_CPUID: {
4378 struct kvm_cpuid2 __user *cpuid_arg = argp;
4379 struct kvm_cpuid2 cpuid;
4380
4381 r = -EFAULT;
4382 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4383 goto out;
4384
4385 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4386 cpuid_arg->entries);
4387 if (r)
4388 goto out;
4389
4390 r = -EFAULT;
4391 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4392 goto out;
4393 r = 0;
4394 break;
4395 }
4396 default:
4397 r = -EINVAL;
4398 }
4399out:
4400 kfree(u.buffer);
4401out_nofree:
4402 vcpu_put(vcpu);
4403 return r;
4404}
4405
4406vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4407{
4408 return VM_FAULT_SIGBUS;
4409}
4410
4411static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4412{
4413 int ret;
4414
4415 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4416 return -EINVAL;
4417 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4418 return ret;
4419}
4420
4421static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4422 u64 ident_addr)
4423{
4424 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4425}
4426
4427static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4428 unsigned long kvm_nr_mmu_pages)
4429{
4430 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4431 return -EINVAL;
4432
4433 mutex_lock(&kvm->slots_lock);
4434
4435 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4436 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4437
4438 mutex_unlock(&kvm->slots_lock);
4439 return 0;
4440}
4441
4442static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4443{
4444 return kvm->arch.n_max_mmu_pages;
4445}
4446
4447static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4448{
4449 struct kvm_pic *pic = kvm->arch.vpic;
4450 int r;
4451
4452 r = 0;
4453 switch (chip->chip_id) {
4454 case KVM_IRQCHIP_PIC_MASTER:
4455 memcpy(&chip->chip.pic, &pic->pics[0],
4456 sizeof(struct kvm_pic_state));
4457 break;
4458 case KVM_IRQCHIP_PIC_SLAVE:
4459 memcpy(&chip->chip.pic, &pic->pics[1],
4460 sizeof(struct kvm_pic_state));
4461 break;
4462 case KVM_IRQCHIP_IOAPIC:
4463 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4464 break;
4465 default:
4466 r = -EINVAL;
4467 break;
4468 }
4469 return r;
4470}
4471
4472static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4473{
4474 struct kvm_pic *pic = kvm->arch.vpic;
4475 int r;
4476
4477 r = 0;
4478 switch (chip->chip_id) {
4479 case KVM_IRQCHIP_PIC_MASTER:
4480 spin_lock(&pic->lock);
4481 memcpy(&pic->pics[0], &chip->chip.pic,
4482 sizeof(struct kvm_pic_state));
4483 spin_unlock(&pic->lock);
4484 break;
4485 case KVM_IRQCHIP_PIC_SLAVE:
4486 spin_lock(&pic->lock);
4487 memcpy(&pic->pics[1], &chip->chip.pic,
4488 sizeof(struct kvm_pic_state));
4489 spin_unlock(&pic->lock);
4490 break;
4491 case KVM_IRQCHIP_IOAPIC:
4492 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4493 break;
4494 default:
4495 r = -EINVAL;
4496 break;
4497 }
4498 kvm_pic_update_irq(pic);
4499 return r;
4500}
4501
4502static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4503{
4504 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4505
4506 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4507
4508 mutex_lock(&kps->lock);
4509 memcpy(ps, &kps->channels, sizeof(*ps));
4510 mutex_unlock(&kps->lock);
4511 return 0;
4512}
4513
4514static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4515{
4516 int i;
4517 struct kvm_pit *pit = kvm->arch.vpit;
4518
4519 mutex_lock(&pit->pit_state.lock);
4520 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4521 for (i = 0; i < 3; i++)
4522 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4523 mutex_unlock(&pit->pit_state.lock);
4524 return 0;
4525}
4526
4527static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4528{
4529 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4530 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4531 sizeof(ps->channels));
4532 ps->flags = kvm->arch.vpit->pit_state.flags;
4533 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4534 memset(&ps->reserved, 0, sizeof(ps->reserved));
4535 return 0;
4536}
4537
4538static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4539{
4540 int start = 0;
4541 int i;
4542 u32 prev_legacy, cur_legacy;
4543 struct kvm_pit *pit = kvm->arch.vpit;
4544
4545 mutex_lock(&pit->pit_state.lock);
4546 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4547 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4548 if (!prev_legacy && cur_legacy)
4549 start = 1;
4550 memcpy(&pit->pit_state.channels, &ps->channels,
4551 sizeof(pit->pit_state.channels));
4552 pit->pit_state.flags = ps->flags;
4553 for (i = 0; i < 3; i++)
4554 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4555 start && i == 0);
4556 mutex_unlock(&pit->pit_state.lock);
4557 return 0;
4558}
4559
4560static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4561 struct kvm_reinject_control *control)
4562{
4563 struct kvm_pit *pit = kvm->arch.vpit;
4564
4565 if (!pit)
4566 return -ENXIO;
4567
4568 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4569 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4570 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4571 */
4572 mutex_lock(&pit->pit_state.lock);
4573 kvm_pit_set_reinject(pit, control->pit_reinject);
4574 mutex_unlock(&pit->pit_state.lock);
4575
4576 return 0;
4577}
4578
4579/**
4580 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4581 * @kvm: kvm instance
4582 * @log: slot id and address to which we copy the log
4583 *
4584 * Steps 1-4 below provide general overview of dirty page logging. See
4585 * kvm_get_dirty_log_protect() function description for additional details.
4586 *
4587 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4588 * always flush the TLB (step 4) even if previous step failed and the dirty
4589 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4590 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4591 * writes will be marked dirty for next log read.
4592 *
4593 * 1. Take a snapshot of the bit and clear it if needed.
4594 * 2. Write protect the corresponding page.
4595 * 3. Copy the snapshot to the userspace.
4596 * 4. Flush TLB's if needed.
4597 */
4598int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4599{
4600 bool flush = false;
4601 int r;
4602
4603 mutex_lock(&kvm->slots_lock);
4604
4605 /*
4606 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4607 */
4608 if (kvm_x86_ops->flush_log_dirty)
4609 kvm_x86_ops->flush_log_dirty(kvm);
4610
4611 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4612
4613 /*
4614 * All the TLBs can be flushed out of mmu lock, see the comments in
4615 * kvm_mmu_slot_remove_write_access().
4616 */
4617 lockdep_assert_held(&kvm->slots_lock);
4618 if (flush)
4619 kvm_flush_remote_tlbs(kvm);
4620
4621 mutex_unlock(&kvm->slots_lock);
4622 return r;
4623}
4624
4625int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4626{
4627 bool flush = false;
4628 int r;
4629
4630 mutex_lock(&kvm->slots_lock);
4631
4632 /*
4633 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4634 */
4635 if (kvm_x86_ops->flush_log_dirty)
4636 kvm_x86_ops->flush_log_dirty(kvm);
4637
4638 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4639
4640 /*
4641 * All the TLBs can be flushed out of mmu lock, see the comments in
4642 * kvm_mmu_slot_remove_write_access().
4643 */
4644 lockdep_assert_held(&kvm->slots_lock);
4645 if (flush)
4646 kvm_flush_remote_tlbs(kvm);
4647
4648 mutex_unlock(&kvm->slots_lock);
4649 return r;
4650}
4651
4652int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4653 bool line_status)
4654{
4655 if (!irqchip_in_kernel(kvm))
4656 return -ENXIO;
4657
4658 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4659 irq_event->irq, irq_event->level,
4660 line_status);
4661 return 0;
4662}
4663
4664int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4665 struct kvm_enable_cap *cap)
4666{
4667 int r;
4668
4669 if (cap->flags)
4670 return -EINVAL;
4671
4672 switch (cap->cap) {
4673 case KVM_CAP_DISABLE_QUIRKS:
4674 kvm->arch.disabled_quirks = cap->args[0];
4675 r = 0;
4676 break;
4677 case KVM_CAP_SPLIT_IRQCHIP: {
4678 mutex_lock(&kvm->lock);
4679 r = -EINVAL;
4680 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4681 goto split_irqchip_unlock;
4682 r = -EEXIST;
4683 if (irqchip_in_kernel(kvm))
4684 goto split_irqchip_unlock;
4685 if (kvm->created_vcpus)
4686 goto split_irqchip_unlock;
4687 r = kvm_setup_empty_irq_routing(kvm);
4688 if (r)
4689 goto split_irqchip_unlock;
4690 /* Pairs with irqchip_in_kernel. */
4691 smp_wmb();
4692 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4693 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4694 r = 0;
4695split_irqchip_unlock:
4696 mutex_unlock(&kvm->lock);
4697 break;
4698 }
4699 case KVM_CAP_X2APIC_API:
4700 r = -EINVAL;
4701 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4702 break;
4703
4704 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4705 kvm->arch.x2apic_format = true;
4706 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4707 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4708
4709 r = 0;
4710 break;
4711 case KVM_CAP_X86_DISABLE_EXITS:
4712 r = -EINVAL;
4713 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4714 break;
4715
4716 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4717 kvm_can_mwait_in_guest())
4718 kvm->arch.mwait_in_guest = true;
4719 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4720 kvm->arch.hlt_in_guest = true;
4721 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4722 kvm->arch.pause_in_guest = true;
4723 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4724 kvm->arch.cstate_in_guest = true;
4725 r = 0;
4726 break;
4727 case KVM_CAP_MSR_PLATFORM_INFO:
4728 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4729 r = 0;
4730 break;
4731 case KVM_CAP_EXCEPTION_PAYLOAD:
4732 kvm->arch.exception_payload_enabled = cap->args[0];
4733 r = 0;
4734 break;
4735 default:
4736 r = -EINVAL;
4737 break;
4738 }
4739 return r;
4740}
4741
4742long kvm_arch_vm_ioctl(struct file *filp,
4743 unsigned int ioctl, unsigned long arg)
4744{
4745 struct kvm *kvm = filp->private_data;
4746 void __user *argp = (void __user *)arg;
4747 int r = -ENOTTY;
4748 /*
4749 * This union makes it completely explicit to gcc-3.x
4750 * that these two variables' stack usage should be
4751 * combined, not added together.
4752 */
4753 union {
4754 struct kvm_pit_state ps;
4755 struct kvm_pit_state2 ps2;
4756 struct kvm_pit_config pit_config;
4757 } u;
4758
4759 switch (ioctl) {
4760 case KVM_SET_TSS_ADDR:
4761 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4762 break;
4763 case KVM_SET_IDENTITY_MAP_ADDR: {
4764 u64 ident_addr;
4765
4766 mutex_lock(&kvm->lock);
4767 r = -EINVAL;
4768 if (kvm->created_vcpus)
4769 goto set_identity_unlock;
4770 r = -EFAULT;
4771 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4772 goto set_identity_unlock;
4773 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4774set_identity_unlock:
4775 mutex_unlock(&kvm->lock);
4776 break;
4777 }
4778 case KVM_SET_NR_MMU_PAGES:
4779 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4780 break;
4781 case KVM_GET_NR_MMU_PAGES:
4782 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4783 break;
4784 case KVM_CREATE_IRQCHIP: {
4785 mutex_lock(&kvm->lock);
4786
4787 r = -EEXIST;
4788 if (irqchip_in_kernel(kvm))
4789 goto create_irqchip_unlock;
4790
4791 r = -EINVAL;
4792 if (kvm->created_vcpus)
4793 goto create_irqchip_unlock;
4794
4795 r = kvm_pic_init(kvm);
4796 if (r)
4797 goto create_irqchip_unlock;
4798
4799 r = kvm_ioapic_init(kvm);
4800 if (r) {
4801 kvm_pic_destroy(kvm);
4802 goto create_irqchip_unlock;
4803 }
4804
4805 r = kvm_setup_default_irq_routing(kvm);
4806 if (r) {
4807 kvm_ioapic_destroy(kvm);
4808 kvm_pic_destroy(kvm);
4809 goto create_irqchip_unlock;
4810 }
4811 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4812 smp_wmb();
4813 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4814 create_irqchip_unlock:
4815 mutex_unlock(&kvm->lock);
4816 break;
4817 }
4818 case KVM_CREATE_PIT:
4819 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4820 goto create_pit;
4821 case KVM_CREATE_PIT2:
4822 r = -EFAULT;
4823 if (copy_from_user(&u.pit_config, argp,
4824 sizeof(struct kvm_pit_config)))
4825 goto out;
4826 create_pit:
4827 mutex_lock(&kvm->lock);
4828 r = -EEXIST;
4829 if (kvm->arch.vpit)
4830 goto create_pit_unlock;
4831 r = -ENOMEM;
4832 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4833 if (kvm->arch.vpit)
4834 r = 0;
4835 create_pit_unlock:
4836 mutex_unlock(&kvm->lock);
4837 break;
4838 case KVM_GET_IRQCHIP: {
4839 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4840 struct kvm_irqchip *chip;
4841
4842 chip = memdup_user(argp, sizeof(*chip));
4843 if (IS_ERR(chip)) {
4844 r = PTR_ERR(chip);
4845 goto out;
4846 }
4847
4848 r = -ENXIO;
4849 if (!irqchip_kernel(kvm))
4850 goto get_irqchip_out;
4851 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4852 if (r)
4853 goto get_irqchip_out;
4854 r = -EFAULT;
4855 if (copy_to_user(argp, chip, sizeof(*chip)))
4856 goto get_irqchip_out;
4857 r = 0;
4858 get_irqchip_out:
4859 kfree(chip);
4860 break;
4861 }
4862 case KVM_SET_IRQCHIP: {
4863 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4864 struct kvm_irqchip *chip;
4865
4866 chip = memdup_user(argp, sizeof(*chip));
4867 if (IS_ERR(chip)) {
4868 r = PTR_ERR(chip);
4869 goto out;
4870 }
4871
4872 r = -ENXIO;
4873 if (!irqchip_kernel(kvm))
4874 goto set_irqchip_out;
4875 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4876 if (r)
4877 goto set_irqchip_out;
4878 r = 0;
4879 set_irqchip_out:
4880 kfree(chip);
4881 break;
4882 }
4883 case KVM_GET_PIT: {
4884 r = -EFAULT;
4885 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4886 goto out;
4887 r = -ENXIO;
4888 if (!kvm->arch.vpit)
4889 goto out;
4890 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4891 if (r)
4892 goto out;
4893 r = -EFAULT;
4894 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4895 goto out;
4896 r = 0;
4897 break;
4898 }
4899 case KVM_SET_PIT: {
4900 r = -EFAULT;
4901 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4902 goto out;
4903 r = -ENXIO;
4904 if (!kvm->arch.vpit)
4905 goto out;
4906 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4907 break;
4908 }
4909 case KVM_GET_PIT2: {
4910 r = -ENXIO;
4911 if (!kvm->arch.vpit)
4912 goto out;
4913 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4914 if (r)
4915 goto out;
4916 r = -EFAULT;
4917 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4918 goto out;
4919 r = 0;
4920 break;
4921 }
4922 case KVM_SET_PIT2: {
4923 r = -EFAULT;
4924 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4925 goto out;
4926 r = -ENXIO;
4927 if (!kvm->arch.vpit)
4928 goto out;
4929 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4930 break;
4931 }
4932 case KVM_REINJECT_CONTROL: {
4933 struct kvm_reinject_control control;
4934 r = -EFAULT;
4935 if (copy_from_user(&control, argp, sizeof(control)))
4936 goto out;
4937 r = kvm_vm_ioctl_reinject(kvm, &control);
4938 break;
4939 }
4940 case KVM_SET_BOOT_CPU_ID:
4941 r = 0;
4942 mutex_lock(&kvm->lock);
4943 if (kvm->created_vcpus)
4944 r = -EBUSY;
4945 else
4946 kvm->arch.bsp_vcpu_id = arg;
4947 mutex_unlock(&kvm->lock);
4948 break;
4949 case KVM_XEN_HVM_CONFIG: {
4950 struct kvm_xen_hvm_config xhc;
4951 r = -EFAULT;
4952 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4953 goto out;
4954 r = -EINVAL;
4955 if (xhc.flags)
4956 goto out;
4957 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4958 r = 0;
4959 break;
4960 }
4961 case KVM_SET_CLOCK: {
4962 struct kvm_clock_data user_ns;
4963 u64 now_ns;
4964
4965 r = -EFAULT;
4966 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4967 goto out;
4968
4969 r = -EINVAL;
4970 if (user_ns.flags)
4971 goto out;
4972
4973 r = 0;
4974 /*
4975 * TODO: userspace has to take care of races with VCPU_RUN, so
4976 * kvm_gen_update_masterclock() can be cut down to locked
4977 * pvclock_update_vm_gtod_copy().
4978 */
4979 kvm_gen_update_masterclock(kvm);
4980 now_ns = get_kvmclock_ns(kvm);
4981 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4982 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4983 break;
4984 }
4985 case KVM_GET_CLOCK: {
4986 struct kvm_clock_data user_ns;
4987 u64 now_ns;
4988
4989 now_ns = get_kvmclock_ns(kvm);
4990 user_ns.clock = now_ns;
4991 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4992 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4993
4994 r = -EFAULT;
4995 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4996 goto out;
4997 r = 0;
4998 break;
4999 }
5000 case KVM_MEMORY_ENCRYPT_OP: {
5001 r = -ENOTTY;
5002 if (kvm_x86_ops->mem_enc_op)
5003 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5004 break;
5005 }
5006 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5007 struct kvm_enc_region region;
5008
5009 r = -EFAULT;
5010 if (copy_from_user(&region, argp, sizeof(region)))
5011 goto out;
5012
5013 r = -ENOTTY;
5014 if (kvm_x86_ops->mem_enc_reg_region)
5015 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5016 break;
5017 }
5018 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5019 struct kvm_enc_region region;
5020
5021 r = -EFAULT;
5022 if (copy_from_user(&region, argp, sizeof(region)))
5023 goto out;
5024
5025 r = -ENOTTY;
5026 if (kvm_x86_ops->mem_enc_unreg_region)
5027 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5028 break;
5029 }
5030 case KVM_HYPERV_EVENTFD: {
5031 struct kvm_hyperv_eventfd hvevfd;
5032
5033 r = -EFAULT;
5034 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5035 goto out;
5036 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5037 break;
5038 }
5039 case KVM_SET_PMU_EVENT_FILTER:
5040 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5041 break;
5042 default:
5043 r = -ENOTTY;
5044 }
5045out:
5046 return r;
5047}
5048
5049static void kvm_init_msr_list(void)
5050{
5051 u32 dummy[2];
5052 unsigned i, j;
5053
5054 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
5055 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5056 continue;
5057
5058 /*
5059 * Even MSRs that are valid in the host may not be exposed
5060 * to the guests in some cases.
5061 */
5062 switch (msrs_to_save[i]) {
5063 case MSR_IA32_BNDCFGS:
5064 if (!kvm_mpx_supported())
5065 continue;
5066 break;
5067 case MSR_TSC_AUX:
5068 if (!kvm_x86_ops->rdtscp_supported())
5069 continue;
5070 break;
5071 case MSR_IA32_RTIT_CTL:
5072 case MSR_IA32_RTIT_STATUS:
5073 if (!kvm_x86_ops->pt_supported())
5074 continue;
5075 break;
5076 case MSR_IA32_RTIT_CR3_MATCH:
5077 if (!kvm_x86_ops->pt_supported() ||
5078 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5079 continue;
5080 break;
5081 case MSR_IA32_RTIT_OUTPUT_BASE:
5082 case MSR_IA32_RTIT_OUTPUT_MASK:
5083 if (!kvm_x86_ops->pt_supported() ||
5084 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5085 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5086 continue;
5087 break;
5088 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5089 if (!kvm_x86_ops->pt_supported() ||
5090 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5091 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5092 continue;
5093 break;
5094 }
5095 default:
5096 break;
5097 }
5098
5099 if (j < i)
5100 msrs_to_save[j] = msrs_to_save[i];
5101 j++;
5102 }
5103 num_msrs_to_save = j;
5104
5105 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5106 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5107 continue;
5108
5109 if (j < i)
5110 emulated_msrs[j] = emulated_msrs[i];
5111 j++;
5112 }
5113 num_emulated_msrs = j;
5114
5115 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5116 struct kvm_msr_entry msr;
5117
5118 msr.index = msr_based_features[i];
5119 if (kvm_get_msr_feature(&msr))
5120 continue;
5121
5122 if (j < i)
5123 msr_based_features[j] = msr_based_features[i];
5124 j++;
5125 }
5126 num_msr_based_features = j;
5127}
5128
5129static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5130 const void *v)
5131{
5132 int handled = 0;
5133 int n;
5134
5135 do {
5136 n = min(len, 8);
5137 if (!(lapic_in_kernel(vcpu) &&
5138 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5139 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5140 break;
5141 handled += n;
5142 addr += n;
5143 len -= n;
5144 v += n;
5145 } while (len);
5146
5147 return handled;
5148}
5149
5150static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5151{
5152 int handled = 0;
5153 int n;
5154
5155 do {
5156 n = min(len, 8);
5157 if (!(lapic_in_kernel(vcpu) &&
5158 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5159 addr, n, v))
5160 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5161 break;
5162 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5163 handled += n;
5164 addr += n;
5165 len -= n;
5166 v += n;
5167 } while (len);
5168
5169 return handled;
5170}
5171
5172static void kvm_set_segment(struct kvm_vcpu *vcpu,
5173 struct kvm_segment *var, int seg)
5174{
5175 kvm_x86_ops->set_segment(vcpu, var, seg);
5176}
5177
5178void kvm_get_segment(struct kvm_vcpu *vcpu,
5179 struct kvm_segment *var, int seg)
5180{
5181 kvm_x86_ops->get_segment(vcpu, var, seg);
5182}
5183
5184gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5185 struct x86_exception *exception)
5186{
5187 gpa_t t_gpa;
5188
5189 BUG_ON(!mmu_is_nested(vcpu));
5190
5191 /* NPT walks are always user-walks */
5192 access |= PFERR_USER_MASK;
5193 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5194
5195 return t_gpa;
5196}
5197
5198gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5199 struct x86_exception *exception)
5200{
5201 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5202 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5203}
5204
5205 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5206 struct x86_exception *exception)
5207{
5208 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5209 access |= PFERR_FETCH_MASK;
5210 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5211}
5212
5213gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5214 struct x86_exception *exception)
5215{
5216 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5217 access |= PFERR_WRITE_MASK;
5218 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5219}
5220
5221/* uses this to access any guest's mapped memory without checking CPL */
5222gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5223 struct x86_exception *exception)
5224{
5225 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5226}
5227
5228static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5229 struct kvm_vcpu *vcpu, u32 access,
5230 struct x86_exception *exception)
5231{
5232 void *data = val;
5233 int r = X86EMUL_CONTINUE;
5234
5235 while (bytes) {
5236 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5237 exception);
5238 unsigned offset = addr & (PAGE_SIZE-1);
5239 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5240 int ret;
5241
5242 if (gpa == UNMAPPED_GVA)
5243 return X86EMUL_PROPAGATE_FAULT;
5244 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5245 offset, toread);
5246 if (ret < 0) {
5247 r = X86EMUL_IO_NEEDED;
5248 goto out;
5249 }
5250
5251 bytes -= toread;
5252 data += toread;
5253 addr += toread;
5254 }
5255out:
5256 return r;
5257}
5258
5259/* used for instruction fetching */
5260static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5261 gva_t addr, void *val, unsigned int bytes,
5262 struct x86_exception *exception)
5263{
5264 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5265 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5266 unsigned offset;
5267 int ret;
5268
5269 /* Inline kvm_read_guest_virt_helper for speed. */
5270 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5271 exception);
5272 if (unlikely(gpa == UNMAPPED_GVA))
5273 return X86EMUL_PROPAGATE_FAULT;
5274
5275 offset = addr & (PAGE_SIZE-1);
5276 if (WARN_ON(offset + bytes > PAGE_SIZE))
5277 bytes = (unsigned)PAGE_SIZE - offset;
5278 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5279 offset, bytes);
5280 if (unlikely(ret < 0))
5281 return X86EMUL_IO_NEEDED;
5282
5283 return X86EMUL_CONTINUE;
5284}
5285
5286int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5287 gva_t addr, void *val, unsigned int bytes,
5288 struct x86_exception *exception)
5289{
5290 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5291
5292 /*
5293 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5294 * is returned, but our callers are not ready for that and they blindly
5295 * call kvm_inject_page_fault. Ensure that they at least do not leak
5296 * uninitialized kernel stack memory into cr2 and error code.
5297 */
5298 memset(exception, 0, sizeof(*exception));
5299 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5300 exception);
5301}
5302EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5303
5304static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5305 gva_t addr, void *val, unsigned int bytes,
5306 struct x86_exception *exception, bool system)
5307{
5308 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5309 u32 access = 0;
5310
5311 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5312 access |= PFERR_USER_MASK;
5313
5314 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5315}
5316
5317static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5318 unsigned long addr, void *val, unsigned int bytes)
5319{
5320 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5321 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5322
5323 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5324}
5325
5326static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5327 struct kvm_vcpu *vcpu, u32 access,
5328 struct x86_exception *exception)
5329{
5330 void *data = val;
5331 int r = X86EMUL_CONTINUE;
5332
5333 while (bytes) {
5334 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5335 access,
5336 exception);
5337 unsigned offset = addr & (PAGE_SIZE-1);
5338 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5339 int ret;
5340
5341 if (gpa == UNMAPPED_GVA)
5342 return X86EMUL_PROPAGATE_FAULT;
5343 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5344 if (ret < 0) {
5345 r = X86EMUL_IO_NEEDED;
5346 goto out;
5347 }
5348
5349 bytes -= towrite;
5350 data += towrite;
5351 addr += towrite;
5352 }
5353out:
5354 return r;
5355}
5356
5357static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5358 unsigned int bytes, struct x86_exception *exception,
5359 bool system)
5360{
5361 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5362 u32 access = PFERR_WRITE_MASK;
5363
5364 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5365 access |= PFERR_USER_MASK;
5366
5367 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5368 access, exception);
5369}
5370
5371int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5372 unsigned int bytes, struct x86_exception *exception)
5373{
5374 /* kvm_write_guest_virt_system can pull in tons of pages. */
5375 vcpu->arch.l1tf_flush_l1d = true;
5376
5377 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5378 PFERR_WRITE_MASK, exception);
5379}
5380EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5381
5382int handle_ud(struct kvm_vcpu *vcpu)
5383{
5384 int emul_type = EMULTYPE_TRAP_UD;
5385 enum emulation_result er;
5386 char sig[5]; /* ud2; .ascii "kvm" */
5387 struct x86_exception e;
5388
5389 if (force_emulation_prefix &&
5390 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5391 sig, sizeof(sig), &e) == 0 &&
5392 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5393 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5394 emul_type = 0;
5395 }
5396
5397 er = kvm_emulate_instruction(vcpu, emul_type);
5398 if (er == EMULATE_USER_EXIT)
5399 return 0;
5400 if (er != EMULATE_DONE)
5401 kvm_queue_exception(vcpu, UD_VECTOR);
5402 return 1;
5403}
5404EXPORT_SYMBOL_GPL(handle_ud);
5405
5406static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5407 gpa_t gpa, bool write)
5408{
5409 /* For APIC access vmexit */
5410 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5411 return 1;
5412
5413 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5414 trace_vcpu_match_mmio(gva, gpa, write, true);
5415 return 1;
5416 }
5417
5418 return 0;
5419}
5420
5421static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5422 gpa_t *gpa, struct x86_exception *exception,
5423 bool write)
5424{
5425 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5426 | (write ? PFERR_WRITE_MASK : 0);
5427
5428 /*
5429 * currently PKRU is only applied to ept enabled guest so
5430 * there is no pkey in EPT page table for L1 guest or EPT
5431 * shadow page table for L2 guest.
5432 */
5433 if (vcpu_match_mmio_gva(vcpu, gva)
5434 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5435 vcpu->arch.mmio_access, 0, access)) {
5436 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5437 (gva & (PAGE_SIZE - 1));
5438 trace_vcpu_match_mmio(gva, *gpa, write, false);
5439 return 1;
5440 }
5441
5442 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5443
5444 if (*gpa == UNMAPPED_GVA)
5445 return -1;
5446
5447 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5448}
5449
5450int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5451 const void *val, int bytes)
5452{
5453 int ret;
5454
5455 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5456 if (ret < 0)
5457 return 0;
5458 kvm_page_track_write(vcpu, gpa, val, bytes);
5459 return 1;
5460}
5461
5462struct read_write_emulator_ops {
5463 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5464 int bytes);
5465 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5466 void *val, int bytes);
5467 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5468 int bytes, void *val);
5469 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5470 void *val, int bytes);
5471 bool write;
5472};
5473
5474static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5475{
5476 if (vcpu->mmio_read_completed) {
5477 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5478 vcpu->mmio_fragments[0].gpa, val);
5479 vcpu->mmio_read_completed = 0;
5480 return 1;
5481 }
5482
5483 return 0;
5484}
5485
5486static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5487 void *val, int bytes)
5488{
5489 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5490}
5491
5492static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5493 void *val, int bytes)
5494{
5495 return emulator_write_phys(vcpu, gpa, val, bytes);
5496}
5497
5498static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5499{
5500 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5501 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5502}
5503
5504static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5505 void *val, int bytes)
5506{
5507 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5508 return X86EMUL_IO_NEEDED;
5509}
5510
5511static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5512 void *val, int bytes)
5513{
5514 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5515
5516 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5517 return X86EMUL_CONTINUE;
5518}
5519
5520static const struct read_write_emulator_ops read_emultor = {
5521 .read_write_prepare = read_prepare,
5522 .read_write_emulate = read_emulate,
5523 .read_write_mmio = vcpu_mmio_read,
5524 .read_write_exit_mmio = read_exit_mmio,
5525};
5526
5527static const struct read_write_emulator_ops write_emultor = {
5528 .read_write_emulate = write_emulate,
5529 .read_write_mmio = write_mmio,
5530 .read_write_exit_mmio = write_exit_mmio,
5531 .write = true,
5532};
5533
5534static int emulator_read_write_onepage(unsigned long addr, void *val,
5535 unsigned int bytes,
5536 struct x86_exception *exception,
5537 struct kvm_vcpu *vcpu,
5538 const struct read_write_emulator_ops *ops)
5539{
5540 gpa_t gpa;
5541 int handled, ret;
5542 bool write = ops->write;
5543 struct kvm_mmio_fragment *frag;
5544 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5545
5546 /*
5547 * If the exit was due to a NPF we may already have a GPA.
5548 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5549 * Note, this cannot be used on string operations since string
5550 * operation using rep will only have the initial GPA from the NPF
5551 * occurred.
5552 */
5553 if (vcpu->arch.gpa_available &&
5554 emulator_can_use_gpa(ctxt) &&
5555 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5556 gpa = vcpu->arch.gpa_val;
5557 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5558 } else {
5559 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5560 if (ret < 0)
5561 return X86EMUL_PROPAGATE_FAULT;
5562 }
5563
5564 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5565 return X86EMUL_CONTINUE;
5566
5567 /*
5568 * Is this MMIO handled locally?
5569 */
5570 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5571 if (handled == bytes)
5572 return X86EMUL_CONTINUE;
5573
5574 gpa += handled;
5575 bytes -= handled;
5576 val += handled;
5577
5578 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5579 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5580 frag->gpa = gpa;
5581 frag->data = val;
5582 frag->len = bytes;
5583 return X86EMUL_CONTINUE;
5584}
5585
5586static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5587 unsigned long addr,
5588 void *val, unsigned int bytes,
5589 struct x86_exception *exception,
5590 const struct read_write_emulator_ops *ops)
5591{
5592 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5593 gpa_t gpa;
5594 int rc;
5595
5596 if (ops->read_write_prepare &&
5597 ops->read_write_prepare(vcpu, val, bytes))
5598 return X86EMUL_CONTINUE;
5599
5600 vcpu->mmio_nr_fragments = 0;
5601
5602 /* Crossing a page boundary? */
5603 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5604 int now;
5605
5606 now = -addr & ~PAGE_MASK;
5607 rc = emulator_read_write_onepage(addr, val, now, exception,
5608 vcpu, ops);
5609
5610 if (rc != X86EMUL_CONTINUE)
5611 return rc;
5612 addr += now;
5613 if (ctxt->mode != X86EMUL_MODE_PROT64)
5614 addr = (u32)addr;
5615 val += now;
5616 bytes -= now;
5617 }
5618
5619 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5620 vcpu, ops);
5621 if (rc != X86EMUL_CONTINUE)
5622 return rc;
5623
5624 if (!vcpu->mmio_nr_fragments)
5625 return rc;
5626
5627 gpa = vcpu->mmio_fragments[0].gpa;
5628
5629 vcpu->mmio_needed = 1;
5630 vcpu->mmio_cur_fragment = 0;
5631
5632 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5633 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5634 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5635 vcpu->run->mmio.phys_addr = gpa;
5636
5637 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5638}
5639
5640static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5641 unsigned long addr,
5642 void *val,
5643 unsigned int bytes,
5644 struct x86_exception *exception)
5645{
5646 return emulator_read_write(ctxt, addr, val, bytes,
5647 exception, &read_emultor);
5648}
5649
5650static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5651 unsigned long addr,
5652 const void *val,
5653 unsigned int bytes,
5654 struct x86_exception *exception)
5655{
5656 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5657 exception, &write_emultor);
5658}
5659
5660#define CMPXCHG_TYPE(t, ptr, old, new) \
5661 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5662
5663#ifdef CONFIG_X86_64
5664# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5665#else
5666# define CMPXCHG64(ptr, old, new) \
5667 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5668#endif
5669
5670static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5671 unsigned long addr,
5672 const void *old,
5673 const void *new,
5674 unsigned int bytes,
5675 struct x86_exception *exception)
5676{
5677 struct kvm_host_map map;
5678 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5679 gpa_t gpa;
5680 char *kaddr;
5681 bool exchanged;
5682
5683 /* guests cmpxchg8b have to be emulated atomically */
5684 if (bytes > 8 || (bytes & (bytes - 1)))
5685 goto emul_write;
5686
5687 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5688
5689 if (gpa == UNMAPPED_GVA ||
5690 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5691 goto emul_write;
5692
5693 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5694 goto emul_write;
5695
5696 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5697 goto emul_write;
5698
5699 kaddr = map.hva + offset_in_page(gpa);
5700
5701 switch (bytes) {
5702 case 1:
5703 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5704 break;
5705 case 2:
5706 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5707 break;
5708 case 4:
5709 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5710 break;
5711 case 8:
5712 exchanged = CMPXCHG64(kaddr, old, new);
5713 break;
5714 default:
5715 BUG();
5716 }
5717
5718 kvm_vcpu_unmap(vcpu, &map, true);
5719
5720 if (!exchanged)
5721 return X86EMUL_CMPXCHG_FAILED;
5722
5723 kvm_page_track_write(vcpu, gpa, new, bytes);
5724
5725 return X86EMUL_CONTINUE;
5726
5727emul_write:
5728 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5729
5730 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5731}
5732
5733static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5734{
5735 int r = 0, i;
5736
5737 for (i = 0; i < vcpu->arch.pio.count; i++) {
5738 if (vcpu->arch.pio.in)
5739 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5740 vcpu->arch.pio.size, pd);
5741 else
5742 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5743 vcpu->arch.pio.port, vcpu->arch.pio.size,
5744 pd);
5745 if (r)
5746 break;
5747 pd += vcpu->arch.pio.size;
5748 }
5749 return r;
5750}
5751
5752static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5753 unsigned short port, void *val,
5754 unsigned int count, bool in)
5755{
5756 vcpu->arch.pio.port = port;
5757 vcpu->arch.pio.in = in;
5758 vcpu->arch.pio.count = count;
5759 vcpu->arch.pio.size = size;
5760
5761 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5762 vcpu->arch.pio.count = 0;
5763 return 1;
5764 }
5765
5766 vcpu->run->exit_reason = KVM_EXIT_IO;
5767 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5768 vcpu->run->io.size = size;
5769 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5770 vcpu->run->io.count = count;
5771 vcpu->run->io.port = port;
5772
5773 return 0;
5774}
5775
5776static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5777 int size, unsigned short port, void *val,
5778 unsigned int count)
5779{
5780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5781 int ret;
5782
5783 if (vcpu->arch.pio.count)
5784 goto data_avail;
5785
5786 memset(vcpu->arch.pio_data, 0, size * count);
5787
5788 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5789 if (ret) {
5790data_avail:
5791 memcpy(val, vcpu->arch.pio_data, size * count);
5792 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5793 vcpu->arch.pio.count = 0;
5794 return 1;
5795 }
5796
5797 return 0;
5798}
5799
5800static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5801 int size, unsigned short port,
5802 const void *val, unsigned int count)
5803{
5804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5805
5806 memcpy(vcpu->arch.pio_data, val, size * count);
5807 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5808 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5809}
5810
5811static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5812{
5813 return kvm_x86_ops->get_segment_base(vcpu, seg);
5814}
5815
5816static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5817{
5818 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5819}
5820
5821static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5822{
5823 if (!need_emulate_wbinvd(vcpu))
5824 return X86EMUL_CONTINUE;
5825
5826 if (kvm_x86_ops->has_wbinvd_exit()) {
5827 int cpu = get_cpu();
5828
5829 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5830 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5831 wbinvd_ipi, NULL, 1);
5832 put_cpu();
5833 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5834 } else
5835 wbinvd();
5836 return X86EMUL_CONTINUE;
5837}
5838
5839int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5840{
5841 kvm_emulate_wbinvd_noskip(vcpu);
5842 return kvm_skip_emulated_instruction(vcpu);
5843}
5844EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5845
5846
5847
5848static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5849{
5850 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5851}
5852
5853static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5854 unsigned long *dest)
5855{
5856 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5857}
5858
5859static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5860 unsigned long value)
5861{
5862
5863 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5864}
5865
5866static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5867{
5868 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5869}
5870
5871static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5872{
5873 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5874 unsigned long value;
5875
5876 switch (cr) {
5877 case 0:
5878 value = kvm_read_cr0(vcpu);
5879 break;
5880 case 2:
5881 value = vcpu->arch.cr2;
5882 break;
5883 case 3:
5884 value = kvm_read_cr3(vcpu);
5885 break;
5886 case 4:
5887 value = kvm_read_cr4(vcpu);
5888 break;
5889 case 8:
5890 value = kvm_get_cr8(vcpu);
5891 break;
5892 default:
5893 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5894 return 0;
5895 }
5896
5897 return value;
5898}
5899
5900static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5901{
5902 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5903 int res = 0;
5904
5905 switch (cr) {
5906 case 0:
5907 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5908 break;
5909 case 2:
5910 vcpu->arch.cr2 = val;
5911 break;
5912 case 3:
5913 res = kvm_set_cr3(vcpu, val);
5914 break;
5915 case 4:
5916 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5917 break;
5918 case 8:
5919 res = kvm_set_cr8(vcpu, val);
5920 break;
5921 default:
5922 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5923 res = -1;
5924 }
5925
5926 return res;
5927}
5928
5929static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5930{
5931 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5932}
5933
5934static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5935{
5936 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5937}
5938
5939static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5940{
5941 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5942}
5943
5944static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5945{
5946 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5947}
5948
5949static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5950{
5951 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5952}
5953
5954static unsigned long emulator_get_cached_segment_base(
5955 struct x86_emulate_ctxt *ctxt, int seg)
5956{
5957 return get_segment_base(emul_to_vcpu(ctxt), seg);
5958}
5959
5960static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5961 struct desc_struct *desc, u32 *base3,
5962 int seg)
5963{
5964 struct kvm_segment var;
5965
5966 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5967 *selector = var.selector;
5968
5969 if (var.unusable) {
5970 memset(desc, 0, sizeof(*desc));
5971 if (base3)
5972 *base3 = 0;
5973 return false;
5974 }
5975
5976 if (var.g)
5977 var.limit >>= 12;
5978 set_desc_limit(desc, var.limit);
5979 set_desc_base(desc, (unsigned long)var.base);
5980#ifdef CONFIG_X86_64
5981 if (base3)
5982 *base3 = var.base >> 32;
5983#endif
5984 desc->type = var.type;
5985 desc->s = var.s;
5986 desc->dpl = var.dpl;
5987 desc->p = var.present;
5988 desc->avl = var.avl;
5989 desc->l = var.l;
5990 desc->d = var.db;
5991 desc->g = var.g;
5992
5993 return true;
5994}
5995
5996static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5997 struct desc_struct *desc, u32 base3,
5998 int seg)
5999{
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6001 struct kvm_segment var;
6002
6003 var.selector = selector;
6004 var.base = get_desc_base(desc);
6005#ifdef CONFIG_X86_64
6006 var.base |= ((u64)base3) << 32;
6007#endif
6008 var.limit = get_desc_limit(desc);
6009 if (desc->g)
6010 var.limit = (var.limit << 12) | 0xfff;
6011 var.type = desc->type;
6012 var.dpl = desc->dpl;
6013 var.db = desc->d;
6014 var.s = desc->s;
6015 var.l = desc->l;
6016 var.g = desc->g;
6017 var.avl = desc->avl;
6018 var.present = desc->p;
6019 var.unusable = !var.present;
6020 var.padding = 0;
6021
6022 kvm_set_segment(vcpu, &var, seg);
6023 return;
6024}
6025
6026static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6027 u32 msr_index, u64 *pdata)
6028{
6029 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6030}
6031
6032static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6033 u32 msr_index, u64 data)
6034{
6035 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6036}
6037
6038static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6039{
6040 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6041
6042 return vcpu->arch.smbase;
6043}
6044
6045static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6046{
6047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6048
6049 vcpu->arch.smbase = smbase;
6050}
6051
6052static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6053 u32 pmc)
6054{
6055 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6056}
6057
6058static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6059 u32 pmc, u64 *pdata)
6060{
6061 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6062}
6063
6064static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6065{
6066 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6067}
6068
6069static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6070 struct x86_instruction_info *info,
6071 enum x86_intercept_stage stage)
6072{
6073 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6074}
6075
6076static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6077 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6078{
6079 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6080}
6081
6082static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6083{
6084 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6085}
6086
6087static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6088{
6089 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6090}
6091
6092static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6093{
6094 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6095}
6096
6097static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6098{
6099 return emul_to_vcpu(ctxt)->arch.hflags;
6100}
6101
6102static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6103{
6104 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6105}
6106
6107static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6108 const char *smstate)
6109{
6110 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6111}
6112
6113static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6114{
6115 kvm_smm_changed(emul_to_vcpu(ctxt));
6116}
6117
6118static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6119{
6120 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6121}
6122
6123static const struct x86_emulate_ops emulate_ops = {
6124 .read_gpr = emulator_read_gpr,
6125 .write_gpr = emulator_write_gpr,
6126 .read_std = emulator_read_std,
6127 .write_std = emulator_write_std,
6128 .read_phys = kvm_read_guest_phys_system,
6129 .fetch = kvm_fetch_guest_virt,
6130 .read_emulated = emulator_read_emulated,
6131 .write_emulated = emulator_write_emulated,
6132 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6133 .invlpg = emulator_invlpg,
6134 .pio_in_emulated = emulator_pio_in_emulated,
6135 .pio_out_emulated = emulator_pio_out_emulated,
6136 .get_segment = emulator_get_segment,
6137 .set_segment = emulator_set_segment,
6138 .get_cached_segment_base = emulator_get_cached_segment_base,
6139 .get_gdt = emulator_get_gdt,
6140 .get_idt = emulator_get_idt,
6141 .set_gdt = emulator_set_gdt,
6142 .set_idt = emulator_set_idt,
6143 .get_cr = emulator_get_cr,
6144 .set_cr = emulator_set_cr,
6145 .cpl = emulator_get_cpl,
6146 .get_dr = emulator_get_dr,
6147 .set_dr = emulator_set_dr,
6148 .get_smbase = emulator_get_smbase,
6149 .set_smbase = emulator_set_smbase,
6150 .set_msr = emulator_set_msr,
6151 .get_msr = emulator_get_msr,
6152 .check_pmc = emulator_check_pmc,
6153 .read_pmc = emulator_read_pmc,
6154 .halt = emulator_halt,
6155 .wbinvd = emulator_wbinvd,
6156 .fix_hypercall = emulator_fix_hypercall,
6157 .intercept = emulator_intercept,
6158 .get_cpuid = emulator_get_cpuid,
6159 .set_nmi_mask = emulator_set_nmi_mask,
6160 .get_hflags = emulator_get_hflags,
6161 .set_hflags = emulator_set_hflags,
6162 .pre_leave_smm = emulator_pre_leave_smm,
6163 .post_leave_smm = emulator_post_leave_smm,
6164 .set_xcr = emulator_set_xcr,
6165};
6166
6167static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6168{
6169 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6170 /*
6171 * an sti; sti; sequence only disable interrupts for the first
6172 * instruction. So, if the last instruction, be it emulated or
6173 * not, left the system with the INT_STI flag enabled, it
6174 * means that the last instruction is an sti. We should not
6175 * leave the flag on in this case. The same goes for mov ss
6176 */
6177 if (int_shadow & mask)
6178 mask = 0;
6179 if (unlikely(int_shadow || mask)) {
6180 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6181 if (!mask)
6182 kvm_make_request(KVM_REQ_EVENT, vcpu);
6183 }
6184}
6185
6186static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6187{
6188 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6189 if (ctxt->exception.vector == PF_VECTOR)
6190 return kvm_propagate_fault(vcpu, &ctxt->exception);
6191
6192 if (ctxt->exception.error_code_valid)
6193 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6194 ctxt->exception.error_code);
6195 else
6196 kvm_queue_exception(vcpu, ctxt->exception.vector);
6197 return false;
6198}
6199
6200static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6201{
6202 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6203 int cs_db, cs_l;
6204
6205 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6206
6207 ctxt->eflags = kvm_get_rflags(vcpu);
6208 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6209
6210 ctxt->eip = kvm_rip_read(vcpu);
6211 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6212 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6213 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6214 cs_db ? X86EMUL_MODE_PROT32 :
6215 X86EMUL_MODE_PROT16;
6216 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6217 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6218 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6219
6220 init_decode_cache(ctxt);
6221 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6222}
6223
6224int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6225{
6226 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6227 int ret;
6228
6229 init_emulate_ctxt(vcpu);
6230
6231 ctxt->op_bytes = 2;
6232 ctxt->ad_bytes = 2;
6233 ctxt->_eip = ctxt->eip + inc_eip;
6234 ret = emulate_int_real(ctxt, irq);
6235
6236 if (ret != X86EMUL_CONTINUE)
6237 return EMULATE_FAIL;
6238
6239 ctxt->eip = ctxt->_eip;
6240 kvm_rip_write(vcpu, ctxt->eip);
6241 kvm_set_rflags(vcpu, ctxt->eflags);
6242
6243 return EMULATE_DONE;
6244}
6245EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6246
6247static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6248{
6249 int r = EMULATE_DONE;
6250
6251 ++vcpu->stat.insn_emulation_fail;
6252 trace_kvm_emulate_insn_failed(vcpu);
6253
6254 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6255 return EMULATE_FAIL;
6256
6257 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6258 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6259 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6260 vcpu->run->internal.ndata = 0;
6261 r = EMULATE_USER_EXIT;
6262 }
6263
6264 kvm_queue_exception(vcpu, UD_VECTOR);
6265
6266 return r;
6267}
6268
6269static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6270 bool write_fault_to_shadow_pgtable,
6271 int emulation_type)
6272{
6273 gpa_t gpa = cr2;
6274 kvm_pfn_t pfn;
6275
6276 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6277 return false;
6278
6279 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6280 return false;
6281
6282 if (!vcpu->arch.mmu->direct_map) {
6283 /*
6284 * Write permission should be allowed since only
6285 * write access need to be emulated.
6286 */
6287 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6288
6289 /*
6290 * If the mapping is invalid in guest, let cpu retry
6291 * it to generate fault.
6292 */
6293 if (gpa == UNMAPPED_GVA)
6294 return true;
6295 }
6296
6297 /*
6298 * Do not retry the unhandleable instruction if it faults on the
6299 * readonly host memory, otherwise it will goto a infinite loop:
6300 * retry instruction -> write #PF -> emulation fail -> retry
6301 * instruction -> ...
6302 */
6303 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6304
6305 /*
6306 * If the instruction failed on the error pfn, it can not be fixed,
6307 * report the error to userspace.
6308 */
6309 if (is_error_noslot_pfn(pfn))
6310 return false;
6311
6312 kvm_release_pfn_clean(pfn);
6313
6314 /* The instructions are well-emulated on direct mmu. */
6315 if (vcpu->arch.mmu->direct_map) {
6316 unsigned int indirect_shadow_pages;
6317
6318 spin_lock(&vcpu->kvm->mmu_lock);
6319 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6320 spin_unlock(&vcpu->kvm->mmu_lock);
6321
6322 if (indirect_shadow_pages)
6323 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6324
6325 return true;
6326 }
6327
6328 /*
6329 * if emulation was due to access to shadowed page table
6330 * and it failed try to unshadow page and re-enter the
6331 * guest to let CPU execute the instruction.
6332 */
6333 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6334
6335 /*
6336 * If the access faults on its page table, it can not
6337 * be fixed by unprotecting shadow page and it should
6338 * be reported to userspace.
6339 */
6340 return !write_fault_to_shadow_pgtable;
6341}
6342
6343static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6344 unsigned long cr2, int emulation_type)
6345{
6346 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6347 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6348
6349 last_retry_eip = vcpu->arch.last_retry_eip;
6350 last_retry_addr = vcpu->arch.last_retry_addr;
6351
6352 /*
6353 * If the emulation is caused by #PF and it is non-page_table
6354 * writing instruction, it means the VM-EXIT is caused by shadow
6355 * page protected, we can zap the shadow page and retry this
6356 * instruction directly.
6357 *
6358 * Note: if the guest uses a non-page-table modifying instruction
6359 * on the PDE that points to the instruction, then we will unmap
6360 * the instruction and go to an infinite loop. So, we cache the
6361 * last retried eip and the last fault address, if we meet the eip
6362 * and the address again, we can break out of the potential infinite
6363 * loop.
6364 */
6365 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6366
6367 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6368 return false;
6369
6370 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6371 return false;
6372
6373 if (x86_page_table_writing_insn(ctxt))
6374 return false;
6375
6376 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6377 return false;
6378
6379 vcpu->arch.last_retry_eip = ctxt->eip;
6380 vcpu->arch.last_retry_addr = cr2;
6381
6382 if (!vcpu->arch.mmu->direct_map)
6383 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6384
6385 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6386
6387 return true;
6388}
6389
6390static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6391static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6392
6393static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6394{
6395 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6396 /* This is a good place to trace that we are exiting SMM. */
6397 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6398
6399 /* Process a latched INIT or SMI, if any. */
6400 kvm_make_request(KVM_REQ_EVENT, vcpu);
6401 }
6402
6403 kvm_mmu_reset_context(vcpu);
6404}
6405
6406static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6407 unsigned long *db)
6408{
6409 u32 dr6 = 0;
6410 int i;
6411 u32 enable, rwlen;
6412
6413 enable = dr7;
6414 rwlen = dr7 >> 16;
6415 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6416 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6417 dr6 |= (1 << i);
6418 return dr6;
6419}
6420
6421static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6422{
6423 struct kvm_run *kvm_run = vcpu->run;
6424
6425 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6426 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6427 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6428 kvm_run->debug.arch.exception = DB_VECTOR;
6429 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6430 *r = EMULATE_USER_EXIT;
6431 } else {
6432 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6433 }
6434}
6435
6436int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6437{
6438 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6439 int r;
6440
6441 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6442 if (unlikely(r != EMULATE_DONE))
6443 return 0;
6444
6445 /*
6446 * rflags is the old, "raw" value of the flags. The new value has
6447 * not been saved yet.
6448 *
6449 * This is correct even for TF set by the guest, because "the
6450 * processor will not generate this exception after the instruction
6451 * that sets the TF flag".
6452 */
6453 if (unlikely(rflags & X86_EFLAGS_TF))
6454 kvm_vcpu_do_singlestep(vcpu, &r);
6455 return r == EMULATE_DONE;
6456}
6457EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6458
6459static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6460{
6461 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6462 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6463 struct kvm_run *kvm_run = vcpu->run;
6464 unsigned long eip = kvm_get_linear_rip(vcpu);
6465 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6466 vcpu->arch.guest_debug_dr7,
6467 vcpu->arch.eff_db);
6468
6469 if (dr6 != 0) {
6470 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6471 kvm_run->debug.arch.pc = eip;
6472 kvm_run->debug.arch.exception = DB_VECTOR;
6473 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6474 *r = EMULATE_USER_EXIT;
6475 return true;
6476 }
6477 }
6478
6479 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6480 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6481 unsigned long eip = kvm_get_linear_rip(vcpu);
6482 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6483 vcpu->arch.dr7,
6484 vcpu->arch.db);
6485
6486 if (dr6 != 0) {
6487 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6488 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6489 kvm_queue_exception(vcpu, DB_VECTOR);
6490 *r = EMULATE_DONE;
6491 return true;
6492 }
6493 }
6494
6495 return false;
6496}
6497
6498static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6499{
6500 switch (ctxt->opcode_len) {
6501 case 1:
6502 switch (ctxt->b) {
6503 case 0xe4: /* IN */
6504 case 0xe5:
6505 case 0xec:
6506 case 0xed:
6507 case 0xe6: /* OUT */
6508 case 0xe7:
6509 case 0xee:
6510 case 0xef:
6511 case 0x6c: /* INS */
6512 case 0x6d:
6513 case 0x6e: /* OUTS */
6514 case 0x6f:
6515 return true;
6516 }
6517 break;
6518 case 2:
6519 switch (ctxt->b) {
6520 case 0x33: /* RDPMC */
6521 return true;
6522 }
6523 break;
6524 }
6525
6526 return false;
6527}
6528
6529int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6530 unsigned long cr2,
6531 int emulation_type,
6532 void *insn,
6533 int insn_len)
6534{
6535 int r;
6536 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6537 bool writeback = true;
6538 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6539
6540 vcpu->arch.l1tf_flush_l1d = true;
6541
6542 /*
6543 * Clear write_fault_to_shadow_pgtable here to ensure it is
6544 * never reused.
6545 */
6546 vcpu->arch.write_fault_to_shadow_pgtable = false;
6547 kvm_clear_exception_queue(vcpu);
6548
6549 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6550 init_emulate_ctxt(vcpu);
6551
6552 /*
6553 * We will reenter on the same instruction since
6554 * we do not set complete_userspace_io. This does not
6555 * handle watchpoints yet, those would be handled in
6556 * the emulate_ops.
6557 */
6558 if (!(emulation_type & EMULTYPE_SKIP) &&
6559 kvm_vcpu_check_breakpoint(vcpu, &r))
6560 return r;
6561
6562 ctxt->interruptibility = 0;
6563 ctxt->have_exception = false;
6564 ctxt->exception.vector = -1;
6565 ctxt->perm_ok = false;
6566
6567 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6568
6569 r = x86_decode_insn(ctxt, insn, insn_len);
6570
6571 trace_kvm_emulate_insn_start(vcpu);
6572 ++vcpu->stat.insn_emulation;
6573 if (r != EMULATION_OK) {
6574 if (emulation_type & EMULTYPE_TRAP_UD)
6575 return EMULATE_FAIL;
6576 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6577 emulation_type))
6578 return EMULATE_DONE;
6579 if (ctxt->have_exception) {
6580 inject_emulated_exception(vcpu);
6581 return EMULATE_DONE;
6582 }
6583 if (emulation_type & EMULTYPE_SKIP)
6584 return EMULATE_FAIL;
6585 return handle_emulation_failure(vcpu, emulation_type);
6586 }
6587 }
6588
6589 if ((emulation_type & EMULTYPE_VMWARE) &&
6590 !is_vmware_backdoor_opcode(ctxt))
6591 return EMULATE_FAIL;
6592
6593 if (emulation_type & EMULTYPE_SKIP) {
6594 kvm_rip_write(vcpu, ctxt->_eip);
6595 if (ctxt->eflags & X86_EFLAGS_RF)
6596 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6597 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
6598 return EMULATE_DONE;
6599 }
6600
6601 if (retry_instruction(ctxt, cr2, emulation_type))
6602 return EMULATE_DONE;
6603
6604 /* this is needed for vmware backdoor interface to work since it
6605 changes registers values during IO operation */
6606 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6607 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6608 emulator_invalidate_register_cache(ctxt);
6609 }
6610
6611restart:
6612 /* Save the faulting GPA (cr2) in the address field */
6613 ctxt->exception.address = cr2;
6614
6615 r = x86_emulate_insn(ctxt);
6616
6617 if (r == EMULATION_INTERCEPTED)
6618 return EMULATE_DONE;
6619
6620 if (r == EMULATION_FAILED) {
6621 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6622 emulation_type))
6623 return EMULATE_DONE;
6624
6625 return handle_emulation_failure(vcpu, emulation_type);
6626 }
6627
6628 if (ctxt->have_exception) {
6629 r = EMULATE_DONE;
6630 if (inject_emulated_exception(vcpu))
6631 return r;
6632 } else if (vcpu->arch.pio.count) {
6633 if (!vcpu->arch.pio.in) {
6634 /* FIXME: return into emulator if single-stepping. */
6635 vcpu->arch.pio.count = 0;
6636 } else {
6637 writeback = false;
6638 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6639 }
6640 r = EMULATE_USER_EXIT;
6641 } else if (vcpu->mmio_needed) {
6642 if (!vcpu->mmio_is_write)
6643 writeback = false;
6644 r = EMULATE_USER_EXIT;
6645 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6646 } else if (r == EMULATION_RESTART)
6647 goto restart;
6648 else
6649 r = EMULATE_DONE;
6650
6651 if (writeback) {
6652 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6653 toggle_interruptibility(vcpu, ctxt->interruptibility);
6654 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6655 kvm_rip_write(vcpu, ctxt->eip);
6656 if (r == EMULATE_DONE && ctxt->tf)
6657 kvm_vcpu_do_singlestep(vcpu, &r);
6658 if (!ctxt->have_exception ||
6659 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6660 __kvm_set_rflags(vcpu, ctxt->eflags);
6661
6662 /*
6663 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6664 * do nothing, and it will be requested again as soon as
6665 * the shadow expires. But we still need to check here,
6666 * because POPF has no interrupt shadow.
6667 */
6668 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6669 kvm_make_request(KVM_REQ_EVENT, vcpu);
6670 } else
6671 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6672
6673 return r;
6674}
6675
6676int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6677{
6678 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6679}
6680EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6681
6682int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6683 void *insn, int insn_len)
6684{
6685 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6686}
6687EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6688
6689static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6690{
6691 vcpu->arch.pio.count = 0;
6692 return 1;
6693}
6694
6695static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6696{
6697 vcpu->arch.pio.count = 0;
6698
6699 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6700 return 1;
6701
6702 return kvm_skip_emulated_instruction(vcpu);
6703}
6704
6705static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6706 unsigned short port)
6707{
6708 unsigned long val = kvm_rax_read(vcpu);
6709 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6710 size, port, &val, 1);
6711 if (ret)
6712 return ret;
6713
6714 /*
6715 * Workaround userspace that relies on old KVM behavior of %rip being
6716 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6717 */
6718 if (port == 0x7e &&
6719 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6720 vcpu->arch.complete_userspace_io =
6721 complete_fast_pio_out_port_0x7e;
6722 kvm_skip_emulated_instruction(vcpu);
6723 } else {
6724 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6725 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6726 }
6727 return 0;
6728}
6729
6730static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6731{
6732 unsigned long val;
6733
6734 /* We should only ever be called with arch.pio.count equal to 1 */
6735 BUG_ON(vcpu->arch.pio.count != 1);
6736
6737 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6738 vcpu->arch.pio.count = 0;
6739 return 1;
6740 }
6741
6742 /* For size less than 4 we merge, else we zero extend */
6743 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6744
6745 /*
6746 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6747 * the copy and tracing
6748 */
6749 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6750 vcpu->arch.pio.port, &val, 1);
6751 kvm_rax_write(vcpu, val);
6752
6753 return kvm_skip_emulated_instruction(vcpu);
6754}
6755
6756static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6757 unsigned short port)
6758{
6759 unsigned long val;
6760 int ret;
6761
6762 /* For size less than 4 we merge, else we zero extend */
6763 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6764
6765 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6766 &val, 1);
6767 if (ret) {
6768 kvm_rax_write(vcpu, val);
6769 return ret;
6770 }
6771
6772 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6773 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6774
6775 return 0;
6776}
6777
6778int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6779{
6780 int ret;
6781
6782 if (in)
6783 ret = kvm_fast_pio_in(vcpu, size, port);
6784 else
6785 ret = kvm_fast_pio_out(vcpu, size, port);
6786 return ret && kvm_skip_emulated_instruction(vcpu);
6787}
6788EXPORT_SYMBOL_GPL(kvm_fast_pio);
6789
6790static int kvmclock_cpu_down_prep(unsigned int cpu)
6791{
6792 __this_cpu_write(cpu_tsc_khz, 0);
6793 return 0;
6794}
6795
6796static void tsc_khz_changed(void *data)
6797{
6798 struct cpufreq_freqs *freq = data;
6799 unsigned long khz = 0;
6800
6801 if (data)
6802 khz = freq->new;
6803 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6804 khz = cpufreq_quick_get(raw_smp_processor_id());
6805 if (!khz)
6806 khz = tsc_khz;
6807 __this_cpu_write(cpu_tsc_khz, khz);
6808}
6809
6810#ifdef CONFIG_X86_64
6811static void kvm_hyperv_tsc_notifier(void)
6812{
6813 struct kvm *kvm;
6814 struct kvm_vcpu *vcpu;
6815 int cpu;
6816
6817 mutex_lock(&kvm_lock);
6818 list_for_each_entry(kvm, &vm_list, vm_list)
6819 kvm_make_mclock_inprogress_request(kvm);
6820
6821 hyperv_stop_tsc_emulation();
6822
6823 /* TSC frequency always matches when on Hyper-V */
6824 for_each_present_cpu(cpu)
6825 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6826 kvm_max_guest_tsc_khz = tsc_khz;
6827
6828 list_for_each_entry(kvm, &vm_list, vm_list) {
6829 struct kvm_arch *ka = &kvm->arch;
6830
6831 spin_lock(&ka->pvclock_gtod_sync_lock);
6832
6833 pvclock_update_vm_gtod_copy(kvm);
6834
6835 kvm_for_each_vcpu(cpu, vcpu, kvm)
6836 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6837
6838 kvm_for_each_vcpu(cpu, vcpu, kvm)
6839 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6840
6841 spin_unlock(&ka->pvclock_gtod_sync_lock);
6842 }
6843 mutex_unlock(&kvm_lock);
6844}
6845#endif
6846
6847static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6848{
6849 struct kvm *kvm;
6850 struct kvm_vcpu *vcpu;
6851 int i, send_ipi = 0;
6852
6853 /*
6854 * We allow guests to temporarily run on slowing clocks,
6855 * provided we notify them after, or to run on accelerating
6856 * clocks, provided we notify them before. Thus time never
6857 * goes backwards.
6858 *
6859 * However, we have a problem. We can't atomically update
6860 * the frequency of a given CPU from this function; it is
6861 * merely a notifier, which can be called from any CPU.
6862 * Changing the TSC frequency at arbitrary points in time
6863 * requires a recomputation of local variables related to
6864 * the TSC for each VCPU. We must flag these local variables
6865 * to be updated and be sure the update takes place with the
6866 * new frequency before any guests proceed.
6867 *
6868 * Unfortunately, the combination of hotplug CPU and frequency
6869 * change creates an intractable locking scenario; the order
6870 * of when these callouts happen is undefined with respect to
6871 * CPU hotplug, and they can race with each other. As such,
6872 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6873 * undefined; you can actually have a CPU frequency change take
6874 * place in between the computation of X and the setting of the
6875 * variable. To protect against this problem, all updates of
6876 * the per_cpu tsc_khz variable are done in an interrupt
6877 * protected IPI, and all callers wishing to update the value
6878 * must wait for a synchronous IPI to complete (which is trivial
6879 * if the caller is on the CPU already). This establishes the
6880 * necessary total order on variable updates.
6881 *
6882 * Note that because a guest time update may take place
6883 * anytime after the setting of the VCPU's request bit, the
6884 * correct TSC value must be set before the request. However,
6885 * to ensure the update actually makes it to any guest which
6886 * starts running in hardware virtualization between the set
6887 * and the acquisition of the spinlock, we must also ping the
6888 * CPU after setting the request bit.
6889 *
6890 */
6891
6892 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6893
6894 mutex_lock(&kvm_lock);
6895 list_for_each_entry(kvm, &vm_list, vm_list) {
6896 kvm_for_each_vcpu(i, vcpu, kvm) {
6897 if (vcpu->cpu != cpu)
6898 continue;
6899 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6900 if (vcpu->cpu != raw_smp_processor_id())
6901 send_ipi = 1;
6902 }
6903 }
6904 mutex_unlock(&kvm_lock);
6905
6906 if (freq->old < freq->new && send_ipi) {
6907 /*
6908 * We upscale the frequency. Must make the guest
6909 * doesn't see old kvmclock values while running with
6910 * the new frequency, otherwise we risk the guest sees
6911 * time go backwards.
6912 *
6913 * In case we update the frequency for another cpu
6914 * (which might be in guest context) send an interrupt
6915 * to kick the cpu out of guest context. Next time
6916 * guest context is entered kvmclock will be updated,
6917 * so the guest will not see stale values.
6918 */
6919 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6920 }
6921}
6922
6923static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6924 void *data)
6925{
6926 struct cpufreq_freqs *freq = data;
6927 int cpu;
6928
6929 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6930 return 0;
6931 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6932 return 0;
6933
6934 for_each_cpu(cpu, freq->policy->cpus)
6935 __kvmclock_cpufreq_notifier(freq, cpu);
6936
6937 return 0;
6938}
6939
6940static struct notifier_block kvmclock_cpufreq_notifier_block = {
6941 .notifier_call = kvmclock_cpufreq_notifier
6942};
6943
6944static int kvmclock_cpu_online(unsigned int cpu)
6945{
6946 tsc_khz_changed(NULL);
6947 return 0;
6948}
6949
6950static void kvm_timer_init(void)
6951{
6952 max_tsc_khz = tsc_khz;
6953
6954 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6955#ifdef CONFIG_CPU_FREQ
6956 struct cpufreq_policy policy;
6957 int cpu;
6958
6959 memset(&policy, 0, sizeof(policy));
6960 cpu = get_cpu();
6961 cpufreq_get_policy(&policy, cpu);
6962 if (policy.cpuinfo.max_freq)
6963 max_tsc_khz = policy.cpuinfo.max_freq;
6964 put_cpu();
6965#endif
6966 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6967 CPUFREQ_TRANSITION_NOTIFIER);
6968 }
6969
6970 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6971 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6972}
6973
6974DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6975EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6976
6977int kvm_is_in_guest(void)
6978{
6979 return __this_cpu_read(current_vcpu) != NULL;
6980}
6981
6982static int kvm_is_user_mode(void)
6983{
6984 int user_mode = 3;
6985
6986 if (__this_cpu_read(current_vcpu))
6987 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6988
6989 return user_mode != 0;
6990}
6991
6992static unsigned long kvm_get_guest_ip(void)
6993{
6994 unsigned long ip = 0;
6995
6996 if (__this_cpu_read(current_vcpu))
6997 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6998
6999 return ip;
7000}
7001
7002static void kvm_handle_intel_pt_intr(void)
7003{
7004 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7005
7006 kvm_make_request(KVM_REQ_PMI, vcpu);
7007 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7008 (unsigned long *)&vcpu->arch.pmu.global_status);
7009}
7010
7011static struct perf_guest_info_callbacks kvm_guest_cbs = {
7012 .is_in_guest = kvm_is_in_guest,
7013 .is_user_mode = kvm_is_user_mode,
7014 .get_guest_ip = kvm_get_guest_ip,
7015 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7016};
7017
7018#ifdef CONFIG_X86_64
7019static void pvclock_gtod_update_fn(struct work_struct *work)
7020{
7021 struct kvm *kvm;
7022
7023 struct kvm_vcpu *vcpu;
7024 int i;
7025
7026 mutex_lock(&kvm_lock);
7027 list_for_each_entry(kvm, &vm_list, vm_list)
7028 kvm_for_each_vcpu(i, vcpu, kvm)
7029 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7030 atomic_set(&kvm_guest_has_master_clock, 0);
7031 mutex_unlock(&kvm_lock);
7032}
7033
7034static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7035
7036/*
7037 * Notification about pvclock gtod data update.
7038 */
7039static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7040 void *priv)
7041{
7042 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7043 struct timekeeper *tk = priv;
7044
7045 update_pvclock_gtod(tk);
7046
7047 /* disable master clock if host does not trust, or does not
7048 * use, TSC based clocksource.
7049 */
7050 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7051 atomic_read(&kvm_guest_has_master_clock) != 0)
7052 queue_work(system_long_wq, &pvclock_gtod_work);
7053
7054 return 0;
7055}
7056
7057static struct notifier_block pvclock_gtod_notifier = {
7058 .notifier_call = pvclock_gtod_notify,
7059};
7060#endif
7061
7062int kvm_arch_init(void *opaque)
7063{
7064 int r;
7065 struct kvm_x86_ops *ops = opaque;
7066
7067 if (kvm_x86_ops) {
7068 printk(KERN_ERR "kvm: already loaded the other module\n");
7069 r = -EEXIST;
7070 goto out;
7071 }
7072
7073 if (!ops->cpu_has_kvm_support()) {
7074 printk(KERN_ERR "kvm: no hardware support\n");
7075 r = -EOPNOTSUPP;
7076 goto out;
7077 }
7078 if (ops->disabled_by_bios()) {
7079 printk(KERN_ERR "kvm: disabled by bios\n");
7080 r = -EOPNOTSUPP;
7081 goto out;
7082 }
7083
7084 /*
7085 * KVM explicitly assumes that the guest has an FPU and
7086 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7087 * vCPU's FPU state as a fxregs_state struct.
7088 */
7089 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7090 printk(KERN_ERR "kvm: inadequate fpu\n");
7091 r = -EOPNOTSUPP;
7092 goto out;
7093 }
7094
7095 r = -ENOMEM;
7096 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7097 __alignof__(struct fpu), SLAB_ACCOUNT,
7098 NULL);
7099 if (!x86_fpu_cache) {
7100 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7101 goto out;
7102 }
7103
7104 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7105 if (!shared_msrs) {
7106 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7107 goto out_free_x86_fpu_cache;
7108 }
7109
7110 r = kvm_mmu_module_init();
7111 if (r)
7112 goto out_free_percpu;
7113
7114 kvm_x86_ops = ops;
7115
7116 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7117 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7118 PT_PRESENT_MASK, 0, sme_me_mask);
7119 kvm_timer_init();
7120
7121 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7122
7123 if (boot_cpu_has(X86_FEATURE_XSAVE))
7124 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7125
7126 kvm_lapic_init();
7127 if (pi_inject_timer == -1)
7128 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7129#ifdef CONFIG_X86_64
7130 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7131
7132 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7133 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7134#endif
7135
7136 return 0;
7137
7138out_free_percpu:
7139 free_percpu(shared_msrs);
7140out_free_x86_fpu_cache:
7141 kmem_cache_destroy(x86_fpu_cache);
7142out:
7143 return r;
7144}
7145
7146void kvm_arch_exit(void)
7147{
7148#ifdef CONFIG_X86_64
7149 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7150 clear_hv_tscchange_cb();
7151#endif
7152 kvm_lapic_exit();
7153 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7154
7155 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7156 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7157 CPUFREQ_TRANSITION_NOTIFIER);
7158 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7159#ifdef CONFIG_X86_64
7160 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7161#endif
7162 kvm_x86_ops = NULL;
7163 kvm_mmu_module_exit();
7164 free_percpu(shared_msrs);
7165 kmem_cache_destroy(x86_fpu_cache);
7166}
7167
7168int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7169{
7170 ++vcpu->stat.halt_exits;
7171 if (lapic_in_kernel(vcpu)) {
7172 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7173 return 1;
7174 } else {
7175 vcpu->run->exit_reason = KVM_EXIT_HLT;
7176 return 0;
7177 }
7178}
7179EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7180
7181int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7182{
7183 int ret = kvm_skip_emulated_instruction(vcpu);
7184 /*
7185 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7186 * KVM_EXIT_DEBUG here.
7187 */
7188 return kvm_vcpu_halt(vcpu) && ret;
7189}
7190EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7191
7192#ifdef CONFIG_X86_64
7193static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7194 unsigned long clock_type)
7195{
7196 struct kvm_clock_pairing clock_pairing;
7197 struct timespec64 ts;
7198 u64 cycle;
7199 int ret;
7200
7201 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7202 return -KVM_EOPNOTSUPP;
7203
7204 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7205 return -KVM_EOPNOTSUPP;
7206
7207 clock_pairing.sec = ts.tv_sec;
7208 clock_pairing.nsec = ts.tv_nsec;
7209 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7210 clock_pairing.flags = 0;
7211 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7212
7213 ret = 0;
7214 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7215 sizeof(struct kvm_clock_pairing)))
7216 ret = -KVM_EFAULT;
7217
7218 return ret;
7219}
7220#endif
7221
7222/*
7223 * kvm_pv_kick_cpu_op: Kick a vcpu.
7224 *
7225 * @apicid - apicid of vcpu to be kicked.
7226 */
7227static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7228{
7229 struct kvm_lapic_irq lapic_irq;
7230
7231 lapic_irq.shorthand = 0;
7232 lapic_irq.dest_mode = 0;
7233 lapic_irq.level = 0;
7234 lapic_irq.dest_id = apicid;
7235 lapic_irq.msi_redir_hint = false;
7236
7237 lapic_irq.delivery_mode = APIC_DM_REMRD;
7238 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7239}
7240
7241void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7242{
7243 if (!lapic_in_kernel(vcpu)) {
7244 WARN_ON_ONCE(vcpu->arch.apicv_active);
7245 return;
7246 }
7247 if (!vcpu->arch.apicv_active)
7248 return;
7249
7250 vcpu->arch.apicv_active = false;
7251 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7252}
7253
7254static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7255{
7256 struct kvm_vcpu *target = NULL;
7257 struct kvm_apic_map *map;
7258
7259 rcu_read_lock();
7260 map = rcu_dereference(kvm->arch.apic_map);
7261
7262 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7263 target = map->phys_map[dest_id]->vcpu;
7264
7265 rcu_read_unlock();
7266
7267 if (target && READ_ONCE(target->ready))
7268 kvm_vcpu_yield_to(target);
7269}
7270
7271int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7272{
7273 unsigned long nr, a0, a1, a2, a3, ret;
7274 int op_64_bit;
7275
7276 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7277 return kvm_hv_hypercall(vcpu);
7278
7279 nr = kvm_rax_read(vcpu);
7280 a0 = kvm_rbx_read(vcpu);
7281 a1 = kvm_rcx_read(vcpu);
7282 a2 = kvm_rdx_read(vcpu);
7283 a3 = kvm_rsi_read(vcpu);
7284
7285 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7286
7287 op_64_bit = is_64_bit_mode(vcpu);
7288 if (!op_64_bit) {
7289 nr &= 0xFFFFFFFF;
7290 a0 &= 0xFFFFFFFF;
7291 a1 &= 0xFFFFFFFF;
7292 a2 &= 0xFFFFFFFF;
7293 a3 &= 0xFFFFFFFF;
7294 }
7295
7296 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7297 ret = -KVM_EPERM;
7298 goto out;
7299 }
7300
7301 switch (nr) {
7302 case KVM_HC_VAPIC_POLL_IRQ:
7303 ret = 0;
7304 break;
7305 case KVM_HC_KICK_CPU:
7306 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7307 kvm_sched_yield(vcpu->kvm, a1);
7308 ret = 0;
7309 break;
7310#ifdef CONFIG_X86_64
7311 case KVM_HC_CLOCK_PAIRING:
7312 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7313 break;
7314#endif
7315 case KVM_HC_SEND_IPI:
7316 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7317 break;
7318 case KVM_HC_SCHED_YIELD:
7319 kvm_sched_yield(vcpu->kvm, a0);
7320 ret = 0;
7321 break;
7322 default:
7323 ret = -KVM_ENOSYS;
7324 break;
7325 }
7326out:
7327 if (!op_64_bit)
7328 ret = (u32)ret;
7329 kvm_rax_write(vcpu, ret);
7330
7331 ++vcpu->stat.hypercalls;
7332 return kvm_skip_emulated_instruction(vcpu);
7333}
7334EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7335
7336static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7337{
7338 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7339 char instruction[3];
7340 unsigned long rip = kvm_rip_read(vcpu);
7341
7342 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7343
7344 return emulator_write_emulated(ctxt, rip, instruction, 3,
7345 &ctxt->exception);
7346}
7347
7348static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7349{
7350 return vcpu->run->request_interrupt_window &&
7351 likely(!pic_in_kernel(vcpu->kvm));
7352}
7353
7354static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7355{
7356 struct kvm_run *kvm_run = vcpu->run;
7357
7358 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7359 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7360 kvm_run->cr8 = kvm_get_cr8(vcpu);
7361 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7362 kvm_run->ready_for_interrupt_injection =
7363 pic_in_kernel(vcpu->kvm) ||
7364 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7365}
7366
7367static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7368{
7369 int max_irr, tpr;
7370
7371 if (!kvm_x86_ops->update_cr8_intercept)
7372 return;
7373
7374 if (!lapic_in_kernel(vcpu))
7375 return;
7376
7377 if (vcpu->arch.apicv_active)
7378 return;
7379
7380 if (!vcpu->arch.apic->vapic_addr)
7381 max_irr = kvm_lapic_find_highest_irr(vcpu);
7382 else
7383 max_irr = -1;
7384
7385 if (max_irr != -1)
7386 max_irr >>= 4;
7387
7388 tpr = kvm_lapic_get_cr8(vcpu);
7389
7390 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7391}
7392
7393static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7394{
7395 int r;
7396
7397 /* try to reinject previous events if any */
7398
7399 if (vcpu->arch.exception.injected)
7400 kvm_x86_ops->queue_exception(vcpu);
7401 /*
7402 * Do not inject an NMI or interrupt if there is a pending
7403 * exception. Exceptions and interrupts are recognized at
7404 * instruction boundaries, i.e. the start of an instruction.
7405 * Trap-like exceptions, e.g. #DB, have higher priority than
7406 * NMIs and interrupts, i.e. traps are recognized before an
7407 * NMI/interrupt that's pending on the same instruction.
7408 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7409 * priority, but are only generated (pended) during instruction
7410 * execution, i.e. a pending fault-like exception means the
7411 * fault occurred on the *previous* instruction and must be
7412 * serviced prior to recognizing any new events in order to
7413 * fully complete the previous instruction.
7414 */
7415 else if (!vcpu->arch.exception.pending) {
7416 if (vcpu->arch.nmi_injected)
7417 kvm_x86_ops->set_nmi(vcpu);
7418 else if (vcpu->arch.interrupt.injected)
7419 kvm_x86_ops->set_irq(vcpu);
7420 }
7421
7422 /*
7423 * Call check_nested_events() even if we reinjected a previous event
7424 * in order for caller to determine if it should require immediate-exit
7425 * from L2 to L1 due to pending L1 events which require exit
7426 * from L2 to L1.
7427 */
7428 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7429 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7430 if (r != 0)
7431 return r;
7432 }
7433
7434 /* try to inject new event if pending */
7435 if (vcpu->arch.exception.pending) {
7436 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7437 vcpu->arch.exception.has_error_code,
7438 vcpu->arch.exception.error_code);
7439
7440 WARN_ON_ONCE(vcpu->arch.exception.injected);
7441 vcpu->arch.exception.pending = false;
7442 vcpu->arch.exception.injected = true;
7443
7444 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7445 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7446 X86_EFLAGS_RF);
7447
7448 if (vcpu->arch.exception.nr == DB_VECTOR) {
7449 /*
7450 * This code assumes that nSVM doesn't use
7451 * check_nested_events(). If it does, the
7452 * DR6/DR7 changes should happen before L1
7453 * gets a #VMEXIT for an intercepted #DB in
7454 * L2. (Under VMX, on the other hand, the
7455 * DR6/DR7 changes should not happen in the
7456 * event of a VM-exit to L1 for an intercepted
7457 * #DB in L2.)
7458 */
7459 kvm_deliver_exception_payload(vcpu);
7460 if (vcpu->arch.dr7 & DR7_GD) {
7461 vcpu->arch.dr7 &= ~DR7_GD;
7462 kvm_update_dr7(vcpu);
7463 }
7464 }
7465
7466 kvm_x86_ops->queue_exception(vcpu);
7467 }
7468
7469 /* Don't consider new event if we re-injected an event */
7470 if (kvm_event_needs_reinjection(vcpu))
7471 return 0;
7472
7473 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7474 kvm_x86_ops->smi_allowed(vcpu)) {
7475 vcpu->arch.smi_pending = false;
7476 ++vcpu->arch.smi_count;
7477 enter_smm(vcpu);
7478 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7479 --vcpu->arch.nmi_pending;
7480 vcpu->arch.nmi_injected = true;
7481 kvm_x86_ops->set_nmi(vcpu);
7482 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7483 /*
7484 * Because interrupts can be injected asynchronously, we are
7485 * calling check_nested_events again here to avoid a race condition.
7486 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7487 * proposal and current concerns. Perhaps we should be setting
7488 * KVM_REQ_EVENT only on certain events and not unconditionally?
7489 */
7490 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7491 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7492 if (r != 0)
7493 return r;
7494 }
7495 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7496 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7497 false);
7498 kvm_x86_ops->set_irq(vcpu);
7499 }
7500 }
7501
7502 return 0;
7503}
7504
7505static void process_nmi(struct kvm_vcpu *vcpu)
7506{
7507 unsigned limit = 2;
7508
7509 /*
7510 * x86 is limited to one NMI running, and one NMI pending after it.
7511 * If an NMI is already in progress, limit further NMIs to just one.
7512 * Otherwise, allow two (and we'll inject the first one immediately).
7513 */
7514 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7515 limit = 1;
7516
7517 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7518 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7519 kvm_make_request(KVM_REQ_EVENT, vcpu);
7520}
7521
7522static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7523{
7524 u32 flags = 0;
7525 flags |= seg->g << 23;
7526 flags |= seg->db << 22;
7527 flags |= seg->l << 21;
7528 flags |= seg->avl << 20;
7529 flags |= seg->present << 15;
7530 flags |= seg->dpl << 13;
7531 flags |= seg->s << 12;
7532 flags |= seg->type << 8;
7533 return flags;
7534}
7535
7536static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7537{
7538 struct kvm_segment seg;
7539 int offset;
7540
7541 kvm_get_segment(vcpu, &seg, n);
7542 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7543
7544 if (n < 3)
7545 offset = 0x7f84 + n * 12;
7546 else
7547 offset = 0x7f2c + (n - 3) * 12;
7548
7549 put_smstate(u32, buf, offset + 8, seg.base);
7550 put_smstate(u32, buf, offset + 4, seg.limit);
7551 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7552}
7553
7554#ifdef CONFIG_X86_64
7555static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7556{
7557 struct kvm_segment seg;
7558 int offset;
7559 u16 flags;
7560
7561 kvm_get_segment(vcpu, &seg, n);
7562 offset = 0x7e00 + n * 16;
7563
7564 flags = enter_smm_get_segment_flags(&seg) >> 8;
7565 put_smstate(u16, buf, offset, seg.selector);
7566 put_smstate(u16, buf, offset + 2, flags);
7567 put_smstate(u32, buf, offset + 4, seg.limit);
7568 put_smstate(u64, buf, offset + 8, seg.base);
7569}
7570#endif
7571
7572static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7573{
7574 struct desc_ptr dt;
7575 struct kvm_segment seg;
7576 unsigned long val;
7577 int i;
7578
7579 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7580 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7581 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7582 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7583
7584 for (i = 0; i < 8; i++)
7585 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7586
7587 kvm_get_dr(vcpu, 6, &val);
7588 put_smstate(u32, buf, 0x7fcc, (u32)val);
7589 kvm_get_dr(vcpu, 7, &val);
7590 put_smstate(u32, buf, 0x7fc8, (u32)val);
7591
7592 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7593 put_smstate(u32, buf, 0x7fc4, seg.selector);
7594 put_smstate(u32, buf, 0x7f64, seg.base);
7595 put_smstate(u32, buf, 0x7f60, seg.limit);
7596 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7597
7598 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7599 put_smstate(u32, buf, 0x7fc0, seg.selector);
7600 put_smstate(u32, buf, 0x7f80, seg.base);
7601 put_smstate(u32, buf, 0x7f7c, seg.limit);
7602 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7603
7604 kvm_x86_ops->get_gdt(vcpu, &dt);
7605 put_smstate(u32, buf, 0x7f74, dt.address);
7606 put_smstate(u32, buf, 0x7f70, dt.size);
7607
7608 kvm_x86_ops->get_idt(vcpu, &dt);
7609 put_smstate(u32, buf, 0x7f58, dt.address);
7610 put_smstate(u32, buf, 0x7f54, dt.size);
7611
7612 for (i = 0; i < 6; i++)
7613 enter_smm_save_seg_32(vcpu, buf, i);
7614
7615 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7616
7617 /* revision id */
7618 put_smstate(u32, buf, 0x7efc, 0x00020000);
7619 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7620}
7621
7622#ifdef CONFIG_X86_64
7623static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7624{
7625 struct desc_ptr dt;
7626 struct kvm_segment seg;
7627 unsigned long val;
7628 int i;
7629
7630 for (i = 0; i < 16; i++)
7631 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7632
7633 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7634 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7635
7636 kvm_get_dr(vcpu, 6, &val);
7637 put_smstate(u64, buf, 0x7f68, val);
7638 kvm_get_dr(vcpu, 7, &val);
7639 put_smstate(u64, buf, 0x7f60, val);
7640
7641 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7642 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7643 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7644
7645 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7646
7647 /* revision id */
7648 put_smstate(u32, buf, 0x7efc, 0x00020064);
7649
7650 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7651
7652 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7653 put_smstate(u16, buf, 0x7e90, seg.selector);
7654 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7655 put_smstate(u32, buf, 0x7e94, seg.limit);
7656 put_smstate(u64, buf, 0x7e98, seg.base);
7657
7658 kvm_x86_ops->get_idt(vcpu, &dt);
7659 put_smstate(u32, buf, 0x7e84, dt.size);
7660 put_smstate(u64, buf, 0x7e88, dt.address);
7661
7662 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7663 put_smstate(u16, buf, 0x7e70, seg.selector);
7664 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7665 put_smstate(u32, buf, 0x7e74, seg.limit);
7666 put_smstate(u64, buf, 0x7e78, seg.base);
7667
7668 kvm_x86_ops->get_gdt(vcpu, &dt);
7669 put_smstate(u32, buf, 0x7e64, dt.size);
7670 put_smstate(u64, buf, 0x7e68, dt.address);
7671
7672 for (i = 0; i < 6; i++)
7673 enter_smm_save_seg_64(vcpu, buf, i);
7674}
7675#endif
7676
7677static void enter_smm(struct kvm_vcpu *vcpu)
7678{
7679 struct kvm_segment cs, ds;
7680 struct desc_ptr dt;
7681 char buf[512];
7682 u32 cr0;
7683
7684 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7685 memset(buf, 0, 512);
7686#ifdef CONFIG_X86_64
7687 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7688 enter_smm_save_state_64(vcpu, buf);
7689 else
7690#endif
7691 enter_smm_save_state_32(vcpu, buf);
7692
7693 /*
7694 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7695 * vCPU state (e.g. leave guest mode) after we've saved the state into
7696 * the SMM state-save area.
7697 */
7698 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7699
7700 vcpu->arch.hflags |= HF_SMM_MASK;
7701 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7702
7703 if (kvm_x86_ops->get_nmi_mask(vcpu))
7704 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7705 else
7706 kvm_x86_ops->set_nmi_mask(vcpu, true);
7707
7708 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7709 kvm_rip_write(vcpu, 0x8000);
7710
7711 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7712 kvm_x86_ops->set_cr0(vcpu, cr0);
7713 vcpu->arch.cr0 = cr0;
7714
7715 kvm_x86_ops->set_cr4(vcpu, 0);
7716
7717 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7718 dt.address = dt.size = 0;
7719 kvm_x86_ops->set_idt(vcpu, &dt);
7720
7721 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7722
7723 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7724 cs.base = vcpu->arch.smbase;
7725
7726 ds.selector = 0;
7727 ds.base = 0;
7728
7729 cs.limit = ds.limit = 0xffffffff;
7730 cs.type = ds.type = 0x3;
7731 cs.dpl = ds.dpl = 0;
7732 cs.db = ds.db = 0;
7733 cs.s = ds.s = 1;
7734 cs.l = ds.l = 0;
7735 cs.g = ds.g = 1;
7736 cs.avl = ds.avl = 0;
7737 cs.present = ds.present = 1;
7738 cs.unusable = ds.unusable = 0;
7739 cs.padding = ds.padding = 0;
7740
7741 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7742 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7743 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7744 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7745 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7746 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7747
7748#ifdef CONFIG_X86_64
7749 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7750 kvm_x86_ops->set_efer(vcpu, 0);
7751#endif
7752
7753 kvm_update_cpuid(vcpu);
7754 kvm_mmu_reset_context(vcpu);
7755}
7756
7757static void process_smi(struct kvm_vcpu *vcpu)
7758{
7759 vcpu->arch.smi_pending = true;
7760 kvm_make_request(KVM_REQ_EVENT, vcpu);
7761}
7762
7763void kvm_make_scan_ioapic_request(struct kvm *kvm)
7764{
7765 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7766}
7767
7768static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7769{
7770 if (!kvm_apic_present(vcpu))
7771 return;
7772
7773 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7774
7775 if (irqchip_split(vcpu->kvm))
7776 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7777 else {
7778 if (vcpu->arch.apicv_active)
7779 kvm_x86_ops->sync_pir_to_irr(vcpu);
7780 if (ioapic_in_kernel(vcpu->kvm))
7781 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7782 }
7783
7784 if (is_guest_mode(vcpu))
7785 vcpu->arch.load_eoi_exitmap_pending = true;
7786 else
7787 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7788}
7789
7790static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7791{
7792 u64 eoi_exit_bitmap[4];
7793
7794 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7795 return;
7796
7797 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7798 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7799 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7800}
7801
7802int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7803 unsigned long start, unsigned long end,
7804 bool blockable)
7805{
7806 unsigned long apic_address;
7807
7808 /*
7809 * The physical address of apic access page is stored in the VMCS.
7810 * Update it when it becomes invalid.
7811 */
7812 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7813 if (start <= apic_address && apic_address < end)
7814 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7815
7816 return 0;
7817}
7818
7819void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7820{
7821 struct page *page = NULL;
7822
7823 if (!lapic_in_kernel(vcpu))
7824 return;
7825
7826 if (!kvm_x86_ops->set_apic_access_page_addr)
7827 return;
7828
7829 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7830 if (is_error_page(page))
7831 return;
7832 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7833
7834 /*
7835 * Do not pin apic access page in memory, the MMU notifier
7836 * will call us again if it is migrated or swapped out.
7837 */
7838 put_page(page);
7839}
7840EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7841
7842void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7843{
7844 smp_send_reschedule(vcpu->cpu);
7845}
7846EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7847
7848/*
7849 * Returns 1 to let vcpu_run() continue the guest execution loop without
7850 * exiting to the userspace. Otherwise, the value will be returned to the
7851 * userspace.
7852 */
7853static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7854{
7855 int r;
7856 bool req_int_win =
7857 dm_request_for_irq_injection(vcpu) &&
7858 kvm_cpu_accept_dm_intr(vcpu);
7859
7860 bool req_immediate_exit = false;
7861
7862 if (kvm_request_pending(vcpu)) {
7863 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7864 kvm_x86_ops->get_vmcs12_pages(vcpu);
7865 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7866 kvm_mmu_unload(vcpu);
7867 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7868 __kvm_migrate_timers(vcpu);
7869 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7870 kvm_gen_update_masterclock(vcpu->kvm);
7871 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7872 kvm_gen_kvmclock_update(vcpu);
7873 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7874 r = kvm_guest_time_update(vcpu);
7875 if (unlikely(r))
7876 goto out;
7877 }
7878 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7879 kvm_mmu_sync_roots(vcpu);
7880 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7881 kvm_mmu_load_cr3(vcpu);
7882 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7883 kvm_vcpu_flush_tlb(vcpu, true);
7884 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7885 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7886 r = 0;
7887 goto out;
7888 }
7889 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7890 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7891 vcpu->mmio_needed = 0;
7892 r = 0;
7893 goto out;
7894 }
7895 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7896 /* Page is swapped out. Do synthetic halt */
7897 vcpu->arch.apf.halted = true;
7898 r = 1;
7899 goto out;
7900 }
7901 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7902 record_steal_time(vcpu);
7903 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7904 process_smi(vcpu);
7905 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7906 process_nmi(vcpu);
7907 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7908 kvm_pmu_handle_event(vcpu);
7909 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7910 kvm_pmu_deliver_pmi(vcpu);
7911 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7912 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7913 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7914 vcpu->arch.ioapic_handled_vectors)) {
7915 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7916 vcpu->run->eoi.vector =
7917 vcpu->arch.pending_ioapic_eoi;
7918 r = 0;
7919 goto out;
7920 }
7921 }
7922 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7923 vcpu_scan_ioapic(vcpu);
7924 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7925 vcpu_load_eoi_exitmap(vcpu);
7926 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7927 kvm_vcpu_reload_apic_access_page(vcpu);
7928 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7929 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7930 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7931 r = 0;
7932 goto out;
7933 }
7934 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7935 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7936 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7937 r = 0;
7938 goto out;
7939 }
7940 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7941 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7942 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7943 r = 0;
7944 goto out;
7945 }
7946
7947 /*
7948 * KVM_REQ_HV_STIMER has to be processed after
7949 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7950 * depend on the guest clock being up-to-date
7951 */
7952 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7953 kvm_hv_process_stimers(vcpu);
7954 }
7955
7956 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7957 ++vcpu->stat.req_event;
7958 kvm_apic_accept_events(vcpu);
7959 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7960 r = 1;
7961 goto out;
7962 }
7963
7964 if (inject_pending_event(vcpu, req_int_win) != 0)
7965 req_immediate_exit = true;
7966 else {
7967 /* Enable SMI/NMI/IRQ window open exits if needed.
7968 *
7969 * SMIs have three cases:
7970 * 1) They can be nested, and then there is nothing to
7971 * do here because RSM will cause a vmexit anyway.
7972 * 2) There is an ISA-specific reason why SMI cannot be
7973 * injected, and the moment when this changes can be
7974 * intercepted.
7975 * 3) Or the SMI can be pending because
7976 * inject_pending_event has completed the injection
7977 * of an IRQ or NMI from the previous vmexit, and
7978 * then we request an immediate exit to inject the
7979 * SMI.
7980 */
7981 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7982 if (!kvm_x86_ops->enable_smi_window(vcpu))
7983 req_immediate_exit = true;
7984 if (vcpu->arch.nmi_pending)
7985 kvm_x86_ops->enable_nmi_window(vcpu);
7986 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7987 kvm_x86_ops->enable_irq_window(vcpu);
7988 WARN_ON(vcpu->arch.exception.pending);
7989 }
7990
7991 if (kvm_lapic_enabled(vcpu)) {
7992 update_cr8_intercept(vcpu);
7993 kvm_lapic_sync_to_vapic(vcpu);
7994 }
7995 }
7996
7997 r = kvm_mmu_reload(vcpu);
7998 if (unlikely(r)) {
7999 goto cancel_injection;
8000 }
8001
8002 preempt_disable();
8003
8004 kvm_x86_ops->prepare_guest_switch(vcpu);
8005
8006 /*
8007 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8008 * IPI are then delayed after guest entry, which ensures that they
8009 * result in virtual interrupt delivery.
8010 */
8011 local_irq_disable();
8012 vcpu->mode = IN_GUEST_MODE;
8013
8014 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8015
8016 /*
8017 * 1) We should set ->mode before checking ->requests. Please see
8018 * the comment in kvm_vcpu_exiting_guest_mode().
8019 *
8020 * 2) For APICv, we should set ->mode before checking PID.ON. This
8021 * pairs with the memory barrier implicit in pi_test_and_set_on
8022 * (see vmx_deliver_posted_interrupt).
8023 *
8024 * 3) This also orders the write to mode from any reads to the page
8025 * tables done while the VCPU is running. Please see the comment
8026 * in kvm_flush_remote_tlbs.
8027 */
8028 smp_mb__after_srcu_read_unlock();
8029
8030 /*
8031 * This handles the case where a posted interrupt was
8032 * notified with kvm_vcpu_kick.
8033 */
8034 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8035 kvm_x86_ops->sync_pir_to_irr(vcpu);
8036
8037 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8038 || need_resched() || signal_pending(current)) {
8039 vcpu->mode = OUTSIDE_GUEST_MODE;
8040 smp_wmb();
8041 local_irq_enable();
8042 preempt_enable();
8043 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8044 r = 1;
8045 goto cancel_injection;
8046 }
8047
8048 if (req_immediate_exit) {
8049 kvm_make_request(KVM_REQ_EVENT, vcpu);
8050 kvm_x86_ops->request_immediate_exit(vcpu);
8051 }
8052
8053 trace_kvm_entry(vcpu->vcpu_id);
8054 guest_enter_irqoff();
8055
8056 /* The preempt notifier should have taken care of the FPU already. */
8057 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8058
8059 if (unlikely(vcpu->arch.switch_db_regs)) {
8060 set_debugreg(0, 7);
8061 set_debugreg(vcpu->arch.eff_db[0], 0);
8062 set_debugreg(vcpu->arch.eff_db[1], 1);
8063 set_debugreg(vcpu->arch.eff_db[2], 2);
8064 set_debugreg(vcpu->arch.eff_db[3], 3);
8065 set_debugreg(vcpu->arch.dr6, 6);
8066 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8067 }
8068
8069 kvm_x86_ops->run(vcpu);
8070
8071 /*
8072 * Do this here before restoring debug registers on the host. And
8073 * since we do this before handling the vmexit, a DR access vmexit
8074 * can (a) read the correct value of the debug registers, (b) set
8075 * KVM_DEBUGREG_WONT_EXIT again.
8076 */
8077 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8078 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8079 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8080 kvm_update_dr0123(vcpu);
8081 kvm_update_dr6(vcpu);
8082 kvm_update_dr7(vcpu);
8083 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8084 }
8085
8086 /*
8087 * If the guest has used debug registers, at least dr7
8088 * will be disabled while returning to the host.
8089 * If we don't have active breakpoints in the host, we don't
8090 * care about the messed up debug address registers. But if
8091 * we have some of them active, restore the old state.
8092 */
8093 if (hw_breakpoint_active())
8094 hw_breakpoint_restore();
8095
8096 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8097
8098 vcpu->mode = OUTSIDE_GUEST_MODE;
8099 smp_wmb();
8100
8101 kvm_x86_ops->handle_exit_irqoff(vcpu);
8102
8103 /*
8104 * Consume any pending interrupts, including the possible source of
8105 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8106 * An instruction is required after local_irq_enable() to fully unblock
8107 * interrupts on processors that implement an interrupt shadow, the
8108 * stat.exits increment will do nicely.
8109 */
8110 kvm_before_interrupt(vcpu);
8111 local_irq_enable();
8112 ++vcpu->stat.exits;
8113 local_irq_disable();
8114 kvm_after_interrupt(vcpu);
8115
8116 guest_exit_irqoff();
8117 if (lapic_in_kernel(vcpu)) {
8118 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8119 if (delta != S64_MIN) {
8120 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8121 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8122 }
8123 }
8124
8125 local_irq_enable();
8126 preempt_enable();
8127
8128 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8129
8130 /*
8131 * Profile KVM exit RIPs:
8132 */
8133 if (unlikely(prof_on == KVM_PROFILING)) {
8134 unsigned long rip = kvm_rip_read(vcpu);
8135 profile_hit(KVM_PROFILING, (void *)rip);
8136 }
8137
8138 if (unlikely(vcpu->arch.tsc_always_catchup))
8139 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8140
8141 if (vcpu->arch.apic_attention)
8142 kvm_lapic_sync_from_vapic(vcpu);
8143
8144 vcpu->arch.gpa_available = false;
8145 r = kvm_x86_ops->handle_exit(vcpu);
8146 return r;
8147
8148cancel_injection:
8149 kvm_x86_ops->cancel_injection(vcpu);
8150 if (unlikely(vcpu->arch.apic_attention))
8151 kvm_lapic_sync_from_vapic(vcpu);
8152out:
8153 return r;
8154}
8155
8156static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8157{
8158 if (!kvm_arch_vcpu_runnable(vcpu) &&
8159 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8160 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8161 kvm_vcpu_block(vcpu);
8162 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8163
8164 if (kvm_x86_ops->post_block)
8165 kvm_x86_ops->post_block(vcpu);
8166
8167 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8168 return 1;
8169 }
8170
8171 kvm_apic_accept_events(vcpu);
8172 switch(vcpu->arch.mp_state) {
8173 case KVM_MP_STATE_HALTED:
8174 vcpu->arch.pv.pv_unhalted = false;
8175 vcpu->arch.mp_state =
8176 KVM_MP_STATE_RUNNABLE;
8177 /* fall through */
8178 case KVM_MP_STATE_RUNNABLE:
8179 vcpu->arch.apf.halted = false;
8180 break;
8181 case KVM_MP_STATE_INIT_RECEIVED:
8182 break;
8183 default:
8184 return -EINTR;
8185 break;
8186 }
8187 return 1;
8188}
8189
8190static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8191{
8192 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8193 kvm_x86_ops->check_nested_events(vcpu, false);
8194
8195 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8196 !vcpu->arch.apf.halted);
8197}
8198
8199static int vcpu_run(struct kvm_vcpu *vcpu)
8200{
8201 int r;
8202 struct kvm *kvm = vcpu->kvm;
8203
8204 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8205 vcpu->arch.l1tf_flush_l1d = true;
8206
8207 for (;;) {
8208 if (kvm_vcpu_running(vcpu)) {
8209 r = vcpu_enter_guest(vcpu);
8210 } else {
8211 r = vcpu_block(kvm, vcpu);
8212 }
8213
8214 if (r <= 0)
8215 break;
8216
8217 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8218 if (kvm_cpu_has_pending_timer(vcpu))
8219 kvm_inject_pending_timer_irqs(vcpu);
8220
8221 if (dm_request_for_irq_injection(vcpu) &&
8222 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8223 r = 0;
8224 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8225 ++vcpu->stat.request_irq_exits;
8226 break;
8227 }
8228
8229 kvm_check_async_pf_completion(vcpu);
8230
8231 if (signal_pending(current)) {
8232 r = -EINTR;
8233 vcpu->run->exit_reason = KVM_EXIT_INTR;
8234 ++vcpu->stat.signal_exits;
8235 break;
8236 }
8237 if (need_resched()) {
8238 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8239 cond_resched();
8240 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8241 }
8242 }
8243
8244 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8245
8246 return r;
8247}
8248
8249static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8250{
8251 int r;
8252 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8253 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8254 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8255 if (r != EMULATE_DONE)
8256 return 0;
8257 return 1;
8258}
8259
8260static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8261{
8262 BUG_ON(!vcpu->arch.pio.count);
8263
8264 return complete_emulated_io(vcpu);
8265}
8266
8267/*
8268 * Implements the following, as a state machine:
8269 *
8270 * read:
8271 * for each fragment
8272 * for each mmio piece in the fragment
8273 * write gpa, len
8274 * exit
8275 * copy data
8276 * execute insn
8277 *
8278 * write:
8279 * for each fragment
8280 * for each mmio piece in the fragment
8281 * write gpa, len
8282 * copy data
8283 * exit
8284 */
8285static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8286{
8287 struct kvm_run *run = vcpu->run;
8288 struct kvm_mmio_fragment *frag;
8289 unsigned len;
8290
8291 BUG_ON(!vcpu->mmio_needed);
8292
8293 /* Complete previous fragment */
8294 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8295 len = min(8u, frag->len);
8296 if (!vcpu->mmio_is_write)
8297 memcpy(frag->data, run->mmio.data, len);
8298
8299 if (frag->len <= 8) {
8300 /* Switch to the next fragment. */
8301 frag++;
8302 vcpu->mmio_cur_fragment++;
8303 } else {
8304 /* Go forward to the next mmio piece. */
8305 frag->data += len;
8306 frag->gpa += len;
8307 frag->len -= len;
8308 }
8309
8310 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8311 vcpu->mmio_needed = 0;
8312
8313 /* FIXME: return into emulator if single-stepping. */
8314 if (vcpu->mmio_is_write)
8315 return 1;
8316 vcpu->mmio_read_completed = 1;
8317 return complete_emulated_io(vcpu);
8318 }
8319
8320 run->exit_reason = KVM_EXIT_MMIO;
8321 run->mmio.phys_addr = frag->gpa;
8322 if (vcpu->mmio_is_write)
8323 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8324 run->mmio.len = min(8u, frag->len);
8325 run->mmio.is_write = vcpu->mmio_is_write;
8326 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8327 return 0;
8328}
8329
8330/* Swap (qemu) user FPU context for the guest FPU context. */
8331static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8332{
8333 fpregs_lock();
8334
8335 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8336 /* PKRU is separately restored in kvm_x86_ops->run. */
8337 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8338 ~XFEATURE_MASK_PKRU);
8339
8340 fpregs_mark_activate();
8341 fpregs_unlock();
8342
8343 trace_kvm_fpu(1);
8344}
8345
8346/* When vcpu_run ends, restore user space FPU context. */
8347static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8348{
8349 fpregs_lock();
8350
8351 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8352 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8353
8354 fpregs_mark_activate();
8355 fpregs_unlock();
8356
8357 ++vcpu->stat.fpu_reload;
8358 trace_kvm_fpu(0);
8359}
8360
8361int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8362{
8363 int r;
8364
8365 vcpu_load(vcpu);
8366 kvm_sigset_activate(vcpu);
8367 kvm_load_guest_fpu(vcpu);
8368
8369 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8370 if (kvm_run->immediate_exit) {
8371 r = -EINTR;
8372 goto out;
8373 }
8374 kvm_vcpu_block(vcpu);
8375 kvm_apic_accept_events(vcpu);
8376 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8377 r = -EAGAIN;
8378 if (signal_pending(current)) {
8379 r = -EINTR;
8380 vcpu->run->exit_reason = KVM_EXIT_INTR;
8381 ++vcpu->stat.signal_exits;
8382 }
8383 goto out;
8384 }
8385
8386 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8387 r = -EINVAL;
8388 goto out;
8389 }
8390
8391 if (vcpu->run->kvm_dirty_regs) {
8392 r = sync_regs(vcpu);
8393 if (r != 0)
8394 goto out;
8395 }
8396
8397 /* re-sync apic's tpr */
8398 if (!lapic_in_kernel(vcpu)) {
8399 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8400 r = -EINVAL;
8401 goto out;
8402 }
8403 }
8404
8405 if (unlikely(vcpu->arch.complete_userspace_io)) {
8406 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8407 vcpu->arch.complete_userspace_io = NULL;
8408 r = cui(vcpu);
8409 if (r <= 0)
8410 goto out;
8411 } else
8412 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8413
8414 if (kvm_run->immediate_exit)
8415 r = -EINTR;
8416 else
8417 r = vcpu_run(vcpu);
8418
8419out:
8420 kvm_put_guest_fpu(vcpu);
8421 if (vcpu->run->kvm_valid_regs)
8422 store_regs(vcpu);
8423 post_kvm_run_save(vcpu);
8424 kvm_sigset_deactivate(vcpu);
8425
8426 vcpu_put(vcpu);
8427 return r;
8428}
8429
8430static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8431{
8432 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8433 /*
8434 * We are here if userspace calls get_regs() in the middle of
8435 * instruction emulation. Registers state needs to be copied
8436 * back from emulation context to vcpu. Userspace shouldn't do
8437 * that usually, but some bad designed PV devices (vmware
8438 * backdoor interface) need this to work
8439 */
8440 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8441 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8442 }
8443 regs->rax = kvm_rax_read(vcpu);
8444 regs->rbx = kvm_rbx_read(vcpu);
8445 regs->rcx = kvm_rcx_read(vcpu);
8446 regs->rdx = kvm_rdx_read(vcpu);
8447 regs->rsi = kvm_rsi_read(vcpu);
8448 regs->rdi = kvm_rdi_read(vcpu);
8449 regs->rsp = kvm_rsp_read(vcpu);
8450 regs->rbp = kvm_rbp_read(vcpu);
8451#ifdef CONFIG_X86_64
8452 regs->r8 = kvm_r8_read(vcpu);
8453 regs->r9 = kvm_r9_read(vcpu);
8454 regs->r10 = kvm_r10_read(vcpu);
8455 regs->r11 = kvm_r11_read(vcpu);
8456 regs->r12 = kvm_r12_read(vcpu);
8457 regs->r13 = kvm_r13_read(vcpu);
8458 regs->r14 = kvm_r14_read(vcpu);
8459 regs->r15 = kvm_r15_read(vcpu);
8460#endif
8461
8462 regs->rip = kvm_rip_read(vcpu);
8463 regs->rflags = kvm_get_rflags(vcpu);
8464}
8465
8466int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8467{
8468 vcpu_load(vcpu);
8469 __get_regs(vcpu, regs);
8470 vcpu_put(vcpu);
8471 return 0;
8472}
8473
8474static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8475{
8476 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8477 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8478
8479 kvm_rax_write(vcpu, regs->rax);
8480 kvm_rbx_write(vcpu, regs->rbx);
8481 kvm_rcx_write(vcpu, regs->rcx);
8482 kvm_rdx_write(vcpu, regs->rdx);
8483 kvm_rsi_write(vcpu, regs->rsi);
8484 kvm_rdi_write(vcpu, regs->rdi);
8485 kvm_rsp_write(vcpu, regs->rsp);
8486 kvm_rbp_write(vcpu, regs->rbp);
8487#ifdef CONFIG_X86_64
8488 kvm_r8_write(vcpu, regs->r8);
8489 kvm_r9_write(vcpu, regs->r9);
8490 kvm_r10_write(vcpu, regs->r10);
8491 kvm_r11_write(vcpu, regs->r11);
8492 kvm_r12_write(vcpu, regs->r12);
8493 kvm_r13_write(vcpu, regs->r13);
8494 kvm_r14_write(vcpu, regs->r14);
8495 kvm_r15_write(vcpu, regs->r15);
8496#endif
8497
8498 kvm_rip_write(vcpu, regs->rip);
8499 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8500
8501 vcpu->arch.exception.pending = false;
8502
8503 kvm_make_request(KVM_REQ_EVENT, vcpu);
8504}
8505
8506int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8507{
8508 vcpu_load(vcpu);
8509 __set_regs(vcpu, regs);
8510 vcpu_put(vcpu);
8511 return 0;
8512}
8513
8514void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8515{
8516 struct kvm_segment cs;
8517
8518 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8519 *db = cs.db;
8520 *l = cs.l;
8521}
8522EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8523
8524static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8525{
8526 struct desc_ptr dt;
8527
8528 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8529 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8530 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8531 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8532 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8533 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8534
8535 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8536 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8537
8538 kvm_x86_ops->get_idt(vcpu, &dt);
8539 sregs->idt.limit = dt.size;
8540 sregs->idt.base = dt.address;
8541 kvm_x86_ops->get_gdt(vcpu, &dt);
8542 sregs->gdt.limit = dt.size;
8543 sregs->gdt.base = dt.address;
8544
8545 sregs->cr0 = kvm_read_cr0(vcpu);
8546 sregs->cr2 = vcpu->arch.cr2;
8547 sregs->cr3 = kvm_read_cr3(vcpu);
8548 sregs->cr4 = kvm_read_cr4(vcpu);
8549 sregs->cr8 = kvm_get_cr8(vcpu);
8550 sregs->efer = vcpu->arch.efer;
8551 sregs->apic_base = kvm_get_apic_base(vcpu);
8552
8553 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8554
8555 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8556 set_bit(vcpu->arch.interrupt.nr,
8557 (unsigned long *)sregs->interrupt_bitmap);
8558}
8559
8560int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8561 struct kvm_sregs *sregs)
8562{
8563 vcpu_load(vcpu);
8564 __get_sregs(vcpu, sregs);
8565 vcpu_put(vcpu);
8566 return 0;
8567}
8568
8569int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8570 struct kvm_mp_state *mp_state)
8571{
8572 vcpu_load(vcpu);
8573
8574 kvm_apic_accept_events(vcpu);
8575 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8576 vcpu->arch.pv.pv_unhalted)
8577 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8578 else
8579 mp_state->mp_state = vcpu->arch.mp_state;
8580
8581 vcpu_put(vcpu);
8582 return 0;
8583}
8584
8585int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8586 struct kvm_mp_state *mp_state)
8587{
8588 int ret = -EINVAL;
8589
8590 vcpu_load(vcpu);
8591
8592 if (!lapic_in_kernel(vcpu) &&
8593 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8594 goto out;
8595
8596 /* INITs are latched while in SMM */
8597 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8598 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8599 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8600 goto out;
8601
8602 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8603 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8604 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8605 } else
8606 vcpu->arch.mp_state = mp_state->mp_state;
8607 kvm_make_request(KVM_REQ_EVENT, vcpu);
8608
8609 ret = 0;
8610out:
8611 vcpu_put(vcpu);
8612 return ret;
8613}
8614
8615int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8616 int reason, bool has_error_code, u32 error_code)
8617{
8618 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8619 int ret;
8620
8621 init_emulate_ctxt(vcpu);
8622
8623 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8624 has_error_code, error_code);
8625
8626 if (ret)
8627 return EMULATE_FAIL;
8628
8629 kvm_rip_write(vcpu, ctxt->eip);
8630 kvm_set_rflags(vcpu, ctxt->eflags);
8631 kvm_make_request(KVM_REQ_EVENT, vcpu);
8632 return EMULATE_DONE;
8633}
8634EXPORT_SYMBOL_GPL(kvm_task_switch);
8635
8636static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8637{
8638 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8639 (sregs->cr4 & X86_CR4_OSXSAVE))
8640 return -EINVAL;
8641
8642 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8643 /*
8644 * When EFER.LME and CR0.PG are set, the processor is in
8645 * 64-bit mode (though maybe in a 32-bit code segment).
8646 * CR4.PAE and EFER.LMA must be set.
8647 */
8648 if (!(sregs->cr4 & X86_CR4_PAE)
8649 || !(sregs->efer & EFER_LMA))
8650 return -EINVAL;
8651 } else {
8652 /*
8653 * Not in 64-bit mode: EFER.LMA is clear and the code
8654 * segment cannot be 64-bit.
8655 */
8656 if (sregs->efer & EFER_LMA || sregs->cs.l)
8657 return -EINVAL;
8658 }
8659
8660 return 0;
8661}
8662
8663static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8664{
8665 struct msr_data apic_base_msr;
8666 int mmu_reset_needed = 0;
8667 int cpuid_update_needed = 0;
8668 int pending_vec, max_bits, idx;
8669 struct desc_ptr dt;
8670 int ret = -EINVAL;
8671
8672 if (kvm_valid_sregs(vcpu, sregs))
8673 goto out;
8674
8675 apic_base_msr.data = sregs->apic_base;
8676 apic_base_msr.host_initiated = true;
8677 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8678 goto out;
8679
8680 dt.size = sregs->idt.limit;
8681 dt.address = sregs->idt.base;
8682 kvm_x86_ops->set_idt(vcpu, &dt);
8683 dt.size = sregs->gdt.limit;
8684 dt.address = sregs->gdt.base;
8685 kvm_x86_ops->set_gdt(vcpu, &dt);
8686
8687 vcpu->arch.cr2 = sregs->cr2;
8688 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8689 vcpu->arch.cr3 = sregs->cr3;
8690 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8691
8692 kvm_set_cr8(vcpu, sregs->cr8);
8693
8694 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8695 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8696
8697 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8698 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8699 vcpu->arch.cr0 = sregs->cr0;
8700
8701 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8702 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8703 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8704 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8705 if (cpuid_update_needed)
8706 kvm_update_cpuid(vcpu);
8707
8708 idx = srcu_read_lock(&vcpu->kvm->srcu);
8709 if (is_pae_paging(vcpu)) {
8710 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8711 mmu_reset_needed = 1;
8712 }
8713 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8714
8715 if (mmu_reset_needed)
8716 kvm_mmu_reset_context(vcpu);
8717
8718 max_bits = KVM_NR_INTERRUPTS;
8719 pending_vec = find_first_bit(
8720 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8721 if (pending_vec < max_bits) {
8722 kvm_queue_interrupt(vcpu, pending_vec, false);
8723 pr_debug("Set back pending irq %d\n", pending_vec);
8724 }
8725
8726 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8727 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8728 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8729 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8730 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8731 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8732
8733 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8734 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8735
8736 update_cr8_intercept(vcpu);
8737
8738 /* Older userspace won't unhalt the vcpu on reset. */
8739 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8740 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8741 !is_protmode(vcpu))
8742 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8743
8744 kvm_make_request(KVM_REQ_EVENT, vcpu);
8745
8746 ret = 0;
8747out:
8748 return ret;
8749}
8750
8751int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8752 struct kvm_sregs *sregs)
8753{
8754 int ret;
8755
8756 vcpu_load(vcpu);
8757 ret = __set_sregs(vcpu, sregs);
8758 vcpu_put(vcpu);
8759 return ret;
8760}
8761
8762int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8763 struct kvm_guest_debug *dbg)
8764{
8765 unsigned long rflags;
8766 int i, r;
8767
8768 vcpu_load(vcpu);
8769
8770 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8771 r = -EBUSY;
8772 if (vcpu->arch.exception.pending)
8773 goto out;
8774 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8775 kvm_queue_exception(vcpu, DB_VECTOR);
8776 else
8777 kvm_queue_exception(vcpu, BP_VECTOR);
8778 }
8779
8780 /*
8781 * Read rflags as long as potentially injected trace flags are still
8782 * filtered out.
8783 */
8784 rflags = kvm_get_rflags(vcpu);
8785
8786 vcpu->guest_debug = dbg->control;
8787 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8788 vcpu->guest_debug = 0;
8789
8790 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8791 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8792 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8793 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8794 } else {
8795 for (i = 0; i < KVM_NR_DB_REGS; i++)
8796 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8797 }
8798 kvm_update_dr7(vcpu);
8799
8800 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8801 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8802 get_segment_base(vcpu, VCPU_SREG_CS);
8803
8804 /*
8805 * Trigger an rflags update that will inject or remove the trace
8806 * flags.
8807 */
8808 kvm_set_rflags(vcpu, rflags);
8809
8810 kvm_x86_ops->update_bp_intercept(vcpu);
8811
8812 r = 0;
8813
8814out:
8815 vcpu_put(vcpu);
8816 return r;
8817}
8818
8819/*
8820 * Translate a guest virtual address to a guest physical address.
8821 */
8822int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8823 struct kvm_translation *tr)
8824{
8825 unsigned long vaddr = tr->linear_address;
8826 gpa_t gpa;
8827 int idx;
8828
8829 vcpu_load(vcpu);
8830
8831 idx = srcu_read_lock(&vcpu->kvm->srcu);
8832 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8833 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8834 tr->physical_address = gpa;
8835 tr->valid = gpa != UNMAPPED_GVA;
8836 tr->writeable = 1;
8837 tr->usermode = 0;
8838
8839 vcpu_put(vcpu);
8840 return 0;
8841}
8842
8843int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8844{
8845 struct fxregs_state *fxsave;
8846
8847 vcpu_load(vcpu);
8848
8849 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8850 memcpy(fpu->fpr, fxsave->st_space, 128);
8851 fpu->fcw = fxsave->cwd;
8852 fpu->fsw = fxsave->swd;
8853 fpu->ftwx = fxsave->twd;
8854 fpu->last_opcode = fxsave->fop;
8855 fpu->last_ip = fxsave->rip;
8856 fpu->last_dp = fxsave->rdp;
8857 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8858
8859 vcpu_put(vcpu);
8860 return 0;
8861}
8862
8863int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8864{
8865 struct fxregs_state *fxsave;
8866
8867 vcpu_load(vcpu);
8868
8869 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8870
8871 memcpy(fxsave->st_space, fpu->fpr, 128);
8872 fxsave->cwd = fpu->fcw;
8873 fxsave->swd = fpu->fsw;
8874 fxsave->twd = fpu->ftwx;
8875 fxsave->fop = fpu->last_opcode;
8876 fxsave->rip = fpu->last_ip;
8877 fxsave->rdp = fpu->last_dp;
8878 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8879
8880 vcpu_put(vcpu);
8881 return 0;
8882}
8883
8884static void store_regs(struct kvm_vcpu *vcpu)
8885{
8886 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8887
8888 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8889 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8890
8891 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8892 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8893
8894 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8895 kvm_vcpu_ioctl_x86_get_vcpu_events(
8896 vcpu, &vcpu->run->s.regs.events);
8897}
8898
8899static int sync_regs(struct kvm_vcpu *vcpu)
8900{
8901 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8902 return -EINVAL;
8903
8904 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8905 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8906 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8907 }
8908 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8909 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8910 return -EINVAL;
8911 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8912 }
8913 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8914 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8915 vcpu, &vcpu->run->s.regs.events))
8916 return -EINVAL;
8917 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8918 }
8919
8920 return 0;
8921}
8922
8923static void fx_init(struct kvm_vcpu *vcpu)
8924{
8925 fpstate_init(&vcpu->arch.guest_fpu->state);
8926 if (boot_cpu_has(X86_FEATURE_XSAVES))
8927 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8928 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8929
8930 /*
8931 * Ensure guest xcr0 is valid for loading
8932 */
8933 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8934
8935 vcpu->arch.cr0 |= X86_CR0_ET;
8936}
8937
8938void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8939{
8940 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8941
8942 kvmclock_reset(vcpu);
8943
8944 kvm_x86_ops->vcpu_free(vcpu);
8945 free_cpumask_var(wbinvd_dirty_mask);
8946}
8947
8948struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8949 unsigned int id)
8950{
8951 struct kvm_vcpu *vcpu;
8952
8953 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8954 printk_once(KERN_WARNING
8955 "kvm: SMP vm created on host with unstable TSC; "
8956 "guest TSC will not be reliable\n");
8957
8958 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8959
8960 return vcpu;
8961}
8962
8963int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8964{
8965 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8966 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8967 kvm_vcpu_mtrr_init(vcpu);
8968 vcpu_load(vcpu);
8969 kvm_vcpu_reset(vcpu, false);
8970 kvm_init_mmu(vcpu, false);
8971 vcpu_put(vcpu);
8972 return 0;
8973}
8974
8975void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8976{
8977 struct msr_data msr;
8978 struct kvm *kvm = vcpu->kvm;
8979
8980 kvm_hv_vcpu_postcreate(vcpu);
8981
8982 if (mutex_lock_killable(&vcpu->mutex))
8983 return;
8984 vcpu_load(vcpu);
8985 msr.data = 0x0;
8986 msr.index = MSR_IA32_TSC;
8987 msr.host_initiated = true;
8988 kvm_write_tsc(vcpu, &msr);
8989 vcpu_put(vcpu);
8990
8991 /* poll control enabled by default */
8992 vcpu->arch.msr_kvm_poll_control = 1;
8993
8994 mutex_unlock(&vcpu->mutex);
8995
8996 if (!kvmclock_periodic_sync)
8997 return;
8998
8999 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9000 KVMCLOCK_SYNC_PERIOD);
9001}
9002
9003void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9004{
9005 vcpu->arch.apf.msr_val = 0;
9006
9007 vcpu_load(vcpu);
9008 kvm_mmu_unload(vcpu);
9009 vcpu_put(vcpu);
9010
9011 kvm_x86_ops->vcpu_free(vcpu);
9012}
9013
9014void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9015{
9016 kvm_lapic_reset(vcpu, init_event);
9017
9018 vcpu->arch.hflags = 0;
9019
9020 vcpu->arch.smi_pending = 0;
9021 vcpu->arch.smi_count = 0;
9022 atomic_set(&vcpu->arch.nmi_queued, 0);
9023 vcpu->arch.nmi_pending = 0;
9024 vcpu->arch.nmi_injected = false;
9025 kvm_clear_interrupt_queue(vcpu);
9026 kvm_clear_exception_queue(vcpu);
9027 vcpu->arch.exception.pending = false;
9028
9029 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9030 kvm_update_dr0123(vcpu);
9031 vcpu->arch.dr6 = DR6_INIT;
9032 kvm_update_dr6(vcpu);
9033 vcpu->arch.dr7 = DR7_FIXED_1;
9034 kvm_update_dr7(vcpu);
9035
9036 vcpu->arch.cr2 = 0;
9037
9038 kvm_make_request(KVM_REQ_EVENT, vcpu);
9039 vcpu->arch.apf.msr_val = 0;
9040 vcpu->arch.st.msr_val = 0;
9041
9042 kvmclock_reset(vcpu);
9043
9044 kvm_clear_async_pf_completion_queue(vcpu);
9045 kvm_async_pf_hash_reset(vcpu);
9046 vcpu->arch.apf.halted = false;
9047
9048 if (kvm_mpx_supported()) {
9049 void *mpx_state_buffer;
9050
9051 /*
9052 * To avoid have the INIT path from kvm_apic_has_events() that be
9053 * called with loaded FPU and does not let userspace fix the state.
9054 */
9055 if (init_event)
9056 kvm_put_guest_fpu(vcpu);
9057 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9058 XFEATURE_BNDREGS);
9059 if (mpx_state_buffer)
9060 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9061 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9062 XFEATURE_BNDCSR);
9063 if (mpx_state_buffer)
9064 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9065 if (init_event)
9066 kvm_load_guest_fpu(vcpu);
9067 }
9068
9069 if (!init_event) {
9070 kvm_pmu_reset(vcpu);
9071 vcpu->arch.smbase = 0x30000;
9072
9073 vcpu->arch.msr_misc_features_enables = 0;
9074
9075 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9076 }
9077
9078 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9079 vcpu->arch.regs_avail = ~0;
9080 vcpu->arch.regs_dirty = ~0;
9081
9082 vcpu->arch.ia32_xss = 0;
9083
9084 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9085}
9086
9087void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9088{
9089 struct kvm_segment cs;
9090
9091 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9092 cs.selector = vector << 8;
9093 cs.base = vector << 12;
9094 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9095 kvm_rip_write(vcpu, 0);
9096}
9097
9098int kvm_arch_hardware_enable(void)
9099{
9100 struct kvm *kvm;
9101 struct kvm_vcpu *vcpu;
9102 int i;
9103 int ret;
9104 u64 local_tsc;
9105 u64 max_tsc = 0;
9106 bool stable, backwards_tsc = false;
9107
9108 kvm_shared_msr_cpu_online();
9109 ret = kvm_x86_ops->hardware_enable();
9110 if (ret != 0)
9111 return ret;
9112
9113 local_tsc = rdtsc();
9114 stable = !kvm_check_tsc_unstable();
9115 list_for_each_entry(kvm, &vm_list, vm_list) {
9116 kvm_for_each_vcpu(i, vcpu, kvm) {
9117 if (!stable && vcpu->cpu == smp_processor_id())
9118 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9119 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9120 backwards_tsc = true;
9121 if (vcpu->arch.last_host_tsc > max_tsc)
9122 max_tsc = vcpu->arch.last_host_tsc;
9123 }
9124 }
9125 }
9126
9127 /*
9128 * Sometimes, even reliable TSCs go backwards. This happens on
9129 * platforms that reset TSC during suspend or hibernate actions, but
9130 * maintain synchronization. We must compensate. Fortunately, we can
9131 * detect that condition here, which happens early in CPU bringup,
9132 * before any KVM threads can be running. Unfortunately, we can't
9133 * bring the TSCs fully up to date with real time, as we aren't yet far
9134 * enough into CPU bringup that we know how much real time has actually
9135 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9136 * variables that haven't been updated yet.
9137 *
9138 * So we simply find the maximum observed TSC above, then record the
9139 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9140 * the adjustment will be applied. Note that we accumulate
9141 * adjustments, in case multiple suspend cycles happen before some VCPU
9142 * gets a chance to run again. In the event that no KVM threads get a
9143 * chance to run, we will miss the entire elapsed period, as we'll have
9144 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9145 * loose cycle time. This isn't too big a deal, since the loss will be
9146 * uniform across all VCPUs (not to mention the scenario is extremely
9147 * unlikely). It is possible that a second hibernate recovery happens
9148 * much faster than a first, causing the observed TSC here to be
9149 * smaller; this would require additional padding adjustment, which is
9150 * why we set last_host_tsc to the local tsc observed here.
9151 *
9152 * N.B. - this code below runs only on platforms with reliable TSC,
9153 * as that is the only way backwards_tsc is set above. Also note
9154 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9155 * have the same delta_cyc adjustment applied if backwards_tsc
9156 * is detected. Note further, this adjustment is only done once,
9157 * as we reset last_host_tsc on all VCPUs to stop this from being
9158 * called multiple times (one for each physical CPU bringup).
9159 *
9160 * Platforms with unreliable TSCs don't have to deal with this, they
9161 * will be compensated by the logic in vcpu_load, which sets the TSC to
9162 * catchup mode. This will catchup all VCPUs to real time, but cannot
9163 * guarantee that they stay in perfect synchronization.
9164 */
9165 if (backwards_tsc) {
9166 u64 delta_cyc = max_tsc - local_tsc;
9167 list_for_each_entry(kvm, &vm_list, vm_list) {
9168 kvm->arch.backwards_tsc_observed = true;
9169 kvm_for_each_vcpu(i, vcpu, kvm) {
9170 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9171 vcpu->arch.last_host_tsc = local_tsc;
9172 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9173 }
9174
9175 /*
9176 * We have to disable TSC offset matching.. if you were
9177 * booting a VM while issuing an S4 host suspend....
9178 * you may have some problem. Solving this issue is
9179 * left as an exercise to the reader.
9180 */
9181 kvm->arch.last_tsc_nsec = 0;
9182 kvm->arch.last_tsc_write = 0;
9183 }
9184
9185 }
9186 return 0;
9187}
9188
9189void kvm_arch_hardware_disable(void)
9190{
9191 kvm_x86_ops->hardware_disable();
9192 drop_user_return_notifiers();
9193}
9194
9195int kvm_arch_hardware_setup(void)
9196{
9197 int r;
9198
9199 r = kvm_x86_ops->hardware_setup();
9200 if (r != 0)
9201 return r;
9202
9203 if (kvm_has_tsc_control) {
9204 /*
9205 * Make sure the user can only configure tsc_khz values that
9206 * fit into a signed integer.
9207 * A min value is not calculated because it will always
9208 * be 1 on all machines.
9209 */
9210 u64 max = min(0x7fffffffULL,
9211 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9212 kvm_max_guest_tsc_khz = max;
9213
9214 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9215 }
9216
9217 kvm_init_msr_list();
9218 return 0;
9219}
9220
9221void kvm_arch_hardware_unsetup(void)
9222{
9223 kvm_x86_ops->hardware_unsetup();
9224}
9225
9226int kvm_arch_check_processor_compat(void)
9227{
9228 return kvm_x86_ops->check_processor_compatibility();
9229}
9230
9231bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9232{
9233 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9234}
9235EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9236
9237bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9238{
9239 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9240}
9241
9242struct static_key kvm_no_apic_vcpu __read_mostly;
9243EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9244
9245int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9246{
9247 struct page *page;
9248 int r;
9249
9250 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9251 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9252 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9253 else
9254 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9255
9256 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9257 if (!page) {
9258 r = -ENOMEM;
9259 goto fail;
9260 }
9261 vcpu->arch.pio_data = page_address(page);
9262
9263 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9264
9265 r = kvm_mmu_create(vcpu);
9266 if (r < 0)
9267 goto fail_free_pio_data;
9268
9269 if (irqchip_in_kernel(vcpu->kvm)) {
9270 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9271 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9272 if (r < 0)
9273 goto fail_mmu_destroy;
9274 } else
9275 static_key_slow_inc(&kvm_no_apic_vcpu);
9276
9277 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9278 GFP_KERNEL_ACCOUNT);
9279 if (!vcpu->arch.mce_banks) {
9280 r = -ENOMEM;
9281 goto fail_free_lapic;
9282 }
9283 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9284
9285 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9286 GFP_KERNEL_ACCOUNT)) {
9287 r = -ENOMEM;
9288 goto fail_free_mce_banks;
9289 }
9290
9291 fx_init(vcpu);
9292
9293 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9294
9295 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9296
9297 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9298
9299 kvm_async_pf_hash_reset(vcpu);
9300 kvm_pmu_init(vcpu);
9301
9302 vcpu->arch.pending_external_vector = -1;
9303 vcpu->arch.preempted_in_kernel = false;
9304
9305 kvm_hv_vcpu_init(vcpu);
9306
9307 return 0;
9308
9309fail_free_mce_banks:
9310 kfree(vcpu->arch.mce_banks);
9311fail_free_lapic:
9312 kvm_free_lapic(vcpu);
9313fail_mmu_destroy:
9314 kvm_mmu_destroy(vcpu);
9315fail_free_pio_data:
9316 free_page((unsigned long)vcpu->arch.pio_data);
9317fail:
9318 return r;
9319}
9320
9321void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9322{
9323 int idx;
9324
9325 kvm_hv_vcpu_uninit(vcpu);
9326 kvm_pmu_destroy(vcpu);
9327 kfree(vcpu->arch.mce_banks);
9328 kvm_free_lapic(vcpu);
9329 idx = srcu_read_lock(&vcpu->kvm->srcu);
9330 kvm_mmu_destroy(vcpu);
9331 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9332 free_page((unsigned long)vcpu->arch.pio_data);
9333 if (!lapic_in_kernel(vcpu))
9334 static_key_slow_dec(&kvm_no_apic_vcpu);
9335}
9336
9337void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9338{
9339 vcpu->arch.l1tf_flush_l1d = true;
9340 kvm_x86_ops->sched_in(vcpu, cpu);
9341}
9342
9343int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9344{
9345 if (type)
9346 return -EINVAL;
9347
9348 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9349 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9350 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9351 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9352
9353 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9354 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9355 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9356 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9357 &kvm->arch.irq_sources_bitmap);
9358
9359 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9360 mutex_init(&kvm->arch.apic_map_lock);
9361 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9362
9363 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9364 pvclock_update_vm_gtod_copy(kvm);
9365
9366 kvm->arch.guest_can_read_msr_platform_info = true;
9367
9368 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9369 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9370
9371 kvm_hv_init_vm(kvm);
9372 kvm_page_track_init(kvm);
9373 kvm_mmu_init_vm(kvm);
9374
9375 return kvm_x86_ops->vm_init(kvm);
9376}
9377
9378static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9379{
9380 vcpu_load(vcpu);
9381 kvm_mmu_unload(vcpu);
9382 vcpu_put(vcpu);
9383}
9384
9385static void kvm_free_vcpus(struct kvm *kvm)
9386{
9387 unsigned int i;
9388 struct kvm_vcpu *vcpu;
9389
9390 /*
9391 * Unpin any mmu pages first.
9392 */
9393 kvm_for_each_vcpu(i, vcpu, kvm) {
9394 kvm_clear_async_pf_completion_queue(vcpu);
9395 kvm_unload_vcpu_mmu(vcpu);
9396 }
9397 kvm_for_each_vcpu(i, vcpu, kvm)
9398 kvm_arch_vcpu_free(vcpu);
9399
9400 mutex_lock(&kvm->lock);
9401 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9402 kvm->vcpus[i] = NULL;
9403
9404 atomic_set(&kvm->online_vcpus, 0);
9405 mutex_unlock(&kvm->lock);
9406}
9407
9408void kvm_arch_sync_events(struct kvm *kvm)
9409{
9410 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9411 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9412 kvm_free_pit(kvm);
9413}
9414
9415int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9416{
9417 int i, r;
9418 unsigned long hva;
9419 struct kvm_memslots *slots = kvm_memslots(kvm);
9420 struct kvm_memory_slot *slot, old;
9421
9422 /* Called with kvm->slots_lock held. */
9423 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9424 return -EINVAL;
9425
9426 slot = id_to_memslot(slots, id);
9427 if (size) {
9428 if (slot->npages)
9429 return -EEXIST;
9430
9431 /*
9432 * MAP_SHARED to prevent internal slot pages from being moved
9433 * by fork()/COW.
9434 */
9435 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9436 MAP_SHARED | MAP_ANONYMOUS, 0);
9437 if (IS_ERR((void *)hva))
9438 return PTR_ERR((void *)hva);
9439 } else {
9440 if (!slot->npages)
9441 return 0;
9442
9443 hva = 0;
9444 }
9445
9446 old = *slot;
9447 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9448 struct kvm_userspace_memory_region m;
9449
9450 m.slot = id | (i << 16);
9451 m.flags = 0;
9452 m.guest_phys_addr = gpa;
9453 m.userspace_addr = hva;
9454 m.memory_size = size;
9455 r = __kvm_set_memory_region(kvm, &m);
9456 if (r < 0)
9457 return r;
9458 }
9459
9460 if (!size)
9461 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9462
9463 return 0;
9464}
9465EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9466
9467int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9468{
9469 int r;
9470
9471 mutex_lock(&kvm->slots_lock);
9472 r = __x86_set_memory_region(kvm, id, gpa, size);
9473 mutex_unlock(&kvm->slots_lock);
9474
9475 return r;
9476}
9477EXPORT_SYMBOL_GPL(x86_set_memory_region);
9478
9479void kvm_arch_destroy_vm(struct kvm *kvm)
9480{
9481 if (current->mm == kvm->mm) {
9482 /*
9483 * Free memory regions allocated on behalf of userspace,
9484 * unless the the memory map has changed due to process exit
9485 * or fd copying.
9486 */
9487 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9488 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9489 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9490 }
9491 if (kvm_x86_ops->vm_destroy)
9492 kvm_x86_ops->vm_destroy(kvm);
9493 kvm_pic_destroy(kvm);
9494 kvm_ioapic_destroy(kvm);
9495 kvm_free_vcpus(kvm);
9496 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9497 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9498 kvm_mmu_uninit_vm(kvm);
9499 kvm_page_track_cleanup(kvm);
9500 kvm_hv_destroy_vm(kvm);
9501}
9502
9503void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9504 struct kvm_memory_slot *dont)
9505{
9506 int i;
9507
9508 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9509 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9510 kvfree(free->arch.rmap[i]);
9511 free->arch.rmap[i] = NULL;
9512 }
9513 if (i == 0)
9514 continue;
9515
9516 if (!dont || free->arch.lpage_info[i - 1] !=
9517 dont->arch.lpage_info[i - 1]) {
9518 kvfree(free->arch.lpage_info[i - 1]);
9519 free->arch.lpage_info[i - 1] = NULL;
9520 }
9521 }
9522
9523 kvm_page_track_free_memslot(free, dont);
9524}
9525
9526int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9527 unsigned long npages)
9528{
9529 int i;
9530
9531 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9532 struct kvm_lpage_info *linfo;
9533 unsigned long ugfn;
9534 int lpages;
9535 int level = i + 1;
9536
9537 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9538 slot->base_gfn, level) + 1;
9539
9540 slot->arch.rmap[i] =
9541 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9542 GFP_KERNEL_ACCOUNT);
9543 if (!slot->arch.rmap[i])
9544 goto out_free;
9545 if (i == 0)
9546 continue;
9547
9548 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9549 if (!linfo)
9550 goto out_free;
9551
9552 slot->arch.lpage_info[i - 1] = linfo;
9553
9554 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9555 linfo[0].disallow_lpage = 1;
9556 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9557 linfo[lpages - 1].disallow_lpage = 1;
9558 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9559 /*
9560 * If the gfn and userspace address are not aligned wrt each
9561 * other, or if explicitly asked to, disable large page
9562 * support for this slot
9563 */
9564 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9565 !kvm_largepages_enabled()) {
9566 unsigned long j;
9567
9568 for (j = 0; j < lpages; ++j)
9569 linfo[j].disallow_lpage = 1;
9570 }
9571 }
9572
9573 if (kvm_page_track_create_memslot(slot, npages))
9574 goto out_free;
9575
9576 return 0;
9577
9578out_free:
9579 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9580 kvfree(slot->arch.rmap[i]);
9581 slot->arch.rmap[i] = NULL;
9582 if (i == 0)
9583 continue;
9584
9585 kvfree(slot->arch.lpage_info[i - 1]);
9586 slot->arch.lpage_info[i - 1] = NULL;
9587 }
9588 return -ENOMEM;
9589}
9590
9591void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9592{
9593 /*
9594 * memslots->generation has been incremented.
9595 * mmio generation may have reached its maximum value.
9596 */
9597 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9598}
9599
9600int kvm_arch_prepare_memory_region(struct kvm *kvm,
9601 struct kvm_memory_slot *memslot,
9602 const struct kvm_userspace_memory_region *mem,
9603 enum kvm_mr_change change)
9604{
9605 return 0;
9606}
9607
9608static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9609 struct kvm_memory_slot *new)
9610{
9611 /* Still write protect RO slot */
9612 if (new->flags & KVM_MEM_READONLY) {
9613 kvm_mmu_slot_remove_write_access(kvm, new);
9614 return;
9615 }
9616
9617 /*
9618 * Call kvm_x86_ops dirty logging hooks when they are valid.
9619 *
9620 * kvm_x86_ops->slot_disable_log_dirty is called when:
9621 *
9622 * - KVM_MR_CREATE with dirty logging is disabled
9623 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9624 *
9625 * The reason is, in case of PML, we need to set D-bit for any slots
9626 * with dirty logging disabled in order to eliminate unnecessary GPA
9627 * logging in PML buffer (and potential PML buffer full VMEXT). This
9628 * guarantees leaving PML enabled during guest's lifetime won't have
9629 * any additional overhead from PML when guest is running with dirty
9630 * logging disabled for memory slots.
9631 *
9632 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9633 * to dirty logging mode.
9634 *
9635 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9636 *
9637 * In case of write protect:
9638 *
9639 * Write protect all pages for dirty logging.
9640 *
9641 * All the sptes including the large sptes which point to this
9642 * slot are set to readonly. We can not create any new large
9643 * spte on this slot until the end of the logging.
9644 *
9645 * See the comments in fast_page_fault().
9646 */
9647 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9648 if (kvm_x86_ops->slot_enable_log_dirty)
9649 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9650 else
9651 kvm_mmu_slot_remove_write_access(kvm, new);
9652 } else {
9653 if (kvm_x86_ops->slot_disable_log_dirty)
9654 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9655 }
9656}
9657
9658void kvm_arch_commit_memory_region(struct kvm *kvm,
9659 const struct kvm_userspace_memory_region *mem,
9660 const struct kvm_memory_slot *old,
9661 const struct kvm_memory_slot *new,
9662 enum kvm_mr_change change)
9663{
9664 if (!kvm->arch.n_requested_mmu_pages)
9665 kvm_mmu_change_mmu_pages(kvm,
9666 kvm_mmu_calculate_default_mmu_pages(kvm));
9667
9668 /*
9669 * Dirty logging tracks sptes in 4k granularity, meaning that large
9670 * sptes have to be split. If live migration is successful, the guest
9671 * in the source machine will be destroyed and large sptes will be
9672 * created in the destination. However, if the guest continues to run
9673 * in the source machine (for example if live migration fails), small
9674 * sptes will remain around and cause bad performance.
9675 *
9676 * Scan sptes if dirty logging has been stopped, dropping those
9677 * which can be collapsed into a single large-page spte. Later
9678 * page faults will create the large-page sptes.
9679 */
9680 if ((change != KVM_MR_DELETE) &&
9681 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9682 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9683 kvm_mmu_zap_collapsible_sptes(kvm, new);
9684
9685 /*
9686 * Set up write protection and/or dirty logging for the new slot.
9687 *
9688 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9689 * been zapped so no dirty logging staff is needed for old slot. For
9690 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9691 * new and it's also covered when dealing with the new slot.
9692 *
9693 * FIXME: const-ify all uses of struct kvm_memory_slot.
9694 */
9695 if (change != KVM_MR_DELETE)
9696 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9697}
9698
9699void kvm_arch_flush_shadow_all(struct kvm *kvm)
9700{
9701 kvm_mmu_zap_all(kvm);
9702}
9703
9704void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9705 struct kvm_memory_slot *slot)
9706{
9707 kvm_page_track_flush_slot(kvm, slot);
9708}
9709
9710static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9711{
9712 return (is_guest_mode(vcpu) &&
9713 kvm_x86_ops->guest_apic_has_interrupt &&
9714 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9715}
9716
9717static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9718{
9719 if (!list_empty_careful(&vcpu->async_pf.done))
9720 return true;
9721
9722 if (kvm_apic_has_events(vcpu))
9723 return true;
9724
9725 if (vcpu->arch.pv.pv_unhalted)
9726 return true;
9727
9728 if (vcpu->arch.exception.pending)
9729 return true;
9730
9731 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9732 (vcpu->arch.nmi_pending &&
9733 kvm_x86_ops->nmi_allowed(vcpu)))
9734 return true;
9735
9736 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9737 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9738 return true;
9739
9740 if (kvm_arch_interrupt_allowed(vcpu) &&
9741 (kvm_cpu_has_interrupt(vcpu) ||
9742 kvm_guest_apic_has_interrupt(vcpu)))
9743 return true;
9744
9745 if (kvm_hv_has_stimer_pending(vcpu))
9746 return true;
9747
9748 return false;
9749}
9750
9751int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9752{
9753 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9754}
9755
9756bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9757{
9758 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9759 return true;
9760
9761 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9762 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9763 kvm_test_request(KVM_REQ_EVENT, vcpu))
9764 return true;
9765
9766 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9767 return true;
9768
9769 return false;
9770}
9771
9772bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9773{
9774 return vcpu->arch.preempted_in_kernel;
9775}
9776
9777int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9778{
9779 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9780}
9781
9782int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9783{
9784 return kvm_x86_ops->interrupt_allowed(vcpu);
9785}
9786
9787unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9788{
9789 if (is_64_bit_mode(vcpu))
9790 return kvm_rip_read(vcpu);
9791 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9792 kvm_rip_read(vcpu));
9793}
9794EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9795
9796bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9797{
9798 return kvm_get_linear_rip(vcpu) == linear_rip;
9799}
9800EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9801
9802unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9803{
9804 unsigned long rflags;
9805
9806 rflags = kvm_x86_ops->get_rflags(vcpu);
9807 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9808 rflags &= ~X86_EFLAGS_TF;
9809 return rflags;
9810}
9811EXPORT_SYMBOL_GPL(kvm_get_rflags);
9812
9813static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9814{
9815 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9816 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9817 rflags |= X86_EFLAGS_TF;
9818 kvm_x86_ops->set_rflags(vcpu, rflags);
9819}
9820
9821void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9822{
9823 __kvm_set_rflags(vcpu, rflags);
9824 kvm_make_request(KVM_REQ_EVENT, vcpu);
9825}
9826EXPORT_SYMBOL_GPL(kvm_set_rflags);
9827
9828void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9829{
9830 int r;
9831
9832 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9833 work->wakeup_all)
9834 return;
9835
9836 r = kvm_mmu_reload(vcpu);
9837 if (unlikely(r))
9838 return;
9839
9840 if (!vcpu->arch.mmu->direct_map &&
9841 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9842 return;
9843
9844 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9845}
9846
9847static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9848{
9849 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9850}
9851
9852static inline u32 kvm_async_pf_next_probe(u32 key)
9853{
9854 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9855}
9856
9857static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9858{
9859 u32 key = kvm_async_pf_hash_fn(gfn);
9860
9861 while (vcpu->arch.apf.gfns[key] != ~0)
9862 key = kvm_async_pf_next_probe(key);
9863
9864 vcpu->arch.apf.gfns[key] = gfn;
9865}
9866
9867static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9868{
9869 int i;
9870 u32 key = kvm_async_pf_hash_fn(gfn);
9871
9872 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9873 (vcpu->arch.apf.gfns[key] != gfn &&
9874 vcpu->arch.apf.gfns[key] != ~0); i++)
9875 key = kvm_async_pf_next_probe(key);
9876
9877 return key;
9878}
9879
9880bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9881{
9882 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9883}
9884
9885static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9886{
9887 u32 i, j, k;
9888
9889 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9890 while (true) {
9891 vcpu->arch.apf.gfns[i] = ~0;
9892 do {
9893 j = kvm_async_pf_next_probe(j);
9894 if (vcpu->arch.apf.gfns[j] == ~0)
9895 return;
9896 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9897 /*
9898 * k lies cyclically in ]i,j]
9899 * | i.k.j |
9900 * |....j i.k.| or |.k..j i...|
9901 */
9902 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9903 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9904 i = j;
9905 }
9906}
9907
9908static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9909{
9910
9911 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9912 sizeof(val));
9913}
9914
9915static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9916{
9917
9918 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9919 sizeof(u32));
9920}
9921
9922static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9923{
9924 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9925 return false;
9926
9927 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9928 (vcpu->arch.apf.send_user_only &&
9929 kvm_x86_ops->get_cpl(vcpu) == 0))
9930 return false;
9931
9932 return true;
9933}
9934
9935bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9936{
9937 if (unlikely(!lapic_in_kernel(vcpu) ||
9938 kvm_event_needs_reinjection(vcpu) ||
9939 vcpu->arch.exception.pending))
9940 return false;
9941
9942 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9943 return false;
9944
9945 /*
9946 * If interrupts are off we cannot even use an artificial
9947 * halt state.
9948 */
9949 return kvm_x86_ops->interrupt_allowed(vcpu);
9950}
9951
9952void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9953 struct kvm_async_pf *work)
9954{
9955 struct x86_exception fault;
9956
9957 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9958 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9959
9960 if (kvm_can_deliver_async_pf(vcpu) &&
9961 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9962 fault.vector = PF_VECTOR;
9963 fault.error_code_valid = true;
9964 fault.error_code = 0;
9965 fault.nested_page_fault = false;
9966 fault.address = work->arch.token;
9967 fault.async_page_fault = true;
9968 kvm_inject_page_fault(vcpu, &fault);
9969 } else {
9970 /*
9971 * It is not possible to deliver a paravirtualized asynchronous
9972 * page fault, but putting the guest in an artificial halt state
9973 * can be beneficial nevertheless: if an interrupt arrives, we
9974 * can deliver it timely and perhaps the guest will schedule
9975 * another process. When the instruction that triggered a page
9976 * fault is retried, hopefully the page will be ready in the host.
9977 */
9978 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9979 }
9980}
9981
9982void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9983 struct kvm_async_pf *work)
9984{
9985 struct x86_exception fault;
9986 u32 val;
9987
9988 if (work->wakeup_all)
9989 work->arch.token = ~0; /* broadcast wakeup */
9990 else
9991 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9992 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9993
9994 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9995 !apf_get_user(vcpu, &val)) {
9996 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9997 vcpu->arch.exception.pending &&
9998 vcpu->arch.exception.nr == PF_VECTOR &&
9999 !apf_put_user(vcpu, 0)) {
10000 vcpu->arch.exception.injected = false;
10001 vcpu->arch.exception.pending = false;
10002 vcpu->arch.exception.nr = 0;
10003 vcpu->arch.exception.has_error_code = false;
10004 vcpu->arch.exception.error_code = 0;
10005 vcpu->arch.exception.has_payload = false;
10006 vcpu->arch.exception.payload = 0;
10007 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10008 fault.vector = PF_VECTOR;
10009 fault.error_code_valid = true;
10010 fault.error_code = 0;
10011 fault.nested_page_fault = false;
10012 fault.address = work->arch.token;
10013 fault.async_page_fault = true;
10014 kvm_inject_page_fault(vcpu, &fault);
10015 }
10016 }
10017 vcpu->arch.apf.halted = false;
10018 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10019}
10020
10021bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10022{
10023 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10024 return true;
10025 else
10026 return kvm_can_do_async_pf(vcpu);
10027}
10028
10029void kvm_arch_start_assignment(struct kvm *kvm)
10030{
10031 atomic_inc(&kvm->arch.assigned_device_count);
10032}
10033EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10034
10035void kvm_arch_end_assignment(struct kvm *kvm)
10036{
10037 atomic_dec(&kvm->arch.assigned_device_count);
10038}
10039EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10040
10041bool kvm_arch_has_assigned_device(struct kvm *kvm)
10042{
10043 return atomic_read(&kvm->arch.assigned_device_count);
10044}
10045EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10046
10047void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10048{
10049 atomic_inc(&kvm->arch.noncoherent_dma_count);
10050}
10051EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10052
10053void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10054{
10055 atomic_dec(&kvm->arch.noncoherent_dma_count);
10056}
10057EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10058
10059bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10060{
10061 return atomic_read(&kvm->arch.noncoherent_dma_count);
10062}
10063EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10064
10065bool kvm_arch_has_irq_bypass(void)
10066{
10067 return true;
10068}
10069
10070int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10071 struct irq_bypass_producer *prod)
10072{
10073 struct kvm_kernel_irqfd *irqfd =
10074 container_of(cons, struct kvm_kernel_irqfd, consumer);
10075
10076 irqfd->producer = prod;
10077
10078 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10079 prod->irq, irqfd->gsi, 1);
10080}
10081
10082void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10083 struct irq_bypass_producer *prod)
10084{
10085 int ret;
10086 struct kvm_kernel_irqfd *irqfd =
10087 container_of(cons, struct kvm_kernel_irqfd, consumer);
10088
10089 WARN_ON(irqfd->producer != prod);
10090 irqfd->producer = NULL;
10091
10092 /*
10093 * When producer of consumer is unregistered, we change back to
10094 * remapped mode, so we can re-use the current implementation
10095 * when the irq is masked/disabled or the consumer side (KVM
10096 * int this case doesn't want to receive the interrupts.
10097 */
10098 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10099 if (ret)
10100 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10101 " fails: %d\n", irqfd->consumer.token, ret);
10102}
10103
10104int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10105 uint32_t guest_irq, bool set)
10106{
10107 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10108}
10109
10110bool kvm_vector_hashing_enabled(void)
10111{
10112 return vector_hashing;
10113}
10114EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10115
10116bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10117{
10118 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10119}
10120EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10121
10122
10123EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10124EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10125EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10126EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10127EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10128EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10129EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10130EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10131EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10132EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10133EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10134EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10135EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10136EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10137EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10138EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10139EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10140EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10141EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10142EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)