[linux-2.6-block.git] / arch / x86 / kvm / lapic.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __KVM_X86_LAPIC_H
#define __KVM_X86_LAPIC_H

#include <kvm/iodev.h>

#include <linux/kvm_host.h>

#include "hyperv.h"
#include "smm.h"

#define KVM_APIC_INIT		0
#define KVM_APIC_SIPI		1

#define APIC_SHORT_MASK			0xc0000
#define APIC_DEST_NOSHORT		0x0
#define APIC_DEST_MASK			0x800

#define APIC_BUS_CYCLE_NS_DEFAULT	1

#define APIC_BROADCAST			0xFF
#define X2APIC_BROADCAST		0xFFFFFFFFul

enum lapic_mode {
	LAPIC_MODE_DISABLED = 0,
	LAPIC_MODE_INVALID = X2APIC_ENABLE,
	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
};

enum lapic_lvt_entry {
	LVT_TIMER,
	LVT_THERMAL_MONITOR,
	LVT_PERFORMANCE_COUNTER,
	LVT_LINT0,
	LVT_LINT1,
	LVT_ERROR,
	LVT_CMCI,

	KVM_APIC_MAX_NR_LVT_ENTRIES,
};

#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))

struct kvm_timer {
	struct hrtimer timer;
	s64 period; 				/* unit: ns */
	ktime_t target_expiration;
	u32 timer_mode;
	u32 timer_mode_mask;
	u64 tscdeadline;
	u64 expired_tscdeadline;
	u32 timer_advance_ns;
	atomic_t pending;			/* accumulated triggered timers */
	bool hv_timer_in_use;
};

struct kvm_lapic {
	unsigned long base_address;
	struct kvm_io_device dev;
	struct kvm_timer lapic_timer;
	u32 divide_count;
	struct kvm_vcpu *vcpu;
	bool apicv_active;
	bool sw_enabled;
	bool irr_pending;
	bool lvt0_in_nmi_mode;
	/* Select registers in the vAPIC cannot be read/written. */
	bool guest_apic_protected;
	/* Number of bits set in ISR. */
	s16 isr_count;
	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	int highest_isr_cache;
	/**
	 * APIC register page.  The layout matches the register layout seen by
	 * the guest 1:1, because it is accessed by the vmx microcode.
	 * Note: Only one register, the TPR, is used by the microcode.
	 */
	void *regs;
	gpa_t vapic_addr;
	struct gfn_to_hva_cache vapic_cache;
	unsigned long pending_events;
	unsigned int sipi_vector;
	int nr_lvt_entries;
};

struct dest_map;

int kvm_create_lapic(struct kvm_vcpu *vcpu);
void kvm_free_lapic(struct kvm_vcpu *vcpu);

int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector);
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
void kvm_apic_set_version(struct kvm_vcpu *vcpu);
void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
			   int shorthand, unsigned int dest, int dest_mode);
int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr);
bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *max_irr);
void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
		     struct dest_map *dest_map);
int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
int kvm_alloc_apic_access_page(struct kvm *kvm);
void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);

bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);

int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated);
int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
void kvm_apic_update_hwapic_isr(struct kvm_vcpu *vcpu);
int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);

u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);

void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);

int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);

int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);

int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
void kvm_lapic_exit(void);

u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);

#define VEC_POS(v) ((v) & (32 - 1))
#define REG_POS(v) (((v) >> 5) << 4)

static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
{
	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void kvm_lapic_set_vector(int vec, void *bitmap)
{
	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
}

static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
{
	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	/*
	 * irr_pending must be true if any interrupt is pending; set it after
	 * APIC_IRR to avoid race with apic_clear_irr
	 */
	apic->irr_pending = true;
}

static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
{
	return *((u32 *) (regs + reg_off));
}

static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
{
	return __kvm_lapic_get_reg(apic->regs, reg_off);
}

DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);

static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
{
	if (static_branch_unlikely(&kvm_has_noapic_vcpu))
		return vcpu->arch.apic;
	return true;
}

extern struct static_key_false_deferred apic_hw_disabled;

static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
{
	if (static_branch_unlikely(&apic_hw_disabled.key))
		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
	return true;
}

extern struct static_key_false_deferred apic_sw_disabled;

static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
{
	if (static_branch_unlikely(&apic_sw_disabled.key))
		return apic->sw_enabled;
	return true;
}

static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
}

static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
{
	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
}

static inline int apic_x2apic_mode(struct kvm_lapic *apic)
{
	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
}

static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
}

static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
}

static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
{
	return !is_smm(vcpu) &&
	       !kvm_x86_call(apic_init_signal_blocked)(vcpu);
}

static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
{
	return (irq->delivery_mode == APIC_DM_LOWEST ||
			irq->msi_redir_hint);
}

static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
{
	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
}

bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);

void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);

void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
			      unsigned long *vcpu_bitmap);

bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
			struct kvm_vcpu **dest_vcpu);
int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
			const unsigned long *bitmap, u32 bitmap_size);
void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);

static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
{
	return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
}

static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
{
	return kvm_apic_mode(vcpu->arch.apic_base);
}

static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
{
	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
}

#endif
Commit	Line	Data
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef __KVM_X86_LAPIC_H
	3	#define __KVM_X86_LAPIC_H
	4
	5	#include <kvm/iodev.h>
	6
	7	#include <linux/kvm_host.h>
	8
	9	#include "hyperv.h"
	10	#include "smm.h"
	11
	12	#define KVM_APIC_INIT 0
	13	#define KVM_APIC_SIPI 1
	14
	15	#define APIC_SHORT_MASK 0xc0000
	16	#define APIC_DEST_NOSHORT 0x0
	17	#define APIC_DEST_MASK 0x800
	18
	19	#define APIC_BUS_CYCLE_NS_DEFAULT 1
	20
	21	#define APIC_BROADCAST 0xFF
	22	#define X2APIC_BROADCAST 0xFFFFFFFFul
	23
	24	enum lapic_mode {
	25	LAPIC_MODE_DISABLED = 0,
	26	LAPIC_MODE_INVALID = X2APIC_ENABLE,
	27	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
	28	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE \| X2APIC_ENABLE,
	29	};
	30
	31	enum lapic_lvt_entry {
	32	LVT_TIMER,
	33	LVT_THERMAL_MONITOR,
	34	LVT_PERFORMANCE_COUNTER,
	35	LVT_LINT0,
	36	LVT_LINT1,
	37	LVT_ERROR,
	38	LVT_CMCI,
	39
	40	KVM_APIC_MAX_NR_LVT_ENTRIES,
	41	};
	42
	43	#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
	44
	45	struct kvm_timer {
	46	struct hrtimer timer;
	47	s64 period; /* unit: ns */
	48	ktime_t target_expiration;
	49	u32 timer_mode;
	50	u32 timer_mode_mask;
	51	u64 tscdeadline;
	52	u64 expired_tscdeadline;
	53	u32 timer_advance_ns;
	54	atomic_t pending; /* accumulated triggered timers */
	55	bool hv_timer_in_use;
	56	};
	57
	58	struct kvm_lapic {
	59	unsigned long base_address;
	60	struct kvm_io_device dev;
	61	struct kvm_timer lapic_timer;
	62	u32 divide_count;
	63	struct kvm_vcpu *vcpu;
	64	bool apicv_active;
	65	bool sw_enabled;
	66	bool irr_pending;
	67	bool lvt0_in_nmi_mode;
	68	/* Select registers in the vAPIC cannot be read/written. */
	69	bool guest_apic_protected;
	70	/* Number of bits set in ISR. */
	71	s16 isr_count;
	72	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
	73	int highest_isr_cache;
	74	/**
	75	* APIC register page. The layout matches the register layout seen by
	76	* the guest 1:1, because it is accessed by the vmx microcode.
	77	* Note: Only one register, the TPR, is used by the microcode.
	78	*/
	79	void *regs;
	80	gpa_t vapic_addr;
	81	struct gfn_to_hva_cache vapic_cache;
	82	unsigned long pending_events;
	83	unsigned int sipi_vector;
	84	int nr_lvt_entries;
	85	};
	86
	87	struct dest_map;
	88
	89	int kvm_create_lapic(struct kvm_vcpu *vcpu);
	90	void kvm_free_lapic(struct kvm_vcpu *vcpu);
	91
	92	int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
	93	void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector);
	94	int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
	95	int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
	96	void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
	97	u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
	98	void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
	99	void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
	100	void kvm_apic_set_version(struct kvm_vcpu *vcpu);
	101	void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
	102	bool kvm_apic_match_dest(struct kvm_vcpu vcpu, struct kvm_lapic source,
	103	int shorthand, unsigned int dest, int dest_mode);
	104	int kvm_apic_compare_prio(struct kvm_vcpu vcpu1, struct kvm_vcpu vcpu2);
	105	void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
	106	bool __kvm_apic_update_irr(unsigned long pir, void regs, int *max_irr);
	107	bool kvm_apic_update_irr(struct kvm_vcpu vcpu, unsigned long pir, int *max_irr);
	108	void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
	109	int kvm_apic_set_irq(struct kvm_vcpu vcpu, struct kvm_lapic_irq irq,
	110	struct dest_map *dest_map);
	111	int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
	112	void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
	113	int kvm_alloc_apic_access_page(struct kvm *kvm);
	114	void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);
	115
	116	bool kvm_irq_delivery_to_apic_fast(struct kvm kvm, struct kvm_lapic src,
	117	struct kvm_lapic_irq irq, int r, struct dest_map *dest_map);
	118	void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
	119
	120	int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated);
	121	int kvm_apic_get_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
	122	int kvm_apic_set_state(struct kvm_vcpu vcpu, struct kvm_lapic_state s);
	123	void kvm_apic_update_hwapic_isr(struct kvm_vcpu *vcpu);
	124	int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
	125
	126	u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
	127	void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
	128
	129	void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
	130	void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
	131
	132	int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
	133	void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
	134	void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
	135
	136	int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
	137	int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
	138	int kvm_x2apic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
	139
	140	int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
	141	int kvm_hv_vapic_msr_read(struct kvm_vcpu vcpu, u32 msr, u64 data);
	142
	143	int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
	144	void kvm_lapic_exit(void);
	145
	146	u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
	147
	148	#define VEC_POS(v) ((v) & (32 - 1))
	149	#define REG_POS(v) (((v) >> 5) << 4)
	150
	151	static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
	152	{
	153	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
	154	}
	155
	156	static inline void kvm_lapic_set_vector(int vec, void *bitmap)
	157	{
	158	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
	159	}
	160
	161	static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
	162	{
	163	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
	164	/*
	165	* irr_pending must be true if any interrupt is pending; set it after
	166	* APIC_IRR to avoid race with apic_clear_irr
	167	*/
	168	apic->irr_pending = true;
	169	}
	170
	171	static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
	172	{
	173	return ((u32 ) (regs + reg_off));
	174	}
	175
	176	static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
	177	{
	178	return __kvm_lapic_get_reg(apic->regs, reg_off);
	179	}
	180
	181	DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
	182
	183	static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
	184	{
	185	if (static_branch_unlikely(&kvm_has_noapic_vcpu))
	186	return vcpu->arch.apic;
	187	return true;
	188	}
	189
	190	extern struct static_key_false_deferred apic_hw_disabled;
	191
	192	static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
	193	{
	194	if (static_branch_unlikely(&apic_hw_disabled.key))
	195	return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
	196	return true;
	197	}
	198
	199	extern struct static_key_false_deferred apic_sw_disabled;
	200
	201	static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
	202	{
	203	if (static_branch_unlikely(&apic_sw_disabled.key))
	204	return apic->sw_enabled;
	205	return true;
	206	}
	207
	208	static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
	209	{
	210	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
	211	}
	212
	213	static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
	214	{
	215	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
	216	}
	217
	218	static inline int apic_x2apic_mode(struct kvm_lapic *apic)
	219	{
	220	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
	221	}
	222
	223	static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
	224	{
	225	return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
	226	}
	227
	228	static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
	229	{
	230	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
	231	}
	232
	233	static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
	234	{
	235	return !is_smm(vcpu) &&
	236	!kvm_x86_call(apic_init_signal_blocked)(vcpu);
	237	}
	238
	239	static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
	240	{
	241	return (irq->delivery_mode == APIC_DM_LOWEST \|\|
	242	irq->msi_redir_hint);
	243	}
	244
	245	static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
	246	{
	247	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
	248	}
	249
	250	bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
	251
	252	void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
	253
	254	void kvm_bitmap_or_dest_vcpus(struct kvm kvm, struct kvm_lapic_irq irq,
	255	unsigned long *vcpu_bitmap);
	256
	257	bool kvm_intr_is_single_vcpu_fast(struct kvm kvm, struct kvm_lapic_irq irq,
	258	struct kvm_vcpu **dest_vcpu);
	259	int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
	260	const unsigned long *bitmap, u32 bitmap_size);
	261	void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
	262	void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
	263	void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
	264	bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
	265	void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
	266	bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
	267
	268	static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
	269	{
	270	return apic_base & (MSR_IA32_APICBASE_ENABLE \| X2APIC_ENABLE);
	271	}
	272
	273	static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
	274	{
	275	return kvm_apic_mode(vcpu->arch.apic_base);
	276	}
	277
	278	static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
	279	{
	280	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
	281	}
	282
	283	#endif