| 1 | #include <linux/errno.h> |
| 2 | #include <linux/kernel.h> |
| 3 | #include <linux/mm.h> |
| 4 | #include <linux/smp.h> |
| 5 | #include <linux/prctl.h> |
| 6 | #include <linux/slab.h> |
| 7 | #include <linux/sched.h> |
| 8 | #include <linux/module.h> |
| 9 | #include <linux/pm.h> |
| 10 | #include <linux/clockchips.h> |
| 11 | #include <linux/random.h> |
| 12 | #include <linux/user-return-notifier.h> |
| 13 | #include <linux/dmi.h> |
| 14 | #include <linux/utsname.h> |
| 15 | #include <trace/events/power.h> |
| 16 | #include <linux/hw_breakpoint.h> |
| 17 | #include <asm/system.h> |
| 18 | #include <asm/apic.h> |
| 19 | #include <asm/syscalls.h> |
| 20 | #include <asm/idle.h> |
| 21 | #include <asm/uaccess.h> |
| 22 | #include <asm/i387.h> |
| 23 | #include <asm/ds.h> |
| 24 | #include <asm/debugreg.h> |
| 25 | |
| 26 | unsigned long idle_halt; |
| 27 | EXPORT_SYMBOL(idle_halt); |
| 28 | unsigned long idle_nomwait; |
| 29 | EXPORT_SYMBOL(idle_nomwait); |
| 30 | |
| 31 | struct kmem_cache *task_xstate_cachep; |
| 32 | |
| 33 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
| 34 | { |
| 35 | *dst = *src; |
| 36 | if (src->thread.xstate) { |
| 37 | dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep, |
| 38 | GFP_KERNEL); |
| 39 | if (!dst->thread.xstate) |
| 40 | return -ENOMEM; |
| 41 | WARN_ON((unsigned long)dst->thread.xstate & 15); |
| 42 | memcpy(dst->thread.xstate, src->thread.xstate, xstate_size); |
| 43 | } |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | void free_thread_xstate(struct task_struct *tsk) |
| 48 | { |
| 49 | if (tsk->thread.xstate) { |
| 50 | kmem_cache_free(task_xstate_cachep, tsk->thread.xstate); |
| 51 | tsk->thread.xstate = NULL; |
| 52 | } |
| 53 | |
| 54 | WARN(tsk->thread.ds_ctx, "leaking DS context\n"); |
| 55 | } |
| 56 | |
| 57 | void free_thread_info(struct thread_info *ti) |
| 58 | { |
| 59 | free_thread_xstate(ti->task); |
| 60 | free_pages((unsigned long)ti, get_order(THREAD_SIZE)); |
| 61 | } |
| 62 | |
| 63 | void arch_task_cache_init(void) |
| 64 | { |
| 65 | task_xstate_cachep = |
| 66 | kmem_cache_create("task_xstate", xstate_size, |
| 67 | __alignof__(union thread_xstate), |
| 68 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * Free current thread data structures etc.. |
| 73 | */ |
| 74 | void exit_thread(void) |
| 75 | { |
| 76 | struct task_struct *me = current; |
| 77 | struct thread_struct *t = &me->thread; |
| 78 | unsigned long *bp = t->io_bitmap_ptr; |
| 79 | |
| 80 | if (bp) { |
| 81 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
| 82 | |
| 83 | t->io_bitmap_ptr = NULL; |
| 84 | clear_thread_flag(TIF_IO_BITMAP); |
| 85 | /* |
| 86 | * Careful, clear this in the TSS too: |
| 87 | */ |
| 88 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); |
| 89 | t->io_bitmap_max = 0; |
| 90 | put_cpu(); |
| 91 | kfree(bp); |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | void show_regs(struct pt_regs *regs) |
| 96 | { |
| 97 | show_registers(regs); |
| 98 | show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), |
| 99 | regs->bp); |
| 100 | } |
| 101 | |
| 102 | void show_regs_common(void) |
| 103 | { |
| 104 | const char *board, *product; |
| 105 | |
| 106 | board = dmi_get_system_info(DMI_BOARD_NAME); |
| 107 | if (!board) |
| 108 | board = ""; |
| 109 | product = dmi_get_system_info(DMI_PRODUCT_NAME); |
| 110 | if (!product) |
| 111 | product = ""; |
| 112 | |
| 113 | printk(KERN_CONT "\n"); |
| 114 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n", |
| 115 | current->pid, current->comm, print_tainted(), |
| 116 | init_utsname()->release, |
| 117 | (int)strcspn(init_utsname()->version, " "), |
| 118 | init_utsname()->version, board, product); |
| 119 | } |
| 120 | |
| 121 | void flush_thread(void) |
| 122 | { |
| 123 | struct task_struct *tsk = current; |
| 124 | |
| 125 | flush_ptrace_hw_breakpoint(tsk); |
| 126 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
| 127 | /* |
| 128 | * Forget coprocessor state.. |
| 129 | */ |
| 130 | tsk->fpu_counter = 0; |
| 131 | clear_fpu(tsk); |
| 132 | clear_used_math(); |
| 133 | } |
| 134 | |
| 135 | static void hard_disable_TSC(void) |
| 136 | { |
| 137 | write_cr4(read_cr4() | X86_CR4_TSD); |
| 138 | } |
| 139 | |
| 140 | void disable_TSC(void) |
| 141 | { |
| 142 | preempt_disable(); |
| 143 | if (!test_and_set_thread_flag(TIF_NOTSC)) |
| 144 | /* |
| 145 | * Must flip the CPU state synchronously with |
| 146 | * TIF_NOTSC in the current running context. |
| 147 | */ |
| 148 | hard_disable_TSC(); |
| 149 | preempt_enable(); |
| 150 | } |
| 151 | |
| 152 | static void hard_enable_TSC(void) |
| 153 | { |
| 154 | write_cr4(read_cr4() & ~X86_CR4_TSD); |
| 155 | } |
| 156 | |
| 157 | static void enable_TSC(void) |
| 158 | { |
| 159 | preempt_disable(); |
| 160 | if (test_and_clear_thread_flag(TIF_NOTSC)) |
| 161 | /* |
| 162 | * Must flip the CPU state synchronously with |
| 163 | * TIF_NOTSC in the current running context. |
| 164 | */ |
| 165 | hard_enable_TSC(); |
| 166 | preempt_enable(); |
| 167 | } |
| 168 | |
| 169 | int get_tsc_mode(unsigned long adr) |
| 170 | { |
| 171 | unsigned int val; |
| 172 | |
| 173 | if (test_thread_flag(TIF_NOTSC)) |
| 174 | val = PR_TSC_SIGSEGV; |
| 175 | else |
| 176 | val = PR_TSC_ENABLE; |
| 177 | |
| 178 | return put_user(val, (unsigned int __user *)adr); |
| 179 | } |
| 180 | |
| 181 | int set_tsc_mode(unsigned int val) |
| 182 | { |
| 183 | if (val == PR_TSC_SIGSEGV) |
| 184 | disable_TSC(); |
| 185 | else if (val == PR_TSC_ENABLE) |
| 186 | enable_TSC(); |
| 187 | else |
| 188 | return -EINVAL; |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, |
| 194 | struct tss_struct *tss) |
| 195 | { |
| 196 | struct thread_struct *prev, *next; |
| 197 | |
| 198 | prev = &prev_p->thread; |
| 199 | next = &next_p->thread; |
| 200 | |
| 201 | if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) || |
| 202 | test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR)) |
| 203 | ds_switch_to(prev_p, next_p); |
| 204 | else if (next->debugctlmsr != prev->debugctlmsr) |
| 205 | update_debugctlmsr(next->debugctlmsr); |
| 206 | |
| 207 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
| 208 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { |
| 209 | /* prev and next are different */ |
| 210 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) |
| 211 | hard_disable_TSC(); |
| 212 | else |
| 213 | hard_enable_TSC(); |
| 214 | } |
| 215 | |
| 216 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { |
| 217 | /* |
| 218 | * Copy the relevant range of the IO bitmap. |
| 219 | * Normally this is 128 bytes or less: |
| 220 | */ |
| 221 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, |
| 222 | max(prev->io_bitmap_max, next->io_bitmap_max)); |
| 223 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { |
| 224 | /* |
| 225 | * Clear any possible leftover bits: |
| 226 | */ |
| 227 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); |
| 228 | } |
| 229 | propagate_user_return_notify(prev_p, next_p); |
| 230 | } |
| 231 | |
| 232 | int sys_fork(struct pt_regs *regs) |
| 233 | { |
| 234 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); |
| 235 | } |
| 236 | |
| 237 | /* |
| 238 | * This is trivial, and on the face of it looks like it |
| 239 | * could equally well be done in user mode. |
| 240 | * |
| 241 | * Not so, for quite unobvious reasons - register pressure. |
| 242 | * In user mode vfork() cannot have a stack frame, and if |
| 243 | * done by calling the "clone()" system call directly, you |
| 244 | * do not have enough call-clobbered registers to hold all |
| 245 | * the information you need. |
| 246 | */ |
| 247 | int sys_vfork(struct pt_regs *regs) |
| 248 | { |
| 249 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, |
| 250 | NULL, NULL); |
| 251 | } |
| 252 | |
| 253 | long |
| 254 | sys_clone(unsigned long clone_flags, unsigned long newsp, |
| 255 | void __user *parent_tid, void __user *child_tid, struct pt_regs *regs) |
| 256 | { |
| 257 | if (!newsp) |
| 258 | newsp = regs->sp; |
| 259 | return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid); |
| 260 | } |
| 261 | |
| 262 | /* |
| 263 | * This gets run with %si containing the |
| 264 | * function to call, and %di containing |
| 265 | * the "args". |
| 266 | */ |
| 267 | extern void kernel_thread_helper(void); |
| 268 | |
| 269 | /* |
| 270 | * Create a kernel thread |
| 271 | */ |
| 272 | int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) |
| 273 | { |
| 274 | struct pt_regs regs; |
| 275 | |
| 276 | memset(®s, 0, sizeof(regs)); |
| 277 | |
| 278 | regs.si = (unsigned long) fn; |
| 279 | regs.di = (unsigned long) arg; |
| 280 | |
| 281 | #ifdef CONFIG_X86_32 |
| 282 | regs.ds = __USER_DS; |
| 283 | regs.es = __USER_DS; |
| 284 | regs.fs = __KERNEL_PERCPU; |
| 285 | regs.gs = __KERNEL_STACK_CANARY; |
| 286 | #else |
| 287 | regs.ss = __KERNEL_DS; |
| 288 | #endif |
| 289 | |
| 290 | regs.orig_ax = -1; |
| 291 | regs.ip = (unsigned long) kernel_thread_helper; |
| 292 | regs.cs = __KERNEL_CS | get_kernel_rpl(); |
| 293 | regs.flags = X86_EFLAGS_IF | 0x2; |
| 294 | |
| 295 | /* Ok, create the new process.. */ |
| 296 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); |
| 297 | } |
| 298 | EXPORT_SYMBOL(kernel_thread); |
| 299 | |
| 300 | /* |
| 301 | * sys_execve() executes a new program. |
| 302 | */ |
| 303 | long sys_execve(char __user *name, char __user * __user *argv, |
| 304 | char __user * __user *envp, struct pt_regs *regs) |
| 305 | { |
| 306 | long error; |
| 307 | char *filename; |
| 308 | |
| 309 | filename = getname(name); |
| 310 | error = PTR_ERR(filename); |
| 311 | if (IS_ERR(filename)) |
| 312 | return error; |
| 313 | error = do_execve(filename, argv, envp, regs); |
| 314 | |
| 315 | #ifdef CONFIG_X86_32 |
| 316 | if (error == 0) { |
| 317 | /* Make sure we don't return using sysenter.. */ |
| 318 | set_thread_flag(TIF_IRET); |
| 319 | } |
| 320 | #endif |
| 321 | |
| 322 | putname(filename); |
| 323 | return error; |
| 324 | } |
| 325 | |
| 326 | /* |
| 327 | * Idle related variables and functions |
| 328 | */ |
| 329 | unsigned long boot_option_idle_override = 0; |
| 330 | EXPORT_SYMBOL(boot_option_idle_override); |
| 331 | |
| 332 | /* |
| 333 | * Powermanagement idle function, if any.. |
| 334 | */ |
| 335 | void (*pm_idle)(void); |
| 336 | EXPORT_SYMBOL(pm_idle); |
| 337 | |
| 338 | #ifdef CONFIG_X86_32 |
| 339 | /* |
| 340 | * This halt magic was a workaround for ancient floppy DMA |
| 341 | * wreckage. It should be safe to remove. |
| 342 | */ |
| 343 | static int hlt_counter; |
| 344 | void disable_hlt(void) |
| 345 | { |
| 346 | hlt_counter++; |
| 347 | } |
| 348 | EXPORT_SYMBOL(disable_hlt); |
| 349 | |
| 350 | void enable_hlt(void) |
| 351 | { |
| 352 | hlt_counter--; |
| 353 | } |
| 354 | EXPORT_SYMBOL(enable_hlt); |
| 355 | |
| 356 | static inline int hlt_use_halt(void) |
| 357 | { |
| 358 | return (!hlt_counter && boot_cpu_data.hlt_works_ok); |
| 359 | } |
| 360 | #else |
| 361 | static inline int hlt_use_halt(void) |
| 362 | { |
| 363 | return 1; |
| 364 | } |
| 365 | #endif |
| 366 | |
| 367 | /* |
| 368 | * We use this if we don't have any better |
| 369 | * idle routine.. |
| 370 | */ |
| 371 | void default_idle(void) |
| 372 | { |
| 373 | if (hlt_use_halt()) { |
| 374 | trace_power_start(POWER_CSTATE, 1); |
| 375 | current_thread_info()->status &= ~TS_POLLING; |
| 376 | /* |
| 377 | * TS_POLLING-cleared state must be visible before we |
| 378 | * test NEED_RESCHED: |
| 379 | */ |
| 380 | smp_mb(); |
| 381 | |
| 382 | if (!need_resched()) |
| 383 | safe_halt(); /* enables interrupts racelessly */ |
| 384 | else |
| 385 | local_irq_enable(); |
| 386 | current_thread_info()->status |= TS_POLLING; |
| 387 | } else { |
| 388 | local_irq_enable(); |
| 389 | /* loop is done by the caller */ |
| 390 | cpu_relax(); |
| 391 | } |
| 392 | } |
| 393 | #ifdef CONFIG_APM_MODULE |
| 394 | EXPORT_SYMBOL(default_idle); |
| 395 | #endif |
| 396 | |
| 397 | void stop_this_cpu(void *dummy) |
| 398 | { |
| 399 | local_irq_disable(); |
| 400 | /* |
| 401 | * Remove this CPU: |
| 402 | */ |
| 403 | set_cpu_online(smp_processor_id(), false); |
| 404 | disable_local_APIC(); |
| 405 | |
| 406 | for (;;) { |
| 407 | if (hlt_works(smp_processor_id())) |
| 408 | halt(); |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | static void do_nothing(void *unused) |
| 413 | { |
| 414 | } |
| 415 | |
| 416 | /* |
| 417 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of |
| 418 | * pm_idle and update to new pm_idle value. Required while changing pm_idle |
| 419 | * handler on SMP systems. |
| 420 | * |
| 421 | * Caller must have changed pm_idle to the new value before the call. Old |
| 422 | * pm_idle value will not be used by any CPU after the return of this function. |
| 423 | */ |
| 424 | void cpu_idle_wait(void) |
| 425 | { |
| 426 | smp_mb(); |
| 427 | /* kick all the CPUs so that they exit out of pm_idle */ |
| 428 | smp_call_function(do_nothing, NULL, 1); |
| 429 | } |
| 430 | EXPORT_SYMBOL_GPL(cpu_idle_wait); |
| 431 | |
| 432 | /* |
| 433 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, |
| 434 | * which can obviate IPI to trigger checking of need_resched. |
| 435 | * We execute MONITOR against need_resched and enter optimized wait state |
| 436 | * through MWAIT. Whenever someone changes need_resched, we would be woken |
| 437 | * up from MWAIT (without an IPI). |
| 438 | * |
| 439 | * New with Core Duo processors, MWAIT can take some hints based on CPU |
| 440 | * capability. |
| 441 | */ |
| 442 | void mwait_idle_with_hints(unsigned long ax, unsigned long cx) |
| 443 | { |
| 444 | trace_power_start(POWER_CSTATE, (ax>>4)+1); |
| 445 | if (!need_resched()) { |
| 446 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
| 447 | clflush((void *)¤t_thread_info()->flags); |
| 448 | |
| 449 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
| 450 | smp_mb(); |
| 451 | if (!need_resched()) |
| 452 | __mwait(ax, cx); |
| 453 | } |
| 454 | } |
| 455 | |
| 456 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ |
| 457 | static void mwait_idle(void) |
| 458 | { |
| 459 | if (!need_resched()) { |
| 460 | trace_power_start(POWER_CSTATE, 1); |
| 461 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
| 462 | clflush((void *)¤t_thread_info()->flags); |
| 463 | |
| 464 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
| 465 | smp_mb(); |
| 466 | if (!need_resched()) |
| 467 | __sti_mwait(0, 0); |
| 468 | else |
| 469 | local_irq_enable(); |
| 470 | } else |
| 471 | local_irq_enable(); |
| 472 | } |
| 473 | |
| 474 | /* |
| 475 | * On SMP it's slightly faster (but much more power-consuming!) |
| 476 | * to poll the ->work.need_resched flag instead of waiting for the |
| 477 | * cross-CPU IPI to arrive. Use this option with caution. |
| 478 | */ |
| 479 | static void poll_idle(void) |
| 480 | { |
| 481 | trace_power_start(POWER_CSTATE, 0); |
| 482 | local_irq_enable(); |
| 483 | while (!need_resched()) |
| 484 | cpu_relax(); |
| 485 | trace_power_end(0); |
| 486 | } |
| 487 | |
| 488 | /* |
| 489 | * mwait selection logic: |
| 490 | * |
| 491 | * It depends on the CPU. For AMD CPUs that support MWAIT this is |
| 492 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings |
| 493 | * then depend on a clock divisor and current Pstate of the core. If |
| 494 | * all cores of a processor are in halt state (C1) the processor can |
| 495 | * enter the C1E (C1 enhanced) state. If mwait is used this will never |
| 496 | * happen. |
| 497 | * |
| 498 | * idle=mwait overrides this decision and forces the usage of mwait. |
| 499 | */ |
| 500 | static int __cpuinitdata force_mwait; |
| 501 | |
| 502 | #define MWAIT_INFO 0x05 |
| 503 | #define MWAIT_ECX_EXTENDED_INFO 0x01 |
| 504 | #define MWAIT_EDX_C1 0xf0 |
| 505 | |
| 506 | static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) |
| 507 | { |
| 508 | u32 eax, ebx, ecx, edx; |
| 509 | |
| 510 | if (force_mwait) |
| 511 | return 1; |
| 512 | |
| 513 | if (c->cpuid_level < MWAIT_INFO) |
| 514 | return 0; |
| 515 | |
| 516 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); |
| 517 | /* Check, whether EDX has extended info about MWAIT */ |
| 518 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) |
| 519 | return 1; |
| 520 | |
| 521 | /* |
| 522 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether |
| 523 | * C1 supports MWAIT |
| 524 | */ |
| 525 | return (edx & MWAIT_EDX_C1); |
| 526 | } |
| 527 | |
| 528 | /* |
| 529 | * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e. |
| 530 | * For more information see |
| 531 | * - Erratum #400 for NPT family 0xf and family 0x10 CPUs |
| 532 | * - Erratum #365 for family 0x11 (not affected because C1e not in use) |
| 533 | */ |
| 534 | static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) |
| 535 | { |
| 536 | u64 val; |
| 537 | if (c->x86_vendor != X86_VENDOR_AMD) |
| 538 | goto no_c1e_idle; |
| 539 | |
| 540 | /* Family 0x0f models < rev F do not have C1E */ |
| 541 | if (c->x86 == 0x0F && c->x86_model >= 0x40) |
| 542 | return 1; |
| 543 | |
| 544 | if (c->x86 == 0x10) { |
| 545 | /* |
| 546 | * check OSVW bit for CPUs that are not affected |
| 547 | * by erratum #400 |
| 548 | */ |
| 549 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val); |
| 550 | if (val >= 2) { |
| 551 | rdmsrl(MSR_AMD64_OSVW_STATUS, val); |
| 552 | if (!(val & BIT(1))) |
| 553 | goto no_c1e_idle; |
| 554 | } |
| 555 | return 1; |
| 556 | } |
| 557 | |
| 558 | no_c1e_idle: |
| 559 | return 0; |
| 560 | } |
| 561 | |
| 562 | static cpumask_var_t c1e_mask; |
| 563 | static int c1e_detected; |
| 564 | |
| 565 | void c1e_remove_cpu(int cpu) |
| 566 | { |
| 567 | if (c1e_mask != NULL) |
| 568 | cpumask_clear_cpu(cpu, c1e_mask); |
| 569 | } |
| 570 | |
| 571 | /* |
| 572 | * C1E aware idle routine. We check for C1E active in the interrupt |
| 573 | * pending message MSR. If we detect C1E, then we handle it the same |
| 574 | * way as C3 power states (local apic timer and TSC stop) |
| 575 | */ |
| 576 | static void c1e_idle(void) |
| 577 | { |
| 578 | if (need_resched()) |
| 579 | return; |
| 580 | |
| 581 | if (!c1e_detected) { |
| 582 | u32 lo, hi; |
| 583 | |
| 584 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); |
| 585 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
| 586 | c1e_detected = 1; |
| 587 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
| 588 | mark_tsc_unstable("TSC halt in AMD C1E"); |
| 589 | printk(KERN_INFO "System has AMD C1E enabled\n"); |
| 590 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E); |
| 591 | } |
| 592 | } |
| 593 | |
| 594 | if (c1e_detected) { |
| 595 | int cpu = smp_processor_id(); |
| 596 | |
| 597 | if (!cpumask_test_cpu(cpu, c1e_mask)) { |
| 598 | cpumask_set_cpu(cpu, c1e_mask); |
| 599 | /* |
| 600 | * Force broadcast so ACPI can not interfere. |
| 601 | */ |
| 602 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
| 603 | &cpu); |
| 604 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", |
| 605 | cpu); |
| 606 | } |
| 607 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); |
| 608 | |
| 609 | default_idle(); |
| 610 | |
| 611 | /* |
| 612 | * The switch back from broadcast mode needs to be |
| 613 | * called with interrupts disabled. |
| 614 | */ |
| 615 | local_irq_disable(); |
| 616 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); |
| 617 | local_irq_enable(); |
| 618 | } else |
| 619 | default_idle(); |
| 620 | } |
| 621 | |
| 622 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
| 623 | { |
| 624 | #ifdef CONFIG_SMP |
| 625 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
| 626 | printk_once(KERN_WARNING "WARNING: polling idle and HT enabled," |
| 627 | " performance may degrade.\n"); |
| 628 | } |
| 629 | #endif |
| 630 | if (pm_idle) |
| 631 | return; |
| 632 | |
| 633 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
| 634 | /* |
| 635 | * One CPU supports mwait => All CPUs supports mwait |
| 636 | */ |
| 637 | printk(KERN_INFO "using mwait in idle threads.\n"); |
| 638 | pm_idle = mwait_idle; |
| 639 | } else if (check_c1e_idle(c)) { |
| 640 | printk(KERN_INFO "using C1E aware idle routine\n"); |
| 641 | pm_idle = c1e_idle; |
| 642 | } else |
| 643 | pm_idle = default_idle; |
| 644 | } |
| 645 | |
| 646 | void __init init_c1e_mask(void) |
| 647 | { |
| 648 | /* If we're using c1e_idle, we need to allocate c1e_mask. */ |
| 649 | if (pm_idle == c1e_idle) |
| 650 | zalloc_cpumask_var(&c1e_mask, GFP_KERNEL); |
| 651 | } |
| 652 | |
| 653 | static int __init idle_setup(char *str) |
| 654 | { |
| 655 | if (!str) |
| 656 | return -EINVAL; |
| 657 | |
| 658 | if (!strcmp(str, "poll")) { |
| 659 | printk("using polling idle threads.\n"); |
| 660 | pm_idle = poll_idle; |
| 661 | } else if (!strcmp(str, "mwait")) |
| 662 | force_mwait = 1; |
| 663 | else if (!strcmp(str, "halt")) { |
| 664 | /* |
| 665 | * When the boot option of idle=halt is added, halt is |
| 666 | * forced to be used for CPU idle. In such case CPU C2/C3 |
| 667 | * won't be used again. |
| 668 | * To continue to load the CPU idle driver, don't touch |
| 669 | * the boot_option_idle_override. |
| 670 | */ |
| 671 | pm_idle = default_idle; |
| 672 | idle_halt = 1; |
| 673 | return 0; |
| 674 | } else if (!strcmp(str, "nomwait")) { |
| 675 | /* |
| 676 | * If the boot option of "idle=nomwait" is added, |
| 677 | * it means that mwait will be disabled for CPU C2/C3 |
| 678 | * states. In such case it won't touch the variable |
| 679 | * of boot_option_idle_override. |
| 680 | */ |
| 681 | idle_nomwait = 1; |
| 682 | return 0; |
| 683 | } else |
| 684 | return -1; |
| 685 | |
| 686 | boot_option_idle_override = 1; |
| 687 | return 0; |
| 688 | } |
| 689 | early_param("idle", idle_setup); |
| 690 | |
| 691 | unsigned long arch_align_stack(unsigned long sp) |
| 692 | { |
| 693 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) |
| 694 | sp -= get_random_int() % 8192; |
| 695 | return sp & ~0xf; |
| 696 | } |
| 697 | |
| 698 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
| 699 | { |
| 700 | unsigned long range_end = mm->brk + 0x02000000; |
| 701 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; |
| 702 | } |
| 703 | |