[linux-2.6-block.git] / arch / x86 / kernel / process.c

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/prctl.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/clockchips.h>
#include <linux/random.h>
#include <linux/user-return-notifier.h>
#include <linux/dmi.h>
#include <linux/utsname.h>
#include <linux/stackprotector.h>
#include <linux/tick.h>
#include <linux/cpuidle.h>
#include <trace/events/power.h>
#include <linux/hw_breakpoint.h>
#include <asm/cpu.h>
#include <asm/apic.h>
#include <asm/syscalls.h>
#include <asm/idle.h>
#include <asm/uaccess.h>
#include <asm/i387.h>
#include <asm/fpu-internal.h>
#include <asm/debugreg.h>
#include <asm/nmi.h>
#include <asm/tlbflush.h>

/*
 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
 * no more per-task TSS's. The TSS size is kept cacheline-aligned
 * so they are allowed to end up in the .data..cacheline_aligned
 * section. Since TSS's are completely CPU-local, we want them
 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
 */
__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;

#ifdef CONFIG_X86_64
static DEFINE_PER_CPU(unsigned char, is_idle);
static ATOMIC_NOTIFIER_HEAD(idle_notifier);

void idle_notifier_register(struct notifier_block *n)
{
	atomic_notifier_chain_register(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_register);

void idle_notifier_unregister(struct notifier_block *n)
{
	atomic_notifier_chain_unregister(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_unregister);
#endif

struct kmem_cache *task_xstate_cachep;
EXPORT_SYMBOL_GPL(task_xstate_cachep);

/*
 * this gets called so that we can store lazy state into memory and copy the
 * current task into the new thread.
 */
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	*dst = *src;

	dst->thread.fpu_counter = 0;
	dst->thread.fpu.has_fpu = 0;
	dst->thread.fpu.state = NULL;
	task_disable_lazy_fpu_restore(dst);
	if (tsk_used_math(src)) {
		int err = fpu_alloc(&dst->thread.fpu);
		if (err)
			return err;
		fpu_copy(dst, src);
	}
	return 0;
}

void free_thread_xstate(struct task_struct *tsk)
{
	fpu_free(&tsk->thread.fpu);
}

void arch_release_task_struct(struct task_struct *tsk)
{
	free_thread_xstate(tsk);
}

void arch_task_cache_init(void)
{
        task_xstate_cachep =
        	kmem_cache_create("task_xstate", xstate_size,
				  __alignof__(union thread_xstate),
				  SLAB_PANIC | SLAB_NOTRACK, NULL);
	setup_xstate_comp();
}

/*
 * Free current thread data structures etc..
 */
void exit_thread(void)
{
	struct task_struct *me = current;
	struct thread_struct *t = &me->thread;
	unsigned long *bp = t->io_bitmap_ptr;

	if (bp) {
		struct tss_struct *tss = &per_cpu(init_tss, get_cpu());

		t->io_bitmap_ptr = NULL;
		clear_thread_flag(TIF_IO_BITMAP);
		/*
		 * Careful, clear this in the TSS too:
		 */
		memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
		t->io_bitmap_max = 0;
		put_cpu();
		kfree(bp);
	}

	drop_fpu(me);
}

void flush_thread(void)
{
	struct task_struct *tsk = current;

	flush_ptrace_hw_breakpoint(tsk);
	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));

	drop_init_fpu(tsk);
	/*
	 * Free the FPU state for non xsave platforms. They get reallocated
	 * lazily at the first use.
	 */
	if (!use_eager_fpu())
		free_thread_xstate(tsk);
	else if (!used_math()) {
		/* kthread execs. TODO: cleanup this horror. */
		if (WARN_ON(init_fpu(current)))
			force_sig(SIGKILL, current);
		user_fpu_begin();
		restore_init_xstate();
	}
}

static void hard_disable_TSC(void)
{
	cr4_set_bits(X86_CR4_TSD);
}

void disable_TSC(void)
{
	preempt_disable();
	if (!test_and_set_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_disable_TSC();
	preempt_enable();
}

static void hard_enable_TSC(void)
{
	cr4_clear_bits(X86_CR4_TSD);
}

static void enable_TSC(void)
{
	preempt_disable();
	if (test_and_clear_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_enable_TSC();
	preempt_enable();
}

int get_tsc_mode(unsigned long adr)
{
	unsigned int val;

	if (test_thread_flag(TIF_NOTSC))
		val = PR_TSC_SIGSEGV;
	else
		val = PR_TSC_ENABLE;

	return put_user(val, (unsigned int __user *)adr);
}

int set_tsc_mode(unsigned int val)
{
	if (val == PR_TSC_SIGSEGV)
		disable_TSC();
	else if (val == PR_TSC_ENABLE)
		enable_TSC();
	else
		return -EINVAL;

	return 0;
}

void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
		      struct tss_struct *tss)
{
	struct thread_struct *prev, *next;

	prev = &prev_p->thread;
	next = &next_p->thread;

	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	    test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
		unsigned long debugctl = get_debugctlmsr();

		debugctl &= ~DEBUGCTLMSR_BTF;
		if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
			debugctl |= DEBUGCTLMSR_BTF;

		update_debugctlmsr(debugctl);
	}

	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	    test_tsk_thread_flag(next_p, TIF_NOTSC)) {
		/* prev and next are different */
		if (test_tsk_thread_flag(next_p, TIF_NOTSC))
			hard_disable_TSC();
		else
			hard_enable_TSC();
	}

	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
		/*
		 * Copy the relevant range of the IO bitmap.
		 * Normally this is 128 bytes or less:
		 */
		memcpy(tss->io_bitmap, next->io_bitmap_ptr,
		       max(prev->io_bitmap_max, next->io_bitmap_max));
	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
		/*
		 * Clear any possible leftover bits:
		 */
		memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	}
	propagate_user_return_notify(prev_p, next_p);
}

/*
 * Idle related variables and functions
 */
unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
EXPORT_SYMBOL(boot_option_idle_override);

static void (*x86_idle)(void);

#ifndef CONFIG_SMP
static inline void play_dead(void)
{
	BUG();
}
#endif

#ifdef CONFIG_X86_64
void enter_idle(void)
{
	this_cpu_write(is_idle, 1);
	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
}

static void __exit_idle(void)
{
	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
		return;
	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
}

/* Called from interrupts to signify idle end */
void exit_idle(void)
{
	/* idle loop has pid 0 */
	if (current->pid)
		return;
	__exit_idle();
}
#endif

void arch_cpu_idle_enter(void)
{
	local_touch_nmi();
	enter_idle();
}

void arch_cpu_idle_exit(void)
{
	__exit_idle();
}

void arch_cpu_idle_dead(void)
{
	play_dead();
}

/*
 * Called from the generic idle code.
 */
void arch_cpu_idle(void)
{
	x86_idle();
}

/*
 * We use this if we don't have any better idle routine..
 */
void default_idle(void)
{
	trace_cpu_idle_rcuidle(1, smp_processor_id());
	safe_halt();
	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}
#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

#ifdef CONFIG_XEN
bool xen_set_default_idle(void)
{
	bool ret = !!x86_idle;

	x86_idle = default_idle;

	return ret;
}
#endif
void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
	 * Remove this CPU:
	 */
	set_cpu_online(smp_processor_id(), false);
	disable_local_APIC();

	for (;;)
		halt();
}

bool amd_e400_c1e_detected;
EXPORT_SYMBOL(amd_e400_c1e_detected);

static cpumask_var_t amd_e400_c1e_mask;

void amd_e400_remove_cpu(int cpu)
{
	if (amd_e400_c1e_mask != NULL)
		cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
}

/*
 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
 * pending message MSR. If we detect C1E, then we handle it the same
 * way as C3 power states (local apic timer and TSC stop)
 */
static void amd_e400_idle(void)
{
	if (!amd_e400_c1e_detected) {
		u32 lo, hi;

		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);

		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
			amd_e400_c1e_detected = true;
			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
				mark_tsc_unstable("TSC halt in AMD C1E");
			pr_info("System has AMD C1E enabled\n");
		}
	}

	if (amd_e400_c1e_detected) {
		int cpu = smp_processor_id();

		if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
			cpumask_set_cpu(cpu, amd_e400_c1e_mask);
			/*
			 * Force broadcast so ACPI can not interfere.
			 */
			clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
					   &cpu);
			pr_info("Switch to broadcast mode on CPU%d\n", cpu);
		}
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

		default_idle();

		/*
		 * The switch back from broadcast mode needs to be
		 * called with interrupts disabled.
		 */
		local_irq_disable();
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
		local_irq_enable();
	} else
		default_idle();
}

void select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
		pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
#endif
	if (x86_idle || boot_option_idle_override == IDLE_POLL)
		return;

	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
		/* E400: APIC timer interrupt does not wake up CPU from C1e */
		pr_info("using AMD E400 aware idle routine\n");
		x86_idle = amd_e400_idle;
	} else
		x86_idle = default_idle;
}

void __init init_amd_e400_c1e_mask(void)
{
	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
	if (x86_idle == amd_e400_idle)
		zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
}

static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		pr_info("using polling idle threads\n");
		boot_option_idle_override = IDLE_POLL;
		cpu_idle_poll_ctrl(true);
	} else if (!strcmp(str, "halt")) {
		/*
		 * When the boot option of idle=halt is added, halt is
		 * forced to be used for CPU idle. In such case CPU C2/C3
		 * won't be used again.
		 * To continue to load the CPU idle driver, don't touch
		 * the boot_option_idle_override.
		 */
		x86_idle = default_idle;
		boot_option_idle_override = IDLE_HALT;
	} else if (!strcmp(str, "nomwait")) {
		/*
		 * If the boot option of "idle=nomwait" is added,
		 * it means that mwait will be disabled for CPU C2/C3
		 * states. In such case it won't touch the variable
		 * of boot_option_idle_override.
		 */
		boot_option_idle_override = IDLE_NOMWAIT;
	} else
		return -1;

	return 0;
}
early_param("idle", idle_setup);

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() % 8192;
	return sp & ~0xf;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	unsigned long range_end = mm->brk + 0x02000000;
	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
}
Commit	Line	Data
	1	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	2
	3	#include <linux/errno.h>
	4	#include <linux/kernel.h>
	5	#include <linux/mm.h>
	6	#include <linux/smp.h>
	7	#include <linux/prctl.h>
	8	#include <linux/slab.h>
	9	#include <linux/sched.h>
	10	#include <linux/module.h>
	11	#include <linux/pm.h>
	12	#include <linux/clockchips.h>
	13	#include <linux/random.h>
	14	#include <linux/user-return-notifier.h>
	15	#include <linux/dmi.h>
	16	#include <linux/utsname.h>
	17	#include <linux/stackprotector.h>
	18	#include <linux/tick.h>
	19	#include <linux/cpuidle.h>
	20	#include <trace/events/power.h>
	21	#include <linux/hw_breakpoint.h>
	22	#include <asm/cpu.h>
	23	#include <asm/apic.h>
	24	#include <asm/syscalls.h>
	25	#include <asm/idle.h>
	26	#include <asm/uaccess.h>
	27	#include <asm/i387.h>
	28	#include <asm/fpu-internal.h>
	29	#include <asm/debugreg.h>
	30	#include <asm/nmi.h>
	31	#include <asm/tlbflush.h>
	32
	33	/*
	34	* per-CPU TSS segments. Threads are completely 'soft' on Linux,
	35	* no more per-task TSS's. The TSS size is kept cacheline-aligned
	36	* so they are allowed to end up in the .data..cacheline_aligned
	37	* section. Since TSS's are completely CPU-local, we want them
	38	* on exact cacheline boundaries, to eliminate cacheline ping-pong.
	39	*/
	40	__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
	41
	42	#ifdef CONFIG_X86_64
	43	static DEFINE_PER_CPU(unsigned char, is_idle);
	44	static ATOMIC_NOTIFIER_HEAD(idle_notifier);
	45
	46	void idle_notifier_register(struct notifier_block *n)
	47	{
	48	atomic_notifier_chain_register(&idle_notifier, n);
	49	}
	50	EXPORT_SYMBOL_GPL(idle_notifier_register);
	51
	52	void idle_notifier_unregister(struct notifier_block *n)
	53	{
	54	atomic_notifier_chain_unregister(&idle_notifier, n);
	55	}
	56	EXPORT_SYMBOL_GPL(idle_notifier_unregister);
	57	#endif
	58
	59	struct kmem_cache *task_xstate_cachep;
	60	EXPORT_SYMBOL_GPL(task_xstate_cachep);
	61
	62	/*
	63	* this gets called so that we can store lazy state into memory and copy the
	64	* current task into the new thread.
	65	*/
	66	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	67	{
	68	dst = src;
	69
	70	dst->thread.fpu_counter = 0;
	71	dst->thread.fpu.has_fpu = 0;
	72	dst->thread.fpu.state = NULL;
	73	task_disable_lazy_fpu_restore(dst);
	74	if (tsk_used_math(src)) {
	75	int err = fpu_alloc(&dst->thread.fpu);
	76	if (err)
	77	return err;
	78	fpu_copy(dst, src);
	79	}
	80	return 0;
	81	}
	82
	83	void free_thread_xstate(struct task_struct *tsk)
	84	{
	85	fpu_free(&tsk->thread.fpu);
	86	}
	87
	88	void arch_release_task_struct(struct task_struct *tsk)
	89	{
	90	free_thread_xstate(tsk);
	91	}
	92
	93	void arch_task_cache_init(void)
	94	{
	95	task_xstate_cachep =
	96	kmem_cache_create("task_xstate", xstate_size,
	97	__alignof__(union thread_xstate),
	98	SLAB_PANIC \| SLAB_NOTRACK, NULL);
	99	setup_xstate_comp();
	100	}
	101
	102	/*
	103	* Free current thread data structures etc..
	104	*/
	105	void exit_thread(void)
	106	{
	107	struct task_struct *me = current;
	108	struct thread_struct *t = &me->thread;
	109	unsigned long *bp = t->io_bitmap_ptr;
	110
	111	if (bp) {
	112	struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
	113
	114	t->io_bitmap_ptr = NULL;
	115	clear_thread_flag(TIF_IO_BITMAP);
	116	/*
	117	* Careful, clear this in the TSS too:
	118	*/
	119	memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
	120	t->io_bitmap_max = 0;
	121	put_cpu();
	122	kfree(bp);
	123	}
	124
	125	drop_fpu(me);
	126	}
	127
	128	void flush_thread(void)
	129	{
	130	struct task_struct *tsk = current;
	131
	132	flush_ptrace_hw_breakpoint(tsk);
	133	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
	134
	135	drop_init_fpu(tsk);
	136	/*
	137	* Free the FPU state for non xsave platforms. They get reallocated
	138	* lazily at the first use.
	139	*/
	140	if (!use_eager_fpu())
	141	free_thread_xstate(tsk);
	142	else if (!used_math()) {
	143	/* kthread execs. TODO: cleanup this horror. */
	144	if (WARN_ON(init_fpu(current)))
	145	force_sig(SIGKILL, current);
	146	user_fpu_begin();
	147	restore_init_xstate();
	148	}
	149	}
	150
	151	static void hard_disable_TSC(void)
	152	{
	153	cr4_set_bits(X86_CR4_TSD);
	154	}
	155
	156	void disable_TSC(void)
	157	{
	158	preempt_disable();
	159	if (!test_and_set_thread_flag(TIF_NOTSC))
	160	/*
	161	* Must flip the CPU state synchronously with
	162	* TIF_NOTSC in the current running context.
	163	*/
	164	hard_disable_TSC();
	165	preempt_enable();
	166	}
	167
	168	static void hard_enable_TSC(void)
	169	{
	170	cr4_clear_bits(X86_CR4_TSD);
	171	}
	172
	173	static void enable_TSC(void)
	174	{
	175	preempt_disable();
	176	if (test_and_clear_thread_flag(TIF_NOTSC))
	177	/*
	178	* Must flip the CPU state synchronously with
	179	* TIF_NOTSC in the current running context.
	180	*/
	181	hard_enable_TSC();
	182	preempt_enable();
	183	}
	184
	185	int get_tsc_mode(unsigned long adr)
	186	{
	187	unsigned int val;
	188
	189	if (test_thread_flag(TIF_NOTSC))
	190	val = PR_TSC_SIGSEGV;
	191	else
	192	val = PR_TSC_ENABLE;
	193
	194	return put_user(val, (unsigned int __user *)adr);
	195	}
	196
	197	int set_tsc_mode(unsigned int val)
	198	{
	199	if (val == PR_TSC_SIGSEGV)
	200	disable_TSC();
	201	else if (val == PR_TSC_ENABLE)
	202	enable_TSC();
	203	else
	204	return -EINVAL;
	205
	206	return 0;
	207	}
	208
	209	void __switch_to_xtra(struct task_struct prev_p, struct task_struct next_p,
	210	struct tss_struct *tss)
	211	{
	212	struct thread_struct prev, next;
	213
	214	prev = &prev_p->thread;
	215	next = &next_p->thread;
	216
	217	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	218	test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
	219	unsigned long debugctl = get_debugctlmsr();
	220
	221	debugctl &= ~DEBUGCTLMSR_BTF;
	222	if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
	223	debugctl \|= DEBUGCTLMSR_BTF;
	224
	225	update_debugctlmsr(debugctl);
	226	}
	227
	228	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	229	test_tsk_thread_flag(next_p, TIF_NOTSC)) {
	230	/* prev and next are different */
	231	if (test_tsk_thread_flag(next_p, TIF_NOTSC))
	232	hard_disable_TSC();
	233	else
	234	hard_enable_TSC();
	235	}
	236
	237	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
	238	/*
	239	* Copy the relevant range of the IO bitmap.
	240	* Normally this is 128 bytes or less:
	241	*/
	242	memcpy(tss->io_bitmap, next->io_bitmap_ptr,
	243	max(prev->io_bitmap_max, next->io_bitmap_max));
	244	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
	245	/*
	246	* Clear any possible leftover bits:
	247	*/
	248	memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	249	}
	250	propagate_user_return_notify(prev_p, next_p);
	251	}
	252
	253	/*
	254	* Idle related variables and functions
	255	*/
	256	unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
	257	EXPORT_SYMBOL(boot_option_idle_override);
	258
	259	static void (*x86_idle)(void);
	260
	261	#ifndef CONFIG_SMP
	262	static inline void play_dead(void)
	263	{
	264	BUG();
	265	}
	266	#endif
	267
	268	#ifdef CONFIG_X86_64
	269	void enter_idle(void)
	270	{
	271	this_cpu_write(is_idle, 1);
	272	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
	273	}
	274
	275	static void __exit_idle(void)
	276	{
	277	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
	278	return;
	279	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
	280	}
	281
	282	/* Called from interrupts to signify idle end */
	283	void exit_idle(void)
	284	{
	285	/* idle loop has pid 0 */
	286	if (current->pid)
	287	return;
	288	__exit_idle();
	289	}
	290	#endif
	291
	292	void arch_cpu_idle_enter(void)
	293	{
	294	local_touch_nmi();
	295	enter_idle();
	296	}
	297
	298	void arch_cpu_idle_exit(void)
	299	{
	300	__exit_idle();
	301	}
	302
	303	void arch_cpu_idle_dead(void)
	304	{
	305	play_dead();
	306	}
	307
	308	/*
	309	* Called from the generic idle code.
	310	*/
	311	void arch_cpu_idle(void)
	312	{
	313	x86_idle();
	314	}
	315
	316	/*
	317	* We use this if we don't have any better idle routine..
	318	*/
	319	void default_idle(void)
	320	{
	321	trace_cpu_idle_rcuidle(1, smp_processor_id());
	322	safe_halt();
	323	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
	324	}
	325	#ifdef CONFIG_APM_MODULE
	326	EXPORT_SYMBOL(default_idle);
	327	#endif
	328
	329	#ifdef CONFIG_XEN
	330	bool xen_set_default_idle(void)
	331	{
	332	bool ret = !!x86_idle;
	333
	334	x86_idle = default_idle;
	335
	336	return ret;
	337	}
	338	#endif
	339	void stop_this_cpu(void *dummy)
	340	{
	341	local_irq_disable();
	342	/*
	343	* Remove this CPU:
	344	*/
	345	set_cpu_online(smp_processor_id(), false);
	346	disable_local_APIC();
	347
	348	for (;;)
	349	halt();
	350	}
	351
	352	bool amd_e400_c1e_detected;
	353	EXPORT_SYMBOL(amd_e400_c1e_detected);
	354
	355	static cpumask_var_t amd_e400_c1e_mask;
	356
	357	void amd_e400_remove_cpu(int cpu)
	358	{
	359	if (amd_e400_c1e_mask != NULL)
	360	cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
	361	}
	362
	363	/*
	364	* AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
	365	* pending message MSR. If we detect C1E, then we handle it the same
	366	* way as C3 power states (local apic timer and TSC stop)
	367	*/
	368	static void amd_e400_idle(void)
	369	{
	370	if (!amd_e400_c1e_detected) {
	371	u32 lo, hi;
	372
	373	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
	374
	375	if (lo & K8_INTP_C1E_ACTIVE_MASK) {
	376	amd_e400_c1e_detected = true;
	377	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
	378	mark_tsc_unstable("TSC halt in AMD C1E");
	379	pr_info("System has AMD C1E enabled\n");
	380	}
	381	}
	382
	383	if (amd_e400_c1e_detected) {
	384	int cpu = smp_processor_id();
	385
	386	if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
	387	cpumask_set_cpu(cpu, amd_e400_c1e_mask);
	388	/*
	389	* Force broadcast so ACPI can not interfere.
	390	*/
	391	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
	392	&cpu);
	393	pr_info("Switch to broadcast mode on CPU%d\n", cpu);
	394	}
	395	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
	396
	397	default_idle();
	398
	399	/*
	400	* The switch back from broadcast mode needs to be
	401	* called with interrupts disabled.
	402	*/
	403	local_irq_disable();
	404	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	405	local_irq_enable();
	406	} else
	407	default_idle();
	408	}
	409
	410	void select_idle_routine(const struct cpuinfo_x86 *c)
	411	{
	412	#ifdef CONFIG_SMP
	413	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
	414	pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
	415	#endif
	416	if (x86_idle \|\| boot_option_idle_override == IDLE_POLL)
	417	return;
	418
	419	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
	420	/* E400: APIC timer interrupt does not wake up CPU from C1e */
	421	pr_info("using AMD E400 aware idle routine\n");
	422	x86_idle = amd_e400_idle;
	423	} else
	424	x86_idle = default_idle;
	425	}
	426
	427	void __init init_amd_e400_c1e_mask(void)
	428	{
	429	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
	430	if (x86_idle == amd_e400_idle)
	431	zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
	432	}
	433
	434	static int __init idle_setup(char *str)
	435	{
	436	if (!str)
	437	return -EINVAL;
	438
	439	if (!strcmp(str, "poll")) {
	440	pr_info("using polling idle threads\n");
	441	boot_option_idle_override = IDLE_POLL;
	442	cpu_idle_poll_ctrl(true);
	443	} else if (!strcmp(str, "halt")) {
	444	/*
	445	* When the boot option of idle=halt is added, halt is
	446	* forced to be used for CPU idle. In such case CPU C2/C3
	447	* won't be used again.
	448	* To continue to load the CPU idle driver, don't touch
	449	* the boot_option_idle_override.
	450	*/
	451	x86_idle = default_idle;
	452	boot_option_idle_override = IDLE_HALT;
	453	} else if (!strcmp(str, "nomwait")) {
	454	/*
	455	* If the boot option of "idle=nomwait" is added,
	456	* it means that mwait will be disabled for CPU C2/C3
	457	* states. In such case it won't touch the variable
	458	* of boot_option_idle_override.
	459	*/
	460	boot_option_idle_override = IDLE_NOMWAIT;
	461	} else
	462	return -1;
	463
	464	return 0;
	465	}
	466	early_param("idle", idle_setup);
	467
	468	unsigned long arch_align_stack(unsigned long sp)
	469	{
	470	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	471	sp -= get_random_int() % 8192;
	472	return sp & ~0xf;
	473	}
	474
	475	unsigned long arch_randomize_brk(struct mm_struct *mm)
	476	{
	477	unsigned long range_end = mm->brk + 0x02000000;
	478	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
	479	}
	480