| 1 | /* |
| 2 | * Performance events x86 architecture code |
| 3 | * |
| 4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
| 5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
| 6 | * Copyright (C) 2009 Jaswinder Singh Rajput |
| 7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
| 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> |
| 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
| 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
| 11 | * |
| 12 | * For licencing details see kernel-base/COPYING |
| 13 | */ |
| 14 | |
| 15 | #include <linux/perf_event.h> |
| 16 | #include <linux/capability.h> |
| 17 | #include <linux/notifier.h> |
| 18 | #include <linux/hardirq.h> |
| 19 | #include <linux/kprobes.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/kdebug.h> |
| 22 | #include <linux/sched.h> |
| 23 | #include <linux/uaccess.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/highmem.h> |
| 26 | #include <linux/cpu.h> |
| 27 | #include <linux/bitops.h> |
| 28 | |
| 29 | #include <asm/apic.h> |
| 30 | #include <asm/stacktrace.h> |
| 31 | #include <asm/nmi.h> |
| 32 | #include <asm/compat.h> |
| 33 | |
| 34 | #if 0 |
| 35 | #undef wrmsrl |
| 36 | #define wrmsrl(msr, val) \ |
| 37 | do { \ |
| 38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ |
| 39 | (unsigned long)(val)); \ |
| 40 | native_write_msr((msr), (u32)((u64)(val)), \ |
| 41 | (u32)((u64)(val) >> 32)); \ |
| 42 | } while (0) |
| 43 | #endif |
| 44 | |
| 45 | /* |
| 46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context |
| 47 | */ |
| 48 | static unsigned long |
| 49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) |
| 50 | { |
| 51 | unsigned long offset, addr = (unsigned long)from; |
| 52 | unsigned long size, len = 0; |
| 53 | struct page *page; |
| 54 | void *map; |
| 55 | int ret; |
| 56 | |
| 57 | do { |
| 58 | ret = __get_user_pages_fast(addr, 1, 0, &page); |
| 59 | if (!ret) |
| 60 | break; |
| 61 | |
| 62 | offset = addr & (PAGE_SIZE - 1); |
| 63 | size = min(PAGE_SIZE - offset, n - len); |
| 64 | |
| 65 | map = kmap_atomic(page); |
| 66 | memcpy(to, map+offset, size); |
| 67 | kunmap_atomic(map); |
| 68 | put_page(page); |
| 69 | |
| 70 | len += size; |
| 71 | to += size; |
| 72 | addr += size; |
| 73 | |
| 74 | } while (len < n); |
| 75 | |
| 76 | return len; |
| 77 | } |
| 78 | |
| 79 | struct event_constraint { |
| 80 | union { |
| 81 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 82 | u64 idxmsk64; |
| 83 | }; |
| 84 | u64 code; |
| 85 | u64 cmask; |
| 86 | int weight; |
| 87 | }; |
| 88 | |
| 89 | struct amd_nb { |
| 90 | int nb_id; /* NorthBridge id */ |
| 91 | int refcnt; /* reference count */ |
| 92 | struct perf_event *owners[X86_PMC_IDX_MAX]; |
| 93 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; |
| 94 | }; |
| 95 | |
| 96 | struct intel_percore; |
| 97 | |
| 98 | #define MAX_LBR_ENTRIES 16 |
| 99 | |
| 100 | struct cpu_hw_events { |
| 101 | /* |
| 102 | * Generic x86 PMC bits |
| 103 | */ |
| 104 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
| 105 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 106 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 107 | int enabled; |
| 108 | |
| 109 | int n_events; |
| 110 | int n_added; |
| 111 | int n_txn; |
| 112 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
| 113 | u64 tags[X86_PMC_IDX_MAX]; |
| 114 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
| 115 | |
| 116 | unsigned int group_flag; |
| 117 | |
| 118 | /* |
| 119 | * Intel DebugStore bits |
| 120 | */ |
| 121 | struct debug_store *ds; |
| 122 | u64 pebs_enabled; |
| 123 | |
| 124 | /* |
| 125 | * Intel LBR bits |
| 126 | */ |
| 127 | int lbr_users; |
| 128 | void *lbr_context; |
| 129 | struct perf_branch_stack lbr_stack; |
| 130 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; |
| 131 | |
| 132 | /* |
| 133 | * Intel percore register state. |
| 134 | * Coordinate shared resources between HT threads. |
| 135 | */ |
| 136 | int percore_used; /* Used by this CPU? */ |
| 137 | struct intel_percore *per_core; |
| 138 | |
| 139 | /* |
| 140 | * AMD specific bits |
| 141 | */ |
| 142 | struct amd_nb *amd_nb; |
| 143 | }; |
| 144 | |
| 145 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
| 146 | { .idxmsk64 = (n) }, \ |
| 147 | .code = (c), \ |
| 148 | .cmask = (m), \ |
| 149 | .weight = (w), \ |
| 150 | } |
| 151 | |
| 152 | #define EVENT_CONSTRAINT(c, n, m) \ |
| 153 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) |
| 154 | |
| 155 | /* |
| 156 | * Constraint on the Event code. |
| 157 | */ |
| 158 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
| 159 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
| 160 | |
| 161 | /* |
| 162 | * Constraint on the Event code + UMask + fixed-mask |
| 163 | * |
| 164 | * filter mask to validate fixed counter events. |
| 165 | * the following filters disqualify for fixed counters: |
| 166 | * - inv |
| 167 | * - edge |
| 168 | * - cnt-mask |
| 169 | * The other filters are supported by fixed counters. |
| 170 | * The any-thread option is supported starting with v3. |
| 171 | */ |
| 172 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
| 173 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
| 174 | |
| 175 | /* |
| 176 | * Constraint on the Event code + UMask |
| 177 | */ |
| 178 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ |
| 179 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) |
| 180 | #define PEBS_EVENT_CONSTRAINT(c, n) \ |
| 181 | INTEL_UEVENT_CONSTRAINT(c, n) |
| 182 | |
| 183 | #define EVENT_CONSTRAINT_END \ |
| 184 | EVENT_CONSTRAINT(0, 0, 0) |
| 185 | |
| 186 | #define for_each_event_constraint(e, c) \ |
| 187 | for ((e) = (c); (e)->weight; (e)++) |
| 188 | |
| 189 | /* |
| 190 | * Extra registers for specific events. |
| 191 | * Some events need large masks and require external MSRs. |
| 192 | * Define a mapping to these extra registers. |
| 193 | */ |
| 194 | struct extra_reg { |
| 195 | unsigned int event; |
| 196 | unsigned int msr; |
| 197 | u64 config_mask; |
| 198 | u64 valid_mask; |
| 199 | }; |
| 200 | |
| 201 | #define EVENT_EXTRA_REG(e, ms, m, vm) { \ |
| 202 | .event = (e), \ |
| 203 | .msr = (ms), \ |
| 204 | .config_mask = (m), \ |
| 205 | .valid_mask = (vm), \ |
| 206 | } |
| 207 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm) \ |
| 208 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm) |
| 209 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0) |
| 210 | |
| 211 | union perf_capabilities { |
| 212 | struct { |
| 213 | u64 lbr_format : 6; |
| 214 | u64 pebs_trap : 1; |
| 215 | u64 pebs_arch_reg : 1; |
| 216 | u64 pebs_format : 4; |
| 217 | u64 smm_freeze : 1; |
| 218 | }; |
| 219 | u64 capabilities; |
| 220 | }; |
| 221 | |
| 222 | /* |
| 223 | * struct x86_pmu - generic x86 pmu |
| 224 | */ |
| 225 | struct x86_pmu { |
| 226 | /* |
| 227 | * Generic x86 PMC bits |
| 228 | */ |
| 229 | const char *name; |
| 230 | int version; |
| 231 | int (*handle_irq)(struct pt_regs *); |
| 232 | void (*disable_all)(void); |
| 233 | void (*enable_all)(int added); |
| 234 | void (*enable)(struct perf_event *); |
| 235 | void (*disable)(struct perf_event *); |
| 236 | int (*hw_config)(struct perf_event *event); |
| 237 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
| 238 | unsigned eventsel; |
| 239 | unsigned perfctr; |
| 240 | u64 (*event_map)(int); |
| 241 | int max_events; |
| 242 | int num_counters; |
| 243 | int num_counters_fixed; |
| 244 | int cntval_bits; |
| 245 | u64 cntval_mask; |
| 246 | int apic; |
| 247 | u64 max_period; |
| 248 | struct event_constraint * |
| 249 | (*get_event_constraints)(struct cpu_hw_events *cpuc, |
| 250 | struct perf_event *event); |
| 251 | |
| 252 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
| 253 | struct perf_event *event); |
| 254 | struct event_constraint *event_constraints; |
| 255 | struct event_constraint *percore_constraints; |
| 256 | void (*quirks)(void); |
| 257 | int perfctr_second_write; |
| 258 | |
| 259 | int (*cpu_prepare)(int cpu); |
| 260 | void (*cpu_starting)(int cpu); |
| 261 | void (*cpu_dying)(int cpu); |
| 262 | void (*cpu_dead)(int cpu); |
| 263 | |
| 264 | /* |
| 265 | * Intel Arch Perfmon v2+ |
| 266 | */ |
| 267 | u64 intel_ctrl; |
| 268 | union perf_capabilities intel_cap; |
| 269 | |
| 270 | /* |
| 271 | * Intel DebugStore bits |
| 272 | */ |
| 273 | int bts, pebs; |
| 274 | int bts_active, pebs_active; |
| 275 | int pebs_record_size; |
| 276 | void (*drain_pebs)(struct pt_regs *regs); |
| 277 | struct event_constraint *pebs_constraints; |
| 278 | |
| 279 | /* |
| 280 | * Intel LBR |
| 281 | */ |
| 282 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ |
| 283 | int lbr_nr; /* hardware stack size */ |
| 284 | |
| 285 | /* |
| 286 | * Extra registers for events |
| 287 | */ |
| 288 | struct extra_reg *extra_regs; |
| 289 | }; |
| 290 | |
| 291 | static struct x86_pmu x86_pmu __read_mostly; |
| 292 | |
| 293 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
| 294 | .enabled = 1, |
| 295 | }; |
| 296 | |
| 297 | static int x86_perf_event_set_period(struct perf_event *event); |
| 298 | |
| 299 | /* |
| 300 | * Generalized hw caching related hw_event table, filled |
| 301 | * in on a per model basis. A value of 0 means |
| 302 | * 'not supported', -1 means 'hw_event makes no sense on |
| 303 | * this CPU', any other value means the raw hw_event |
| 304 | * ID. |
| 305 | */ |
| 306 | |
| 307 | #define C(x) PERF_COUNT_HW_CACHE_##x |
| 308 | |
| 309 | static u64 __read_mostly hw_cache_event_ids |
| 310 | [PERF_COUNT_HW_CACHE_MAX] |
| 311 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 312 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 313 | static u64 __read_mostly hw_cache_extra_regs |
| 314 | [PERF_COUNT_HW_CACHE_MAX] |
| 315 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 316 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 317 | |
| 318 | /* |
| 319 | * Propagate event elapsed time into the generic event. |
| 320 | * Can only be executed on the CPU where the event is active. |
| 321 | * Returns the delta events processed. |
| 322 | */ |
| 323 | static u64 |
| 324 | x86_perf_event_update(struct perf_event *event) |
| 325 | { |
| 326 | struct hw_perf_event *hwc = &event->hw; |
| 327 | int shift = 64 - x86_pmu.cntval_bits; |
| 328 | u64 prev_raw_count, new_raw_count; |
| 329 | int idx = hwc->idx; |
| 330 | s64 delta; |
| 331 | |
| 332 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 333 | return 0; |
| 334 | |
| 335 | /* |
| 336 | * Careful: an NMI might modify the previous event value. |
| 337 | * |
| 338 | * Our tactic to handle this is to first atomically read and |
| 339 | * exchange a new raw count - then add that new-prev delta |
| 340 | * count to the generic event atomically: |
| 341 | */ |
| 342 | again: |
| 343 | prev_raw_count = local64_read(&hwc->prev_count); |
| 344 | rdmsrl(hwc->event_base, new_raw_count); |
| 345 | |
| 346 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 347 | new_raw_count) != prev_raw_count) |
| 348 | goto again; |
| 349 | |
| 350 | /* |
| 351 | * Now we have the new raw value and have updated the prev |
| 352 | * timestamp already. We can now calculate the elapsed delta |
| 353 | * (event-)time and add that to the generic event. |
| 354 | * |
| 355 | * Careful, not all hw sign-extends above the physical width |
| 356 | * of the count. |
| 357 | */ |
| 358 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 359 | delta >>= shift; |
| 360 | |
| 361 | local64_add(delta, &event->count); |
| 362 | local64_sub(delta, &hwc->period_left); |
| 363 | |
| 364 | return new_raw_count; |
| 365 | } |
| 366 | |
| 367 | /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */ |
| 368 | static inline int x86_pmu_addr_offset(int index) |
| 369 | { |
| 370 | if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) |
| 371 | return index << 1; |
| 372 | return index; |
| 373 | } |
| 374 | |
| 375 | static inline unsigned int x86_pmu_config_addr(int index) |
| 376 | { |
| 377 | return x86_pmu.eventsel + x86_pmu_addr_offset(index); |
| 378 | } |
| 379 | |
| 380 | static inline unsigned int x86_pmu_event_addr(int index) |
| 381 | { |
| 382 | return x86_pmu.perfctr + x86_pmu_addr_offset(index); |
| 383 | } |
| 384 | |
| 385 | /* |
| 386 | * Find and validate any extra registers to set up. |
| 387 | */ |
| 388 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) |
| 389 | { |
| 390 | struct extra_reg *er; |
| 391 | |
| 392 | event->hw.extra_reg = 0; |
| 393 | event->hw.extra_config = 0; |
| 394 | |
| 395 | if (!x86_pmu.extra_regs) |
| 396 | return 0; |
| 397 | |
| 398 | for (er = x86_pmu.extra_regs; er->msr; er++) { |
| 399 | if (er->event != (config & er->config_mask)) |
| 400 | continue; |
| 401 | if (event->attr.config1 & ~er->valid_mask) |
| 402 | return -EINVAL; |
| 403 | event->hw.extra_reg = er->msr; |
| 404 | event->hw.extra_config = event->attr.config1; |
| 405 | break; |
| 406 | } |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static atomic_t active_events; |
| 411 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 412 | |
| 413 | #ifdef CONFIG_X86_LOCAL_APIC |
| 414 | |
| 415 | static bool reserve_pmc_hardware(void) |
| 416 | { |
| 417 | int i; |
| 418 | |
| 419 | for (i = 0; i < x86_pmu.num_counters; i++) { |
| 420 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
| 421 | goto perfctr_fail; |
| 422 | } |
| 423 | |
| 424 | for (i = 0; i < x86_pmu.num_counters; i++) { |
| 425 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
| 426 | goto eventsel_fail; |
| 427 | } |
| 428 | |
| 429 | return true; |
| 430 | |
| 431 | eventsel_fail: |
| 432 | for (i--; i >= 0; i--) |
| 433 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
| 434 | |
| 435 | i = x86_pmu.num_counters; |
| 436 | |
| 437 | perfctr_fail: |
| 438 | for (i--; i >= 0; i--) |
| 439 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
| 440 | |
| 441 | return false; |
| 442 | } |
| 443 | |
| 444 | static void release_pmc_hardware(void) |
| 445 | { |
| 446 | int i; |
| 447 | |
| 448 | for (i = 0; i < x86_pmu.num_counters; i++) { |
| 449 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
| 450 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | #else |
| 455 | |
| 456 | static bool reserve_pmc_hardware(void) { return true; } |
| 457 | static void release_pmc_hardware(void) {} |
| 458 | |
| 459 | #endif |
| 460 | |
| 461 | static bool check_hw_exists(void) |
| 462 | { |
| 463 | u64 val, val_new = 0; |
| 464 | int i, reg, ret = 0; |
| 465 | |
| 466 | /* |
| 467 | * Check to see if the BIOS enabled any of the counters, if so |
| 468 | * complain and bail. |
| 469 | */ |
| 470 | for (i = 0; i < x86_pmu.num_counters; i++) { |
| 471 | reg = x86_pmu_config_addr(i); |
| 472 | ret = rdmsrl_safe(reg, &val); |
| 473 | if (ret) |
| 474 | goto msr_fail; |
| 475 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) |
| 476 | goto bios_fail; |
| 477 | } |
| 478 | |
| 479 | if (x86_pmu.num_counters_fixed) { |
| 480 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 481 | ret = rdmsrl_safe(reg, &val); |
| 482 | if (ret) |
| 483 | goto msr_fail; |
| 484 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { |
| 485 | if (val & (0x03 << i*4)) |
| 486 | goto bios_fail; |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | /* |
| 491 | * Now write a value and read it back to see if it matches, |
| 492 | * this is needed to detect certain hardware emulators (qemu/kvm) |
| 493 | * that don't trap on the MSR access and always return 0s. |
| 494 | */ |
| 495 | val = 0xabcdUL; |
| 496 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
| 497 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); |
| 498 | if (ret || val != val_new) |
| 499 | goto msr_fail; |
| 500 | |
| 501 | return true; |
| 502 | |
| 503 | bios_fail: |
| 504 | printk(KERN_CONT "Broken BIOS detected, using software events only.\n"); |
| 505 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
| 506 | return false; |
| 507 | |
| 508 | msr_fail: |
| 509 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); |
| 510 | return false; |
| 511 | } |
| 512 | |
| 513 | static void reserve_ds_buffers(void); |
| 514 | static void release_ds_buffers(void); |
| 515 | |
| 516 | static void hw_perf_event_destroy(struct perf_event *event) |
| 517 | { |
| 518 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
| 519 | release_pmc_hardware(); |
| 520 | release_ds_buffers(); |
| 521 | mutex_unlock(&pmc_reserve_mutex); |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | static inline int x86_pmu_initialized(void) |
| 526 | { |
| 527 | return x86_pmu.handle_irq != NULL; |
| 528 | } |
| 529 | |
| 530 | static inline int |
| 531 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
| 532 | { |
| 533 | struct perf_event_attr *attr = &event->attr; |
| 534 | unsigned int cache_type, cache_op, cache_result; |
| 535 | u64 config, val; |
| 536 | |
| 537 | config = attr->config; |
| 538 | |
| 539 | cache_type = (config >> 0) & 0xff; |
| 540 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 541 | return -EINVAL; |
| 542 | |
| 543 | cache_op = (config >> 8) & 0xff; |
| 544 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 545 | return -EINVAL; |
| 546 | |
| 547 | cache_result = (config >> 16) & 0xff; |
| 548 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 549 | return -EINVAL; |
| 550 | |
| 551 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; |
| 552 | |
| 553 | if (val == 0) |
| 554 | return -ENOENT; |
| 555 | |
| 556 | if (val == -1) |
| 557 | return -EINVAL; |
| 558 | |
| 559 | hwc->config |= val; |
| 560 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
| 561 | return x86_pmu_extra_regs(val, event); |
| 562 | } |
| 563 | |
| 564 | static int x86_setup_perfctr(struct perf_event *event) |
| 565 | { |
| 566 | struct perf_event_attr *attr = &event->attr; |
| 567 | struct hw_perf_event *hwc = &event->hw; |
| 568 | u64 config; |
| 569 | |
| 570 | if (!is_sampling_event(event)) { |
| 571 | hwc->sample_period = x86_pmu.max_period; |
| 572 | hwc->last_period = hwc->sample_period; |
| 573 | local64_set(&hwc->period_left, hwc->sample_period); |
| 574 | } else { |
| 575 | /* |
| 576 | * If we have a PMU initialized but no APIC |
| 577 | * interrupts, we cannot sample hardware |
| 578 | * events (user-space has to fall back and |
| 579 | * sample via a hrtimer based software event): |
| 580 | */ |
| 581 | if (!x86_pmu.apic) |
| 582 | return -EOPNOTSUPP; |
| 583 | } |
| 584 | |
| 585 | if (attr->type == PERF_TYPE_RAW) |
| 586 | return x86_pmu_extra_regs(event->attr.config, event); |
| 587 | |
| 588 | if (attr->type == PERF_TYPE_HW_CACHE) |
| 589 | return set_ext_hw_attr(hwc, event); |
| 590 | |
| 591 | if (attr->config >= x86_pmu.max_events) |
| 592 | return -EINVAL; |
| 593 | |
| 594 | /* |
| 595 | * The generic map: |
| 596 | */ |
| 597 | config = x86_pmu.event_map(attr->config); |
| 598 | |
| 599 | if (config == 0) |
| 600 | return -ENOENT; |
| 601 | |
| 602 | if (config == -1LL) |
| 603 | return -EINVAL; |
| 604 | |
| 605 | /* |
| 606 | * Branch tracing: |
| 607 | */ |
| 608 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && |
| 609 | (hwc->sample_period == 1)) { |
| 610 | /* BTS is not supported by this architecture. */ |
| 611 | if (!x86_pmu.bts_active) |
| 612 | return -EOPNOTSUPP; |
| 613 | |
| 614 | /* BTS is currently only allowed for user-mode. */ |
| 615 | if (!attr->exclude_kernel) |
| 616 | return -EOPNOTSUPP; |
| 617 | } |
| 618 | |
| 619 | hwc->config |= config; |
| 620 | |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | static int x86_pmu_hw_config(struct perf_event *event) |
| 625 | { |
| 626 | if (event->attr.precise_ip) { |
| 627 | int precise = 0; |
| 628 | |
| 629 | /* Support for constant skid */ |
| 630 | if (x86_pmu.pebs_active) { |
| 631 | precise++; |
| 632 | |
| 633 | /* Support for IP fixup */ |
| 634 | if (x86_pmu.lbr_nr) |
| 635 | precise++; |
| 636 | } |
| 637 | |
| 638 | if (event->attr.precise_ip > precise) |
| 639 | return -EOPNOTSUPP; |
| 640 | } |
| 641 | |
| 642 | /* |
| 643 | * Generate PMC IRQs: |
| 644 | * (keep 'enabled' bit clear for now) |
| 645 | */ |
| 646 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
| 647 | |
| 648 | /* |
| 649 | * Count user and OS events unless requested not to |
| 650 | */ |
| 651 | if (!event->attr.exclude_user) |
| 652 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; |
| 653 | if (!event->attr.exclude_kernel) |
| 654 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; |
| 655 | |
| 656 | if (event->attr.type == PERF_TYPE_RAW) |
| 657 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; |
| 658 | |
| 659 | return x86_setup_perfctr(event); |
| 660 | } |
| 661 | |
| 662 | /* |
| 663 | * Setup the hardware configuration for a given attr_type |
| 664 | */ |
| 665 | static int __x86_pmu_event_init(struct perf_event *event) |
| 666 | { |
| 667 | int err; |
| 668 | |
| 669 | if (!x86_pmu_initialized()) |
| 670 | return -ENODEV; |
| 671 | |
| 672 | err = 0; |
| 673 | if (!atomic_inc_not_zero(&active_events)) { |
| 674 | mutex_lock(&pmc_reserve_mutex); |
| 675 | if (atomic_read(&active_events) == 0) { |
| 676 | if (!reserve_pmc_hardware()) |
| 677 | err = -EBUSY; |
| 678 | else |
| 679 | reserve_ds_buffers(); |
| 680 | } |
| 681 | if (!err) |
| 682 | atomic_inc(&active_events); |
| 683 | mutex_unlock(&pmc_reserve_mutex); |
| 684 | } |
| 685 | if (err) |
| 686 | return err; |
| 687 | |
| 688 | event->destroy = hw_perf_event_destroy; |
| 689 | |
| 690 | event->hw.idx = -1; |
| 691 | event->hw.last_cpu = -1; |
| 692 | event->hw.last_tag = ~0ULL; |
| 693 | |
| 694 | return x86_pmu.hw_config(event); |
| 695 | } |
| 696 | |
| 697 | static void x86_pmu_disable_all(void) |
| 698 | { |
| 699 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 700 | int idx; |
| 701 | |
| 702 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
| 703 | u64 val; |
| 704 | |
| 705 | if (!test_bit(idx, cpuc->active_mask)) |
| 706 | continue; |
| 707 | rdmsrl(x86_pmu_config_addr(idx), val); |
| 708 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
| 709 | continue; |
| 710 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
| 711 | wrmsrl(x86_pmu_config_addr(idx), val); |
| 712 | } |
| 713 | } |
| 714 | |
| 715 | static void x86_pmu_disable(struct pmu *pmu) |
| 716 | { |
| 717 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 718 | |
| 719 | if (!x86_pmu_initialized()) |
| 720 | return; |
| 721 | |
| 722 | if (!cpuc->enabled) |
| 723 | return; |
| 724 | |
| 725 | cpuc->n_added = 0; |
| 726 | cpuc->enabled = 0; |
| 727 | barrier(); |
| 728 | |
| 729 | x86_pmu.disable_all(); |
| 730 | } |
| 731 | |
| 732 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
| 733 | u64 enable_mask) |
| 734 | { |
| 735 | if (hwc->extra_reg) |
| 736 | wrmsrl(hwc->extra_reg, hwc->extra_config); |
| 737 | wrmsrl(hwc->config_base, hwc->config | enable_mask); |
| 738 | } |
| 739 | |
| 740 | static void x86_pmu_enable_all(int added) |
| 741 | { |
| 742 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 743 | int idx; |
| 744 | |
| 745 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
| 746 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
| 747 | |
| 748 | if (!test_bit(idx, cpuc->active_mask)) |
| 749 | continue; |
| 750 | |
| 751 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
| 752 | } |
| 753 | } |
| 754 | |
| 755 | static struct pmu pmu; |
| 756 | |
| 757 | static inline int is_x86_event(struct perf_event *event) |
| 758 | { |
| 759 | return event->pmu == &pmu; |
| 760 | } |
| 761 | |
| 762 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
| 763 | { |
| 764 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
| 765 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 766 | int i, j, w, wmax, num = 0; |
| 767 | struct hw_perf_event *hwc; |
| 768 | |
| 769 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 770 | |
| 771 | for (i = 0; i < n; i++) { |
| 772 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
| 773 | constraints[i] = c; |
| 774 | } |
| 775 | |
| 776 | /* |
| 777 | * fastpath, try to reuse previous register |
| 778 | */ |
| 779 | for (i = 0; i < n; i++) { |
| 780 | hwc = &cpuc->event_list[i]->hw; |
| 781 | c = constraints[i]; |
| 782 | |
| 783 | /* never assigned */ |
| 784 | if (hwc->idx == -1) |
| 785 | break; |
| 786 | |
| 787 | /* constraint still honored */ |
| 788 | if (!test_bit(hwc->idx, c->idxmsk)) |
| 789 | break; |
| 790 | |
| 791 | /* not already used */ |
| 792 | if (test_bit(hwc->idx, used_mask)) |
| 793 | break; |
| 794 | |
| 795 | __set_bit(hwc->idx, used_mask); |
| 796 | if (assign) |
| 797 | assign[i] = hwc->idx; |
| 798 | } |
| 799 | if (i == n) |
| 800 | goto done; |
| 801 | |
| 802 | /* |
| 803 | * begin slow path |
| 804 | */ |
| 805 | |
| 806 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 807 | |
| 808 | /* |
| 809 | * weight = number of possible counters |
| 810 | * |
| 811 | * 1 = most constrained, only works on one counter |
| 812 | * wmax = least constrained, works on any counter |
| 813 | * |
| 814 | * assign events to counters starting with most |
| 815 | * constrained events. |
| 816 | */ |
| 817 | wmax = x86_pmu.num_counters; |
| 818 | |
| 819 | /* |
| 820 | * when fixed event counters are present, |
| 821 | * wmax is incremented by 1 to account |
| 822 | * for one more choice |
| 823 | */ |
| 824 | if (x86_pmu.num_counters_fixed) |
| 825 | wmax++; |
| 826 | |
| 827 | for (w = 1, num = n; num && w <= wmax; w++) { |
| 828 | /* for each event */ |
| 829 | for (i = 0; num && i < n; i++) { |
| 830 | c = constraints[i]; |
| 831 | hwc = &cpuc->event_list[i]->hw; |
| 832 | |
| 833 | if (c->weight != w) |
| 834 | continue; |
| 835 | |
| 836 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
| 837 | if (!test_bit(j, used_mask)) |
| 838 | break; |
| 839 | } |
| 840 | |
| 841 | if (j == X86_PMC_IDX_MAX) |
| 842 | break; |
| 843 | |
| 844 | __set_bit(j, used_mask); |
| 845 | |
| 846 | if (assign) |
| 847 | assign[i] = j; |
| 848 | num--; |
| 849 | } |
| 850 | } |
| 851 | done: |
| 852 | /* |
| 853 | * scheduling failed or is just a simulation, |
| 854 | * free resources if necessary |
| 855 | */ |
| 856 | if (!assign || num) { |
| 857 | for (i = 0; i < n; i++) { |
| 858 | if (x86_pmu.put_event_constraints) |
| 859 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); |
| 860 | } |
| 861 | } |
| 862 | return num ? -ENOSPC : 0; |
| 863 | } |
| 864 | |
| 865 | /* |
| 866 | * dogrp: true if must collect siblings events (group) |
| 867 | * returns total number of events and error code |
| 868 | */ |
| 869 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) |
| 870 | { |
| 871 | struct perf_event *event; |
| 872 | int n, max_count; |
| 873 | |
| 874 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
| 875 | |
| 876 | /* current number of events already accepted */ |
| 877 | n = cpuc->n_events; |
| 878 | |
| 879 | if (is_x86_event(leader)) { |
| 880 | if (n >= max_count) |
| 881 | return -ENOSPC; |
| 882 | cpuc->event_list[n] = leader; |
| 883 | n++; |
| 884 | } |
| 885 | if (!dogrp) |
| 886 | return n; |
| 887 | |
| 888 | list_for_each_entry(event, &leader->sibling_list, group_entry) { |
| 889 | if (!is_x86_event(event) || |
| 890 | event->state <= PERF_EVENT_STATE_OFF) |
| 891 | continue; |
| 892 | |
| 893 | if (n >= max_count) |
| 894 | return -ENOSPC; |
| 895 | |
| 896 | cpuc->event_list[n] = event; |
| 897 | n++; |
| 898 | } |
| 899 | return n; |
| 900 | } |
| 901 | |
| 902 | static inline void x86_assign_hw_event(struct perf_event *event, |
| 903 | struct cpu_hw_events *cpuc, int i) |
| 904 | { |
| 905 | struct hw_perf_event *hwc = &event->hw; |
| 906 | |
| 907 | hwc->idx = cpuc->assign[i]; |
| 908 | hwc->last_cpu = smp_processor_id(); |
| 909 | hwc->last_tag = ++cpuc->tags[i]; |
| 910 | |
| 911 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { |
| 912 | hwc->config_base = 0; |
| 913 | hwc->event_base = 0; |
| 914 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { |
| 915 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 916 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0; |
| 917 | } else { |
| 918 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
| 919 | hwc->event_base = x86_pmu_event_addr(hwc->idx); |
| 920 | } |
| 921 | } |
| 922 | |
| 923 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
| 924 | struct cpu_hw_events *cpuc, |
| 925 | int i) |
| 926 | { |
| 927 | return hwc->idx == cpuc->assign[i] && |
| 928 | hwc->last_cpu == smp_processor_id() && |
| 929 | hwc->last_tag == cpuc->tags[i]; |
| 930 | } |
| 931 | |
| 932 | static void x86_pmu_start(struct perf_event *event, int flags); |
| 933 | static void x86_pmu_stop(struct perf_event *event, int flags); |
| 934 | |
| 935 | static void x86_pmu_enable(struct pmu *pmu) |
| 936 | { |
| 937 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 938 | struct perf_event *event; |
| 939 | struct hw_perf_event *hwc; |
| 940 | int i, added = cpuc->n_added; |
| 941 | |
| 942 | if (!x86_pmu_initialized()) |
| 943 | return; |
| 944 | |
| 945 | if (cpuc->enabled) |
| 946 | return; |
| 947 | |
| 948 | if (cpuc->n_added) { |
| 949 | int n_running = cpuc->n_events - cpuc->n_added; |
| 950 | /* |
| 951 | * apply assignment obtained either from |
| 952 | * hw_perf_group_sched_in() or x86_pmu_enable() |
| 953 | * |
| 954 | * step1: save events moving to new counters |
| 955 | * step2: reprogram moved events into new counters |
| 956 | */ |
| 957 | for (i = 0; i < n_running; i++) { |
| 958 | event = cpuc->event_list[i]; |
| 959 | hwc = &event->hw; |
| 960 | |
| 961 | /* |
| 962 | * we can avoid reprogramming counter if: |
| 963 | * - assigned same counter as last time |
| 964 | * - running on same CPU as last time |
| 965 | * - no other event has used the counter since |
| 966 | */ |
| 967 | if (hwc->idx == -1 || |
| 968 | match_prev_assignment(hwc, cpuc, i)) |
| 969 | continue; |
| 970 | |
| 971 | /* |
| 972 | * Ensure we don't accidentally enable a stopped |
| 973 | * counter simply because we rescheduled. |
| 974 | */ |
| 975 | if (hwc->state & PERF_HES_STOPPED) |
| 976 | hwc->state |= PERF_HES_ARCH; |
| 977 | |
| 978 | x86_pmu_stop(event, PERF_EF_UPDATE); |
| 979 | } |
| 980 | |
| 981 | for (i = 0; i < cpuc->n_events; i++) { |
| 982 | event = cpuc->event_list[i]; |
| 983 | hwc = &event->hw; |
| 984 | |
| 985 | if (!match_prev_assignment(hwc, cpuc, i)) |
| 986 | x86_assign_hw_event(event, cpuc, i); |
| 987 | else if (i < n_running) |
| 988 | continue; |
| 989 | |
| 990 | if (hwc->state & PERF_HES_ARCH) |
| 991 | continue; |
| 992 | |
| 993 | x86_pmu_start(event, PERF_EF_RELOAD); |
| 994 | } |
| 995 | cpuc->n_added = 0; |
| 996 | perf_events_lapic_init(); |
| 997 | } |
| 998 | |
| 999 | cpuc->enabled = 1; |
| 1000 | barrier(); |
| 1001 | |
| 1002 | x86_pmu.enable_all(added); |
| 1003 | } |
| 1004 | |
| 1005 | static inline void x86_pmu_disable_event(struct perf_event *event) |
| 1006 | { |
| 1007 | struct hw_perf_event *hwc = &event->hw; |
| 1008 | |
| 1009 | wrmsrl(hwc->config_base, hwc->config); |
| 1010 | } |
| 1011 | |
| 1012 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
| 1013 | |
| 1014 | /* |
| 1015 | * Set the next IRQ period, based on the hwc->period_left value. |
| 1016 | * To be called with the event disabled in hw: |
| 1017 | */ |
| 1018 | static int |
| 1019 | x86_perf_event_set_period(struct perf_event *event) |
| 1020 | { |
| 1021 | struct hw_perf_event *hwc = &event->hw; |
| 1022 | s64 left = local64_read(&hwc->period_left); |
| 1023 | s64 period = hwc->sample_period; |
| 1024 | int ret = 0, idx = hwc->idx; |
| 1025 | |
| 1026 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 1027 | return 0; |
| 1028 | |
| 1029 | /* |
| 1030 | * If we are way outside a reasonable range then just skip forward: |
| 1031 | */ |
| 1032 | if (unlikely(left <= -period)) { |
| 1033 | left = period; |
| 1034 | local64_set(&hwc->period_left, left); |
| 1035 | hwc->last_period = period; |
| 1036 | ret = 1; |
| 1037 | } |
| 1038 | |
| 1039 | if (unlikely(left <= 0)) { |
| 1040 | left += period; |
| 1041 | local64_set(&hwc->period_left, left); |
| 1042 | hwc->last_period = period; |
| 1043 | ret = 1; |
| 1044 | } |
| 1045 | /* |
| 1046 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
| 1047 | */ |
| 1048 | if (unlikely(left < 2)) |
| 1049 | left = 2; |
| 1050 | |
| 1051 | if (left > x86_pmu.max_period) |
| 1052 | left = x86_pmu.max_period; |
| 1053 | |
| 1054 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
| 1055 | |
| 1056 | /* |
| 1057 | * The hw event starts counting from this event offset, |
| 1058 | * mark it to be able to extra future deltas: |
| 1059 | */ |
| 1060 | local64_set(&hwc->prev_count, (u64)-left); |
| 1061 | |
| 1062 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
| 1063 | |
| 1064 | /* |
| 1065 | * Due to erratum on certan cpu we need |
| 1066 | * a second write to be sure the register |
| 1067 | * is updated properly |
| 1068 | */ |
| 1069 | if (x86_pmu.perfctr_second_write) { |
| 1070 | wrmsrl(hwc->event_base, |
| 1071 | (u64)(-left) & x86_pmu.cntval_mask); |
| 1072 | } |
| 1073 | |
| 1074 | perf_event_update_userpage(event); |
| 1075 | |
| 1076 | return ret; |
| 1077 | } |
| 1078 | |
| 1079 | static void x86_pmu_enable_event(struct perf_event *event) |
| 1080 | { |
| 1081 | if (__this_cpu_read(cpu_hw_events.enabled)) |
| 1082 | __x86_pmu_enable_event(&event->hw, |
| 1083 | ARCH_PERFMON_EVENTSEL_ENABLE); |
| 1084 | } |
| 1085 | |
| 1086 | /* |
| 1087 | * Add a single event to the PMU. |
| 1088 | * |
| 1089 | * The event is added to the group of enabled events |
| 1090 | * but only if it can be scehduled with existing events. |
| 1091 | */ |
| 1092 | static int x86_pmu_add(struct perf_event *event, int flags) |
| 1093 | { |
| 1094 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1095 | struct hw_perf_event *hwc; |
| 1096 | int assign[X86_PMC_IDX_MAX]; |
| 1097 | int n, n0, ret; |
| 1098 | |
| 1099 | hwc = &event->hw; |
| 1100 | |
| 1101 | perf_pmu_disable(event->pmu); |
| 1102 | n0 = cpuc->n_events; |
| 1103 | ret = n = collect_events(cpuc, event, false); |
| 1104 | if (ret < 0) |
| 1105 | goto out; |
| 1106 | |
| 1107 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
| 1108 | if (!(flags & PERF_EF_START)) |
| 1109 | hwc->state |= PERF_HES_ARCH; |
| 1110 | |
| 1111 | /* |
| 1112 | * If group events scheduling transaction was started, |
| 1113 | * skip the schedulability test here, it will be peformed |
| 1114 | * at commit time (->commit_txn) as a whole |
| 1115 | */ |
| 1116 | if (cpuc->group_flag & PERF_EVENT_TXN) |
| 1117 | goto done_collect; |
| 1118 | |
| 1119 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
| 1120 | if (ret) |
| 1121 | goto out; |
| 1122 | /* |
| 1123 | * copy new assignment, now we know it is possible |
| 1124 | * will be used by hw_perf_enable() |
| 1125 | */ |
| 1126 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
| 1127 | |
| 1128 | done_collect: |
| 1129 | cpuc->n_events = n; |
| 1130 | cpuc->n_added += n - n0; |
| 1131 | cpuc->n_txn += n - n0; |
| 1132 | |
| 1133 | ret = 0; |
| 1134 | out: |
| 1135 | perf_pmu_enable(event->pmu); |
| 1136 | return ret; |
| 1137 | } |
| 1138 | |
| 1139 | static void x86_pmu_start(struct perf_event *event, int flags) |
| 1140 | { |
| 1141 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1142 | int idx = event->hw.idx; |
| 1143 | |
| 1144 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
| 1145 | return; |
| 1146 | |
| 1147 | if (WARN_ON_ONCE(idx == -1)) |
| 1148 | return; |
| 1149 | |
| 1150 | if (flags & PERF_EF_RELOAD) { |
| 1151 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); |
| 1152 | x86_perf_event_set_period(event); |
| 1153 | } |
| 1154 | |
| 1155 | event->hw.state = 0; |
| 1156 | |
| 1157 | cpuc->events[idx] = event; |
| 1158 | __set_bit(idx, cpuc->active_mask); |
| 1159 | __set_bit(idx, cpuc->running); |
| 1160 | x86_pmu.enable(event); |
| 1161 | perf_event_update_userpage(event); |
| 1162 | } |
| 1163 | |
| 1164 | void perf_event_print_debug(void) |
| 1165 | { |
| 1166 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
| 1167 | u64 pebs; |
| 1168 | struct cpu_hw_events *cpuc; |
| 1169 | unsigned long flags; |
| 1170 | int cpu, idx; |
| 1171 | |
| 1172 | if (!x86_pmu.num_counters) |
| 1173 | return; |
| 1174 | |
| 1175 | local_irq_save(flags); |
| 1176 | |
| 1177 | cpu = smp_processor_id(); |
| 1178 | cpuc = &per_cpu(cpu_hw_events, cpu); |
| 1179 | |
| 1180 | if (x86_pmu.version >= 2) { |
| 1181 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
| 1182 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 1183 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); |
| 1184 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
| 1185 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
| 1186 | |
| 1187 | pr_info("\n"); |
| 1188 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); |
| 1189 | pr_info("CPU#%d: status: %016llx\n", cpu, status); |
| 1190 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); |
| 1191 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); |
| 1192 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
| 1193 | } |
| 1194 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
| 1195 | |
| 1196 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
| 1197 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
| 1198 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); |
| 1199 | |
| 1200 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
| 1201 | |
| 1202 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
| 1203 | cpu, idx, pmc_ctrl); |
| 1204 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
| 1205 | cpu, idx, pmc_count); |
| 1206 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
| 1207 | cpu, idx, prev_left); |
| 1208 | } |
| 1209 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
| 1210 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
| 1211 | |
| 1212 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
| 1213 | cpu, idx, pmc_count); |
| 1214 | } |
| 1215 | local_irq_restore(flags); |
| 1216 | } |
| 1217 | |
| 1218 | static void x86_pmu_stop(struct perf_event *event, int flags) |
| 1219 | { |
| 1220 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1221 | struct hw_perf_event *hwc = &event->hw; |
| 1222 | |
| 1223 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
| 1224 | x86_pmu.disable(event); |
| 1225 | cpuc->events[hwc->idx] = NULL; |
| 1226 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); |
| 1227 | hwc->state |= PERF_HES_STOPPED; |
| 1228 | } |
| 1229 | |
| 1230 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
| 1231 | /* |
| 1232 | * Drain the remaining delta count out of a event |
| 1233 | * that we are disabling: |
| 1234 | */ |
| 1235 | x86_perf_event_update(event); |
| 1236 | hwc->state |= PERF_HES_UPTODATE; |
| 1237 | } |
| 1238 | } |
| 1239 | |
| 1240 | static void x86_pmu_del(struct perf_event *event, int flags) |
| 1241 | { |
| 1242 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1243 | int i; |
| 1244 | |
| 1245 | /* |
| 1246 | * If we're called during a txn, we don't need to do anything. |
| 1247 | * The events never got scheduled and ->cancel_txn will truncate |
| 1248 | * the event_list. |
| 1249 | */ |
| 1250 | if (cpuc->group_flag & PERF_EVENT_TXN) |
| 1251 | return; |
| 1252 | |
| 1253 | x86_pmu_stop(event, PERF_EF_UPDATE); |
| 1254 | |
| 1255 | for (i = 0; i < cpuc->n_events; i++) { |
| 1256 | if (event == cpuc->event_list[i]) { |
| 1257 | |
| 1258 | if (x86_pmu.put_event_constraints) |
| 1259 | x86_pmu.put_event_constraints(cpuc, event); |
| 1260 | |
| 1261 | while (++i < cpuc->n_events) |
| 1262 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
| 1263 | |
| 1264 | --cpuc->n_events; |
| 1265 | break; |
| 1266 | } |
| 1267 | } |
| 1268 | perf_event_update_userpage(event); |
| 1269 | } |
| 1270 | |
| 1271 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
| 1272 | { |
| 1273 | struct perf_sample_data data; |
| 1274 | struct cpu_hw_events *cpuc; |
| 1275 | struct perf_event *event; |
| 1276 | int idx, handled = 0; |
| 1277 | u64 val; |
| 1278 | |
| 1279 | perf_sample_data_init(&data, 0); |
| 1280 | |
| 1281 | cpuc = &__get_cpu_var(cpu_hw_events); |
| 1282 | |
| 1283 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
| 1284 | if (!test_bit(idx, cpuc->active_mask)) { |
| 1285 | /* |
| 1286 | * Though we deactivated the counter some cpus |
| 1287 | * might still deliver spurious interrupts still |
| 1288 | * in flight. Catch them: |
| 1289 | */ |
| 1290 | if (__test_and_clear_bit(idx, cpuc->running)) |
| 1291 | handled++; |
| 1292 | continue; |
| 1293 | } |
| 1294 | |
| 1295 | event = cpuc->events[idx]; |
| 1296 | |
| 1297 | val = x86_perf_event_update(event); |
| 1298 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
| 1299 | continue; |
| 1300 | |
| 1301 | /* |
| 1302 | * event overflow |
| 1303 | */ |
| 1304 | handled++; |
| 1305 | data.period = event->hw.last_period; |
| 1306 | |
| 1307 | if (!x86_perf_event_set_period(event)) |
| 1308 | continue; |
| 1309 | |
| 1310 | if (perf_event_overflow(event, 1, &data, regs)) |
| 1311 | x86_pmu_stop(event, 0); |
| 1312 | } |
| 1313 | |
| 1314 | if (handled) |
| 1315 | inc_irq_stat(apic_perf_irqs); |
| 1316 | |
| 1317 | return handled; |
| 1318 | } |
| 1319 | |
| 1320 | void perf_events_lapic_init(void) |
| 1321 | { |
| 1322 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
| 1323 | return; |
| 1324 | |
| 1325 | /* |
| 1326 | * Always use NMI for PMU |
| 1327 | */ |
| 1328 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 1329 | } |
| 1330 | |
| 1331 | struct pmu_nmi_state { |
| 1332 | unsigned int marked; |
| 1333 | int handled; |
| 1334 | }; |
| 1335 | |
| 1336 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); |
| 1337 | |
| 1338 | static int __kprobes |
| 1339 | perf_event_nmi_handler(struct notifier_block *self, |
| 1340 | unsigned long cmd, void *__args) |
| 1341 | { |
| 1342 | struct die_args *args = __args; |
| 1343 | unsigned int this_nmi; |
| 1344 | int handled; |
| 1345 | |
| 1346 | if (!atomic_read(&active_events)) |
| 1347 | return NOTIFY_DONE; |
| 1348 | |
| 1349 | switch (cmd) { |
| 1350 | case DIE_NMI: |
| 1351 | break; |
| 1352 | case DIE_NMIUNKNOWN: |
| 1353 | this_nmi = percpu_read(irq_stat.__nmi_count); |
| 1354 | if (this_nmi != __this_cpu_read(pmu_nmi.marked)) |
| 1355 | /* let the kernel handle the unknown nmi */ |
| 1356 | return NOTIFY_DONE; |
| 1357 | /* |
| 1358 | * This one is a PMU back-to-back nmi. Two events |
| 1359 | * trigger 'simultaneously' raising two back-to-back |
| 1360 | * NMIs. If the first NMI handles both, the latter |
| 1361 | * will be empty and daze the CPU. So, we drop it to |
| 1362 | * avoid false-positive 'unknown nmi' messages. |
| 1363 | */ |
| 1364 | return NOTIFY_STOP; |
| 1365 | default: |
| 1366 | return NOTIFY_DONE; |
| 1367 | } |
| 1368 | |
| 1369 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 1370 | |
| 1371 | handled = x86_pmu.handle_irq(args->regs); |
| 1372 | if (!handled) |
| 1373 | return NOTIFY_DONE; |
| 1374 | |
| 1375 | this_nmi = percpu_read(irq_stat.__nmi_count); |
| 1376 | if ((handled > 1) || |
| 1377 | /* the next nmi could be a back-to-back nmi */ |
| 1378 | ((__this_cpu_read(pmu_nmi.marked) == this_nmi) && |
| 1379 | (__this_cpu_read(pmu_nmi.handled) > 1))) { |
| 1380 | /* |
| 1381 | * We could have two subsequent back-to-back nmis: The |
| 1382 | * first handles more than one counter, the 2nd |
| 1383 | * handles only one counter and the 3rd handles no |
| 1384 | * counter. |
| 1385 | * |
| 1386 | * This is the 2nd nmi because the previous was |
| 1387 | * handling more than one counter. We will mark the |
| 1388 | * next (3rd) and then drop it if unhandled. |
| 1389 | */ |
| 1390 | __this_cpu_write(pmu_nmi.marked, this_nmi + 1); |
| 1391 | __this_cpu_write(pmu_nmi.handled, handled); |
| 1392 | } |
| 1393 | |
| 1394 | return NOTIFY_STOP; |
| 1395 | } |
| 1396 | |
| 1397 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
| 1398 | .notifier_call = perf_event_nmi_handler, |
| 1399 | .next = NULL, |
| 1400 | .priority = NMI_LOCAL_LOW_PRIOR, |
| 1401 | }; |
| 1402 | |
| 1403 | static struct event_constraint unconstrained; |
| 1404 | static struct event_constraint emptyconstraint; |
| 1405 | |
| 1406 | static struct event_constraint * |
| 1407 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
| 1408 | { |
| 1409 | struct event_constraint *c; |
| 1410 | |
| 1411 | if (x86_pmu.event_constraints) { |
| 1412 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
| 1413 | if ((event->hw.config & c->cmask) == c->code) |
| 1414 | return c; |
| 1415 | } |
| 1416 | } |
| 1417 | |
| 1418 | return &unconstrained; |
| 1419 | } |
| 1420 | |
| 1421 | #include "perf_event_amd.c" |
| 1422 | #include "perf_event_p6.c" |
| 1423 | #include "perf_event_p4.c" |
| 1424 | #include "perf_event_intel_lbr.c" |
| 1425 | #include "perf_event_intel_ds.c" |
| 1426 | #include "perf_event_intel.c" |
| 1427 | |
| 1428 | static int __cpuinit |
| 1429 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
| 1430 | { |
| 1431 | unsigned int cpu = (long)hcpu; |
| 1432 | int ret = NOTIFY_OK; |
| 1433 | |
| 1434 | switch (action & ~CPU_TASKS_FROZEN) { |
| 1435 | case CPU_UP_PREPARE: |
| 1436 | if (x86_pmu.cpu_prepare) |
| 1437 | ret = x86_pmu.cpu_prepare(cpu); |
| 1438 | break; |
| 1439 | |
| 1440 | case CPU_STARTING: |
| 1441 | if (x86_pmu.cpu_starting) |
| 1442 | x86_pmu.cpu_starting(cpu); |
| 1443 | break; |
| 1444 | |
| 1445 | case CPU_DYING: |
| 1446 | if (x86_pmu.cpu_dying) |
| 1447 | x86_pmu.cpu_dying(cpu); |
| 1448 | break; |
| 1449 | |
| 1450 | case CPU_UP_CANCELED: |
| 1451 | case CPU_DEAD: |
| 1452 | if (x86_pmu.cpu_dead) |
| 1453 | x86_pmu.cpu_dead(cpu); |
| 1454 | break; |
| 1455 | |
| 1456 | default: |
| 1457 | break; |
| 1458 | } |
| 1459 | |
| 1460 | return ret; |
| 1461 | } |
| 1462 | |
| 1463 | static void __init pmu_check_apic(void) |
| 1464 | { |
| 1465 | if (cpu_has_apic) |
| 1466 | return; |
| 1467 | |
| 1468 | x86_pmu.apic = 0; |
| 1469 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); |
| 1470 | pr_info("no hardware sampling interrupt available.\n"); |
| 1471 | } |
| 1472 | |
| 1473 | static int __init init_hw_perf_events(void) |
| 1474 | { |
| 1475 | struct event_constraint *c; |
| 1476 | int err; |
| 1477 | |
| 1478 | pr_info("Performance Events: "); |
| 1479 | |
| 1480 | switch (boot_cpu_data.x86_vendor) { |
| 1481 | case X86_VENDOR_INTEL: |
| 1482 | err = intel_pmu_init(); |
| 1483 | break; |
| 1484 | case X86_VENDOR_AMD: |
| 1485 | err = amd_pmu_init(); |
| 1486 | break; |
| 1487 | default: |
| 1488 | return 0; |
| 1489 | } |
| 1490 | if (err != 0) { |
| 1491 | pr_cont("no PMU driver, software events only.\n"); |
| 1492 | return 0; |
| 1493 | } |
| 1494 | |
| 1495 | pmu_check_apic(); |
| 1496 | |
| 1497 | /* sanity check that the hardware exists or is emulated */ |
| 1498 | if (!check_hw_exists()) |
| 1499 | return 0; |
| 1500 | |
| 1501 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
| 1502 | |
| 1503 | if (x86_pmu.quirks) |
| 1504 | x86_pmu.quirks(); |
| 1505 | |
| 1506 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
| 1507 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
| 1508 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
| 1509 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; |
| 1510 | } |
| 1511 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
| 1512 | |
| 1513 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
| 1514 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
| 1515 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
| 1516 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; |
| 1517 | } |
| 1518 | |
| 1519 | x86_pmu.intel_ctrl |= |
| 1520 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
| 1521 | |
| 1522 | perf_events_lapic_init(); |
| 1523 | register_die_notifier(&perf_event_nmi_notifier); |
| 1524 | |
| 1525 | unconstrained = (struct event_constraint) |
| 1526 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
| 1527 | 0, x86_pmu.num_counters); |
| 1528 | |
| 1529 | if (x86_pmu.event_constraints) { |
| 1530 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
| 1531 | if (c->cmask != X86_RAW_EVENT_MASK) |
| 1532 | continue; |
| 1533 | |
| 1534 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
| 1535 | c->weight += x86_pmu.num_counters; |
| 1536 | } |
| 1537 | } |
| 1538 | |
| 1539 | pr_info("... version: %d\n", x86_pmu.version); |
| 1540 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
| 1541 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); |
| 1542 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); |
| 1543 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
| 1544 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
| 1545 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
| 1546 | |
| 1547 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
| 1548 | perf_cpu_notifier(x86_pmu_notifier); |
| 1549 | |
| 1550 | return 0; |
| 1551 | } |
| 1552 | early_initcall(init_hw_perf_events); |
| 1553 | |
| 1554 | static inline void x86_pmu_read(struct perf_event *event) |
| 1555 | { |
| 1556 | x86_perf_event_update(event); |
| 1557 | } |
| 1558 | |
| 1559 | /* |
| 1560 | * Start group events scheduling transaction |
| 1561 | * Set the flag to make pmu::enable() not perform the |
| 1562 | * schedulability test, it will be performed at commit time |
| 1563 | */ |
| 1564 | static void x86_pmu_start_txn(struct pmu *pmu) |
| 1565 | { |
| 1566 | perf_pmu_disable(pmu); |
| 1567 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
| 1568 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
| 1569 | } |
| 1570 | |
| 1571 | /* |
| 1572 | * Stop group events scheduling transaction |
| 1573 | * Clear the flag and pmu::enable() will perform the |
| 1574 | * schedulability test. |
| 1575 | */ |
| 1576 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
| 1577 | { |
| 1578 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
| 1579 | /* |
| 1580 | * Truncate the collected events. |
| 1581 | */ |
| 1582 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
| 1583 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); |
| 1584 | perf_pmu_enable(pmu); |
| 1585 | } |
| 1586 | |
| 1587 | /* |
| 1588 | * Commit group events scheduling transaction |
| 1589 | * Perform the group schedulability test as a whole |
| 1590 | * Return 0 if success |
| 1591 | */ |
| 1592 | static int x86_pmu_commit_txn(struct pmu *pmu) |
| 1593 | { |
| 1594 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1595 | int assign[X86_PMC_IDX_MAX]; |
| 1596 | int n, ret; |
| 1597 | |
| 1598 | n = cpuc->n_events; |
| 1599 | |
| 1600 | if (!x86_pmu_initialized()) |
| 1601 | return -EAGAIN; |
| 1602 | |
| 1603 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
| 1604 | if (ret) |
| 1605 | return ret; |
| 1606 | |
| 1607 | /* |
| 1608 | * copy new assignment, now we know it is possible |
| 1609 | * will be used by hw_perf_enable() |
| 1610 | */ |
| 1611 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
| 1612 | |
| 1613 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
| 1614 | perf_pmu_enable(pmu); |
| 1615 | return 0; |
| 1616 | } |
| 1617 | |
| 1618 | /* |
| 1619 | * validate that we can schedule this event |
| 1620 | */ |
| 1621 | static int validate_event(struct perf_event *event) |
| 1622 | { |
| 1623 | struct cpu_hw_events *fake_cpuc; |
| 1624 | struct event_constraint *c; |
| 1625 | int ret = 0; |
| 1626 | |
| 1627 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); |
| 1628 | if (!fake_cpuc) |
| 1629 | return -ENOMEM; |
| 1630 | |
| 1631 | c = x86_pmu.get_event_constraints(fake_cpuc, event); |
| 1632 | |
| 1633 | if (!c || !c->weight) |
| 1634 | ret = -ENOSPC; |
| 1635 | |
| 1636 | if (x86_pmu.put_event_constraints) |
| 1637 | x86_pmu.put_event_constraints(fake_cpuc, event); |
| 1638 | |
| 1639 | kfree(fake_cpuc); |
| 1640 | |
| 1641 | return ret; |
| 1642 | } |
| 1643 | |
| 1644 | /* |
| 1645 | * validate a single event group |
| 1646 | * |
| 1647 | * validation include: |
| 1648 | * - check events are compatible which each other |
| 1649 | * - events do not compete for the same counter |
| 1650 | * - number of events <= number of counters |
| 1651 | * |
| 1652 | * validation ensures the group can be loaded onto the |
| 1653 | * PMU if it was the only group available. |
| 1654 | */ |
| 1655 | static int validate_group(struct perf_event *event) |
| 1656 | { |
| 1657 | struct perf_event *leader = event->group_leader; |
| 1658 | struct cpu_hw_events *fake_cpuc; |
| 1659 | int ret, n; |
| 1660 | |
| 1661 | ret = -ENOMEM; |
| 1662 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); |
| 1663 | if (!fake_cpuc) |
| 1664 | goto out; |
| 1665 | |
| 1666 | /* |
| 1667 | * the event is not yet connected with its |
| 1668 | * siblings therefore we must first collect |
| 1669 | * existing siblings, then add the new event |
| 1670 | * before we can simulate the scheduling |
| 1671 | */ |
| 1672 | ret = -ENOSPC; |
| 1673 | n = collect_events(fake_cpuc, leader, true); |
| 1674 | if (n < 0) |
| 1675 | goto out_free; |
| 1676 | |
| 1677 | fake_cpuc->n_events = n; |
| 1678 | n = collect_events(fake_cpuc, event, false); |
| 1679 | if (n < 0) |
| 1680 | goto out_free; |
| 1681 | |
| 1682 | fake_cpuc->n_events = n; |
| 1683 | |
| 1684 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
| 1685 | |
| 1686 | out_free: |
| 1687 | kfree(fake_cpuc); |
| 1688 | out: |
| 1689 | return ret; |
| 1690 | } |
| 1691 | |
| 1692 | static int x86_pmu_event_init(struct perf_event *event) |
| 1693 | { |
| 1694 | struct pmu *tmp; |
| 1695 | int err; |
| 1696 | |
| 1697 | switch (event->attr.type) { |
| 1698 | case PERF_TYPE_RAW: |
| 1699 | case PERF_TYPE_HARDWARE: |
| 1700 | case PERF_TYPE_HW_CACHE: |
| 1701 | break; |
| 1702 | |
| 1703 | default: |
| 1704 | return -ENOENT; |
| 1705 | } |
| 1706 | |
| 1707 | err = __x86_pmu_event_init(event); |
| 1708 | if (!err) { |
| 1709 | /* |
| 1710 | * we temporarily connect event to its pmu |
| 1711 | * such that validate_group() can classify |
| 1712 | * it as an x86 event using is_x86_event() |
| 1713 | */ |
| 1714 | tmp = event->pmu; |
| 1715 | event->pmu = &pmu; |
| 1716 | |
| 1717 | if (event->group_leader != event) |
| 1718 | err = validate_group(event); |
| 1719 | else |
| 1720 | err = validate_event(event); |
| 1721 | |
| 1722 | event->pmu = tmp; |
| 1723 | } |
| 1724 | if (err) { |
| 1725 | if (event->destroy) |
| 1726 | event->destroy(event); |
| 1727 | } |
| 1728 | |
| 1729 | return err; |
| 1730 | } |
| 1731 | |
| 1732 | static struct pmu pmu = { |
| 1733 | .pmu_enable = x86_pmu_enable, |
| 1734 | .pmu_disable = x86_pmu_disable, |
| 1735 | |
| 1736 | .event_init = x86_pmu_event_init, |
| 1737 | |
| 1738 | .add = x86_pmu_add, |
| 1739 | .del = x86_pmu_del, |
| 1740 | .start = x86_pmu_start, |
| 1741 | .stop = x86_pmu_stop, |
| 1742 | .read = x86_pmu_read, |
| 1743 | |
| 1744 | .start_txn = x86_pmu_start_txn, |
| 1745 | .cancel_txn = x86_pmu_cancel_txn, |
| 1746 | .commit_txn = x86_pmu_commit_txn, |
| 1747 | }; |
| 1748 | |
| 1749 | /* |
| 1750 | * callchain support |
| 1751 | */ |
| 1752 | |
| 1753 | static void |
| 1754 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) |
| 1755 | { |
| 1756 | /* Ignore warnings */ |
| 1757 | } |
| 1758 | |
| 1759 | static void backtrace_warning(void *data, char *msg) |
| 1760 | { |
| 1761 | /* Ignore warnings */ |
| 1762 | } |
| 1763 | |
| 1764 | static int backtrace_stack(void *data, char *name) |
| 1765 | { |
| 1766 | return 0; |
| 1767 | } |
| 1768 | |
| 1769 | static void backtrace_address(void *data, unsigned long addr, int reliable) |
| 1770 | { |
| 1771 | struct perf_callchain_entry *entry = data; |
| 1772 | |
| 1773 | perf_callchain_store(entry, addr); |
| 1774 | } |
| 1775 | |
| 1776 | static const struct stacktrace_ops backtrace_ops = { |
| 1777 | .warning = backtrace_warning, |
| 1778 | .warning_symbol = backtrace_warning_symbol, |
| 1779 | .stack = backtrace_stack, |
| 1780 | .address = backtrace_address, |
| 1781 | .walk_stack = print_context_stack_bp, |
| 1782 | }; |
| 1783 | |
| 1784 | void |
| 1785 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) |
| 1786 | { |
| 1787 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 1788 | /* TODO: We don't support guest os callchain now */ |
| 1789 | return; |
| 1790 | } |
| 1791 | |
| 1792 | perf_callchain_store(entry, regs->ip); |
| 1793 | |
| 1794 | dump_trace(NULL, regs, NULL, &backtrace_ops, entry); |
| 1795 | } |
| 1796 | |
| 1797 | #ifdef CONFIG_COMPAT |
| 1798 | static inline int |
| 1799 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1800 | { |
| 1801 | /* 32-bit process in 64-bit kernel. */ |
| 1802 | struct stack_frame_ia32 frame; |
| 1803 | const void __user *fp; |
| 1804 | |
| 1805 | if (!test_thread_flag(TIF_IA32)) |
| 1806 | return 0; |
| 1807 | |
| 1808 | fp = compat_ptr(regs->bp); |
| 1809 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
| 1810 | unsigned long bytes; |
| 1811 | frame.next_frame = 0; |
| 1812 | frame.return_address = 0; |
| 1813 | |
| 1814 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
| 1815 | if (bytes != sizeof(frame)) |
| 1816 | break; |
| 1817 | |
| 1818 | if (fp < compat_ptr(regs->sp)) |
| 1819 | break; |
| 1820 | |
| 1821 | perf_callchain_store(entry, frame.return_address); |
| 1822 | fp = compat_ptr(frame.next_frame); |
| 1823 | } |
| 1824 | return 1; |
| 1825 | } |
| 1826 | #else |
| 1827 | static inline int |
| 1828 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1829 | { |
| 1830 | return 0; |
| 1831 | } |
| 1832 | #endif |
| 1833 | |
| 1834 | void |
| 1835 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) |
| 1836 | { |
| 1837 | struct stack_frame frame; |
| 1838 | const void __user *fp; |
| 1839 | |
| 1840 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 1841 | /* TODO: We don't support guest os callchain now */ |
| 1842 | return; |
| 1843 | } |
| 1844 | |
| 1845 | fp = (void __user *)regs->bp; |
| 1846 | |
| 1847 | perf_callchain_store(entry, regs->ip); |
| 1848 | |
| 1849 | if (perf_callchain_user32(regs, entry)) |
| 1850 | return; |
| 1851 | |
| 1852 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
| 1853 | unsigned long bytes; |
| 1854 | frame.next_frame = NULL; |
| 1855 | frame.return_address = 0; |
| 1856 | |
| 1857 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
| 1858 | if (bytes != sizeof(frame)) |
| 1859 | break; |
| 1860 | |
| 1861 | if ((unsigned long)fp < regs->sp) |
| 1862 | break; |
| 1863 | |
| 1864 | perf_callchain_store(entry, frame.return_address); |
| 1865 | fp = frame.next_frame; |
| 1866 | } |
| 1867 | } |
| 1868 | |
| 1869 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
| 1870 | { |
| 1871 | unsigned long ip; |
| 1872 | |
| 1873 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
| 1874 | ip = perf_guest_cbs->get_guest_ip(); |
| 1875 | else |
| 1876 | ip = instruction_pointer(regs); |
| 1877 | |
| 1878 | return ip; |
| 1879 | } |
| 1880 | |
| 1881 | unsigned long perf_misc_flags(struct pt_regs *regs) |
| 1882 | { |
| 1883 | int misc = 0; |
| 1884 | |
| 1885 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 1886 | if (perf_guest_cbs->is_user_mode()) |
| 1887 | misc |= PERF_RECORD_MISC_GUEST_USER; |
| 1888 | else |
| 1889 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; |
| 1890 | } else { |
| 1891 | if (user_mode(regs)) |
| 1892 | misc |= PERF_RECORD_MISC_USER; |
| 1893 | else |
| 1894 | misc |= PERF_RECORD_MISC_KERNEL; |
| 1895 | } |
| 1896 | |
| 1897 | if (regs->flags & PERF_EFLAGS_EXACT) |
| 1898 | misc |= PERF_RECORD_MISC_EXACT_IP; |
| 1899 | |
| 1900 | return misc; |
| 1901 | } |