| 1 | #include <linux/init.h> |
| 2 | #include <linux/kernel.h> |
| 3 | |
| 4 | #include <linux/string.h> |
| 5 | #include <linux/bitops.h> |
| 6 | #include <linux/smp.h> |
| 7 | #include <linux/sched.h> |
| 8 | #include <linux/thread_info.h> |
| 9 | #include <linux/module.h> |
| 10 | |
| 11 | #include <asm/processor.h> |
| 12 | #include <asm/pgtable.h> |
| 13 | #include <asm/msr.h> |
| 14 | #include <asm/uaccess.h> |
| 15 | #include <asm/ds.h> |
| 16 | #include <asm/bugs.h> |
| 17 | #include <asm/cpu.h> |
| 18 | |
| 19 | #ifdef CONFIG_X86_64 |
| 20 | #include <asm/topology.h> |
| 21 | #include <asm/numa_64.h> |
| 22 | #endif |
| 23 | |
| 24 | #include "cpu.h" |
| 25 | |
| 26 | #ifdef CONFIG_X86_LOCAL_APIC |
| 27 | #include <asm/mpspec.h> |
| 28 | #include <asm/apic.h> |
| 29 | #endif |
| 30 | |
| 31 | static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
| 32 | { |
| 33 | /* Unmask CPUID levels if masked: */ |
| 34 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { |
| 35 | u64 misc_enable; |
| 36 | |
| 37 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); |
| 38 | |
| 39 | if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { |
| 40 | misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; |
| 41 | wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); |
| 42 | c->cpuid_level = cpuid_eax(0); |
| 43 | } |
| 44 | } |
| 45 | |
| 46 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
| 47 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) |
| 48 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
| 49 | |
| 50 | #ifdef CONFIG_X86_64 |
| 51 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); |
| 52 | #else |
| 53 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ |
| 54 | if (c->x86 == 15 && c->x86_cache_alignment == 64) |
| 55 | c->x86_cache_alignment = 128; |
| 56 | #endif |
| 57 | |
| 58 | /* CPUID workaround for 0F33/0F34 CPU */ |
| 59 | if (c->x86 == 0xF && c->x86_model == 0x3 |
| 60 | && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) |
| 61 | c->x86_phys_bits = 36; |
| 62 | |
| 63 | /* |
| 64 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate |
| 65 | * with P/T states and does not stop in deep C-states. |
| 66 | * |
| 67 | * It is also reliable across cores and sockets. (but not across |
| 68 | * cabinets - we turn it off in that case explicitly.) |
| 69 | */ |
| 70 | if (c->x86_power & (1 << 8)) { |
| 71 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
| 72 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
| 73 | set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE); |
| 74 | sched_clock_stable = 1; |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * There is a known erratum on Pentium III and Core Solo |
| 79 | * and Core Duo CPUs. |
| 80 | * " Page with PAT set to WC while associated MTRR is UC |
| 81 | * may consolidate to UC " |
| 82 | * Because of this erratum, it is better to stick with |
| 83 | * setting WC in MTRR rather than using PAT on these CPUs. |
| 84 | * |
| 85 | * Enable PAT WC only on P4, Core 2 or later CPUs. |
| 86 | */ |
| 87 | if (c->x86 == 6 && c->x86_model < 15) |
| 88 | clear_cpu_cap(c, X86_FEATURE_PAT); |
| 89 | } |
| 90 | |
| 91 | #ifdef CONFIG_X86_32 |
| 92 | /* |
| 93 | * Early probe support logic for ppro memory erratum #50 |
| 94 | * |
| 95 | * This is called before we do cpu ident work |
| 96 | */ |
| 97 | |
| 98 | int __cpuinit ppro_with_ram_bug(void) |
| 99 | { |
| 100 | /* Uses data from early_cpu_detect now */ |
| 101 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && |
| 102 | boot_cpu_data.x86 == 6 && |
| 103 | boot_cpu_data.x86_model == 1 && |
| 104 | boot_cpu_data.x86_mask < 8) { |
| 105 | printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); |
| 106 | return 1; |
| 107 | } |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | #ifdef CONFIG_X86_F00F_BUG |
| 112 | static void __cpuinit trap_init_f00f_bug(void) |
| 113 | { |
| 114 | __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO); |
| 115 | |
| 116 | /* |
| 117 | * Update the IDT descriptor and reload the IDT so that |
| 118 | * it uses the read-only mapped virtual address. |
| 119 | */ |
| 120 | idt_descr.address = fix_to_virt(FIX_F00F_IDT); |
| 121 | load_idt(&idt_descr); |
| 122 | } |
| 123 | #endif |
| 124 | |
| 125 | static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c) |
| 126 | { |
| 127 | #ifdef CONFIG_SMP |
| 128 | /* calling is from identify_secondary_cpu() ? */ |
| 129 | if (c->cpu_index == boot_cpu_id) |
| 130 | return; |
| 131 | |
| 132 | /* |
| 133 | * Mask B, Pentium, but not Pentium MMX |
| 134 | */ |
| 135 | if (c->x86 == 5 && |
| 136 | c->x86_mask >= 1 && c->x86_mask <= 4 && |
| 137 | c->x86_model <= 3) { |
| 138 | /* |
| 139 | * Remember we have B step Pentia with bugs |
| 140 | */ |
| 141 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" |
| 142 | "with B stepping processors.\n"); |
| 143 | } |
| 144 | #endif |
| 145 | } |
| 146 | |
| 147 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) |
| 148 | { |
| 149 | unsigned long lo, hi; |
| 150 | |
| 151 | #ifdef CONFIG_X86_F00F_BUG |
| 152 | /* |
| 153 | * All current models of Pentium and Pentium with MMX technology CPUs |
| 154 | * have the F0 0F bug, which lets nonprivileged users lock up the system. |
| 155 | * Note that the workaround only should be initialized once... |
| 156 | */ |
| 157 | c->f00f_bug = 0; |
| 158 | if (!paravirt_enabled() && c->x86 == 5) { |
| 159 | static int f00f_workaround_enabled; |
| 160 | |
| 161 | c->f00f_bug = 1; |
| 162 | if (!f00f_workaround_enabled) { |
| 163 | trap_init_f00f_bug(); |
| 164 | printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); |
| 165 | f00f_workaround_enabled = 1; |
| 166 | } |
| 167 | } |
| 168 | #endif |
| 169 | |
| 170 | /* |
| 171 | * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until |
| 172 | * model 3 mask 3 |
| 173 | */ |
| 174 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) |
| 175 | clear_cpu_cap(c, X86_FEATURE_SEP); |
| 176 | |
| 177 | /* |
| 178 | * P4 Xeon errata 037 workaround. |
| 179 | * Hardware prefetcher may cause stale data to be loaded into the cache. |
| 180 | */ |
| 181 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { |
| 182 | rdmsr(MSR_IA32_MISC_ENABLE, lo, hi); |
| 183 | if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) { |
| 184 | printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); |
| 185 | printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); |
| 186 | lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE; |
| 187 | wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | /* |
| 192 | * See if we have a good local APIC by checking for buggy Pentia, |
| 193 | * i.e. all B steppings and the C2 stepping of P54C when using their |
| 194 | * integrated APIC (see 11AP erratum in "Pentium Processor |
| 195 | * Specification Update"). |
| 196 | */ |
| 197 | if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && |
| 198 | (c->x86_mask < 0x6 || c->x86_mask == 0xb)) |
| 199 | set_cpu_cap(c, X86_FEATURE_11AP); |
| 200 | |
| 201 | |
| 202 | #ifdef CONFIG_X86_INTEL_USERCOPY |
| 203 | /* |
| 204 | * Set up the preferred alignment for movsl bulk memory moves |
| 205 | */ |
| 206 | switch (c->x86) { |
| 207 | case 4: /* 486: untested */ |
| 208 | break; |
| 209 | case 5: /* Old Pentia: untested */ |
| 210 | break; |
| 211 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ |
| 212 | movsl_mask.mask = 7; |
| 213 | break; |
| 214 | case 15: /* P4 is OK down to 8-byte alignment */ |
| 215 | movsl_mask.mask = 7; |
| 216 | break; |
| 217 | } |
| 218 | #endif |
| 219 | |
| 220 | #ifdef CONFIG_X86_NUMAQ |
| 221 | numaq_tsc_disable(); |
| 222 | #endif |
| 223 | |
| 224 | intel_smp_check(c); |
| 225 | } |
| 226 | #else |
| 227 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) |
| 228 | { |
| 229 | } |
| 230 | #endif |
| 231 | |
| 232 | static void __cpuinit srat_detect_node(void) |
| 233 | { |
| 234 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) |
| 235 | unsigned node; |
| 236 | int cpu = smp_processor_id(); |
| 237 | int apicid = hard_smp_processor_id(); |
| 238 | |
| 239 | /* Don't do the funky fallback heuristics the AMD version employs |
| 240 | for now. */ |
| 241 | node = apicid_to_node[apicid]; |
| 242 | if (node == NUMA_NO_NODE || !node_online(node)) |
| 243 | node = first_node(node_online_map); |
| 244 | numa_set_node(cpu, node); |
| 245 | |
| 246 | printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); |
| 247 | #endif |
| 248 | } |
| 249 | |
| 250 | /* |
| 251 | * find out the number of processor cores on the die |
| 252 | */ |
| 253 | static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) |
| 254 | { |
| 255 | unsigned int eax, ebx, ecx, edx; |
| 256 | |
| 257 | if (c->cpuid_level < 4) |
| 258 | return 1; |
| 259 | |
| 260 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
| 261 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); |
| 262 | if (eax & 0x1f) |
| 263 | return ((eax >> 26) + 1); |
| 264 | else |
| 265 | return 1; |
| 266 | } |
| 267 | |
| 268 | static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c) |
| 269 | { |
| 270 | /* Intel VMX MSR indicated features */ |
| 271 | #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 |
| 272 | #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 |
| 273 | #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 |
| 274 | #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 |
| 275 | #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 |
| 276 | #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 |
| 277 | |
| 278 | u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; |
| 279 | |
| 280 | clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); |
| 281 | clear_cpu_cap(c, X86_FEATURE_VNMI); |
| 282 | clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); |
| 283 | clear_cpu_cap(c, X86_FEATURE_EPT); |
| 284 | clear_cpu_cap(c, X86_FEATURE_VPID); |
| 285 | |
| 286 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); |
| 287 | msr_ctl = vmx_msr_high | vmx_msr_low; |
| 288 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) |
| 289 | set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); |
| 290 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) |
| 291 | set_cpu_cap(c, X86_FEATURE_VNMI); |
| 292 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { |
| 293 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
| 294 | vmx_msr_low, vmx_msr_high); |
| 295 | msr_ctl2 = vmx_msr_high | vmx_msr_low; |
| 296 | if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && |
| 297 | (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) |
| 298 | set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); |
| 299 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) |
| 300 | set_cpu_cap(c, X86_FEATURE_EPT); |
| 301 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) |
| 302 | set_cpu_cap(c, X86_FEATURE_VPID); |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
| 307 | { |
| 308 | unsigned int l2 = 0; |
| 309 | |
| 310 | early_init_intel(c); |
| 311 | |
| 312 | intel_workarounds(c); |
| 313 | |
| 314 | /* |
| 315 | * Detect the extended topology information if available. This |
| 316 | * will reinitialise the initial_apicid which will be used |
| 317 | * in init_intel_cacheinfo() |
| 318 | */ |
| 319 | detect_extended_topology(c); |
| 320 | |
| 321 | l2 = init_intel_cacheinfo(c); |
| 322 | if (c->cpuid_level > 9) { |
| 323 | unsigned eax = cpuid_eax(10); |
| 324 | /* Check for version and the number of counters */ |
| 325 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) |
| 326 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
| 327 | } |
| 328 | |
| 329 | if (cpu_has_xmm2) |
| 330 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
| 331 | if (cpu_has_ds) { |
| 332 | unsigned int l1; |
| 333 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); |
| 334 | if (!(l1 & (1<<11))) |
| 335 | set_cpu_cap(c, X86_FEATURE_BTS); |
| 336 | if (!(l1 & (1<<12))) |
| 337 | set_cpu_cap(c, X86_FEATURE_PEBS); |
| 338 | ds_init_intel(c); |
| 339 | } |
| 340 | |
| 341 | if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush) |
| 342 | set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR); |
| 343 | |
| 344 | #ifdef CONFIG_X86_64 |
| 345 | if (c->x86 == 15) |
| 346 | c->x86_cache_alignment = c->x86_clflush_size * 2; |
| 347 | if (c->x86 == 6) |
| 348 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
| 349 | #else |
| 350 | /* |
| 351 | * Names for the Pentium II/Celeron processors |
| 352 | * detectable only by also checking the cache size. |
| 353 | * Dixon is NOT a Celeron. |
| 354 | */ |
| 355 | if (c->x86 == 6) { |
| 356 | char *p = NULL; |
| 357 | |
| 358 | switch (c->x86_model) { |
| 359 | case 5: |
| 360 | if (c->x86_mask == 0) { |
| 361 | if (l2 == 0) |
| 362 | p = "Celeron (Covington)"; |
| 363 | else if (l2 == 256) |
| 364 | p = "Mobile Pentium II (Dixon)"; |
| 365 | } |
| 366 | break; |
| 367 | |
| 368 | case 6: |
| 369 | if (l2 == 128) |
| 370 | p = "Celeron (Mendocino)"; |
| 371 | else if (c->x86_mask == 0 || c->x86_mask == 5) |
| 372 | p = "Celeron-A"; |
| 373 | break; |
| 374 | |
| 375 | case 8: |
| 376 | if (l2 == 128) |
| 377 | p = "Celeron (Coppermine)"; |
| 378 | break; |
| 379 | } |
| 380 | |
| 381 | if (p) |
| 382 | strcpy(c->x86_model_id, p); |
| 383 | } |
| 384 | |
| 385 | if (c->x86 == 15) |
| 386 | set_cpu_cap(c, X86_FEATURE_P4); |
| 387 | if (c->x86 == 6) |
| 388 | set_cpu_cap(c, X86_FEATURE_P3); |
| 389 | #endif |
| 390 | |
| 391 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { |
| 392 | /* |
| 393 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology |
| 394 | * detection. |
| 395 | */ |
| 396 | c->x86_max_cores = intel_num_cpu_cores(c); |
| 397 | #ifdef CONFIG_X86_32 |
| 398 | detect_ht(c); |
| 399 | #endif |
| 400 | } |
| 401 | |
| 402 | /* Work around errata */ |
| 403 | srat_detect_node(); |
| 404 | |
| 405 | if (cpu_has(c, X86_FEATURE_VMX)) |
| 406 | detect_vmx_virtcap(c); |
| 407 | } |
| 408 | |
| 409 | #ifdef CONFIG_X86_32 |
| 410 | static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
| 411 | { |
| 412 | /* |
| 413 | * Intel PIII Tualatin. This comes in two flavours. |
| 414 | * One has 256kb of cache, the other 512. We have no way |
| 415 | * to determine which, so we use a boottime override |
| 416 | * for the 512kb model, and assume 256 otherwise. |
| 417 | */ |
| 418 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) |
| 419 | size = 256; |
| 420 | return size; |
| 421 | } |
| 422 | #endif |
| 423 | |
| 424 | static const struct cpu_dev __cpuinitconst intel_cpu_dev = { |
| 425 | .c_vendor = "Intel", |
| 426 | .c_ident = { "GenuineIntel" }, |
| 427 | #ifdef CONFIG_X86_32 |
| 428 | .c_models = { |
| 429 | { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = |
| 430 | { |
| 431 | [0] = "486 DX-25/33", |
| 432 | [1] = "486 DX-50", |
| 433 | [2] = "486 SX", |
| 434 | [3] = "486 DX/2", |
| 435 | [4] = "486 SL", |
| 436 | [5] = "486 SX/2", |
| 437 | [7] = "486 DX/2-WB", |
| 438 | [8] = "486 DX/4", |
| 439 | [9] = "486 DX/4-WB" |
| 440 | } |
| 441 | }, |
| 442 | { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = |
| 443 | { |
| 444 | [0] = "Pentium 60/66 A-step", |
| 445 | [1] = "Pentium 60/66", |
| 446 | [2] = "Pentium 75 - 200", |
| 447 | [3] = "OverDrive PODP5V83", |
| 448 | [4] = "Pentium MMX", |
| 449 | [7] = "Mobile Pentium 75 - 200", |
| 450 | [8] = "Mobile Pentium MMX" |
| 451 | } |
| 452 | }, |
| 453 | { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = |
| 454 | { |
| 455 | [0] = "Pentium Pro A-step", |
| 456 | [1] = "Pentium Pro", |
| 457 | [3] = "Pentium II (Klamath)", |
| 458 | [4] = "Pentium II (Deschutes)", |
| 459 | [5] = "Pentium II (Deschutes)", |
| 460 | [6] = "Mobile Pentium II", |
| 461 | [7] = "Pentium III (Katmai)", |
| 462 | [8] = "Pentium III (Coppermine)", |
| 463 | [10] = "Pentium III (Cascades)", |
| 464 | [11] = "Pentium III (Tualatin)", |
| 465 | } |
| 466 | }, |
| 467 | { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = |
| 468 | { |
| 469 | [0] = "Pentium 4 (Unknown)", |
| 470 | [1] = "Pentium 4 (Willamette)", |
| 471 | [2] = "Pentium 4 (Northwood)", |
| 472 | [4] = "Pentium 4 (Foster)", |
| 473 | [5] = "Pentium 4 (Foster)", |
| 474 | } |
| 475 | }, |
| 476 | }, |
| 477 | .c_size_cache = intel_size_cache, |
| 478 | #endif |
| 479 | .c_early_init = early_init_intel, |
| 480 | .c_init = init_intel, |
| 481 | .c_x86_vendor = X86_VENDOR_INTEL, |
| 482 | }; |
| 483 | |
| 484 | cpu_dev_register(intel_cpu_dev); |
| 485 | |