[linux-2.6-block.git] / arch / x86 / kernel / apic / x2apic_cluster.c

#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/dmar.h>
#include <linux/cpu.h>

#include <asm/smp.h>
#include <asm/x2apic.h>

static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);

static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
	return x2apic_enabled();
}

static inline u32 x2apic_cluster(int cpu)
{
	return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
}

static void
__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
{
	struct cpumask *cpus_in_cluster_ptr;
	struct cpumask *ipi_mask_ptr;
	unsigned int cpu, this_cpu;
	unsigned long flags;
	u32 dest;

	x2apic_wrmsr_fence();

	local_irq_save(flags);

	this_cpu = smp_processor_id();

	/*
	 * We are to modify mask, so we need an own copy
	 * and be sure it's manipulated with irq off.
	 */
	ipi_mask_ptr = __raw_get_cpu_var(ipi_mask);
	cpumask_copy(ipi_mask_ptr, mask);

	/*
	 * The idea is to send one IPI per cluster.
	 */
	for_each_cpu(cpu, ipi_mask_ptr) {
		unsigned long i;

		cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
		dest = 0;

		/* Collect cpus in cluster. */
		for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
			if (apic_dest == APIC_DEST_ALLINC || i != this_cpu)
				dest |= per_cpu(x86_cpu_to_logical_apicid, i);
		}

		if (!dest)
			continue;

		__x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
		/*
		 * Cluster sibling cpus should be discared now so
		 * we would not send IPI them second time.
		 */
		cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
	}

	local_irq_restore(flags);
}

static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
{
	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
}

static void
x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
{
	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
}

static void x2apic_send_IPI_allbutself(int vector)
{
	__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
}

static void x2apic_send_IPI_all(int vector)
{
	__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
}

static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
{
	int cpu = cpumask_first(cpumask);
	u32 dest = 0;
	int i;

	if (cpu > nr_cpu_ids)
		return BAD_APICID;

	for_each_cpu_and(i, cpumask, per_cpu(cpus_in_cluster, cpu))
		dest |= per_cpu(x86_cpu_to_logical_apicid, i);

	return dest;
}

static unsigned int
x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
			      const struct cpumask *andmask)
{
	u32 dest = 0;
	u16 cluster;
	int i;

	for_each_cpu_and(i, cpumask, andmask) {
		if (!cpumask_test_cpu(i, cpu_online_mask))
			continue;
		dest = per_cpu(x86_cpu_to_logical_apicid, i);
		cluster = x2apic_cluster(i);
		break;
	}

	if (!dest)
		return BAD_APICID;

	for_each_cpu_and(i, cpumask, andmask) {
		if (!cpumask_test_cpu(i, cpu_online_mask))
			continue;
		if (cluster != x2apic_cluster(i))
			continue;
		dest |= per_cpu(x86_cpu_to_logical_apicid, i);
	}

	return dest;
}

static void init_x2apic_ldr(void)
{
	unsigned int this_cpu = smp_processor_id();
	unsigned int cpu;

	per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);

	__cpu_set(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
	for_each_online_cpu(cpu) {
		if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
			continue;
		__cpu_set(this_cpu, per_cpu(cpus_in_cluster, cpu));
		__cpu_set(cpu, per_cpu(cpus_in_cluster, this_cpu));
	}
}

 /*
  * At CPU state changes, update the x2apic cluster sibling info.
  */
static int __cpuinit
update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu)
{
	unsigned int this_cpu = (unsigned long)hcpu;
	unsigned int cpu;
	int err = 0;

	switch (action) {
	case CPU_UP_PREPARE:
		if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu),
					GFP_KERNEL)) {
			err = -ENOMEM;
		} else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu),
					       GFP_KERNEL)) {
			free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
			err = -ENOMEM;
		}
		break;
	case CPU_UP_CANCELED:
	case CPU_UP_CANCELED_FROZEN:
	case CPU_DEAD:
		for_each_online_cpu(cpu) {
			if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
				continue;
			__cpu_clear(this_cpu, per_cpu(cpus_in_cluster, cpu));
			__cpu_clear(cpu, per_cpu(cpus_in_cluster, this_cpu));
		}
		free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
		free_cpumask_var(per_cpu(ipi_mask, this_cpu));
		break;
	}

	return notifier_from_errno(err);
}

static struct notifier_block __refdata x2apic_cpu_notifier = {
	.notifier_call = update_clusterinfo,
};

static int x2apic_init_cpu_notifier(void)
{
	int cpu = smp_processor_id();

	zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL);
	zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL);

	BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu));

	__cpu_set(cpu, per_cpu(cpus_in_cluster, cpu));
	register_hotcpu_notifier(&x2apic_cpu_notifier);
	return 1;
}

static int x2apic_cluster_probe(void)
{
	if (x2apic_mode)
		return x2apic_init_cpu_notifier();
	else
		return 0;
}

/*
 * Each x2apic cluster is an allocation domain.
 */
static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask)
{
	cpumask_clear(retmask);
	cpumask_copy(retmask, per_cpu(cpus_in_cluster, cpu));
}

static struct apic apic_x2apic_cluster = {

	.name				= "cluster x2apic",
	.probe				= x2apic_cluster_probe,
	.acpi_madt_oem_check		= x2apic_acpi_madt_oem_check,
	.apic_id_valid			= x2apic_apic_id_valid,
	.apic_id_registered		= x2apic_apic_id_registered,

	.irq_delivery_mode		= dest_LowestPrio,
	.irq_dest_mode			= 1, /* logical */

	.target_cpus			= online_target_cpus,
	.disable_esr			= 0,
	.dest_logical			= APIC_DEST_LOGICAL,
	.check_apicid_used		= NULL,
	.check_apicid_present		= NULL,

	.vector_allocation_domain	= cluster_vector_allocation_domain,
	.init_apic_ldr			= init_x2apic_ldr,

	.ioapic_phys_id_map		= NULL,
	.setup_apic_routing		= NULL,
	.multi_timer_check		= NULL,
	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
	.apicid_to_cpu_present		= NULL,
	.setup_portio_remap		= NULL,
	.check_phys_apicid_present	= default_check_phys_apicid_present,
	.enable_apic_mode		= NULL,
	.phys_pkg_id			= x2apic_phys_pkg_id,
	.mps_oem_check			= NULL,

	.get_apic_id			= x2apic_get_apic_id,
	.set_apic_id			= x2apic_set_apic_id,
	.apic_id_mask			= 0xFFFFFFFFu,

	.cpu_mask_to_apicid		= x2apic_cpu_mask_to_apicid,
	.cpu_mask_to_apicid_and		= x2apic_cpu_mask_to_apicid_and,

	.send_IPI_mask			= x2apic_send_IPI_mask,
	.send_IPI_mask_allbutself	= x2apic_send_IPI_mask_allbutself,
	.send_IPI_allbutself		= x2apic_send_IPI_allbutself,
	.send_IPI_all			= x2apic_send_IPI_all,
	.send_IPI_self			= x2apic_send_IPI_self,

	.trampoline_phys_low		= DEFAULT_TRAMPOLINE_PHYS_LOW,
	.trampoline_phys_high		= DEFAULT_TRAMPOLINE_PHYS_HIGH,
	.wait_for_init_deassert		= NULL,
	.smp_callin_clear_local_apic	= NULL,
	.inquire_remote_apic		= NULL,

	.read				= native_apic_msr_read,
	.write				= native_apic_msr_write,
	.eoi_write			= native_apic_msr_eoi_write,
	.icr_read			= native_x2apic_icr_read,
	.icr_write			= native_x2apic_icr_write,
	.wait_icr_idle			= native_x2apic_wait_icr_idle,
	.safe_wait_icr_idle		= native_safe_x2apic_wait_icr_idle,
};

apic_driver(apic_x2apic_cluster);
Commit	Line	Data
	1	#include <linux/threads.h>
	2	#include <linux/cpumask.h>
	3	#include <linux/string.h>
	4	#include <linux/kernel.h>
	5	#include <linux/ctype.h>
	6	#include <linux/init.h>
	7	#include <linux/dmar.h>
	8	#include <linux/cpu.h>
	9
	10	#include <asm/smp.h>
	11	#include <asm/x2apic.h>
	12
	13	static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
	14	static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
	15	static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
	16
	17	static int x2apic_acpi_madt_oem_check(char oem_id, char oem_table_id)
	18	{
	19	return x2apic_enabled();
	20	}
	21
	22	static inline u32 x2apic_cluster(int cpu)
	23	{
	24	return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
	25	}
	26
	27	static void
	28	__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
	29	{
	30	struct cpumask *cpus_in_cluster_ptr;
	31	struct cpumask *ipi_mask_ptr;
	32	unsigned int cpu, this_cpu;
	33	unsigned long flags;
	34	u32 dest;
	35
	36	x2apic_wrmsr_fence();
	37
	38	local_irq_save(flags);
	39
	40	this_cpu = smp_processor_id();
	41
	42	/*
	43	* We are to modify mask, so we need an own copy
	44	* and be sure it's manipulated with irq off.
	45	*/
	46	ipi_mask_ptr = __raw_get_cpu_var(ipi_mask);
	47	cpumask_copy(ipi_mask_ptr, mask);
	48
	49	/*
	50	* The idea is to send one IPI per cluster.
	51	*/
	52	for_each_cpu(cpu, ipi_mask_ptr) {
	53	unsigned long i;
	54
	55	cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
	56	dest = 0;
	57
	58	/* Collect cpus in cluster. */
	59	for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
	60	if (apic_dest == APIC_DEST_ALLINC \|\| i != this_cpu)
	61	dest \|= per_cpu(x86_cpu_to_logical_apicid, i);
	62	}
	63
	64	if (!dest)
	65	continue;
	66
	67	__x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
	68	/*
	69	* Cluster sibling cpus should be discared now so
	70	* we would not send IPI them second time.
	71	*/
	72	cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
	73	}
	74
	75	local_irq_restore(flags);
	76	}
	77
	78	static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
	79	{
	80	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
	81	}
	82
	83	static void
	84	x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
	85	{
	86	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
	87	}
	88
	89	static void x2apic_send_IPI_allbutself(int vector)
	90	{
	91	__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
	92	}
	93
	94	static void x2apic_send_IPI_all(int vector)
	95	{
	96	__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
	97	}
	98
	99	static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
	100	{
	101	int cpu = cpumask_first(cpumask);
	102	u32 dest = 0;
	103	int i;
	104
	105	if (cpu > nr_cpu_ids)
	106	return BAD_APICID;
	107
	108	for_each_cpu_and(i, cpumask, per_cpu(cpus_in_cluster, cpu))
	109	dest \|= per_cpu(x86_cpu_to_logical_apicid, i);
	110
	111	return dest;
	112	}
	113
	114	static unsigned int
	115	x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
	116	const struct cpumask *andmask)
	117	{
	118	u32 dest = 0;
	119	u16 cluster;
	120	int i;
	121
	122	for_each_cpu_and(i, cpumask, andmask) {
	123	if (!cpumask_test_cpu(i, cpu_online_mask))
	124	continue;
	125	dest = per_cpu(x86_cpu_to_logical_apicid, i);
	126	cluster = x2apic_cluster(i);
	127	break;
	128	}
	129
	130	if (!dest)
	131	return BAD_APICID;
	132
	133	for_each_cpu_and(i, cpumask, andmask) {
	134	if (!cpumask_test_cpu(i, cpu_online_mask))
	135	continue;
	136	if (cluster != x2apic_cluster(i))
	137	continue;
	138	dest \|= per_cpu(x86_cpu_to_logical_apicid, i);
	139	}
	140
	141	return dest;
	142	}
	143
	144	static void init_x2apic_ldr(void)
	145	{
	146	unsigned int this_cpu = smp_processor_id();
	147	unsigned int cpu;
	148
	149	per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);
	150
	151	__cpu_set(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
	152	for_each_online_cpu(cpu) {
	153	if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
	154	continue;
	155	__cpu_set(this_cpu, per_cpu(cpus_in_cluster, cpu));
	156	__cpu_set(cpu, per_cpu(cpus_in_cluster, this_cpu));
	157	}
	158	}
	159
	160	/*
	161	* At CPU state changes, update the x2apic cluster sibling info.
	162	*/
	163	static int __cpuinit
	164	update_clusterinfo(struct notifier_block nfb, unsigned long action, void hcpu)
	165	{
	166	unsigned int this_cpu = (unsigned long)hcpu;
	167	unsigned int cpu;
	168	int err = 0;
	169
	170	switch (action) {
	171	case CPU_UP_PREPARE:
	172	if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu),
	173	GFP_KERNEL)) {
	174	err = -ENOMEM;
	175	} else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu),
	176	GFP_KERNEL)) {
	177	free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
	178	err = -ENOMEM;
	179	}
	180	break;
	181	case CPU_UP_CANCELED:
	182	case CPU_UP_CANCELED_FROZEN:
	183	case CPU_DEAD:
	184	for_each_online_cpu(cpu) {
	185	if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
	186	continue;
	187	__cpu_clear(this_cpu, per_cpu(cpus_in_cluster, cpu));
	188	__cpu_clear(cpu, per_cpu(cpus_in_cluster, this_cpu));
	189	}
	190	free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
	191	free_cpumask_var(per_cpu(ipi_mask, this_cpu));
	192	break;
	193	}
	194
	195	return notifier_from_errno(err);
	196	}
	197
	198	static struct notifier_block __refdata x2apic_cpu_notifier = {
	199	.notifier_call = update_clusterinfo,
	200	};
	201
	202	static int x2apic_init_cpu_notifier(void)
	203	{
	204	int cpu = smp_processor_id();
	205
	206	zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL);
	207	zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL);
	208
	209	BUG_ON(!per_cpu(cpus_in_cluster, cpu) \|\| !per_cpu(ipi_mask, cpu));
	210
	211	__cpu_set(cpu, per_cpu(cpus_in_cluster, cpu));
	212	register_hotcpu_notifier(&x2apic_cpu_notifier);
	213	return 1;
	214	}
	215
	216	static int x2apic_cluster_probe(void)
	217	{
	218	if (x2apic_mode)
	219	return x2apic_init_cpu_notifier();
	220	else
	221	return 0;
	222	}
	223
	224	/*
	225	* Each x2apic cluster is an allocation domain.
	226	*/
	227	static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask)
	228	{
	229	cpumask_clear(retmask);
	230	cpumask_copy(retmask, per_cpu(cpus_in_cluster, cpu));
	231	}
	232
	233	static struct apic apic_x2apic_cluster = {
	234
	235	.name = "cluster x2apic",
	236	.probe = x2apic_cluster_probe,
	237	.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
	238	.apic_id_valid = x2apic_apic_id_valid,
	239	.apic_id_registered = x2apic_apic_id_registered,
	240
	241	.irq_delivery_mode = dest_LowestPrio,
	242	.irq_dest_mode = 1, /* logical */
	243
	244	.target_cpus = online_target_cpus,
	245	.disable_esr = 0,
	246	.dest_logical = APIC_DEST_LOGICAL,
	247	.check_apicid_used = NULL,
	248	.check_apicid_present = NULL,
	249
	250	.vector_allocation_domain = cluster_vector_allocation_domain,
	251	.init_apic_ldr = init_x2apic_ldr,
	252
	253	.ioapic_phys_id_map = NULL,
	254	.setup_apic_routing = NULL,
	255	.multi_timer_check = NULL,
	256	.cpu_present_to_apicid = default_cpu_present_to_apicid,
	257	.apicid_to_cpu_present = NULL,
	258	.setup_portio_remap = NULL,
	259	.check_phys_apicid_present = default_check_phys_apicid_present,
	260	.enable_apic_mode = NULL,
	261	.phys_pkg_id = x2apic_phys_pkg_id,
	262	.mps_oem_check = NULL,
	263
	264	.get_apic_id = x2apic_get_apic_id,
	265	.set_apic_id = x2apic_set_apic_id,
	266	.apic_id_mask = 0xFFFFFFFFu,
	267
	268	.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
	269	.cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
	270
	271	.send_IPI_mask = x2apic_send_IPI_mask,
	272	.send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
	273	.send_IPI_allbutself = x2apic_send_IPI_allbutself,
	274	.send_IPI_all = x2apic_send_IPI_all,
	275	.send_IPI_self = x2apic_send_IPI_self,
	276
	277	.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
	278	.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
	279	.wait_for_init_deassert = NULL,
	280	.smp_callin_clear_local_apic = NULL,
	281	.inquire_remote_apic = NULL,
	282
	283	.read = native_apic_msr_read,
	284	.write = native_apic_msr_write,
	285	.eoi_write = native_apic_msr_eoi_write,
	286	.icr_read = native_x2apic_icr_read,
	287	.icr_write = native_x2apic_icr_write,
	288	.wait_icr_idle = native_x2apic_wait_icr_idle,
	289	.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
	290	};
	291
	292	apic_driver(apic_x2apic_cluster);