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Merge tag 'mm-hotfixes-stable-2025-07-11-16-16' of git://git.kernel.org/pub/scm/linux...
[linux-block.git] / arch / sparc / mm / srmmu.c
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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * srmmu.c: SRMMU specific routines for memory management.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
10 */
11
12#include <linux/seq_file.h>
13#include <linux/spinlock.h>
14#include <linux/memblock.h>
15#include <linux/pagemap.h>
16#include <linux/vmalloc.h>
17#include <linux/kdebug.h>
18#include <linux/export.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/log2.h>
22#include <linux/gfp.h>
23#include <linux/fs.h>
24#include <linux/mm.h>
25
26#include <asm/mmu_context.h>
27#include <asm/cacheflush.h>
28#include <asm/tlbflush.h>
29#include <asm/io-unit.h>
30#include <asm/pgalloc.h>
31#include <asm/pgtable.h>
32#include <asm/bitext.h>
33#include <asm/vaddrs.h>
34#include <asm/cache.h>
35#include <asm/traps.h>
36#include <asm/oplib.h>
37#include <asm/mbus.h>
38#include <asm/page.h>
39#include <asm/asi.h>
40#include <asm/smp.h>
41#include <asm/io.h>
42
43/* Now the cpu specific definitions. */
44#include <asm/turbosparc.h>
45#include <asm/tsunami.h>
46#include <asm/viking.h>
47#include <asm/swift.h>
48#include <asm/leon.h>
49#include <asm/mxcc.h>
50#include <asm/ross.h>
51
52#include "mm_32.h"
53
54enum mbus_module srmmu_modtype;
55static unsigned int hwbug_bitmask;
56int vac_cache_size;
57EXPORT_SYMBOL(vac_cache_size);
58int vac_line_size;
59
60extern struct resource sparc_iomap;
61
62extern unsigned long last_valid_pfn;
63
64static pgd_t *srmmu_swapper_pg_dir;
65
66const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
67EXPORT_SYMBOL(sparc32_cachetlb_ops);
68
69#ifdef CONFIG_SMP
70const struct sparc32_cachetlb_ops *local_ops;
71
72#define FLUSH_BEGIN(mm)
73#define FLUSH_END
74#else
75#define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
76#define FLUSH_END }
77#endif
78
79int flush_page_for_dma_global = 1;
80
81char *srmmu_name;
82
83ctxd_t *srmmu_ctx_table_phys;
84static ctxd_t *srmmu_context_table;
85
86int viking_mxcc_present;
87static DEFINE_SPINLOCK(srmmu_context_spinlock);
88
89static int is_hypersparc;
90
91static int srmmu_cache_pagetables;
92
93/* these will be initialized in srmmu_nocache_calcsize() */
94static unsigned long srmmu_nocache_size;
95static unsigned long srmmu_nocache_end;
96
97/* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
98#define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
99
100/* The context table is a nocache user with the biggest alignment needs. */
101#define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
102
103void *srmmu_nocache_pool;
104static struct bit_map srmmu_nocache_map;
105
106static inline int srmmu_pmd_none(pmd_t pmd)
107{ return !(pmd_val(pmd) & 0xFFFFFFF); }
108
109/* XXX should we hyper_flush_whole_icache here - Anton */
110static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
111{
112 pte_t pte;
113
114 pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4)));
115 set_pte((pte_t *)ctxp, pte);
116}
117
118/*
119 * Locations of MSI Registers.
120 */
121#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
122
123/*
124 * Useful bits in the MSI Registers.
125 */
126#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
127
128static void msi_set_sync(void)
129{
130 __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
131 "andn %%g3, %2, %%g3\n\t"
132 "sta %%g3, [%0] %1\n\t" : :
133 "r" (MSI_MBUS_ARBEN),
134 "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
135}
136
137void pmd_set(pmd_t *pmdp, pte_t *ptep)
138{
139 unsigned long ptp = __nocache_pa(ptep) >> 4;
140 set_pte((pte_t *)&pmd_val(*pmdp), __pte(SRMMU_ET_PTD | ptp));
141}
142
143/*
144 * size: bytes to allocate in the nocache area.
145 * align: bytes, number to align at.
146 * Returns the virtual address of the allocated area.
147 */
148static void *__srmmu_get_nocache(int size, int align)
149{
150 int offset, minsz = 1 << SRMMU_NOCACHE_BITMAP_SHIFT;
151 unsigned long addr;
152
153 if (size < minsz) {
154 printk(KERN_ERR "Size 0x%x too small for nocache request\n",
155 size);
156 size = minsz;
157 }
158 if (size & (minsz - 1)) {
159 printk(KERN_ERR "Size 0x%x unaligned in nocache request\n",
160 size);
161 size += minsz - 1;
162 }
163 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
164
165 offset = bit_map_string_get(&srmmu_nocache_map,
166 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
167 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
168 if (offset == -1) {
169 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
170 size, (int) srmmu_nocache_size,
171 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
172 return NULL;
173 }
174
175 addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
176 return (void *)addr;
177}
178
179void *srmmu_get_nocache(int size, int align)
180{
181 void *tmp;
182
183 tmp = __srmmu_get_nocache(size, align);
184
185 if (tmp)
186 memset(tmp, 0, size);
187
188 return tmp;
189}
190
191void srmmu_free_nocache(void *addr, int size)
192{
193 unsigned long vaddr;
194 int offset;
195
196 vaddr = (unsigned long)addr;
197 if (vaddr < SRMMU_NOCACHE_VADDR) {
198 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
199 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
200 BUG();
201 }
202 if (vaddr + size > srmmu_nocache_end) {
203 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
204 vaddr, srmmu_nocache_end);
205 BUG();
206 }
207 if (!is_power_of_2(size)) {
208 printk("Size 0x%x is not a power of 2\n", size);
209 BUG();
210 }
211 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
212 printk("Size 0x%x is too small\n", size);
213 BUG();
214 }
215 if (vaddr & (size - 1)) {
216 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
217 BUG();
218 }
219
220 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
221 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
222
223 bit_map_clear(&srmmu_nocache_map, offset, size);
224}
225
226static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
227 unsigned long end);
228
229/* Return how much physical memory we have. */
230static unsigned long __init probe_memory(void)
231{
232 unsigned long total = 0;
233 int i;
234
235 for (i = 0; sp_banks[i].num_bytes; i++)
236 total += sp_banks[i].num_bytes;
237
238 return total;
239}
240
241/*
242 * Reserve nocache dynamically proportionally to the amount of
243 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
244 */
245static void __init srmmu_nocache_calcsize(void)
246{
247 unsigned long sysmemavail = probe_memory() / 1024;
248 int srmmu_nocache_npages;
249
250 srmmu_nocache_npages =
251 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
252
253 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
254 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
255 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
256 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
257
258 /* anything above 1280 blows up */
259 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
260 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
261
262 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
263 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
264}
265
266static void __init srmmu_nocache_init(void)
267{
268 void *srmmu_nocache_bitmap;
269 unsigned int bitmap_bits;
270 pgd_t *pgd;
271 p4d_t *p4d;
272 pud_t *pud;
273 pmd_t *pmd;
274 pte_t *pte;
275 unsigned long paddr, vaddr;
276 unsigned long pteval;
277
278 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
279
280 srmmu_nocache_pool = memblock_alloc_or_panic(srmmu_nocache_size,
281 SRMMU_NOCACHE_ALIGN_MAX);
282 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
283
284 srmmu_nocache_bitmap =
285 memblock_alloc_or_panic(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
286 SMP_CACHE_BYTES);
287 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
288
289 srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
290 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
291 init_mm.pgd = srmmu_swapper_pg_dir;
292
293 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
294
295 paddr = __pa((unsigned long)srmmu_nocache_pool);
296 vaddr = SRMMU_NOCACHE_VADDR;
297
298 while (vaddr < srmmu_nocache_end) {
299 pgd = pgd_offset_k(vaddr);
300 p4d = p4d_offset(pgd, vaddr);
301 pud = pud_offset(p4d, vaddr);
302 pmd = pmd_offset(__nocache_fix(pud), vaddr);
303 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
304
305 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
306
307 if (srmmu_cache_pagetables)
308 pteval |= SRMMU_CACHE;
309
310 set_pte(__nocache_fix(pte), __pte(pteval));
311
312 vaddr += PAGE_SIZE;
313 paddr += PAGE_SIZE;
314 }
315
316 flush_cache_all();
317 flush_tlb_all();
318}
319
320pgd_t *get_pgd_fast(void)
321{
322 pgd_t *pgd = NULL;
323
324 pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
325 if (pgd) {
326 pgd_t *init = pgd_offset_k(0);
327 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
328 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
329 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
330 }
331
332 return pgd;
333}
334
335/*
336 * Hardware needs alignment to 256 only, but we align to whole page size
337 * to reduce fragmentation problems due to the buddy principle.
338 * XXX Provide actual fragmentation statistics in /proc.
339 *
340 * Alignments up to the page size are the same for physical and virtual
341 * addresses of the nocache area.
342 */
343pgtable_t pte_alloc_one(struct mm_struct *mm)
344{
345 pte_t *ptep;
346 struct page *page;
347
348 if (!(ptep = pte_alloc_one_kernel(mm)))
349 return NULL;
350 page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
351 spin_lock(&mm->page_table_lock);
352 if (page_ref_inc_return(page) == 2 &&
353 !pagetable_pte_ctor(mm, page_ptdesc(page))) {
354 page_ref_dec(page);
355 ptep = NULL;
356 }
357 spin_unlock(&mm->page_table_lock);
358
359 return ptep;
360}
361
362void pte_free(struct mm_struct *mm, pgtable_t ptep)
363{
364 struct page *page;
365
366 page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
367 spin_lock(&mm->page_table_lock);
368 if (page_ref_dec_return(page) == 1)
369 pagetable_dtor(page_ptdesc(page));
370 spin_unlock(&mm->page_table_lock);
371
372 srmmu_free_nocache(ptep, SRMMU_PTE_TABLE_SIZE);
373}
374
375/* context handling - a dynamically sized pool is used */
376#define NO_CONTEXT -1
377
378struct ctx_list {
379 struct ctx_list *next;
380 struct ctx_list *prev;
381 unsigned int ctx_number;
382 struct mm_struct *ctx_mm;
383};
384
385static struct ctx_list *ctx_list_pool;
386static struct ctx_list ctx_free;
387static struct ctx_list ctx_used;
388
389/* At boot time we determine the number of contexts */
390static int num_contexts;
391
392static inline void remove_from_ctx_list(struct ctx_list *entry)
393{
394 entry->next->prev = entry->prev;
395 entry->prev->next = entry->next;
396}
397
398static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
399{
400 entry->next = head;
401 (entry->prev = head->prev)->next = entry;
402 head->prev = entry;
403}
404#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
405#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
406
407
408static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
409{
410 struct ctx_list *ctxp;
411
412 ctxp = ctx_free.next;
413 if (ctxp != &ctx_free) {
414 remove_from_ctx_list(ctxp);
415 add_to_used_ctxlist(ctxp);
416 mm->context = ctxp->ctx_number;
417 ctxp->ctx_mm = mm;
418 return;
419 }
420 ctxp = ctx_used.next;
421 if (ctxp->ctx_mm == old_mm)
422 ctxp = ctxp->next;
423 if (ctxp == &ctx_used)
424 panic("out of mmu contexts");
425 flush_cache_mm(ctxp->ctx_mm);
426 flush_tlb_mm(ctxp->ctx_mm);
427 remove_from_ctx_list(ctxp);
428 add_to_used_ctxlist(ctxp);
429 ctxp->ctx_mm->context = NO_CONTEXT;
430 ctxp->ctx_mm = mm;
431 mm->context = ctxp->ctx_number;
432}
433
434static inline void free_context(int context)
435{
436 struct ctx_list *ctx_old;
437
438 ctx_old = ctx_list_pool + context;
439 remove_from_ctx_list(ctx_old);
440 add_to_free_ctxlist(ctx_old);
441}
442
443static void __init sparc_context_init(int numctx)
444{
445 int ctx;
446 unsigned long size;
447
448 size = numctx * sizeof(struct ctx_list);
449 ctx_list_pool = memblock_alloc_or_panic(size, SMP_CACHE_BYTES);
450
451 for (ctx = 0; ctx < numctx; ctx++) {
452 struct ctx_list *clist;
453
454 clist = (ctx_list_pool + ctx);
455 clist->ctx_number = ctx;
456 clist->ctx_mm = NULL;
457 }
458 ctx_free.next = ctx_free.prev = &ctx_free;
459 ctx_used.next = ctx_used.prev = &ctx_used;
460 for (ctx = 0; ctx < numctx; ctx++)
461 add_to_free_ctxlist(ctx_list_pool + ctx);
462}
463
464void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
465 struct task_struct *tsk)
466{
467 unsigned long flags;
468
469 if (mm->context == NO_CONTEXT) {
470 spin_lock_irqsave(&srmmu_context_spinlock, flags);
471 alloc_context(old_mm, mm);
472 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
473 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
474 }
475
476 if (sparc_cpu_model == sparc_leon)
477 leon_switch_mm();
478
479 if (is_hypersparc)
480 hyper_flush_whole_icache();
481
482 srmmu_set_context(mm->context);
483}
484
485/* Low level IO area allocation on the SRMMU. */
486static inline void srmmu_mapioaddr(unsigned long physaddr,
487 unsigned long virt_addr, int bus_type)
488{
489 pgd_t *pgdp;
490 p4d_t *p4dp;
491 pud_t *pudp;
492 pmd_t *pmdp;
493 pte_t *ptep;
494 unsigned long tmp;
495
496 physaddr &= PAGE_MASK;
497 pgdp = pgd_offset_k(virt_addr);
498 p4dp = p4d_offset(pgdp, virt_addr);
499 pudp = pud_offset(p4dp, virt_addr);
500 pmdp = pmd_offset(pudp, virt_addr);
501 ptep = pte_offset_kernel(pmdp, virt_addr);
502 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
503
504 /* I need to test whether this is consistent over all
505 * sun4m's. The bus_type represents the upper 4 bits of
506 * 36-bit physical address on the I/O space lines...
507 */
508 tmp |= (bus_type << 28);
509 tmp |= SRMMU_PRIV;
510 __flush_page_to_ram(virt_addr);
511 set_pte(ptep, __pte(tmp));
512}
513
514void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
515 unsigned long xva, unsigned int len)
516{
517 while (len != 0) {
518 len -= PAGE_SIZE;
519 srmmu_mapioaddr(xpa, xva, bus);
520 xva += PAGE_SIZE;
521 xpa += PAGE_SIZE;
522 }
523 flush_tlb_all();
524}
525
526static inline void srmmu_unmapioaddr(unsigned long virt_addr)
527{
528 pgd_t *pgdp;
529 p4d_t *p4dp;
530 pud_t *pudp;
531 pmd_t *pmdp;
532 pte_t *ptep;
533
534
535 pgdp = pgd_offset_k(virt_addr);
536 p4dp = p4d_offset(pgdp, virt_addr);
537 pudp = pud_offset(p4dp, virt_addr);
538 pmdp = pmd_offset(pudp, virt_addr);
539 ptep = pte_offset_kernel(pmdp, virt_addr);
540
541 /* No need to flush uncacheable page. */
542 __pte_clear(ptep);
543}
544
545void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
546{
547 while (len != 0) {
548 len -= PAGE_SIZE;
549 srmmu_unmapioaddr(virt_addr);
550 virt_addr += PAGE_SIZE;
551 }
552 flush_tlb_all();
553}
554
555/* tsunami.S */
556extern void tsunami_flush_cache_all(void);
557extern void tsunami_flush_cache_mm(struct mm_struct *mm);
558extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
559extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
560extern void tsunami_flush_page_to_ram(unsigned long page);
561extern void tsunami_flush_page_for_dma(unsigned long page);
562extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
563extern void tsunami_flush_tlb_all(void);
564extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
565extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
566extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
567extern void tsunami_setup_blockops(void);
568
569/* swift.S */
570extern void swift_flush_cache_all(void);
571extern void swift_flush_cache_mm(struct mm_struct *mm);
572extern void swift_flush_cache_range(struct vm_area_struct *vma,
573 unsigned long start, unsigned long end);
574extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
575extern void swift_flush_page_to_ram(unsigned long page);
576extern void swift_flush_page_for_dma(unsigned long page);
577extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
578extern void swift_flush_tlb_all(void);
579extern void swift_flush_tlb_mm(struct mm_struct *mm);
580extern void swift_flush_tlb_range(struct vm_area_struct *vma,
581 unsigned long start, unsigned long end);
582extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
583
584#if 0 /* P3: deadwood to debug precise flushes on Swift. */
585void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
586{
587 int cctx, ctx1;
588
589 page &= PAGE_MASK;
590 if ((ctx1 = vma->vm_mm->context) != -1) {
591 cctx = srmmu_get_context();
592/* Is context # ever different from current context? P3 */
593 if (cctx != ctx1) {
594 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
595 srmmu_set_context(ctx1);
596 swift_flush_page(page);
597 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
598 "r" (page), "i" (ASI_M_FLUSH_PROBE));
599 srmmu_set_context(cctx);
600 } else {
601 /* Rm. prot. bits from virt. c. */
602 /* swift_flush_cache_all(); */
603 /* swift_flush_cache_page(vma, page); */
604 swift_flush_page(page);
605
606 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
607 "r" (page), "i" (ASI_M_FLUSH_PROBE));
608 /* same as above: srmmu_flush_tlb_page() */
609 }
610 }
611}
612#endif
613
614/*
615 * The following are all MBUS based SRMMU modules, and therefore could
616 * be found in a multiprocessor configuration. On the whole, these
617 * chips seems to be much more touchy about DVMA and page tables
618 * with respect to cache coherency.
619 */
620
621/* viking.S */
622extern void viking_flush_cache_all(void);
623extern void viking_flush_cache_mm(struct mm_struct *mm);
624extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
625 unsigned long end);
626extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
627extern void viking_flush_page_to_ram(unsigned long page);
628extern void viking_flush_page_for_dma(unsigned long page);
629extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
630extern void viking_flush_page(unsigned long page);
631extern void viking_mxcc_flush_page(unsigned long page);
632extern void viking_flush_tlb_all(void);
633extern void viking_flush_tlb_mm(struct mm_struct *mm);
634extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
635 unsigned long end);
636extern void viking_flush_tlb_page(struct vm_area_struct *vma,
637 unsigned long page);
638extern void sun4dsmp_flush_tlb_all(void);
639extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
640extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
641 unsigned long end);
642extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
643 unsigned long page);
644
645/* hypersparc.S */
646extern void hypersparc_flush_cache_all(void);
647extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
648extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
649extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
650extern void hypersparc_flush_page_to_ram(unsigned long page);
651extern void hypersparc_flush_page_for_dma(unsigned long page);
652extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
653extern void hypersparc_flush_tlb_all(void);
654extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
655extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
656extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
657extern void hypersparc_setup_blockops(void);
658
659/*
660 * NOTE: All of this startup code assumes the low 16mb (approx.) of
661 * kernel mappings are done with one single contiguous chunk of
662 * ram. On small ram machines (classics mainly) we only get
663 * around 8mb mapped for us.
664 */
665
666static void __init early_pgtable_allocfail(char *type)
667{
668 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
669 prom_halt();
670}
671
672static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
673 unsigned long end)
674{
675 pgd_t *pgdp;
676 p4d_t *p4dp;
677 pud_t *pudp;
678 pmd_t *pmdp;
679 pte_t *ptep;
680
681 while (start < end) {
682 pgdp = pgd_offset_k(start);
683 p4dp = p4d_offset(pgdp, start);
684 pudp = pud_offset(p4dp, start);
685 if (pud_none(*__nocache_fix(pudp))) {
686 pmdp = __srmmu_get_nocache(
687 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
688 if (pmdp == NULL)
689 early_pgtable_allocfail("pmd");
690 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
691 pud_set(__nocache_fix(pudp), pmdp);
692 }
693 pmdp = pmd_offset(__nocache_fix(pudp), start);
694 if (srmmu_pmd_none(*__nocache_fix(pmdp))) {
695 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
696 if (ptep == NULL)
697 early_pgtable_allocfail("pte");
698 memset(__nocache_fix(ptep), 0, PTE_SIZE);
699 pmd_set(__nocache_fix(pmdp), ptep);
700 }
701 if (start > (0xffffffffUL - PMD_SIZE))
702 break;
703 start = (start + PMD_SIZE) & PMD_MASK;
704 }
705}
706
707static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
708 unsigned long end)
709{
710 pgd_t *pgdp;
711 p4d_t *p4dp;
712 pud_t *pudp;
713 pmd_t *pmdp;
714 pte_t *ptep;
715
716 while (start < end) {
717 pgdp = pgd_offset_k(start);
718 p4dp = p4d_offset(pgdp, start);
719 pudp = pud_offset(p4dp, start);
720 if (pud_none(*pudp)) {
721 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
722 if (pmdp == NULL)
723 early_pgtable_allocfail("pmd");
724 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
725 pud_set((pud_t *)pgdp, pmdp);
726 }
727 pmdp = pmd_offset(pudp, start);
728 if (srmmu_pmd_none(*pmdp)) {
729 ptep = __srmmu_get_nocache(PTE_SIZE,
730 PTE_SIZE);
731 if (ptep == NULL)
732 early_pgtable_allocfail("pte");
733 memset(ptep, 0, PTE_SIZE);
734 pmd_set(pmdp, ptep);
735 }
736 if (start > (0xffffffffUL - PMD_SIZE))
737 break;
738 start = (start + PMD_SIZE) & PMD_MASK;
739 }
740}
741
742/* These flush types are not available on all chips... */
743static inline unsigned long srmmu_probe(unsigned long vaddr)
744{
745 unsigned long retval;
746
747 if (sparc_cpu_model != sparc_leon) {
748
749 vaddr &= PAGE_MASK;
750 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
751 "=r" (retval) :
752 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
753 } else {
754 retval = leon_swprobe(vaddr, NULL);
755 }
756 return retval;
757}
758
759/*
760 * This is much cleaner than poking around physical address space
761 * looking at the prom's page table directly which is what most
762 * other OS's do. Yuck... this is much better.
763 */
764static void __init srmmu_inherit_prom_mappings(unsigned long start,
765 unsigned long end)
766{
767 unsigned long probed;
768 unsigned long addr;
769 pgd_t *pgdp;
770 p4d_t *p4dp;
771 pud_t *pudp;
772 pmd_t *pmdp;
773 pte_t *ptep;
774 int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
775
776 while (start <= end) {
777 if (start == 0)
778 break; /* probably wrap around */
779 if (start == 0xfef00000)
780 start = KADB_DEBUGGER_BEGVM;
781 probed = srmmu_probe(start);
782 if (!probed) {
783 /* continue probing until we find an entry */
784 start += PAGE_SIZE;
785 continue;
786 }
787
788 /* A red snapper, see what it really is. */
789 what = 0;
790 addr = start - PAGE_SIZE;
791
792 if (!(start & ~(PMD_MASK))) {
793 if (srmmu_probe(addr + PMD_SIZE) == probed)
794 what = 1;
795 }
796
797 if (!(start & ~(PGDIR_MASK))) {
798 if (srmmu_probe(addr + PGDIR_SIZE) == probed)
799 what = 2;
800 }
801
802 pgdp = pgd_offset_k(start);
803 p4dp = p4d_offset(pgdp, start);
804 pudp = pud_offset(p4dp, start);
805 if (what == 2) {
806 *__nocache_fix(pgdp) = __pgd(probed);
807 start += PGDIR_SIZE;
808 continue;
809 }
810 if (pud_none(*__nocache_fix(pudp))) {
811 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
812 SRMMU_PMD_TABLE_SIZE);
813 if (pmdp == NULL)
814 early_pgtable_allocfail("pmd");
815 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
816 pud_set(__nocache_fix(pudp), pmdp);
817 }
818 pmdp = pmd_offset(__nocache_fix(pudp), start);
819 if (what == 1) {
820 *(pmd_t *)__nocache_fix(pmdp) = __pmd(probed);
821 start += PMD_SIZE;
822 continue;
823 }
824 if (srmmu_pmd_none(*__nocache_fix(pmdp))) {
825 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
826 if (ptep == NULL)
827 early_pgtable_allocfail("pte");
828 memset(__nocache_fix(ptep), 0, PTE_SIZE);
829 pmd_set(__nocache_fix(pmdp), ptep);
830 }
831 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
832 *__nocache_fix(ptep) = __pte(probed);
833 start += PAGE_SIZE;
834 }
835}
836
837#define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
838
839/* Create a third-level SRMMU 16MB page mapping. */
840static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
841{
842 pgd_t *pgdp = pgd_offset_k(vaddr);
843 unsigned long big_pte;
844
845 big_pte = KERNEL_PTE(phys_base >> 4);
846 *__nocache_fix(pgdp) = __pgd(big_pte);
847}
848
849/* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
850static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
851{
852 unsigned long pstart = (sp_banks[sp_entry].base_addr & PGDIR_MASK);
853 unsigned long vstart = (vbase & PGDIR_MASK);
854 unsigned long vend = PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
855 /* Map "low" memory only */
856 const unsigned long min_vaddr = PAGE_OFFSET;
857 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
858
859 if (vstart < min_vaddr || vstart >= max_vaddr)
860 return vstart;
861
862 if (vend > max_vaddr || vend < min_vaddr)
863 vend = max_vaddr;
864
865 while (vstart < vend) {
866 do_large_mapping(vstart, pstart);
867 vstart += PGDIR_SIZE; pstart += PGDIR_SIZE;
868 }
869 return vstart;
870}
871
872static void __init map_kernel(void)
873{
874 int i;
875
876 if (phys_base > 0) {
877 do_large_mapping(PAGE_OFFSET, phys_base);
878 }
879
880 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
881 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
882 }
883}
884
885void (*poke_srmmu)(void) = NULL;
886
887void __init srmmu_paging_init(void)
888{
889 int i;
890 phandle cpunode;
891 char node_str[128];
892 pgd_t *pgd;
893 p4d_t *p4d;
894 pud_t *pud;
895 pmd_t *pmd;
896 pte_t *pte;
897 unsigned long pages_avail;
898
899 init_mm.context = (unsigned long) NO_CONTEXT;
900 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
901
902 if (sparc_cpu_model == sun4d)
903 num_contexts = 65536; /* We know it is Viking */
904 else {
905 /* Find the number of contexts on the srmmu. */
906 cpunode = prom_getchild(prom_root_node);
907 num_contexts = 0;
908 while (cpunode != 0) {
909 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
910 if (!strcmp(node_str, "cpu")) {
911 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
912 break;
913 }
914 cpunode = prom_getsibling(cpunode);
915 }
916 }
917
918 if (!num_contexts) {
919 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
920 prom_halt();
921 }
922
923 pages_avail = 0;
924 last_valid_pfn = bootmem_init(&pages_avail);
925
926 srmmu_nocache_calcsize();
927 srmmu_nocache_init();
928 srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
929 map_kernel();
930
931 /* ctx table has to be physically aligned to its size */
932 srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
933 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table);
934
935 for (i = 0; i < num_contexts; i++)
936 srmmu_ctxd_set(__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
937
938 flush_cache_all();
939 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
940#ifdef CONFIG_SMP
941 /* Stop from hanging here... */
942 local_ops->tlb_all();
943#else
944 flush_tlb_all();
945#endif
946 poke_srmmu();
947
948 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
949 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
950
951 srmmu_allocate_ptable_skeleton(
952 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
953 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
954
955 pgd = pgd_offset_k(PKMAP_BASE);
956 p4d = p4d_offset(pgd, PKMAP_BASE);
957 pud = pud_offset(p4d, PKMAP_BASE);
958 pmd = pmd_offset(pud, PKMAP_BASE);
959 pte = pte_offset_kernel(pmd, PKMAP_BASE);
960 pkmap_page_table = pte;
961
962 flush_cache_all();
963 flush_tlb_all();
964
965 sparc_context_init(num_contexts);
966
967 {
968 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
969
970 max_zone_pfn[ZONE_DMA] = max_low_pfn;
971 max_zone_pfn[ZONE_NORMAL] = max_low_pfn;
972 max_zone_pfn[ZONE_HIGHMEM] = highend_pfn;
973
974 free_area_init(max_zone_pfn);
975 }
976}
977
978void mmu_info(struct seq_file *m)
979{
980 seq_printf(m,
981 "MMU type\t: %s\n"
982 "contexts\t: %d\n"
983 "nocache total\t: %ld\n"
984 "nocache used\t: %d\n",
985 srmmu_name,
986 num_contexts,
987 srmmu_nocache_size,
988 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
989}
990
991int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
992{
993 mm->context = NO_CONTEXT;
994 return 0;
995}
996
997void destroy_context(struct mm_struct *mm)
998{
999 unsigned long flags;
1000
1001 if (mm->context != NO_CONTEXT) {
1002 flush_cache_mm(mm);
1003 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1004 flush_tlb_mm(mm);
1005 spin_lock_irqsave(&srmmu_context_spinlock, flags);
1006 free_context(mm->context);
1007 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1008 mm->context = NO_CONTEXT;
1009 }
1010}
1011
1012/* Init various srmmu chip types. */
1013static void __init srmmu_is_bad(void)
1014{
1015 prom_printf("Could not determine SRMMU chip type.\n");
1016 prom_halt();
1017}
1018
1019static void __init init_vac_layout(void)
1020{
1021 phandle nd;
1022 int cache_lines;
1023 char node_str[128];
1024#ifdef CONFIG_SMP
1025 int cpu = 0;
1026 unsigned long max_size = 0;
1027 unsigned long min_line_size = 0x10000000;
1028#endif
1029
1030 nd = prom_getchild(prom_root_node);
1031 while ((nd = prom_getsibling(nd)) != 0) {
1032 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1033 if (!strcmp(node_str, "cpu")) {
1034 vac_line_size = prom_getint(nd, "cache-line-size");
1035 if (vac_line_size == -1) {
1036 prom_printf("can't determine cache-line-size, halting.\n");
1037 prom_halt();
1038 }
1039 cache_lines = prom_getint(nd, "cache-nlines");
1040 if (cache_lines == -1) {
1041 prom_printf("can't determine cache-nlines, halting.\n");
1042 prom_halt();
1043 }
1044
1045 vac_cache_size = cache_lines * vac_line_size;
1046#ifdef CONFIG_SMP
1047 if (vac_cache_size > max_size)
1048 max_size = vac_cache_size;
1049 if (vac_line_size < min_line_size)
1050 min_line_size = vac_line_size;
1051 //FIXME: cpus not contiguous!!
1052 cpu++;
1053 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1054 break;
1055#else
1056 break;
1057#endif
1058 }
1059 }
1060 if (nd == 0) {
1061 prom_printf("No CPU nodes found, halting.\n");
1062 prom_halt();
1063 }
1064#ifdef CONFIG_SMP
1065 vac_cache_size = max_size;
1066 vac_line_size = min_line_size;
1067#endif
1068 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1069 (int)vac_cache_size, (int)vac_line_size);
1070}
1071
1072static void poke_hypersparc(void)
1073{
1074 volatile unsigned long clear;
1075 unsigned long mreg = srmmu_get_mmureg();
1076
1077 hyper_flush_unconditional_combined();
1078
1079 mreg &= ~(HYPERSPARC_CWENABLE);
1080 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1081 mreg |= (HYPERSPARC_CMODE);
1082
1083 srmmu_set_mmureg(mreg);
1084
1085#if 0 /* XXX I think this is bad news... -DaveM */
1086 hyper_clear_all_tags();
1087#endif
1088
1089 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1090 hyper_flush_whole_icache();
1091 clear = srmmu_get_faddr();
1092 clear = srmmu_get_fstatus();
1093}
1094
1095static const struct sparc32_cachetlb_ops hypersparc_ops = {
1096 .cache_all = hypersparc_flush_cache_all,
1097 .cache_mm = hypersparc_flush_cache_mm,
1098 .cache_page = hypersparc_flush_cache_page,
1099 .cache_range = hypersparc_flush_cache_range,
1100 .tlb_all = hypersparc_flush_tlb_all,
1101 .tlb_mm = hypersparc_flush_tlb_mm,
1102 .tlb_page = hypersparc_flush_tlb_page,
1103 .tlb_range = hypersparc_flush_tlb_range,
1104 .page_to_ram = hypersparc_flush_page_to_ram,
1105 .sig_insns = hypersparc_flush_sig_insns,
1106 .page_for_dma = hypersparc_flush_page_for_dma,
1107};
1108
1109static void __init init_hypersparc(void)
1110{
1111 srmmu_name = "ROSS HyperSparc";
1112 srmmu_modtype = HyperSparc;
1113
1114 init_vac_layout();
1115
1116 is_hypersparc = 1;
1117 sparc32_cachetlb_ops = &hypersparc_ops;
1118
1119 poke_srmmu = poke_hypersparc;
1120
1121 hypersparc_setup_blockops();
1122}
1123
1124static void poke_swift(void)
1125{
1126 unsigned long mreg;
1127
1128 /* Clear any crap from the cache or else... */
1129 swift_flush_cache_all();
1130
1131 /* Enable I & D caches */
1132 mreg = srmmu_get_mmureg();
1133 mreg |= (SWIFT_IE | SWIFT_DE);
1134 /*
1135 * The Swift branch folding logic is completely broken. At
1136 * trap time, if things are just right, if can mistakenly
1137 * think that a trap is coming from kernel mode when in fact
1138 * it is coming from user mode (it mis-executes the branch in
1139 * the trap code). So you see things like crashme completely
1140 * hosing your machine which is completely unacceptable. Turn
1141 * this shit off... nice job Fujitsu.
1142 */
1143 mreg &= ~(SWIFT_BF);
1144 srmmu_set_mmureg(mreg);
1145}
1146
1147static const struct sparc32_cachetlb_ops swift_ops = {
1148 .cache_all = swift_flush_cache_all,
1149 .cache_mm = swift_flush_cache_mm,
1150 .cache_page = swift_flush_cache_page,
1151 .cache_range = swift_flush_cache_range,
1152 .tlb_all = swift_flush_tlb_all,
1153 .tlb_mm = swift_flush_tlb_mm,
1154 .tlb_page = swift_flush_tlb_page,
1155 .tlb_range = swift_flush_tlb_range,
1156 .page_to_ram = swift_flush_page_to_ram,
1157 .sig_insns = swift_flush_sig_insns,
1158 .page_for_dma = swift_flush_page_for_dma,
1159};
1160
1161#define SWIFT_MASKID_ADDR 0x10003018
1162static void __init init_swift(void)
1163{
1164 unsigned long swift_rev;
1165
1166 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1167 "srl %0, 0x18, %0\n\t" :
1168 "=r" (swift_rev) :
1169 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1170 srmmu_name = "Fujitsu Swift";
1171 switch (swift_rev) {
1172 case 0x11:
1173 case 0x20:
1174 case 0x23:
1175 case 0x30:
1176 srmmu_modtype = Swift_lots_o_bugs;
1177 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1178 /*
1179 * Gee george, I wonder why Sun is so hush hush about
1180 * this hardware bug... really braindamage stuff going
1181 * on here. However I think we can find a way to avoid
1182 * all of the workaround overhead under Linux. Basically,
1183 * any page fault can cause kernel pages to become user
1184 * accessible (the mmu gets confused and clears some of
1185 * the ACC bits in kernel ptes). Aha, sounds pretty
1186 * horrible eh? But wait, after extensive testing it appears
1187 * that if you use pgd_t level large kernel pte's (like the
1188 * 4MB pages on the Pentium) the bug does not get tripped
1189 * at all. This avoids almost all of the major overhead.
1190 * Welcome to a world where your vendor tells you to,
1191 * "apply this kernel patch" instead of "sorry for the
1192 * broken hardware, send it back and we'll give you
1193 * properly functioning parts"
1194 */
1195 break;
1196 case 0x25:
1197 case 0x31:
1198 srmmu_modtype = Swift_bad_c;
1199 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1200 /*
1201 * You see Sun allude to this hardware bug but never
1202 * admit things directly, they'll say things like,
1203 * "the Swift chip cache problems" or similar.
1204 */
1205 break;
1206 default:
1207 srmmu_modtype = Swift_ok;
1208 break;
1209 }
1210
1211 sparc32_cachetlb_ops = &swift_ops;
1212 flush_page_for_dma_global = 0;
1213
1214 /*
1215 * Are you now convinced that the Swift is one of the
1216 * biggest VLSI abortions of all time? Bravo Fujitsu!
1217 * Fujitsu, the !#?!%$'d up processor people. I bet if
1218 * you examined the microcode of the Swift you'd find
1219 * XXX's all over the place.
1220 */
1221 poke_srmmu = poke_swift;
1222}
1223
1224static void turbosparc_flush_cache_all(void)
1225{
1226 flush_user_windows();
1227 turbosparc_idflash_clear();
1228}
1229
1230static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1231{
1232 FLUSH_BEGIN(mm)
1233 flush_user_windows();
1234 turbosparc_idflash_clear();
1235 FLUSH_END
1236}
1237
1238static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1239{
1240 FLUSH_BEGIN(vma->vm_mm)
1241 flush_user_windows();
1242 turbosparc_idflash_clear();
1243 FLUSH_END
1244}
1245
1246static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1247{
1248 FLUSH_BEGIN(vma->vm_mm)
1249 flush_user_windows();
1250 if (vma->vm_flags & VM_EXEC)
1251 turbosparc_flush_icache();
1252 turbosparc_flush_dcache();
1253 FLUSH_END
1254}
1255
1256/* TurboSparc is copy-back, if we turn it on, but this does not work. */
1257static void turbosparc_flush_page_to_ram(unsigned long page)
1258{
1259#ifdef TURBOSPARC_WRITEBACK
1260 volatile unsigned long clear;
1261
1262 if (srmmu_probe(page))
1263 turbosparc_flush_page_cache(page);
1264 clear = srmmu_get_fstatus();
1265#endif
1266}
1267
1268static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1269{
1270}
1271
1272static void turbosparc_flush_page_for_dma(unsigned long page)
1273{
1274 turbosparc_flush_dcache();
1275}
1276
1277static void turbosparc_flush_tlb_all(void)
1278{
1279 srmmu_flush_whole_tlb();
1280}
1281
1282static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1283{
1284 FLUSH_BEGIN(mm)
1285 srmmu_flush_whole_tlb();
1286 FLUSH_END
1287}
1288
1289static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1290{
1291 FLUSH_BEGIN(vma->vm_mm)
1292 srmmu_flush_whole_tlb();
1293 FLUSH_END
1294}
1295
1296static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1297{
1298 FLUSH_BEGIN(vma->vm_mm)
1299 srmmu_flush_whole_tlb();
1300 FLUSH_END
1301}
1302
1303
1304static void poke_turbosparc(void)
1305{
1306 unsigned long mreg = srmmu_get_mmureg();
1307 unsigned long ccreg;
1308
1309 /* Clear any crap from the cache or else... */
1310 turbosparc_flush_cache_all();
1311 /* Temporarily disable I & D caches */
1312 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1313 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1314 srmmu_set_mmureg(mreg);
1315
1316 ccreg = turbosparc_get_ccreg();
1317
1318#ifdef TURBOSPARC_WRITEBACK
1319 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1320 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1321 /* Write-back D-cache, emulate VLSI
1322 * abortion number three, not number one */
1323#else
1324 /* For now let's play safe, optimize later */
1325 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1326 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1327 ccreg &= ~(TURBOSPARC_uS2);
1328 /* Emulate VLSI abortion number three, not number one */
1329#endif
1330
1331 switch (ccreg & 7) {
1332 case 0: /* No SE cache */
1333 case 7: /* Test mode */
1334 break;
1335 default:
1336 ccreg |= (TURBOSPARC_SCENABLE);
1337 }
1338 turbosparc_set_ccreg(ccreg);
1339
1340 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1341 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1342 srmmu_set_mmureg(mreg);
1343}
1344
1345static const struct sparc32_cachetlb_ops turbosparc_ops = {
1346 .cache_all = turbosparc_flush_cache_all,
1347 .cache_mm = turbosparc_flush_cache_mm,
1348 .cache_page = turbosparc_flush_cache_page,
1349 .cache_range = turbosparc_flush_cache_range,
1350 .tlb_all = turbosparc_flush_tlb_all,
1351 .tlb_mm = turbosparc_flush_tlb_mm,
1352 .tlb_page = turbosparc_flush_tlb_page,
1353 .tlb_range = turbosparc_flush_tlb_range,
1354 .page_to_ram = turbosparc_flush_page_to_ram,
1355 .sig_insns = turbosparc_flush_sig_insns,
1356 .page_for_dma = turbosparc_flush_page_for_dma,
1357};
1358
1359static void __init init_turbosparc(void)
1360{
1361 srmmu_name = "Fujitsu TurboSparc";
1362 srmmu_modtype = TurboSparc;
1363 sparc32_cachetlb_ops = &turbosparc_ops;
1364 poke_srmmu = poke_turbosparc;
1365}
1366
1367static void poke_tsunami(void)
1368{
1369 unsigned long mreg = srmmu_get_mmureg();
1370
1371 tsunami_flush_icache();
1372 tsunami_flush_dcache();
1373 mreg &= ~TSUNAMI_ITD;
1374 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1375 srmmu_set_mmureg(mreg);
1376}
1377
1378static const struct sparc32_cachetlb_ops tsunami_ops = {
1379 .cache_all = tsunami_flush_cache_all,
1380 .cache_mm = tsunami_flush_cache_mm,
1381 .cache_page = tsunami_flush_cache_page,
1382 .cache_range = tsunami_flush_cache_range,
1383 .tlb_all = tsunami_flush_tlb_all,
1384 .tlb_mm = tsunami_flush_tlb_mm,
1385 .tlb_page = tsunami_flush_tlb_page,
1386 .tlb_range = tsunami_flush_tlb_range,
1387 .page_to_ram = tsunami_flush_page_to_ram,
1388 .sig_insns = tsunami_flush_sig_insns,
1389 .page_for_dma = tsunami_flush_page_for_dma,
1390};
1391
1392static void __init init_tsunami(void)
1393{
1394 /*
1395 * Tsunami's pretty sane, Sun and TI actually got it
1396 * somewhat right this time. Fujitsu should have
1397 * taken some lessons from them.
1398 */
1399
1400 srmmu_name = "TI Tsunami";
1401 srmmu_modtype = Tsunami;
1402 sparc32_cachetlb_ops = &tsunami_ops;
1403 poke_srmmu = poke_tsunami;
1404
1405 tsunami_setup_blockops();
1406}
1407
1408static void poke_viking(void)
1409{
1410 unsigned long mreg = srmmu_get_mmureg();
1411 static int smp_catch;
1412
1413 if (viking_mxcc_present) {
1414 unsigned long mxcc_control = mxcc_get_creg();
1415
1416 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1417 mxcc_control &= ~(MXCC_CTL_RRC);
1418 mxcc_set_creg(mxcc_control);
1419
1420 /*
1421 * We don't need memory parity checks.
1422 * XXX This is a mess, have to dig out later. ecd.
1423 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1424 */
1425
1426 /* We do cache ptables on MXCC. */
1427 mreg |= VIKING_TCENABLE;
1428 } else {
1429 unsigned long bpreg;
1430
1431 mreg &= ~(VIKING_TCENABLE);
1432 if (smp_catch++) {
1433 /* Must disable mixed-cmd mode here for other cpu's. */
1434 bpreg = viking_get_bpreg();
1435 bpreg &= ~(VIKING_ACTION_MIX);
1436 viking_set_bpreg(bpreg);
1437
1438 /* Just in case PROM does something funny. */
1439 msi_set_sync();
1440 }
1441 }
1442
1443 mreg |= VIKING_SPENABLE;
1444 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1445 mreg |= VIKING_SBENABLE;
1446 mreg &= ~(VIKING_ACENABLE);
1447 srmmu_set_mmureg(mreg);
1448}
1449
1450static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
1451 .cache_all = viking_flush_cache_all,
1452 .cache_mm = viking_flush_cache_mm,
1453 .cache_page = viking_flush_cache_page,
1454 .cache_range = viking_flush_cache_range,
1455 .tlb_all = viking_flush_tlb_all,
1456 .tlb_mm = viking_flush_tlb_mm,
1457 .tlb_page = viking_flush_tlb_page,
1458 .tlb_range = viking_flush_tlb_range,
1459 .page_to_ram = viking_flush_page_to_ram,
1460 .sig_insns = viking_flush_sig_insns,
1461 .page_for_dma = viking_flush_page_for_dma,
1462};
1463
1464#ifdef CONFIG_SMP
1465/* On sun4d the cpu broadcasts local TLB flushes, so we can just
1466 * perform the local TLB flush and all the other cpus will see it.
1467 * But, unfortunately, there is a bug in the sun4d XBUS backplane
1468 * that requires that we add some synchronization to these flushes.
1469 *
1470 * The bug is that the fifo which keeps track of all the pending TLB
1471 * broadcasts in the system is an entry or two too small, so if we
1472 * have too many going at once we'll overflow that fifo and lose a TLB
1473 * flush resulting in corruption.
1474 *
1475 * Our workaround is to take a global spinlock around the TLB flushes,
1476 * which guarentees we won't ever have too many pending. It's a big
1477 * hammer, but a semaphore like system to make sure we only have N TLB
1478 * flushes going at once will require SMP locking anyways so there's
1479 * no real value in trying any harder than this.
1480 */
1481static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
1482 .cache_all = viking_flush_cache_all,
1483 .cache_mm = viking_flush_cache_mm,
1484 .cache_page = viking_flush_cache_page,
1485 .cache_range = viking_flush_cache_range,
1486 .tlb_all = sun4dsmp_flush_tlb_all,
1487 .tlb_mm = sun4dsmp_flush_tlb_mm,
1488 .tlb_page = sun4dsmp_flush_tlb_page,
1489 .tlb_range = sun4dsmp_flush_tlb_range,
1490 .page_to_ram = viking_flush_page_to_ram,
1491 .sig_insns = viking_flush_sig_insns,
1492 .page_for_dma = viking_flush_page_for_dma,
1493};
1494#endif
1495
1496static void __init init_viking(void)
1497{
1498 unsigned long mreg = srmmu_get_mmureg();
1499
1500 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1501 if (mreg & VIKING_MMODE) {
1502 srmmu_name = "TI Viking";
1503 viking_mxcc_present = 0;
1504 msi_set_sync();
1505
1506 /*
1507 * We need this to make sure old viking takes no hits
1508 * on its cache for dma snoops to workaround the
1509 * "load from non-cacheable memory" interrupt bug.
1510 * This is only necessary because of the new way in
1511 * which we use the IOMMU.
1512 */
1513 viking_ops.page_for_dma = viking_flush_page;
1514#ifdef CONFIG_SMP
1515 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1516#endif
1517 flush_page_for_dma_global = 0;
1518 } else {
1519 srmmu_name = "TI Viking/MXCC";
1520 viking_mxcc_present = 1;
1521 srmmu_cache_pagetables = 1;
1522 }
1523
1524 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1525 &viking_ops;
1526#ifdef CONFIG_SMP
1527 if (sparc_cpu_model == sun4d)
1528 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1529 &viking_sun4d_smp_ops;
1530#endif
1531
1532 poke_srmmu = poke_viking;
1533}
1534
1535/* Probe for the srmmu chip version. */
1536static void __init get_srmmu_type(void)
1537{
1538 unsigned long mreg, psr;
1539 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1540
1541 srmmu_modtype = SRMMU_INVAL_MOD;
1542 hwbug_bitmask = 0;
1543
1544 mreg = srmmu_get_mmureg(); psr = get_psr();
1545 mod_typ = (mreg & 0xf0000000) >> 28;
1546 mod_rev = (mreg & 0x0f000000) >> 24;
1547 psr_typ = (psr >> 28) & 0xf;
1548 psr_vers = (psr >> 24) & 0xf;
1549
1550 /* First, check for sparc-leon. */
1551 if (sparc_cpu_model == sparc_leon) {
1552 init_leon();
1553 return;
1554 }
1555
1556 /* Second, check for HyperSparc or Cypress. */
1557 if (mod_typ == 1) {
1558 switch (mod_rev) {
1559 case 7:
1560 /* UP or MP Hypersparc */
1561 init_hypersparc();
1562 break;
1563 case 0:
1564 case 2:
1565 case 10:
1566 case 11:
1567 case 12:
1568 case 13:
1569 case 14:
1570 case 15:
1571 default:
1572 prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1573 prom_halt();
1574 break;
1575 }
1576 return;
1577 }
1578
1579 /* Now Fujitsu TurboSparc. It might happen that it is
1580 * in Swift emulation mode, so we will check later...
1581 */
1582 if (psr_typ == 0 && psr_vers == 5) {
1583 init_turbosparc();
1584 return;
1585 }
1586
1587 /* Next check for Fujitsu Swift. */
1588 if (psr_typ == 0 && psr_vers == 4) {
1589 phandle cpunode;
1590 char node_str[128];
1591
1592 /* Look if it is not a TurboSparc emulating Swift... */
1593 cpunode = prom_getchild(prom_root_node);
1594 while ((cpunode = prom_getsibling(cpunode)) != 0) {
1595 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1596 if (!strcmp(node_str, "cpu")) {
1597 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1598 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1599 init_turbosparc();
1600 return;
1601 }
1602 break;
1603 }
1604 }
1605
1606 init_swift();
1607 return;
1608 }
1609
1610 /* Now the Viking family of srmmu. */
1611 if (psr_typ == 4 &&
1612 ((psr_vers == 0) ||
1613 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1614 init_viking();
1615 return;
1616 }
1617
1618 /* Finally the Tsunami. */
1619 if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1620 init_tsunami();
1621 return;
1622 }
1623
1624 /* Oh well */
1625 srmmu_is_bad();
1626}
1627
1628#ifdef CONFIG_SMP
1629/* Local cross-calls. */
1630static void smp_flush_page_for_dma(unsigned long page)
1631{
1632 xc1(local_ops->page_for_dma, page);
1633 local_ops->page_for_dma(page);
1634}
1635
1636static void smp_flush_cache_all(void)
1637{
1638 xc0(local_ops->cache_all);
1639 local_ops->cache_all();
1640}
1641
1642static void smp_flush_tlb_all(void)
1643{
1644 xc0(local_ops->tlb_all);
1645 local_ops->tlb_all();
1646}
1647
1648static bool any_other_mm_cpus(struct mm_struct *mm)
1649{
1650 return cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids;
1651}
1652
1653static void smp_flush_cache_mm(struct mm_struct *mm)
1654{
1655 if (mm->context != NO_CONTEXT) {
1656 if (any_other_mm_cpus(mm))
1657 xc1(local_ops->cache_mm, (unsigned long)mm);
1658 local_ops->cache_mm(mm);
1659 }
1660}
1661
1662static void smp_flush_tlb_mm(struct mm_struct *mm)
1663{
1664 if (mm->context != NO_CONTEXT) {
1665 if (any_other_mm_cpus(mm)) {
1666 xc1(local_ops->tlb_mm, (unsigned long)mm);
1667 if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1668 cpumask_copy(mm_cpumask(mm),
1669 cpumask_of(smp_processor_id()));
1670 }
1671 local_ops->tlb_mm(mm);
1672 }
1673}
1674
1675static void smp_flush_cache_range(struct vm_area_struct *vma,
1676 unsigned long start,
1677 unsigned long end)
1678{
1679 struct mm_struct *mm = vma->vm_mm;
1680
1681 if (mm->context != NO_CONTEXT) {
1682 if (any_other_mm_cpus(mm))
1683 xc3(local_ops->cache_range, (unsigned long)vma, start,
1684 end);
1685 local_ops->cache_range(vma, start, end);
1686 }
1687}
1688
1689static void smp_flush_tlb_range(struct vm_area_struct *vma,
1690 unsigned long start,
1691 unsigned long end)
1692{
1693 struct mm_struct *mm = vma->vm_mm;
1694
1695 if (mm->context != NO_CONTEXT) {
1696 if (any_other_mm_cpus(mm))
1697 xc3(local_ops->tlb_range, (unsigned long)vma, start,
1698 end);
1699 local_ops->tlb_range(vma, start, end);
1700 }
1701}
1702
1703static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1704{
1705 struct mm_struct *mm = vma->vm_mm;
1706
1707 if (mm->context != NO_CONTEXT) {
1708 if (any_other_mm_cpus(mm))
1709 xc2(local_ops->cache_page, (unsigned long)vma, page);
1710 local_ops->cache_page(vma, page);
1711 }
1712}
1713
1714static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1715{
1716 struct mm_struct *mm = vma->vm_mm;
1717
1718 if (mm->context != NO_CONTEXT) {
1719 if (any_other_mm_cpus(mm))
1720 xc2(local_ops->tlb_page, (unsigned long)vma, page);
1721 local_ops->tlb_page(vma, page);
1722 }
1723}
1724
1725static void smp_flush_page_to_ram(unsigned long page)
1726{
1727 /* Current theory is that those who call this are the one's
1728 * who have just dirtied their cache with the pages contents
1729 * in kernel space, therefore we only run this on local cpu.
1730 *
1731 * XXX This experiment failed, research further... -DaveM
1732 */
1733#if 1
1734 xc1(local_ops->page_to_ram, page);
1735#endif
1736 local_ops->page_to_ram(page);
1737}
1738
1739static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1740{
1741 if (any_other_mm_cpus(mm))
1742 xc2(local_ops->sig_insns, (unsigned long)mm, insn_addr);
1743 local_ops->sig_insns(mm, insn_addr);
1744}
1745
1746static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
1747 .cache_all = smp_flush_cache_all,
1748 .cache_mm = smp_flush_cache_mm,
1749 .cache_page = smp_flush_cache_page,
1750 .cache_range = smp_flush_cache_range,
1751 .tlb_all = smp_flush_tlb_all,
1752 .tlb_mm = smp_flush_tlb_mm,
1753 .tlb_page = smp_flush_tlb_page,
1754 .tlb_range = smp_flush_tlb_range,
1755 .page_to_ram = smp_flush_page_to_ram,
1756 .sig_insns = smp_flush_sig_insns,
1757 .page_for_dma = smp_flush_page_for_dma,
1758};
1759#endif
1760
1761/* Load up routines and constants for sun4m and sun4d mmu */
1762void __init load_mmu(void)
1763{
1764 /* Functions */
1765 get_srmmu_type();
1766
1767#ifdef CONFIG_SMP
1768 /* El switcheroo... */
1769 local_ops = sparc32_cachetlb_ops;
1770
1771 if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1772 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1773 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1774 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1775 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1776 }
1777
1778 if (poke_srmmu == poke_viking) {
1779 /* Avoid unnecessary cross calls. */
1780 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1781 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1782 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1783 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1784
1785 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1786 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1787 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1788 }
1789
1790 /* It really is const after this point. */
1791 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1792 &smp_cachetlb_ops;
1793#endif
1794
1795 if (sparc_cpu_model != sun4d)
1796 ld_mmu_iommu();
1797#ifdef CONFIG_SMP
1798 if (sparc_cpu_model == sun4d)
1799 sun4d_init_smp();
1800 else if (sparc_cpu_model == sparc_leon)
1801 leon_init_smp();
1802 else
1803 sun4m_init_smp();
1804#endif
1805}
Linux 6.x block layer and io_uring tree(s)