| 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (C) 2005-2008, PA Semi, Inc |
| 4 | * |
| 5 | * Maintained by: Olof Johansson <olof@lixom.net> |
| 6 | */ |
| 7 | |
| 8 | #undef DEBUG |
| 9 | |
| 10 | #include <linux/memblock.h> |
| 11 | #include <linux/types.h> |
| 12 | #include <linux/spinlock.h> |
| 13 | #include <linux/pci.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <asm/iommu.h> |
| 16 | #include <asm/machdep.h> |
| 17 | #include <asm/firmware.h> |
| 18 | |
| 19 | #include "pasemi.h" |
| 20 | |
| 21 | #define IOBMAP_PAGE_SHIFT 12 |
| 22 | #define IOBMAP_PAGE_SIZE (1 << IOBMAP_PAGE_SHIFT) |
| 23 | #define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1) |
| 24 | |
| 25 | #define IOB_BASE 0xe0000000 |
| 26 | #define IOB_SIZE 0x3000 |
| 27 | /* Configuration registers */ |
| 28 | #define IOBCAP_REG 0x40 |
| 29 | #define IOBCOM_REG 0x100 |
| 30 | /* Enable IOB address translation */ |
| 31 | #define IOBCOM_ATEN 0x00000100 |
| 32 | |
| 33 | /* Address decode configuration register */ |
| 34 | #define IOB_AD_REG 0x14c |
| 35 | /* IOBCOM_AD_REG fields */ |
| 36 | #define IOB_AD_VGPRT 0x00000e00 |
| 37 | #define IOB_AD_VGAEN 0x00000100 |
| 38 | /* Direct mapping settings */ |
| 39 | #define IOB_AD_MPSEL_MASK 0x00000030 |
| 40 | #define IOB_AD_MPSEL_B38 0x00000000 |
| 41 | #define IOB_AD_MPSEL_B40 0x00000010 |
| 42 | #define IOB_AD_MPSEL_B42 0x00000020 |
| 43 | /* Translation window size / enable */ |
| 44 | #define IOB_AD_TRNG_MASK 0x00000003 |
| 45 | #define IOB_AD_TRNG_256M 0x00000000 |
| 46 | #define IOB_AD_TRNG_2G 0x00000001 |
| 47 | #define IOB_AD_TRNG_128G 0x00000003 |
| 48 | |
| 49 | #define IOB_TABLEBASE_REG 0x154 |
| 50 | |
| 51 | /* Base of the 64 4-byte L1 registers */ |
| 52 | #define IOB_XLT_L1_REGBASE 0x2b00 |
| 53 | |
| 54 | /* Register to invalidate TLB entries */ |
| 55 | #define IOB_AT_INVAL_TLB_REG 0x2d00 |
| 56 | |
| 57 | /* The top two bits of the level 1 entry contains valid and type flags */ |
| 58 | #define IOBMAP_L1E_V 0x40000000 |
| 59 | #define IOBMAP_L1E_V_B 0x80000000 |
| 60 | |
| 61 | /* For big page entries, the bottom two bits contains flags */ |
| 62 | #define IOBMAP_L1E_BIG_CACHED 0x00000002 |
| 63 | #define IOBMAP_L1E_BIG_PRIORITY 0x00000001 |
| 64 | |
| 65 | /* For regular level 2 entries, top 2 bits contain valid and cache flags */ |
| 66 | #define IOBMAP_L2E_V 0x80000000 |
| 67 | #define IOBMAP_L2E_V_CACHED 0xc0000000 |
| 68 | |
| 69 | static void __iomem *iob; |
| 70 | static u32 iob_l1_emptyval; |
| 71 | static u32 iob_l2_emptyval; |
| 72 | static u32 *iob_l2_base; |
| 73 | |
| 74 | static struct iommu_table iommu_table_iobmap; |
| 75 | static int iommu_table_iobmap_inited; |
| 76 | |
| 77 | static int iobmap_build(struct iommu_table *tbl, long index, |
| 78 | long npages, unsigned long uaddr, |
| 79 | enum dma_data_direction direction, |
| 80 | unsigned long attrs) |
| 81 | { |
| 82 | u32 *ip; |
| 83 | u32 rpn; |
| 84 | unsigned long bus_addr; |
| 85 | |
| 86 | pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr); |
| 87 | |
| 88 | bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT; |
| 89 | |
| 90 | ip = ((u32 *)tbl->it_base) + index; |
| 91 | |
| 92 | while (npages--) { |
| 93 | rpn = __pa(uaddr) >> IOBMAP_PAGE_SHIFT; |
| 94 | |
| 95 | *(ip++) = IOBMAP_L2E_V | rpn; |
| 96 | /* invalidate tlb, can be optimized more */ |
| 97 | out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14); |
| 98 | |
| 99 | uaddr += IOBMAP_PAGE_SIZE; |
| 100 | bus_addr += IOBMAP_PAGE_SIZE; |
| 101 | } |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | |
| 106 | static void iobmap_free(struct iommu_table *tbl, long index, |
| 107 | long npages) |
| 108 | { |
| 109 | u32 *ip; |
| 110 | unsigned long bus_addr; |
| 111 | |
| 112 | pr_debug("iobmap: free at: %lx, %lx\n", index, npages); |
| 113 | |
| 114 | bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT; |
| 115 | |
| 116 | ip = ((u32 *)tbl->it_base) + index; |
| 117 | |
| 118 | while (npages--) { |
| 119 | *(ip++) = iob_l2_emptyval; |
| 120 | /* invalidate tlb, can be optimized more */ |
| 121 | out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14); |
| 122 | bus_addr += IOBMAP_PAGE_SIZE; |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | static struct iommu_table_ops iommu_table_iobmap_ops = { |
| 127 | .set = iobmap_build, |
| 128 | .clear = iobmap_free |
| 129 | }; |
| 130 | |
| 131 | static void iommu_table_iobmap_setup(void) |
| 132 | { |
| 133 | pr_debug(" -> %s\n", __func__); |
| 134 | iommu_table_iobmap.it_busno = 0; |
| 135 | iommu_table_iobmap.it_offset = 0; |
| 136 | iommu_table_iobmap.it_page_shift = IOBMAP_PAGE_SHIFT; |
| 137 | |
| 138 | /* it_size is in number of entries */ |
| 139 | iommu_table_iobmap.it_size = |
| 140 | 0x80000000 >> iommu_table_iobmap.it_page_shift; |
| 141 | |
| 142 | /* Initialize the common IOMMU code */ |
| 143 | iommu_table_iobmap.it_base = (unsigned long)iob_l2_base; |
| 144 | iommu_table_iobmap.it_index = 0; |
| 145 | /* XXXOJN tune this to avoid IOB cache invals. |
| 146 | * Should probably be 8 (64 bytes) |
| 147 | */ |
| 148 | iommu_table_iobmap.it_blocksize = 4; |
| 149 | iommu_table_iobmap.it_ops = &iommu_table_iobmap_ops; |
| 150 | if (!iommu_init_table(&iommu_table_iobmap, 0, 0, 0)) |
| 151 | panic("Failed to initialize iommu table"); |
| 152 | |
| 153 | pr_debug(" <- %s\n", __func__); |
| 154 | } |
| 155 | |
| 156 | |
| 157 | |
| 158 | static void pci_dma_bus_setup_pasemi(struct pci_bus *bus) |
| 159 | { |
| 160 | pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self); |
| 161 | |
| 162 | if (!iommu_table_iobmap_inited) { |
| 163 | iommu_table_iobmap_inited = 1; |
| 164 | iommu_table_iobmap_setup(); |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | |
| 169 | static void pci_dma_dev_setup_pasemi(struct pci_dev *dev) |
| 170 | { |
| 171 | pr_debug("pci_dma_dev_setup, dev %p (%s)\n", dev, pci_name(dev)); |
| 172 | |
| 173 | #if !defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) |
| 174 | /* For non-LPAR environment, don't translate anything for the DMA |
| 175 | * engine. The exception to this is if the user has enabled |
| 176 | * CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE at build time. |
| 177 | */ |
| 178 | if (dev->vendor == 0x1959 && dev->device == 0xa007 && |
| 179 | !firmware_has_feature(FW_FEATURE_LPAR)) { |
| 180 | dev->dev.dma_ops = NULL; |
| 181 | /* |
| 182 | * Set the coherent DMA mask to prevent the iommu |
| 183 | * being used unnecessarily |
| 184 | */ |
| 185 | dev->dev.coherent_dma_mask = DMA_BIT_MASK(44); |
| 186 | return; |
| 187 | } |
| 188 | #endif |
| 189 | |
| 190 | set_iommu_table_base(&dev->dev, &iommu_table_iobmap); |
| 191 | } |
| 192 | |
| 193 | static int __init iob_init(struct device_node *dn) |
| 194 | { |
| 195 | unsigned long tmp; |
| 196 | u32 regword; |
| 197 | int i; |
| 198 | |
| 199 | pr_debug(" -> %s\n", __func__); |
| 200 | |
| 201 | /* For 2G space, 8x64 pages (2^21 bytes) is max total l2 size */ |
| 202 | iob_l2_base = memblock_alloc_try_nid_raw(1UL << 21, 1UL << 21, |
| 203 | MEMBLOCK_LOW_LIMIT, 0x80000000, |
| 204 | NUMA_NO_NODE); |
| 205 | if (!iob_l2_base) |
| 206 | panic("%s: Failed to allocate %lu bytes align=0x%lx max_addr=%x\n", |
| 207 | __func__, 1UL << 21, 1UL << 21, 0x80000000); |
| 208 | |
| 209 | pr_info("IOBMAP L2 allocated at: %p\n", iob_l2_base); |
| 210 | |
| 211 | /* Allocate a spare page to map all invalid IOTLB pages. */ |
| 212 | tmp = memblock_phys_alloc(IOBMAP_PAGE_SIZE, IOBMAP_PAGE_SIZE); |
| 213 | if (!tmp) |
| 214 | panic("IOBMAP: Cannot allocate spare page!"); |
| 215 | /* Empty l1 is marked invalid */ |
| 216 | iob_l1_emptyval = 0; |
| 217 | /* Empty l2 is mapped to dummy page */ |
| 218 | iob_l2_emptyval = IOBMAP_L2E_V | (tmp >> IOBMAP_PAGE_SHIFT); |
| 219 | |
| 220 | iob = ioremap(IOB_BASE, IOB_SIZE); |
| 221 | if (!iob) |
| 222 | panic("IOBMAP: Cannot map registers!"); |
| 223 | |
| 224 | /* setup direct mapping of the L1 entries */ |
| 225 | for (i = 0; i < 64; i++) { |
| 226 | /* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */ |
| 227 | regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12); |
| 228 | out_le32(iob+IOB_XLT_L1_REGBASE+i*4, regword); |
| 229 | } |
| 230 | |
| 231 | /* set 2GB translation window, based at 0 */ |
| 232 | regword = in_le32(iob+IOB_AD_REG); |
| 233 | regword &= ~IOB_AD_TRNG_MASK; |
| 234 | regword |= IOB_AD_TRNG_2G; |
| 235 | out_le32(iob+IOB_AD_REG, regword); |
| 236 | |
| 237 | /* Enable translation */ |
| 238 | regword = in_le32(iob+IOBCOM_REG); |
| 239 | regword |= IOBCOM_ATEN; |
| 240 | out_le32(iob+IOBCOM_REG, regword); |
| 241 | |
| 242 | pr_debug(" <- %s\n", __func__); |
| 243 | |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | |
| 248 | /* These are called very early. */ |
| 249 | void __init iommu_init_early_pasemi(void) |
| 250 | { |
| 251 | int iommu_off; |
| 252 | |
| 253 | #ifndef CONFIG_PPC_PASEMI_IOMMU |
| 254 | iommu_off = 1; |
| 255 | #else |
| 256 | iommu_off = of_chosen && |
| 257 | of_property_read_bool(of_chosen, "linux,iommu-off"); |
| 258 | #endif |
| 259 | if (iommu_off) |
| 260 | return; |
| 261 | |
| 262 | iob_init(NULL); |
| 263 | |
| 264 | pasemi_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pasemi; |
| 265 | pasemi_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pasemi; |
| 266 | set_pci_dma_ops(&dma_iommu_ops); |
| 267 | } |