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powerpc: Remove extra zeros from 32 bit CPU features definitions
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
... / ...
CommitLineData
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4
5#include <asm/asm-compat.h>
6#include <asm/feature-fixups.h>
7#include <uapi/asm/cputable.h>
8
9#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
15
16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
17typedef void (*cpu_restore_t)(void);
18
19enum powerpc_oprofile_type {
20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
24 PPC_OPROFILE_FSL_EMB = 4,
25 PPC_OPROFILE_CELL = 5,
26 PPC_OPROFILE_PA6T = 6,
27};
28
29enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
33 PPC_PMC_G4 = 3,
34};
35
36struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
41extern int machine_check_e500mc(struct pt_regs *regs);
42extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
44extern int machine_check_47x(struct pt_regs *regs);
45
46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
47struct cpu_spec {
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
51
52 char *cpu_name;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
55 unsigned int mmu_features; /* MMU features */
56
57 /* cache line sizes */
58 unsigned int icache_bsize;
59 unsigned int dcache_bsize;
60
61 /* number of performance monitor counters */
62 unsigned int num_pmcs;
63 enum powerpc_pmc_type pmc_type;
64
65 /* this is called to initialize various CPU bits like L1 cache,
66 * BHT, SPD, etc... from head.S before branching to identify_machine
67 */
68 cpu_setup_t cpu_setup;
69 /* Used to restore cpu setup on secondary processors and at resume */
70 cpu_restore_t cpu_restore;
71
72 /* Used by oprofile userspace to select the right counters */
73 char *oprofile_cpu_type;
74
75 /* Processor specific oprofile operations */
76 enum powerpc_oprofile_type oprofile_type;
77
78 /* Bit locations inside the mmcra change */
79 unsigned long oprofile_mmcra_sihv;
80 unsigned long oprofile_mmcra_sipr;
81
82 /* Bits to clear during an oprofile exception */
83 unsigned long oprofile_mmcra_clear;
84
85 /* Name of processor class, for the ELF AT_PLATFORM entry */
86 char *platform;
87
88 /* Processor specific machine check handling. Return negative
89 * if the error is fatal, 1 if it was fully recovered and 0 to
90 * pass up (not CPU originated) */
91 int (*machine_check)(struct pt_regs *regs);
92};
93
94extern struct cpu_spec *cur_cpu_spec;
95
96extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
97
98extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
99extern void do_feature_fixups(unsigned long value, void *fixup_start,
100 void *fixup_end);
101
102extern const char *powerpc_base_platform;
103
104#endif /* __ASSEMBLY__ */
105
106/* CPU kernel features */
107
108/* Retain the 32b definitions all use bottom half of word */
109#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
110#define CPU_FTR_L2CR ASM_CONST(0x00000002)
111#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
112#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
113#define CPU_FTR_TAU ASM_CONST(0x00000010)
114#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
115#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
116#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
117#define CPU_FTR_601 ASM_CONST(0x00000100)
118#define CPU_FTR_DBELL ASM_CONST(0x00000200)
119#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
120#define CPU_FTR_L3CR ASM_CONST(0x00000800)
121#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
122#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
123#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
124#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
125#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
126#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
127#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
128#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
129#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
130#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
131#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
132#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
133#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
134#define CPU_FTR_SPE ASM_CONST(0x02000000)
135#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
136#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
137#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
138#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
139#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
140
141/*
142 * Add the 64-bit processor unique features in the top half of the word;
143 * on 32-bit, make the names available but defined to be 0.
144 */
145#ifdef __powerpc64__
146#define LONG_ASM_CONST(x) ASM_CONST(x)
147#else
148#define LONG_ASM_CONST(x) 0
149#endif
150
151#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000200000000)
152#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000400000000)
153#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000800000000)
154#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000001000000000)
155#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
156#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
157#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
158#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
159#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
160#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
161#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
162#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
163#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
164#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
165#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
166#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
167#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
168#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
169#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
170#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
171#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
172#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
173#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000)
174#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x4000000000000000)
175
176#ifndef __ASSEMBLY__
177
178#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
179
180#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
181 MMU_FTR_16M_PAGE)
182
183/* We only set the altivec features if the kernel was compiled with altivec
184 * support
185 */
186#ifdef CONFIG_ALTIVEC
187#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
188#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
189#else
190#define CPU_FTR_ALTIVEC_COMP 0
191#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
192#endif
193
194/* We only set the VSX features if the kernel was compiled with VSX
195 * support
196 */
197#ifdef CONFIG_VSX
198#define CPU_FTR_VSX_COMP CPU_FTR_VSX
199#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
200#else
201#define CPU_FTR_VSX_COMP 0
202#define PPC_FEATURE_HAS_VSX_COMP 0
203#endif
204
205/* We only set the spe features if the kernel was compiled with spe
206 * support
207 */
208#ifdef CONFIG_SPE
209#define CPU_FTR_SPE_COMP CPU_FTR_SPE
210#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
211#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
212#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
213#else
214#define CPU_FTR_SPE_COMP 0
215#define PPC_FEATURE_HAS_SPE_COMP 0
216#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
217#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
218#endif
219
220/* We need to mark all pages as being coherent if we're SMP or we have a
221 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
222 * require it for PCI "streaming/prefetch" to work properly.
223 * This is also required by 52xx family.
224 */
225#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
226 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
227 || defined(CONFIG_PPC_MPC52xx)
228#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
229#else
230#define CPU_FTR_COMMON 0
231#endif
232
233/* The powersave features NAP & DOZE seems to confuse BDI when
234 debugging. So if a BDI is used, disable theses
235 */
236#ifndef CONFIG_BDI_SWITCH
237#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
238#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
239#else
240#define CPU_FTR_MAYBE_CAN_DOZE 0
241#define CPU_FTR_MAYBE_CAN_NAP 0
242#endif
243
244#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
245 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
246 !defined(CONFIG_BOOKE))
247
248#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
249 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
250#define CPU_FTRS_603 (CPU_FTR_COMMON | \
251 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
252 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
253#define CPU_FTRS_604 (CPU_FTR_COMMON | \
254 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
255#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
256 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
257 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
258#define CPU_FTRS_740 (CPU_FTR_COMMON | \
259 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
260 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
261 CPU_FTR_PPC_LE)
262#define CPU_FTRS_750 (CPU_FTR_COMMON | \
263 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
264 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
265 CPU_FTR_PPC_LE)
266#define CPU_FTRS_750CL (CPU_FTRS_750)
267#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
268#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
269#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
270#define CPU_FTRS_750GX (CPU_FTRS_750FX)
271#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
272 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
273 CPU_FTR_ALTIVEC_COMP | \
274 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
275#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
276 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
277 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
278 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
279#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
280 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
281 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
282 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
283#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
284 CPU_FTR_USE_TB | \
285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
286 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
287 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
288 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
289#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
290 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
291 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
292 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
293 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
294#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
295 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
296 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
297 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
298#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
299 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
301 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
302 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
303 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
304#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
305 CPU_FTR_USE_TB | \
306 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
307 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
308 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
309#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
310 CPU_FTR_USE_TB | \
311 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
312 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
313 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
314 CPU_FTR_NEED_PAIRED_STWCX)
315#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
316 CPU_FTR_USE_TB | \
317 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
318 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
319 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
320#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
321 CPU_FTR_USE_TB | \
322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
323 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
324 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
325#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
326 CPU_FTR_USE_TB | \
327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
328 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
329 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
330#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
331 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
332#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
333 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
334#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
335 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
336 CPU_FTR_COMMON)
337#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
338 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
339 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
340#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
341#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
342#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
343#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
344#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
345 CPU_FTR_INDEXED_DCR)
346#define CPU_FTRS_47X (CPU_FTRS_440x6)
347#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
348 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
349 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
350 CPU_FTR_DEBUG_LVL_EXC)
351#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
352 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
353 CPU_FTR_NOEXECUTE)
354#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
355 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
356 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
357#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
358 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
359 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
360#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
361 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
362 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
363 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
364#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
365 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
366 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
367 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
368#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
369
370/* 64-bit CPUs */
371#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
372 CPU_FTR_IABR | CPU_FTR_PPC_LE)
373#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
374 CPU_FTR_IABR | \
375 CPU_FTR_MMCRA | CPU_FTR_CTRL)
376#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
377 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
378 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
379 CPU_FTR_STCX_CHECKS_ADDRESS)
380#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
381 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
382 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
383 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
384 CPU_FTR_HVMODE)
385#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
386 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
387 CPU_FTR_MMCRA | CPU_FTR_SMT | \
388 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
389 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
390#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
391 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
392 CPU_FTR_MMCRA | CPU_FTR_SMT | \
393 CPU_FTR_COHERENT_ICACHE | \
394 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
395 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
396 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
397#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
398 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
399 CPU_FTR_MMCRA | CPU_FTR_SMT | \
400 CPU_FTR_COHERENT_ICACHE | \
401 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
402 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
403 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
404 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
405 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
406#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
407 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
408 CPU_FTR_MMCRA | CPU_FTR_SMT | \
409 CPU_FTR_COHERENT_ICACHE | \
410 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
411 CPU_FTR_DSCR | CPU_FTR_SAO | \
412 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
413 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
414 CPU_FTR_DBELL | CPU_FTR_HAS_PPR)
415#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
416 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
418 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
419 CPU_FTR_UNALIGNED_LD_STD)
420#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
421 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
422 CPU_FTR_PURR | CPU_FTR_REAL_LE)
423#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
424
425#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
426 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
427
428#ifdef __powerpc64__
429#ifdef CONFIG_PPC_BOOK3E
430#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
431#else
432#define CPU_FTRS_POSSIBLE \
433 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
434 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
435 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \
436 CPU_FTRS_PA6T | CPU_FTR_VSX)
437#endif
438#else
439enum {
440 CPU_FTRS_POSSIBLE =
441#if CLASSIC_PPC
442 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
443 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
444 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
445 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
446 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
447 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
448 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
449 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
450 CPU_FTRS_CLASSIC32 |
451#else
452 CPU_FTRS_GENERIC_32 |
453#endif
454#ifdef CONFIG_8xx
455 CPU_FTRS_8XX |
456#endif
457#ifdef CONFIG_40x
458 CPU_FTRS_40X |
459#endif
460#ifdef CONFIG_44x
461 CPU_FTRS_44X | CPU_FTRS_440x6 |
462#endif
463#ifdef CONFIG_PPC_47x
464 CPU_FTRS_47X | CPU_FTR_476_DD2 |
465#endif
466#ifdef CONFIG_E200
467 CPU_FTRS_E200 |
468#endif
469#ifdef CONFIG_E500
470 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
471#endif
472#ifdef CONFIG_PPC_E500MC
473 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
474#endif
475 0,
476};
477#endif /* __powerpc64__ */
478
479#ifdef __powerpc64__
480#ifdef CONFIG_PPC_BOOK3E
481#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
482#else
483#define CPU_FTRS_ALWAYS \
484 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
485 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
486 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
487#endif
488#else
489enum {
490 CPU_FTRS_ALWAYS =
491#if CLASSIC_PPC
492 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
493 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
494 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
495 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
496 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
497 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
498 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
499 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
500 CPU_FTRS_CLASSIC32 &
501#else
502 CPU_FTRS_GENERIC_32 &
503#endif
504#ifdef CONFIG_8xx
505 CPU_FTRS_8XX &
506#endif
507#ifdef CONFIG_40x
508 CPU_FTRS_40X &
509#endif
510#ifdef CONFIG_44x
511 CPU_FTRS_44X & CPU_FTRS_440x6 &
512#endif
513#ifdef CONFIG_E200
514 CPU_FTRS_E200 &
515#endif
516#ifdef CONFIG_E500
517 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
518#endif
519#ifdef CONFIG_PPC_E500MC
520 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
521#endif
522 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
523 CPU_FTRS_POSSIBLE,
524};
525#endif /* __powerpc64__ */
526
527static inline int cpu_has_feature(unsigned long feature)
528{
529 return (CPU_FTRS_ALWAYS & feature) ||
530 (CPU_FTRS_POSSIBLE
531 & cur_cpu_spec->cpu_features
532 & feature);
533}
534
535#define HBP_NUM 1
536
537#endif /* !__ASSEMBLY__ */
538
539#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)