| 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2007 MIPS Technologies, Inc. |
| 7 | * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> |
| 8 | */ |
| 9 | #include <linux/clockchips.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/percpu.h> |
| 12 | #include <linux/smp.h> |
| 13 | #include <linux/irq.h> |
| 14 | |
| 15 | #include <asm/time.h> |
| 16 | #include <asm/cevt-r4k.h> |
| 17 | |
| 18 | static int mips_next_event(unsigned long delta, |
| 19 | struct clock_event_device *evt) |
| 20 | { |
| 21 | unsigned int cnt; |
| 22 | int res; |
| 23 | |
| 24 | cnt = read_c0_count(); |
| 25 | cnt += delta; |
| 26 | write_c0_compare(cnt); |
| 27 | res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; |
| 28 | return res; |
| 29 | } |
| 30 | |
| 31 | void mips_set_clock_mode(enum clock_event_mode mode, |
| 32 | struct clock_event_device *evt) |
| 33 | { |
| 34 | /* Nothing to do ... */ |
| 35 | } |
| 36 | |
| 37 | DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); |
| 38 | int cp0_timer_irq_installed; |
| 39 | |
| 40 | /* |
| 41 | * Possibly handle a performance counter interrupt. |
| 42 | * Return true if the timer interrupt should not be checked |
| 43 | */ |
| 44 | static inline int handle_perf_irq(int r2) |
| 45 | { |
| 46 | /* |
| 47 | * The performance counter overflow interrupt may be shared with the |
| 48 | * timer interrupt (cp0_perfcount_irq < 0). If it is and a |
| 49 | * performance counter has overflowed (perf_irq() == IRQ_HANDLED) |
| 50 | * and we can't reliably determine if a counter interrupt has also |
| 51 | * happened (!r2) then don't check for a timer interrupt. |
| 52 | */ |
| 53 | return (cp0_perfcount_irq < 0) && |
| 54 | perf_irq() == IRQ_HANDLED && |
| 55 | !r2; |
| 56 | } |
| 57 | |
| 58 | irqreturn_t c0_compare_interrupt(int irq, void *dev_id) |
| 59 | { |
| 60 | const int r2 = cpu_has_mips_r2_r6; |
| 61 | struct clock_event_device *cd; |
| 62 | int cpu = smp_processor_id(); |
| 63 | |
| 64 | /* |
| 65 | * Suckage alert: |
| 66 | * Before R2 of the architecture there was no way to see if a |
| 67 | * performance counter interrupt was pending, so we have to run |
| 68 | * the performance counter interrupt handler anyway. |
| 69 | */ |
| 70 | if (handle_perf_irq(r2)) |
| 71 | goto out; |
| 72 | |
| 73 | /* |
| 74 | * The same applies to performance counter interrupts. But with the |
| 75 | * above we now know that the reason we got here must be a timer |
| 76 | * interrupt. Being the paranoiacs we are we check anyway. |
| 77 | */ |
| 78 | if (!r2 || (read_c0_cause() & CAUSEF_TI)) { |
| 79 | /* Clear Count/Compare Interrupt */ |
| 80 | write_c0_compare(read_c0_compare()); |
| 81 | cd = &per_cpu(mips_clockevent_device, cpu); |
| 82 | cd->event_handler(cd); |
| 83 | } else { |
| 84 | return IRQ_NONE; |
| 85 | } |
| 86 | |
| 87 | out: |
| 88 | return IRQ_HANDLED; |
| 89 | } |
| 90 | |
| 91 | struct irqaction c0_compare_irqaction = { |
| 92 | .handler = c0_compare_interrupt, |
| 93 | /* |
| 94 | * IRQF_SHARED: The timer interrupt may be shared with other interrupts |
| 95 | * such as perf counter and FDC interrupts. |
| 96 | */ |
| 97 | .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED, |
| 98 | .name = "timer", |
| 99 | }; |
| 100 | |
| 101 | |
| 102 | void mips_event_handler(struct clock_event_device *dev) |
| 103 | { |
| 104 | } |
| 105 | |
| 106 | /* |
| 107 | * FIXME: This doesn't hold for the relocated E9000 compare interrupt. |
| 108 | */ |
| 109 | static int c0_compare_int_pending(void) |
| 110 | { |
| 111 | /* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */ |
| 112 | return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); |
| 113 | } |
| 114 | |
| 115 | /* |
| 116 | * Compare interrupt can be routed and latched outside the core, |
| 117 | * so wait up to worst case number of cycle counter ticks for timer interrupt |
| 118 | * changes to propagate to the cause register. |
| 119 | */ |
| 120 | #define COMPARE_INT_SEEN_TICKS 50 |
| 121 | |
| 122 | int c0_compare_int_usable(void) |
| 123 | { |
| 124 | unsigned int delta; |
| 125 | unsigned int cnt; |
| 126 | |
| 127 | #ifdef CONFIG_KVM_GUEST |
| 128 | return 1; |
| 129 | #endif |
| 130 | |
| 131 | /* |
| 132 | * IP7 already pending? Try to clear it by acking the timer. |
| 133 | */ |
| 134 | if (c0_compare_int_pending()) { |
| 135 | cnt = read_c0_count(); |
| 136 | write_c0_compare(cnt); |
| 137 | back_to_back_c0_hazard(); |
| 138 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
| 139 | if (!c0_compare_int_pending()) |
| 140 | break; |
| 141 | if (c0_compare_int_pending()) |
| 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | for (delta = 0x10; delta <= 0x400000; delta <<= 1) { |
| 146 | cnt = read_c0_count(); |
| 147 | cnt += delta; |
| 148 | write_c0_compare(cnt); |
| 149 | back_to_back_c0_hazard(); |
| 150 | if ((int)(read_c0_count() - cnt) < 0) |
| 151 | break; |
| 152 | /* increase delta if the timer was already expired */ |
| 153 | } |
| 154 | |
| 155 | while ((int)(read_c0_count() - cnt) <= 0) |
| 156 | ; /* Wait for expiry */ |
| 157 | |
| 158 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
| 159 | if (c0_compare_int_pending()) |
| 160 | break; |
| 161 | if (!c0_compare_int_pending()) |
| 162 | return 0; |
| 163 | cnt = read_c0_count(); |
| 164 | write_c0_compare(cnt); |
| 165 | back_to_back_c0_hazard(); |
| 166 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
| 167 | if (!c0_compare_int_pending()) |
| 168 | break; |
| 169 | if (c0_compare_int_pending()) |
| 170 | return 0; |
| 171 | |
| 172 | /* |
| 173 | * Feels like a real count / compare timer. |
| 174 | */ |
| 175 | return 1; |
| 176 | } |
| 177 | |
| 178 | int r4k_clockevent_init(void) |
| 179 | { |
| 180 | unsigned int cpu = smp_processor_id(); |
| 181 | struct clock_event_device *cd; |
| 182 | unsigned int irq; |
| 183 | |
| 184 | if (!cpu_has_counter || !mips_hpt_frequency) |
| 185 | return -ENXIO; |
| 186 | |
| 187 | if (!c0_compare_int_usable()) |
| 188 | return -ENXIO; |
| 189 | |
| 190 | /* |
| 191 | * With vectored interrupts things are getting platform specific. |
| 192 | * get_c0_compare_int is a hook to allow a platform to return the |
| 193 | * interrupt number of it's liking. |
| 194 | */ |
| 195 | irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
| 196 | if (get_c0_compare_int) |
| 197 | irq = get_c0_compare_int(); |
| 198 | |
| 199 | cd = &per_cpu(mips_clockevent_device, cpu); |
| 200 | |
| 201 | cd->name = "MIPS"; |
| 202 | cd->features = CLOCK_EVT_FEAT_ONESHOT | |
| 203 | CLOCK_EVT_FEAT_C3STOP | |
| 204 | CLOCK_EVT_FEAT_PERCPU; |
| 205 | |
| 206 | clockevent_set_clock(cd, mips_hpt_frequency); |
| 207 | |
| 208 | /* Calculate the min / max delta */ |
| 209 | cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); |
| 210 | cd->min_delta_ns = clockevent_delta2ns(0x300, cd); |
| 211 | |
| 212 | cd->rating = 300; |
| 213 | cd->irq = irq; |
| 214 | cd->cpumask = cpumask_of(cpu); |
| 215 | cd->set_next_event = mips_next_event; |
| 216 | cd->set_mode = mips_set_clock_mode; |
| 217 | cd->event_handler = mips_event_handler; |
| 218 | |
| 219 | clockevents_register_device(cd); |
| 220 | |
| 221 | if (cp0_timer_irq_installed) |
| 222 | return 0; |
| 223 | |
| 224 | cp0_timer_irq_installed = 1; |
| 225 | |
| 226 | setup_irq(irq, &c0_compare_irqaction); |
| 227 | |
| 228 | return 0; |
| 229 | } |
| 230 | |