| 1 | /* |
| 2 | * Copyright 2004-2009 Analog Devices Inc. |
| 3 | * 2008-2009 Bluetechnix |
| 4 | * 2005 National ICT Australia (NICTA) |
| 5 | * Aidan Williams <aidan@nicta.com.au> |
| 6 | * |
| 7 | * Licensed under the GPL-2 or later. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/device.h> |
| 11 | #include <linux/platform_device.h> |
| 12 | #include <linux/mtd/mtd.h> |
| 13 | #include <linux/mtd/partitions.h> |
| 14 | #include <linux/mtd/physmap.h> |
| 15 | #include <linux/spi/spi.h> |
| 16 | #include <linux/spi/flash.h> |
| 17 | #include <linux/irq.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/usb/musb.h> |
| 20 | #include <asm/bfin5xx_spi.h> |
| 21 | #include <asm/dma.h> |
| 22 | #include <asm/gpio.h> |
| 23 | #include <asm/nand.h> |
| 24 | #include <asm/portmux.h> |
| 25 | #include <asm/bfin_sdh.h> |
| 26 | #include <mach/bf54x_keys.h> |
| 27 | #include <asm/dpmc.h> |
| 28 | #include <linux/input.h> |
| 29 | #include <linux/spi/ad7877.h> |
| 30 | |
| 31 | /* |
| 32 | * Name the Board for the /proc/cpuinfo |
| 33 | */ |
| 34 | const char bfin_board_name[] = "Bluetechnix CM-BF548"; |
| 35 | |
| 36 | /* |
| 37 | * Driver needs to know address, irq and flag pin. |
| 38 | */ |
| 39 | |
| 40 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
| 41 | |
| 42 | #include <mach/bf54x-lq043.h> |
| 43 | |
| 44 | static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { |
| 45 | .width = 480, |
| 46 | .height = 272, |
| 47 | .xres = {480, 480, 480}, |
| 48 | .yres = {272, 272, 272}, |
| 49 | .bpp = {24, 24, 24}, |
| 50 | .disp = GPIO_PE3, |
| 51 | }; |
| 52 | |
| 53 | static struct resource bf54x_lq043_resources[] = { |
| 54 | { |
| 55 | .start = IRQ_EPPI0_ERR, |
| 56 | .end = IRQ_EPPI0_ERR, |
| 57 | .flags = IORESOURCE_IRQ, |
| 58 | }, |
| 59 | }; |
| 60 | |
| 61 | static struct platform_device bf54x_lq043_device = { |
| 62 | .name = "bf54x-lq043", |
| 63 | .id = -1, |
| 64 | .num_resources = ARRAY_SIZE(bf54x_lq043_resources), |
| 65 | .resource = bf54x_lq043_resources, |
| 66 | .dev = { |
| 67 | .platform_data = &bf54x_lq043_data, |
| 68 | }, |
| 69 | }; |
| 70 | #endif |
| 71 | |
| 72 | #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) |
| 73 | static unsigned int bf548_keymap[] = { |
| 74 | KEYVAL(0, 0, KEY_ENTER), |
| 75 | KEYVAL(0, 1, KEY_HELP), |
| 76 | KEYVAL(0, 2, KEY_0), |
| 77 | KEYVAL(0, 3, KEY_BACKSPACE), |
| 78 | KEYVAL(1, 0, KEY_TAB), |
| 79 | KEYVAL(1, 1, KEY_9), |
| 80 | KEYVAL(1, 2, KEY_8), |
| 81 | KEYVAL(1, 3, KEY_7), |
| 82 | KEYVAL(2, 0, KEY_DOWN), |
| 83 | KEYVAL(2, 1, KEY_6), |
| 84 | KEYVAL(2, 2, KEY_5), |
| 85 | KEYVAL(2, 3, KEY_4), |
| 86 | KEYVAL(3, 0, KEY_UP), |
| 87 | KEYVAL(3, 1, KEY_3), |
| 88 | KEYVAL(3, 2, KEY_2), |
| 89 | KEYVAL(3, 3, KEY_1), |
| 90 | }; |
| 91 | |
| 92 | static struct bfin_kpad_platform_data bf54x_kpad_data = { |
| 93 | .rows = 4, |
| 94 | .cols = 4, |
| 95 | .keymap = bf548_keymap, |
| 96 | .keymapsize = ARRAY_SIZE(bf548_keymap), |
| 97 | .repeat = 0, |
| 98 | .debounce_time = 5000, /* ns (5ms) */ |
| 99 | .coldrive_time = 1000, /* ns (1ms) */ |
| 100 | .keyup_test_interval = 50, /* ms (50ms) */ |
| 101 | }; |
| 102 | |
| 103 | static struct resource bf54x_kpad_resources[] = { |
| 104 | { |
| 105 | .start = IRQ_KEY, |
| 106 | .end = IRQ_KEY, |
| 107 | .flags = IORESOURCE_IRQ, |
| 108 | }, |
| 109 | }; |
| 110 | |
| 111 | static struct platform_device bf54x_kpad_device = { |
| 112 | .name = "bf54x-keys", |
| 113 | .id = -1, |
| 114 | .num_resources = ARRAY_SIZE(bf54x_kpad_resources), |
| 115 | .resource = bf54x_kpad_resources, |
| 116 | .dev = { |
| 117 | .platform_data = &bf54x_kpad_data, |
| 118 | }, |
| 119 | }; |
| 120 | #endif |
| 121 | |
| 122 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
| 123 | static struct platform_device rtc_device = { |
| 124 | .name = "rtc-bfin", |
| 125 | .id = -1, |
| 126 | }; |
| 127 | #endif |
| 128 | |
| 129 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
| 130 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
| 131 | static struct resource bfin_uart0_resources[] = { |
| 132 | { |
| 133 | .start = UART0_DLL, |
| 134 | .end = UART0_RBR+2, |
| 135 | .flags = IORESOURCE_MEM, |
| 136 | }, |
| 137 | { |
| 138 | .start = IRQ_UART0_RX, |
| 139 | .end = IRQ_UART0_RX+1, |
| 140 | .flags = IORESOURCE_IRQ, |
| 141 | }, |
| 142 | { |
| 143 | .start = IRQ_UART0_ERROR, |
| 144 | .end = IRQ_UART0_ERROR, |
| 145 | .flags = IORESOURCE_IRQ, |
| 146 | }, |
| 147 | { |
| 148 | .start = CH_UART0_TX, |
| 149 | .end = CH_UART0_TX, |
| 150 | .flags = IORESOURCE_DMA, |
| 151 | }, |
| 152 | { |
| 153 | .start = CH_UART0_RX, |
| 154 | .end = CH_UART0_RX, |
| 155 | .flags = IORESOURCE_DMA, |
| 156 | }, |
| 157 | }; |
| 158 | |
| 159 | unsigned short bfin_uart0_peripherals[] = { |
| 160 | P_UART0_TX, P_UART0_RX, 0 |
| 161 | }; |
| 162 | |
| 163 | static struct platform_device bfin_uart0_device = { |
| 164 | .name = "bfin-uart", |
| 165 | .id = 0, |
| 166 | .num_resources = ARRAY_SIZE(bfin_uart0_resources), |
| 167 | .resource = bfin_uart0_resources, |
| 168 | .dev = { |
| 169 | .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ |
| 170 | }, |
| 171 | }; |
| 172 | #endif |
| 173 | #ifdef CONFIG_SERIAL_BFIN_UART1 |
| 174 | static struct resource bfin_uart1_resources[] = { |
| 175 | { |
| 176 | .start = UART1_DLL, |
| 177 | .end = UART1_RBR+2, |
| 178 | .flags = IORESOURCE_MEM, |
| 179 | }, |
| 180 | { |
| 181 | .start = IRQ_UART1_RX, |
| 182 | .end = IRQ_UART1_RX+1, |
| 183 | .flags = IORESOURCE_IRQ, |
| 184 | }, |
| 185 | { |
| 186 | .start = IRQ_UART1_ERROR, |
| 187 | .end = IRQ_UART1_ERROR, |
| 188 | .flags = IORESOURCE_IRQ, |
| 189 | }, |
| 190 | { |
| 191 | .start = CH_UART1_TX, |
| 192 | .end = CH_UART1_TX, |
| 193 | .flags = IORESOURCE_DMA, |
| 194 | }, |
| 195 | { |
| 196 | .start = CH_UART1_RX, |
| 197 | .end = CH_UART1_RX, |
| 198 | .flags = IORESOURCE_DMA, |
| 199 | }, |
| 200 | #ifdef CONFIG_BFIN_UART1_CTSRTS |
| 201 | { /* CTS pin -- 0 means not supported */ |
| 202 | .start = GPIO_PE10, |
| 203 | .end = GPIO_PE10, |
| 204 | .flags = IORESOURCE_IO, |
| 205 | }, |
| 206 | { /* RTS pin -- 0 means not supported */ |
| 207 | .start = GPIO_PE9, |
| 208 | .end = GPIO_PE9, |
| 209 | .flags = IORESOURCE_IO, |
| 210 | }, |
| 211 | #endif |
| 212 | }; |
| 213 | |
| 214 | unsigned short bfin_uart1_peripherals[] = { |
| 215 | P_UART1_TX, P_UART1_RX, |
| 216 | #ifdef CONFIG_BFIN_UART1_CTSRTS |
| 217 | P_UART1_RTS, P_UART1_CTS, |
| 218 | #endif |
| 219 | 0 |
| 220 | }; |
| 221 | |
| 222 | static struct platform_device bfin_uart1_device = { |
| 223 | .name = "bfin-uart", |
| 224 | .id = 1, |
| 225 | .num_resources = ARRAY_SIZE(bfin_uart1_resources), |
| 226 | .resource = bfin_uart1_resources, |
| 227 | .dev = { |
| 228 | .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ |
| 229 | }, |
| 230 | }; |
| 231 | #endif |
| 232 | #ifdef CONFIG_SERIAL_BFIN_UART2 |
| 233 | static struct resource bfin_uart2_resources[] = { |
| 234 | { |
| 235 | .start = UART2_DLL, |
| 236 | .end = UART2_RBR+2, |
| 237 | .flags = IORESOURCE_MEM, |
| 238 | }, |
| 239 | { |
| 240 | .start = IRQ_UART2_RX, |
| 241 | .end = IRQ_UART2_RX+1, |
| 242 | .flags = IORESOURCE_IRQ, |
| 243 | }, |
| 244 | { |
| 245 | .start = IRQ_UART2_ERROR, |
| 246 | .end = IRQ_UART2_ERROR, |
| 247 | .flags = IORESOURCE_IRQ, |
| 248 | }, |
| 249 | { |
| 250 | .start = CH_UART2_TX, |
| 251 | .end = CH_UART2_TX, |
| 252 | .flags = IORESOURCE_DMA, |
| 253 | }, |
| 254 | { |
| 255 | .start = CH_UART2_RX, |
| 256 | .end = CH_UART2_RX, |
| 257 | .flags = IORESOURCE_DMA, |
| 258 | }, |
| 259 | }; |
| 260 | |
| 261 | unsigned short bfin_uart2_peripherals[] = { |
| 262 | P_UART2_TX, P_UART2_RX, 0 |
| 263 | }; |
| 264 | |
| 265 | static struct platform_device bfin_uart2_device = { |
| 266 | .name = "bfin-uart", |
| 267 | .id = 2, |
| 268 | .num_resources = ARRAY_SIZE(bfin_uart2_resources), |
| 269 | .resource = bfin_uart2_resources, |
| 270 | .dev = { |
| 271 | .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ |
| 272 | }, |
| 273 | }; |
| 274 | #endif |
| 275 | #ifdef CONFIG_SERIAL_BFIN_UART3 |
| 276 | static struct resource bfin_uart3_resources[] = { |
| 277 | { |
| 278 | .start = UART3_DLL, |
| 279 | .end = UART3_RBR+2, |
| 280 | .flags = IORESOURCE_MEM, |
| 281 | }, |
| 282 | { |
| 283 | .start = IRQ_UART3_RX, |
| 284 | .end = IRQ_UART3_RX+1, |
| 285 | .flags = IORESOURCE_IRQ, |
| 286 | }, |
| 287 | { |
| 288 | .start = IRQ_UART3_ERROR, |
| 289 | .end = IRQ_UART3_ERROR, |
| 290 | .flags = IORESOURCE_IRQ, |
| 291 | }, |
| 292 | { |
| 293 | .start = CH_UART3_TX, |
| 294 | .end = CH_UART3_TX, |
| 295 | .flags = IORESOURCE_DMA, |
| 296 | }, |
| 297 | { |
| 298 | .start = CH_UART3_RX, |
| 299 | .end = CH_UART3_RX, |
| 300 | .flags = IORESOURCE_DMA, |
| 301 | }, |
| 302 | #ifdef CONFIG_BFIN_UART3_CTSRTS |
| 303 | { /* CTS pin -- 0 means not supported */ |
| 304 | .start = GPIO_PB3, |
| 305 | .end = GPIO_PB3, |
| 306 | .flags = IORESOURCE_IO, |
| 307 | }, |
| 308 | { /* RTS pin -- 0 means not supported */ |
| 309 | .start = GPIO_PB2, |
| 310 | .end = GPIO_PB2, |
| 311 | .flags = IORESOURCE_IO, |
| 312 | }, |
| 313 | #endif |
| 314 | }; |
| 315 | |
| 316 | unsigned short bfin_uart3_peripherals[] = { |
| 317 | P_UART3_TX, P_UART3_RX, |
| 318 | #ifdef CONFIG_BFIN_UART3_CTSRTS |
| 319 | P_UART3_RTS, P_UART3_CTS, |
| 320 | #endif |
| 321 | 0 |
| 322 | }; |
| 323 | |
| 324 | static struct platform_device bfin_uart3_device = { |
| 325 | .name = "bfin-uart", |
| 326 | .id = 3, |
| 327 | .num_resources = ARRAY_SIZE(bfin_uart3_resources), |
| 328 | .resource = bfin_uart3_resources, |
| 329 | .dev = { |
| 330 | .platform_data = &bfin_uart3_peripherals, /* Passed to driver */ |
| 331 | }, |
| 332 | }; |
| 333 | #endif |
| 334 | #endif |
| 335 | |
| 336 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 337 | #ifdef CONFIG_BFIN_SIR0 |
| 338 | static struct resource bfin_sir0_resources[] = { |
| 339 | { |
| 340 | .start = 0xFFC00400, |
| 341 | .end = 0xFFC004FF, |
| 342 | .flags = IORESOURCE_MEM, |
| 343 | }, |
| 344 | { |
| 345 | .start = IRQ_UART0_RX, |
| 346 | .end = IRQ_UART0_RX+1, |
| 347 | .flags = IORESOURCE_IRQ, |
| 348 | }, |
| 349 | { |
| 350 | .start = CH_UART0_RX, |
| 351 | .end = CH_UART0_RX+1, |
| 352 | .flags = IORESOURCE_DMA, |
| 353 | }, |
| 354 | }; |
| 355 | static struct platform_device bfin_sir0_device = { |
| 356 | .name = "bfin_sir", |
| 357 | .id = 0, |
| 358 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 359 | .resource = bfin_sir0_resources, |
| 360 | }; |
| 361 | #endif |
| 362 | #ifdef CONFIG_BFIN_SIR1 |
| 363 | static struct resource bfin_sir1_resources[] = { |
| 364 | { |
| 365 | .start = 0xFFC02000, |
| 366 | .end = 0xFFC020FF, |
| 367 | .flags = IORESOURCE_MEM, |
| 368 | }, |
| 369 | { |
| 370 | .start = IRQ_UART1_RX, |
| 371 | .end = IRQ_UART1_RX+1, |
| 372 | .flags = IORESOURCE_IRQ, |
| 373 | }, |
| 374 | { |
| 375 | .start = CH_UART1_RX, |
| 376 | .end = CH_UART1_RX+1, |
| 377 | .flags = IORESOURCE_DMA, |
| 378 | }, |
| 379 | }; |
| 380 | static struct platform_device bfin_sir1_device = { |
| 381 | .name = "bfin_sir", |
| 382 | .id = 1, |
| 383 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 384 | .resource = bfin_sir1_resources, |
| 385 | }; |
| 386 | #endif |
| 387 | #ifdef CONFIG_BFIN_SIR2 |
| 388 | static struct resource bfin_sir2_resources[] = { |
| 389 | { |
| 390 | .start = 0xFFC02100, |
| 391 | .end = 0xFFC021FF, |
| 392 | .flags = IORESOURCE_MEM, |
| 393 | }, |
| 394 | { |
| 395 | .start = IRQ_UART2_RX, |
| 396 | .end = IRQ_UART2_RX+1, |
| 397 | .flags = IORESOURCE_IRQ, |
| 398 | }, |
| 399 | { |
| 400 | .start = CH_UART2_RX, |
| 401 | .end = CH_UART2_RX+1, |
| 402 | .flags = IORESOURCE_DMA, |
| 403 | }, |
| 404 | }; |
| 405 | static struct platform_device bfin_sir2_device = { |
| 406 | .name = "bfin_sir", |
| 407 | .id = 2, |
| 408 | .num_resources = ARRAY_SIZE(bfin_sir2_resources), |
| 409 | .resource = bfin_sir2_resources, |
| 410 | }; |
| 411 | #endif |
| 412 | #ifdef CONFIG_BFIN_SIR3 |
| 413 | static struct resource bfin_sir3_resources[] = { |
| 414 | { |
| 415 | .start = 0xFFC03100, |
| 416 | .end = 0xFFC031FF, |
| 417 | .flags = IORESOURCE_MEM, |
| 418 | }, |
| 419 | { |
| 420 | .start = IRQ_UART3_RX, |
| 421 | .end = IRQ_UART3_RX+1, |
| 422 | .flags = IORESOURCE_IRQ, |
| 423 | }, |
| 424 | { |
| 425 | .start = CH_UART3_RX, |
| 426 | .end = CH_UART3_RX+1, |
| 427 | .flags = IORESOURCE_DMA, |
| 428 | }, |
| 429 | }; |
| 430 | static struct platform_device bfin_sir3_device = { |
| 431 | .name = "bfin_sir", |
| 432 | .id = 3, |
| 433 | .num_resources = ARRAY_SIZE(bfin_sir3_resources), |
| 434 | .resource = bfin_sir3_resources, |
| 435 | }; |
| 436 | #endif |
| 437 | #endif |
| 438 | |
| 439 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
| 440 | #include <linux/smsc911x.h> |
| 441 | |
| 442 | static struct resource smsc911x_resources[] = { |
| 443 | { |
| 444 | .name = "smsc911x-memory", |
| 445 | .start = 0x24000000, |
| 446 | .end = 0x24000000 + 0xFF, |
| 447 | .flags = IORESOURCE_MEM, |
| 448 | }, |
| 449 | { |
| 450 | .start = IRQ_PE6, |
| 451 | .end = IRQ_PE6, |
| 452 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
| 453 | }, |
| 454 | }; |
| 455 | |
| 456 | static struct smsc911x_platform_config smsc911x_config = { |
| 457 | .flags = SMSC911X_USE_16BIT, |
| 458 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, |
| 459 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, |
| 460 | .phy_interface = PHY_INTERFACE_MODE_MII, |
| 461 | }; |
| 462 | |
| 463 | static struct platform_device smsc911x_device = { |
| 464 | .name = "smsc911x", |
| 465 | .id = 0, |
| 466 | .num_resources = ARRAY_SIZE(smsc911x_resources), |
| 467 | .resource = smsc911x_resources, |
| 468 | .dev = { |
| 469 | .platform_data = &smsc911x_config, |
| 470 | }, |
| 471 | }; |
| 472 | #endif |
| 473 | |
| 474 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
| 475 | static struct resource musb_resources[] = { |
| 476 | [0] = { |
| 477 | .start = 0xFFC03C00, |
| 478 | .end = 0xFFC040FF, |
| 479 | .flags = IORESOURCE_MEM, |
| 480 | }, |
| 481 | [1] = { /* general IRQ */ |
| 482 | .start = IRQ_USB_INT0, |
| 483 | .end = IRQ_USB_INT0, |
| 484 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
| 485 | .name = "mc" |
| 486 | }, |
| 487 | [2] = { /* DMA IRQ */ |
| 488 | .start = IRQ_USB_DMA, |
| 489 | .end = IRQ_USB_DMA, |
| 490 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
| 491 | .name = "dma" |
| 492 | }, |
| 493 | }; |
| 494 | |
| 495 | static struct musb_hdrc_config musb_config = { |
| 496 | .multipoint = 0, |
| 497 | .dyn_fifo = 0, |
| 498 | .soft_con = 1, |
| 499 | .dma = 1, |
| 500 | .num_eps = 8, |
| 501 | .dma_channels = 8, |
| 502 | .gpio_vrsel = GPIO_PH6, |
| 503 | /* Some custom boards need to be active low, just set it to "0" |
| 504 | * if it is the case. |
| 505 | */ |
| 506 | .gpio_vrsel_active = 1, |
| 507 | }; |
| 508 | |
| 509 | static struct musb_hdrc_platform_data musb_plat = { |
| 510 | #if defined(CONFIG_USB_MUSB_OTG) |
| 511 | .mode = MUSB_OTG, |
| 512 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) |
| 513 | .mode = MUSB_HOST, |
| 514 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) |
| 515 | .mode = MUSB_PERIPHERAL, |
| 516 | #endif |
| 517 | .config = &musb_config, |
| 518 | }; |
| 519 | |
| 520 | static u64 musb_dmamask = ~(u32)0; |
| 521 | |
| 522 | static struct platform_device musb_device = { |
| 523 | .name = "musb_hdrc", |
| 524 | .id = 0, |
| 525 | .dev = { |
| 526 | .dma_mask = &musb_dmamask, |
| 527 | .coherent_dma_mask = 0xffffffff, |
| 528 | .platform_data = &musb_plat, |
| 529 | }, |
| 530 | .num_resources = ARRAY_SIZE(musb_resources), |
| 531 | .resource = musb_resources, |
| 532 | }; |
| 533 | #endif |
| 534 | |
| 535 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
| 536 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART |
| 537 | static struct resource bfin_sport0_uart_resources[] = { |
| 538 | { |
| 539 | .start = SPORT0_TCR1, |
| 540 | .end = SPORT0_MRCS3+4, |
| 541 | .flags = IORESOURCE_MEM, |
| 542 | }, |
| 543 | { |
| 544 | .start = IRQ_SPORT0_RX, |
| 545 | .end = IRQ_SPORT0_RX+1, |
| 546 | .flags = IORESOURCE_IRQ, |
| 547 | }, |
| 548 | { |
| 549 | .start = IRQ_SPORT0_ERROR, |
| 550 | .end = IRQ_SPORT0_ERROR, |
| 551 | .flags = IORESOURCE_IRQ, |
| 552 | }, |
| 553 | }; |
| 554 | |
| 555 | unsigned short bfin_sport0_peripherals[] = { |
| 556 | P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, |
| 557 | P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 |
| 558 | }; |
| 559 | |
| 560 | static struct platform_device bfin_sport0_uart_device = { |
| 561 | .name = "bfin-sport-uart", |
| 562 | .id = 0, |
| 563 | .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), |
| 564 | .resource = bfin_sport0_uart_resources, |
| 565 | .dev = { |
| 566 | .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ |
| 567 | }, |
| 568 | }; |
| 569 | #endif |
| 570 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART |
| 571 | static struct resource bfin_sport1_uart_resources[] = { |
| 572 | { |
| 573 | .start = SPORT1_TCR1, |
| 574 | .end = SPORT1_MRCS3+4, |
| 575 | .flags = IORESOURCE_MEM, |
| 576 | }, |
| 577 | { |
| 578 | .start = IRQ_SPORT1_RX, |
| 579 | .end = IRQ_SPORT1_RX+1, |
| 580 | .flags = IORESOURCE_IRQ, |
| 581 | }, |
| 582 | { |
| 583 | .start = IRQ_SPORT1_ERROR, |
| 584 | .end = IRQ_SPORT1_ERROR, |
| 585 | .flags = IORESOURCE_IRQ, |
| 586 | }, |
| 587 | }; |
| 588 | |
| 589 | unsigned short bfin_sport1_peripherals[] = { |
| 590 | P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, |
| 591 | P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 |
| 592 | }; |
| 593 | |
| 594 | static struct platform_device bfin_sport1_uart_device = { |
| 595 | .name = "bfin-sport-uart", |
| 596 | .id = 1, |
| 597 | .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), |
| 598 | .resource = bfin_sport1_uart_resources, |
| 599 | .dev = { |
| 600 | .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ |
| 601 | }, |
| 602 | }; |
| 603 | #endif |
| 604 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART |
| 605 | static struct resource bfin_sport2_uart_resources[] = { |
| 606 | { |
| 607 | .start = SPORT2_TCR1, |
| 608 | .end = SPORT2_MRCS3+4, |
| 609 | .flags = IORESOURCE_MEM, |
| 610 | }, |
| 611 | { |
| 612 | .start = IRQ_SPORT2_RX, |
| 613 | .end = IRQ_SPORT2_RX+1, |
| 614 | .flags = IORESOURCE_IRQ, |
| 615 | }, |
| 616 | { |
| 617 | .start = IRQ_SPORT2_ERROR, |
| 618 | .end = IRQ_SPORT2_ERROR, |
| 619 | .flags = IORESOURCE_IRQ, |
| 620 | }, |
| 621 | }; |
| 622 | |
| 623 | unsigned short bfin_sport2_peripherals[] = { |
| 624 | P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, |
| 625 | P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 |
| 626 | }; |
| 627 | |
| 628 | static struct platform_device bfin_sport2_uart_device = { |
| 629 | .name = "bfin-sport-uart", |
| 630 | .id = 2, |
| 631 | .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), |
| 632 | .resource = bfin_sport2_uart_resources, |
| 633 | .dev = { |
| 634 | .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ |
| 635 | }, |
| 636 | }; |
| 637 | #endif |
| 638 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART |
| 639 | static struct resource bfin_sport3_uart_resources[] = { |
| 640 | { |
| 641 | .start = SPORT3_TCR1, |
| 642 | .end = SPORT3_MRCS3+4, |
| 643 | .flags = IORESOURCE_MEM, |
| 644 | }, |
| 645 | { |
| 646 | .start = IRQ_SPORT3_RX, |
| 647 | .end = IRQ_SPORT3_RX+1, |
| 648 | .flags = IORESOURCE_IRQ, |
| 649 | }, |
| 650 | { |
| 651 | .start = IRQ_SPORT3_ERROR, |
| 652 | .end = IRQ_SPORT3_ERROR, |
| 653 | .flags = IORESOURCE_IRQ, |
| 654 | }, |
| 655 | }; |
| 656 | |
| 657 | unsigned short bfin_sport3_peripherals[] = { |
| 658 | P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, |
| 659 | P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 |
| 660 | }; |
| 661 | |
| 662 | static struct platform_device bfin_sport3_uart_device = { |
| 663 | .name = "bfin-sport-uart", |
| 664 | .id = 3, |
| 665 | .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources), |
| 666 | .resource = bfin_sport3_uart_resources, |
| 667 | .dev = { |
| 668 | .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ |
| 669 | }, |
| 670 | }; |
| 671 | #endif |
| 672 | #endif |
| 673 | |
| 674 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
| 675 | static struct resource bfin_atapi_resources[] = { |
| 676 | { |
| 677 | .start = 0xFFC03800, |
| 678 | .end = 0xFFC0386F, |
| 679 | .flags = IORESOURCE_MEM, |
| 680 | }, |
| 681 | { |
| 682 | .start = IRQ_ATAPI_ERR, |
| 683 | .end = IRQ_ATAPI_ERR, |
| 684 | .flags = IORESOURCE_IRQ, |
| 685 | }, |
| 686 | }; |
| 687 | |
| 688 | static struct platform_device bfin_atapi_device = { |
| 689 | .name = "pata-bf54x", |
| 690 | .id = -1, |
| 691 | .num_resources = ARRAY_SIZE(bfin_atapi_resources), |
| 692 | .resource = bfin_atapi_resources, |
| 693 | }; |
| 694 | #endif |
| 695 | |
| 696 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) |
| 697 | static struct mtd_partition partition_info[] = { |
| 698 | { |
| 699 | .name = "linux kernel(nand)", |
| 700 | .offset = 0, |
| 701 | .size = 4 * 1024 * 1024, |
| 702 | }, |
| 703 | { |
| 704 | .name = "file system(nand)", |
| 705 | .offset = 4 * 1024 * 1024, |
| 706 | .size = (256 - 4) * 1024 * 1024, |
| 707 | }, |
| 708 | }; |
| 709 | |
| 710 | static struct bf5xx_nand_platform bf5xx_nand_platform = { |
| 711 | .data_width = NFC_NWIDTH_8, |
| 712 | .partitions = partition_info, |
| 713 | .nr_partitions = ARRAY_SIZE(partition_info), |
| 714 | .rd_dly = 3, |
| 715 | .wr_dly = 3, |
| 716 | }; |
| 717 | |
| 718 | static struct resource bf5xx_nand_resources[] = { |
| 719 | { |
| 720 | .start = 0xFFC03B00, |
| 721 | .end = 0xFFC03B4F, |
| 722 | .flags = IORESOURCE_MEM, |
| 723 | }, |
| 724 | { |
| 725 | .start = CH_NFC, |
| 726 | .end = CH_NFC, |
| 727 | .flags = IORESOURCE_IRQ, |
| 728 | }, |
| 729 | }; |
| 730 | |
| 731 | static struct platform_device bf5xx_nand_device = { |
| 732 | .name = "bf5xx-nand", |
| 733 | .id = 0, |
| 734 | .num_resources = ARRAY_SIZE(bf5xx_nand_resources), |
| 735 | .resource = bf5xx_nand_resources, |
| 736 | .dev = { |
| 737 | .platform_data = &bf5xx_nand_platform, |
| 738 | }, |
| 739 | }; |
| 740 | #endif |
| 741 | |
| 742 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
| 743 | static struct bfin_sd_host bfin_sdh_data = { |
| 744 | .dma_chan = CH_SDH, |
| 745 | .irq_int0 = IRQ_SDH_MASK0, |
| 746 | .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, |
| 747 | }; |
| 748 | |
| 749 | static struct platform_device bf54x_sdh_device = { |
| 750 | .name = "bfin-sdh", |
| 751 | .id = 0, |
| 752 | .dev = { |
| 753 | .platform_data = &bfin_sdh_data, |
| 754 | }, |
| 755 | }; |
| 756 | #endif |
| 757 | |
| 758 | #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) |
| 759 | unsigned short bfin_can_peripherals[] = { |
| 760 | P_CAN0_RX, P_CAN0_TX, 0 |
| 761 | }; |
| 762 | |
| 763 | static struct resource bfin_can_resources[] = { |
| 764 | { |
| 765 | .start = 0xFFC02A00, |
| 766 | .end = 0xFFC02FFF, |
| 767 | .flags = IORESOURCE_MEM, |
| 768 | }, |
| 769 | { |
| 770 | .start = IRQ_CAN0_RX, |
| 771 | .end = IRQ_CAN0_RX, |
| 772 | .flags = IORESOURCE_IRQ, |
| 773 | }, |
| 774 | { |
| 775 | .start = IRQ_CAN0_TX, |
| 776 | .end = IRQ_CAN0_TX, |
| 777 | .flags = IORESOURCE_IRQ, |
| 778 | }, |
| 779 | { |
| 780 | .start = IRQ_CAN0_ERROR, |
| 781 | .end = IRQ_CAN0_ERROR, |
| 782 | .flags = IORESOURCE_IRQ, |
| 783 | }, |
| 784 | }; |
| 785 | |
| 786 | static struct platform_device bfin_can_device = { |
| 787 | .name = "bfin_can", |
| 788 | .num_resources = ARRAY_SIZE(bfin_can_resources), |
| 789 | .resource = bfin_can_resources, |
| 790 | .dev = { |
| 791 | .platform_data = &bfin_can_peripherals, /* Passed to driver */ |
| 792 | }, |
| 793 | }; |
| 794 | #endif |
| 795 | |
| 796 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
| 797 | static struct mtd_partition para_partitions[] = { |
| 798 | { |
| 799 | .name = "bootloader(nor)", |
| 800 | .size = 0x40000, |
| 801 | .offset = 0, |
| 802 | }, { |
| 803 | .name = "linux kernel(nor)", |
| 804 | .size = 0x100000, |
| 805 | .offset = MTDPART_OFS_APPEND, |
| 806 | }, { |
| 807 | .name = "file system(nor)", |
| 808 | .size = MTDPART_SIZ_FULL, |
| 809 | .offset = MTDPART_OFS_APPEND, |
| 810 | } |
| 811 | }; |
| 812 | |
| 813 | static struct physmap_flash_data para_flash_data = { |
| 814 | .width = 2, |
| 815 | .parts = para_partitions, |
| 816 | .nr_parts = ARRAY_SIZE(para_partitions), |
| 817 | }; |
| 818 | |
| 819 | static struct resource para_flash_resource = { |
| 820 | .start = 0x20000000, |
| 821 | .end = 0x207fffff, |
| 822 | .flags = IORESOURCE_MEM, |
| 823 | }; |
| 824 | |
| 825 | static struct platform_device para_flash_device = { |
| 826 | .name = "physmap-flash", |
| 827 | .id = 0, |
| 828 | .dev = { |
| 829 | .platform_data = ¶_flash_data, |
| 830 | }, |
| 831 | .num_resources = 1, |
| 832 | .resource = ¶_flash_resource, |
| 833 | }; |
| 834 | #endif |
| 835 | |
| 836 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 837 | /* all SPI peripherals info goes here */ |
| 838 | #if defined(CONFIG_MTD_M25P80) \ |
| 839 | || defined(CONFIG_MTD_M25P80_MODULE) |
| 840 | /* SPI flash chip (m25p16) */ |
| 841 | static struct mtd_partition bfin_spi_flash_partitions[] = { |
| 842 | { |
| 843 | .name = "bootloader(spi)", |
| 844 | .size = 0x00040000, |
| 845 | .offset = 0, |
| 846 | .mask_flags = MTD_CAP_ROM |
| 847 | }, { |
| 848 | .name = "linux kernel(spi)", |
| 849 | .size = 0x1c0000, |
| 850 | .offset = 0x40000 |
| 851 | } |
| 852 | }; |
| 853 | |
| 854 | static struct flash_platform_data bfin_spi_flash_data = { |
| 855 | .name = "m25p80", |
| 856 | .parts = bfin_spi_flash_partitions, |
| 857 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), |
| 858 | .type = "m25p16", |
| 859 | }; |
| 860 | |
| 861 | static struct bfin5xx_spi_chip spi_flash_chip_info = { |
| 862 | .enable_dma = 0, /* use dma transfer with this chip*/ |
| 863 | .bits_per_word = 8, |
| 864 | }; |
| 865 | #endif |
| 866 | |
| 867 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
| 868 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { |
| 869 | .enable_dma = 0, |
| 870 | .bits_per_word = 16, |
| 871 | }; |
| 872 | |
| 873 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { |
| 874 | .model = 7877, |
| 875 | .vref_delay_usecs = 50, /* internal, no capacitor */ |
| 876 | .x_plate_ohms = 419, |
| 877 | .y_plate_ohms = 486, |
| 878 | .pressure_max = 1000, |
| 879 | .pressure_min = 0, |
| 880 | .stopacq_polarity = 1, |
| 881 | .first_conversion_delay = 3, |
| 882 | .acquisition_time = 1, |
| 883 | .averaging = 1, |
| 884 | .pen_down_acc_interval = 1, |
| 885 | }; |
| 886 | #endif |
| 887 | |
| 888 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
| 889 | static struct bfin5xx_spi_chip spidev_chip_info = { |
| 890 | .enable_dma = 0, |
| 891 | .bits_per_word = 8, |
| 892 | }; |
| 893 | #endif |
| 894 | |
| 895 | static struct spi_board_info bf54x_spi_board_info[] __initdata = { |
| 896 | #if defined(CONFIG_MTD_M25P80) \ |
| 897 | || defined(CONFIG_MTD_M25P80_MODULE) |
| 898 | { |
| 899 | /* the modalias must be the same as spi device driver name */ |
| 900 | .modalias = "m25p80", /* Name of spi_driver for this device */ |
| 901 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 902 | .bus_num = 0, /* Framework bus number */ |
| 903 | .chip_select = 1, /* SPI_SSEL1*/ |
| 904 | .platform_data = &bfin_spi_flash_data, |
| 905 | .controller_data = &spi_flash_chip_info, |
| 906 | .mode = SPI_MODE_3, |
| 907 | }, |
| 908 | #endif |
| 909 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
| 910 | { |
| 911 | .modalias = "ad7877", |
| 912 | .platform_data = &bfin_ad7877_ts_info, |
| 913 | .irq = IRQ_PJ11, |
| 914 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ |
| 915 | .bus_num = 0, |
| 916 | .chip_select = 2, |
| 917 | .controller_data = &spi_ad7877_chip_info, |
| 918 | }, |
| 919 | #endif |
| 920 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
| 921 | { |
| 922 | .modalias = "spidev", |
| 923 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
| 924 | .bus_num = 0, |
| 925 | .chip_select = 1, |
| 926 | .controller_data = &spidev_chip_info, |
| 927 | }, |
| 928 | #endif |
| 929 | }; |
| 930 | |
| 931 | /* SPI (0) */ |
| 932 | static struct resource bfin_spi0_resource[] = { |
| 933 | [0] = { |
| 934 | .start = SPI0_REGBASE, |
| 935 | .end = SPI0_REGBASE + 0xFF, |
| 936 | .flags = IORESOURCE_MEM, |
| 937 | }, |
| 938 | [1] = { |
| 939 | .start = CH_SPI0, |
| 940 | .end = CH_SPI0, |
| 941 | .flags = IORESOURCE_DMA, |
| 942 | }, |
| 943 | [2] = { |
| 944 | .start = IRQ_SPI0, |
| 945 | .end = IRQ_SPI0, |
| 946 | .flags = IORESOURCE_IRQ, |
| 947 | } |
| 948 | }; |
| 949 | |
| 950 | /* SPI (1) */ |
| 951 | static struct resource bfin_spi1_resource[] = { |
| 952 | [0] = { |
| 953 | .start = SPI1_REGBASE, |
| 954 | .end = SPI1_REGBASE + 0xFF, |
| 955 | .flags = IORESOURCE_MEM, |
| 956 | }, |
| 957 | [1] = { |
| 958 | .start = CH_SPI1, |
| 959 | .end = CH_SPI1, |
| 960 | .flags = IORESOURCE_DMA, |
| 961 | }, |
| 962 | [2] = { |
| 963 | .start = IRQ_SPI1, |
| 964 | .end = IRQ_SPI1, |
| 965 | .flags = IORESOURCE_IRQ, |
| 966 | } |
| 967 | }; |
| 968 | |
| 969 | /* SPI controller data */ |
| 970 | static struct bfin5xx_spi_master bf54x_spi_master_info0 = { |
| 971 | .num_chipselect = 4, |
| 972 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
| 973 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
| 974 | }; |
| 975 | |
| 976 | static struct platform_device bf54x_spi_master0 = { |
| 977 | .name = "bfin-spi", |
| 978 | .id = 0, /* Bus number */ |
| 979 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), |
| 980 | .resource = bfin_spi0_resource, |
| 981 | .dev = { |
| 982 | .platform_data = &bf54x_spi_master_info0, /* Passed to driver */ |
| 983 | }, |
| 984 | }; |
| 985 | |
| 986 | static struct bfin5xx_spi_master bf54x_spi_master_info1 = { |
| 987 | .num_chipselect = 4, |
| 988 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
| 989 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, |
| 990 | }; |
| 991 | |
| 992 | static struct platform_device bf54x_spi_master1 = { |
| 993 | .name = "bfin-spi", |
| 994 | .id = 1, /* Bus number */ |
| 995 | .num_resources = ARRAY_SIZE(bfin_spi1_resource), |
| 996 | .resource = bfin_spi1_resource, |
| 997 | .dev = { |
| 998 | .platform_data = &bf54x_spi_master_info1, /* Passed to driver */ |
| 999 | }, |
| 1000 | }; |
| 1001 | #endif /* spi master and devices */ |
| 1002 | |
| 1003 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 1004 | static struct resource bfin_twi0_resource[] = { |
| 1005 | [0] = { |
| 1006 | .start = TWI0_REGBASE, |
| 1007 | .end = TWI0_REGBASE + 0xFF, |
| 1008 | .flags = IORESOURCE_MEM, |
| 1009 | }, |
| 1010 | [1] = { |
| 1011 | .start = IRQ_TWI0, |
| 1012 | .end = IRQ_TWI0, |
| 1013 | .flags = IORESOURCE_IRQ, |
| 1014 | }, |
| 1015 | }; |
| 1016 | |
| 1017 | static struct platform_device i2c_bfin_twi0_device = { |
| 1018 | .name = "i2c-bfin-twi", |
| 1019 | .id = 0, |
| 1020 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), |
| 1021 | .resource = bfin_twi0_resource, |
| 1022 | }; |
| 1023 | |
| 1024 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ |
| 1025 | static struct resource bfin_twi1_resource[] = { |
| 1026 | [0] = { |
| 1027 | .start = TWI1_REGBASE, |
| 1028 | .end = TWI1_REGBASE + 0xFF, |
| 1029 | .flags = IORESOURCE_MEM, |
| 1030 | }, |
| 1031 | [1] = { |
| 1032 | .start = IRQ_TWI1, |
| 1033 | .end = IRQ_TWI1, |
| 1034 | .flags = IORESOURCE_IRQ, |
| 1035 | }, |
| 1036 | }; |
| 1037 | |
| 1038 | static struct platform_device i2c_bfin_twi1_device = { |
| 1039 | .name = "i2c-bfin-twi", |
| 1040 | .id = 1, |
| 1041 | .num_resources = ARRAY_SIZE(bfin_twi1_resource), |
| 1042 | .resource = bfin_twi1_resource, |
| 1043 | }; |
| 1044 | #endif |
| 1045 | #endif |
| 1046 | |
| 1047 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
| 1048 | #include <linux/gpio_keys.h> |
| 1049 | |
| 1050 | static struct gpio_keys_button bfin_gpio_keys_table[] = { |
| 1051 | {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"}, |
| 1052 | }; |
| 1053 | |
| 1054 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { |
| 1055 | .buttons = bfin_gpio_keys_table, |
| 1056 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), |
| 1057 | }; |
| 1058 | |
| 1059 | static struct platform_device bfin_device_gpiokeys = { |
| 1060 | .name = "gpio-keys", |
| 1061 | .dev = { |
| 1062 | .platform_data = &bfin_gpio_keys_data, |
| 1063 | }, |
| 1064 | }; |
| 1065 | #endif |
| 1066 | |
| 1067 | static const unsigned int cclk_vlev_datasheet[] = |
| 1068 | { |
| 1069 | /* |
| 1070 | * Internal VLEV BF54XSBBC1533 |
| 1071 | ****temporarily using these values until data sheet is updated |
| 1072 | */ |
| 1073 | VRPAIR(VLEV_085, 150000000), |
| 1074 | VRPAIR(VLEV_090, 250000000), |
| 1075 | VRPAIR(VLEV_110, 276000000), |
| 1076 | VRPAIR(VLEV_115, 301000000), |
| 1077 | VRPAIR(VLEV_120, 525000000), |
| 1078 | VRPAIR(VLEV_125, 550000000), |
| 1079 | VRPAIR(VLEV_130, 600000000), |
| 1080 | }; |
| 1081 | |
| 1082 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { |
| 1083 | .tuple_tab = cclk_vlev_datasheet, |
| 1084 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), |
| 1085 | .vr_settling_time = 25 /* us */, |
| 1086 | }; |
| 1087 | |
| 1088 | static struct platform_device bfin_dpmc = { |
| 1089 | .name = "bfin dpmc", |
| 1090 | .dev = { |
| 1091 | .platform_data = &bfin_dmpc_vreg_data, |
| 1092 | }, |
| 1093 | }; |
| 1094 | |
| 1095 | static struct platform_device *cm_bf548_devices[] __initdata = { |
| 1096 | |
| 1097 | &bfin_dpmc, |
| 1098 | |
| 1099 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
| 1100 | &rtc_device, |
| 1101 | #endif |
| 1102 | |
| 1103 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
| 1104 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
| 1105 | &bfin_uart0_device, |
| 1106 | #endif |
| 1107 | #ifdef CONFIG_SERIAL_BFIN_UART1 |
| 1108 | &bfin_uart1_device, |
| 1109 | #endif |
| 1110 | #ifdef CONFIG_SERIAL_BFIN_UART2 |
| 1111 | &bfin_uart2_device, |
| 1112 | #endif |
| 1113 | #ifdef CONFIG_SERIAL_BFIN_UART3 |
| 1114 | &bfin_uart3_device, |
| 1115 | #endif |
| 1116 | #endif |
| 1117 | |
| 1118 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 1119 | #ifdef CONFIG_BFIN_SIR0 |
| 1120 | &bfin_sir0_device, |
| 1121 | #endif |
| 1122 | #ifdef CONFIG_BFIN_SIR1 |
| 1123 | &bfin_sir1_device, |
| 1124 | #endif |
| 1125 | #ifdef CONFIG_BFIN_SIR2 |
| 1126 | &bfin_sir2_device, |
| 1127 | #endif |
| 1128 | #ifdef CONFIG_BFIN_SIR3 |
| 1129 | &bfin_sir3_device, |
| 1130 | #endif |
| 1131 | #endif |
| 1132 | |
| 1133 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
| 1134 | &bf54x_lq043_device, |
| 1135 | #endif |
| 1136 | |
| 1137 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
| 1138 | &smsc911x_device, |
| 1139 | #endif |
| 1140 | |
| 1141 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
| 1142 | &musb_device, |
| 1143 | #endif |
| 1144 | |
| 1145 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
| 1146 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART |
| 1147 | &bfin_sport0_uart_device, |
| 1148 | #endif |
| 1149 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART |
| 1150 | &bfin_sport1_uart_device, |
| 1151 | #endif |
| 1152 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART |
| 1153 | &bfin_sport2_uart_device, |
| 1154 | #endif |
| 1155 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART |
| 1156 | &bfin_sport3_uart_device, |
| 1157 | #endif |
| 1158 | #endif |
| 1159 | |
| 1160 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
| 1161 | &bfin_atapi_device, |
| 1162 | #endif |
| 1163 | |
| 1164 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) |
| 1165 | &bf5xx_nand_device, |
| 1166 | #endif |
| 1167 | |
| 1168 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
| 1169 | &bf54x_sdh_device, |
| 1170 | #endif |
| 1171 | |
| 1172 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 1173 | &bf54x_spi_master0, |
| 1174 | &bf54x_spi_master1, |
| 1175 | #endif |
| 1176 | |
| 1177 | #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) |
| 1178 | &bf54x_kpad_device, |
| 1179 | #endif |
| 1180 | |
| 1181 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 1182 | &i2c_bfin_twi0_device, |
| 1183 | #if !defined(CONFIG_BF542) |
| 1184 | &i2c_bfin_twi1_device, |
| 1185 | #endif |
| 1186 | #endif |
| 1187 | |
| 1188 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
| 1189 | &bfin_device_gpiokeys, |
| 1190 | #endif |
| 1191 | |
| 1192 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
| 1193 | ¶_flash_device, |
| 1194 | #endif |
| 1195 | |
| 1196 | #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) |
| 1197 | &bfin_can_device, |
| 1198 | #endif |
| 1199 | |
| 1200 | }; |
| 1201 | |
| 1202 | static int __init cm_bf548_init(void) |
| 1203 | { |
| 1204 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
| 1205 | platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices)); |
| 1206 | |
| 1207 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 1208 | spi_register_board_info(bf54x_spi_board_info, |
| 1209 | ARRAY_SIZE(bf54x_spi_board_info)); |
| 1210 | #endif |
| 1211 | |
| 1212 | return 0; |
| 1213 | } |
| 1214 | |
| 1215 | arch_initcall(cm_bf548_init); |
| 1216 | |
| 1217 | static struct platform_device *cm_bf548_early_devices[] __initdata = { |
| 1218 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
| 1219 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
| 1220 | &bfin_uart0_device, |
| 1221 | #endif |
| 1222 | #ifdef CONFIG_SERIAL_BFIN_UART1 |
| 1223 | &bfin_uart1_device, |
| 1224 | #endif |
| 1225 | #ifdef CONFIG_SERIAL_BFIN_UART2 |
| 1226 | &bfin_uart2_device, |
| 1227 | #endif |
| 1228 | #ifdef CONFIG_SERIAL_BFIN_UART3 |
| 1229 | &bfin_uart3_device, |
| 1230 | #endif |
| 1231 | #endif |
| 1232 | |
| 1233 | #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) |
| 1234 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART |
| 1235 | &bfin_sport0_uart_device, |
| 1236 | #endif |
| 1237 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART |
| 1238 | &bfin_sport1_uart_device, |
| 1239 | #endif |
| 1240 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART |
| 1241 | &bfin_sport2_uart_device, |
| 1242 | #endif |
| 1243 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART |
| 1244 | &bfin_sport3_uart_device, |
| 1245 | #endif |
| 1246 | #endif |
| 1247 | }; |
| 1248 | |
| 1249 | void __init native_machine_early_platform_add_devices(void) |
| 1250 | { |
| 1251 | printk(KERN_INFO "register early platform devices\n"); |
| 1252 | early_platform_add_devices(cm_bf548_early_devices, |
| 1253 | ARRAY_SIZE(cm_bf548_early_devices)); |
| 1254 | } |