| 1 | /* |
| 2 | * file: include/asm-blackfin/mach-bf518/bfin_serial_5xx.h |
| 3 | * based on: |
| 4 | * author: |
| 5 | * |
| 6 | * created: |
| 7 | * description: |
| 8 | * blackfin serial driver head file |
| 9 | * rev: |
| 10 | * |
| 11 | * modified: |
| 12 | * |
| 13 | * |
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ |
| 15 | * |
| 16 | * this program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the gnu general public license as published by |
| 18 | * the free software foundation; either version 2, or (at your option) |
| 19 | * any later version. |
| 20 | * |
| 21 | * this program is distributed in the hope that it will be useful, |
| 22 | * but without any warranty; without even the implied warranty of |
| 23 | * merchantability or fitness for a particular purpose. see the |
| 24 | * gnu general public license for more details. |
| 25 | * |
| 26 | * you should have received a copy of the gnu general public license |
| 27 | * along with this program; see the file copying. |
| 28 | * if not, write to the free software foundation, |
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. |
| 30 | */ |
| 31 | |
| 32 | #include <linux/serial.h> |
| 33 | #include <asm/dma.h> |
| 34 | #include <asm/portmux.h> |
| 35 | |
| 36 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) |
| 37 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) |
| 38 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) |
| 39 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) |
| 40 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) |
| 41 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) |
| 42 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) |
| 43 | |
| 44 | #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) |
| 45 | #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) |
| 46 | #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) |
| 47 | #define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) |
| 48 | #define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) |
| 49 | #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) |
| 50 | #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) |
| 51 | #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) |
| 52 | |
| 53 | #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) |
| 54 | #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) |
| 55 | |
| 56 | #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) |
| 57 | #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) |
| 58 | #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) |
| 59 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) |
| 60 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) |
| 61 | |
| 62 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) |
| 63 | # define CONFIG_SERIAL_BFIN_CTSRTS |
| 64 | |
| 65 | # ifndef CONFIG_UART0_CTS_PIN |
| 66 | # define CONFIG_UART0_CTS_PIN -1 |
| 67 | # endif |
| 68 | |
| 69 | # ifndef CONFIG_UART0_RTS_PIN |
| 70 | # define CONFIG_UART0_RTS_PIN -1 |
| 71 | # endif |
| 72 | |
| 73 | # ifndef CONFIG_UART1_CTS_PIN |
| 74 | # define CONFIG_UART1_CTS_PIN -1 |
| 75 | # endif |
| 76 | |
| 77 | # ifndef CONFIG_UART1_RTS_PIN |
| 78 | # define CONFIG_UART1_RTS_PIN -1 |
| 79 | # endif |
| 80 | #endif |
| 81 | |
| 82 | #define BFIN_UART_TX_FIFO_SIZE 2 |
| 83 | |
| 84 | /* |
| 85 | * The pin configuration is different from schematic |
| 86 | */ |
| 87 | struct bfin_serial_port { |
| 88 | struct uart_port port; |
| 89 | unsigned int old_status; |
| 90 | int status_irq; |
| 91 | unsigned int lsr; |
| 92 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 93 | int tx_done; |
| 94 | int tx_count; |
| 95 | struct circ_buf rx_dma_buf; |
| 96 | struct timer_list rx_dma_timer; |
| 97 | int rx_dma_nrows; |
| 98 | unsigned int tx_dma_channel; |
| 99 | unsigned int rx_dma_channel; |
| 100 | struct work_struct tx_dma_workqueue; |
| 101 | #endif |
| 102 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 103 | struct timer_list cts_timer; |
| 104 | int cts_pin; |
| 105 | int rts_pin; |
| 106 | #endif |
| 107 | }; |
| 108 | |
| 109 | /* The hardware clears the LSR bits upon read, so we need to cache |
| 110 | * some of the more fun bits in software so they don't get lost |
| 111 | * when checking the LSR in other code paths (TX). |
| 112 | */ |
| 113 | static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) |
| 114 | { |
| 115 | unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); |
| 116 | uart->lsr |= (lsr & (BI|FE|PE|OE)); |
| 117 | return lsr | uart->lsr; |
| 118 | } |
| 119 | |
| 120 | static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) |
| 121 | { |
| 122 | uart->lsr = 0; |
| 123 | bfin_write16(uart->port.membase + OFFSET_LSR, -1); |
| 124 | } |
| 125 | |
| 126 | struct bfin_serial_res { |
| 127 | unsigned long uart_base_addr; |
| 128 | int uart_irq; |
| 129 | int uart_status_irq; |
| 130 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 131 | unsigned int uart_tx_dma_channel; |
| 132 | unsigned int uart_rx_dma_channel; |
| 133 | #endif |
| 134 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 135 | int uart_cts_pin; |
| 136 | int uart_rts_pin; |
| 137 | #endif |
| 138 | }; |
| 139 | |
| 140 | struct bfin_serial_res bfin_serial_resource[] = { |
| 141 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
| 142 | { |
| 143 | 0xFFC00400, |
| 144 | IRQ_UART0_RX, |
| 145 | IRQ_UART0_ERROR, |
| 146 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 147 | CH_UART0_TX, |
| 148 | CH_UART0_RX, |
| 149 | #endif |
| 150 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 151 | CONFIG_UART0_CTS_PIN, |
| 152 | CONFIG_UART0_RTS_PIN, |
| 153 | #endif |
| 154 | }, |
| 155 | #endif |
| 156 | #ifdef CONFIG_SERIAL_BFIN_UART1 |
| 157 | { |
| 158 | 0xFFC02000, |
| 159 | IRQ_UART1_RX, |
| 160 | IRQ_UART1_ERROR, |
| 161 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 162 | CH_UART1_TX, |
| 163 | CH_UART1_RX, |
| 164 | #endif |
| 165 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 166 | CONFIG_UART1_CTS_PIN, |
| 167 | CONFIG_UART1_RTS_PIN, |
| 168 | #endif |
| 169 | }, |
| 170 | #endif |
| 171 | }; |
| 172 | |
| 173 | #define DRIVER_NAME "bfin-uart" |