arm64: Add page size to the kernel image header
[linux-2.6-block.git] / arch / arm64 / Kconfig
... / ...
CommitLineData
1config ARM64
2 def_bool y
3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARM_AMBA
17 select ARM_ARCH_TIMER
18 select ARM_GIC
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
21 select ARM_GIC_V3
22 select ARM_GIC_V3_ITS if PCI_MSI
23 select ARM_PSCI_FW
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
26 select COMMON_CLK
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
29 select EDAC_SUPPORT
30 select GENERIC_ALLOCATOR
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CLOCKEVENTS_BROADCAST
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IDLE_POLL_SETUP
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select GENERIC_IRQ_SHOW_LEVEL
39 select GENERIC_PCI_IOMAP
40 select GENERIC_SCHED_CLOCK
41 select GENERIC_SMP_IDLE_THREAD
42 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
44 select GENERIC_TIME_VSYSCALL
45 select HANDLE_DOMAIN_IRQ
46 select HARDIRQS_SW_RESEND
47 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
48 select HAVE_ARCH_AUDITSYSCALL
49 select HAVE_ARCH_BITREVERSE
50 select HAVE_ARCH_JUMP_LABEL
51 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP
52 select HAVE_ARCH_KGDB
53 select HAVE_ARCH_SECCOMP_FILTER
54 select HAVE_ARCH_TRACEHOOK
55 select HAVE_BPF_JIT
56 select HAVE_C_RECORDMCOUNT
57 select HAVE_CC_STACKPROTECTOR
58 select HAVE_CMPXCHG_DOUBLE
59 select HAVE_CMPXCHG_LOCAL
60 select HAVE_DEBUG_BUGVERBOSE
61 select HAVE_DEBUG_KMEMLEAK
62 select HAVE_DMA_API_DEBUG
63 select HAVE_DMA_ATTRS
64 select HAVE_DMA_CONTIGUOUS
65 select HAVE_DYNAMIC_FTRACE
66 select HAVE_EFFICIENT_UNALIGNED_ACCESS
67 select HAVE_FTRACE_MCOUNT_RECORD
68 select HAVE_FUNCTION_TRACER
69 select HAVE_FUNCTION_GRAPH_TRACER
70 select HAVE_GENERIC_DMA_COHERENT
71 select HAVE_HW_BREAKPOINT if PERF_EVENTS
72 select HAVE_MEMBLOCK
73 select HAVE_PATA_PLATFORM
74 select HAVE_PERF_EVENTS
75 select HAVE_PERF_REGS
76 select HAVE_PERF_USER_STACK_DUMP
77 select HAVE_RCU_TABLE_FREE
78 select HAVE_SYSCALL_TRACEPOINTS
79 select IRQ_DOMAIN
80 select IRQ_FORCED_THREADING
81 select MODULES_USE_ELF_RELA
82 select NO_BOOTMEM
83 select OF
84 select OF_EARLY_FLATTREE
85 select OF_RESERVED_MEM
86 select PERF_USE_VMALLOC
87 select POWER_RESET
88 select POWER_SUPPLY
89 select RTC_LIB
90 select SPARSE_IRQ
91 select SYSCTL_EXCEPTION_TRACE
92 select HAVE_CONTEXT_TRACKING
93 help
94 ARM 64-bit (AArch64) Linux support.
95
96config 64BIT
97 def_bool y
98
99config ARCH_PHYS_ADDR_T_64BIT
100 def_bool y
101
102config MMU
103 def_bool y
104
105config NO_IOPORT_MAP
106 def_bool y if !PCI
107
108config STACKTRACE_SUPPORT
109 def_bool y
110
111config ILLEGAL_POINTER_VALUE
112 hex
113 default 0xdead000000000000
114
115config LOCKDEP_SUPPORT
116 def_bool y
117
118config TRACE_IRQFLAGS_SUPPORT
119 def_bool y
120
121config RWSEM_XCHGADD_ALGORITHM
122 def_bool y
123
124config GENERIC_BUG
125 def_bool y
126 depends on BUG
127
128config GENERIC_BUG_RELATIVE_POINTERS
129 def_bool y
130 depends on GENERIC_BUG
131
132config GENERIC_HWEIGHT
133 def_bool y
134
135config GENERIC_CSUM
136 def_bool y
137
138config GENERIC_CALIBRATE_DELAY
139 def_bool y
140
141config ZONE_DMA
142 def_bool y
143
144config HAVE_GENERIC_RCU_GUP
145 def_bool y
146
147config ARCH_DMA_ADDR_T_64BIT
148 def_bool y
149
150config NEED_DMA_MAP_STATE
151 def_bool y
152
153config NEED_SG_DMA_LENGTH
154 def_bool y
155
156config SMP
157 def_bool y
158
159config SWIOTLB
160 def_bool y
161
162config IOMMU_HELPER
163 def_bool SWIOTLB
164
165config KERNEL_MODE_NEON
166 def_bool y
167
168config FIX_EARLYCON_MEM
169 def_bool y
170
171config PGTABLE_LEVELS
172 int
173 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
174 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
175 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
176 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
177
178source "init/Kconfig"
179
180source "kernel/Kconfig.freezer"
181
182source "arch/arm64/Kconfig.platforms"
183
184menu "Bus support"
185
186config PCI
187 bool "PCI support"
188 help
189 This feature enables support for PCI bus system. If you say Y
190 here, the kernel will include drivers and infrastructure code
191 to support PCI bus devices.
192
193config PCI_DOMAINS
194 def_bool PCI
195
196config PCI_DOMAINS_GENERIC
197 def_bool PCI
198
199config PCI_SYSCALL
200 def_bool PCI
201
202source "drivers/pci/Kconfig"
203source "drivers/pci/pcie/Kconfig"
204source "drivers/pci/hotplug/Kconfig"
205
206endmenu
207
208menu "Kernel Features"
209
210menu "ARM errata workarounds via the alternatives framework"
211
212config ARM64_ERRATUM_826319
213 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
214 default y
215 help
216 This option adds an alternative code sequence to work around ARM
217 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
218 AXI master interface and an L2 cache.
219
220 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
221 and is unable to accept a certain write via this interface, it will
222 not progress on read data presented on the read data channel and the
223 system can deadlock.
224
225 The workaround promotes data cache clean instructions to
226 data cache clean-and-invalidate.
227 Please note that this does not necessarily enable the workaround,
228 as it depends on the alternative framework, which will only patch
229 the kernel if an affected CPU is detected.
230
231 If unsure, say Y.
232
233config ARM64_ERRATUM_827319
234 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
235 default y
236 help
237 This option adds an alternative code sequence to work around ARM
238 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
239 master interface and an L2 cache.
240
241 Under certain conditions this erratum can cause a clean line eviction
242 to occur at the same time as another transaction to the same address
243 on the AMBA 5 CHI interface, which can cause data corruption if the
244 interconnect reorders the two transactions.
245
246 The workaround promotes data cache clean instructions to
247 data cache clean-and-invalidate.
248 Please note that this does not necessarily enable the workaround,
249 as it depends on the alternative framework, which will only patch
250 the kernel if an affected CPU is detected.
251
252 If unsure, say Y.
253
254config ARM64_ERRATUM_824069
255 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
256 default y
257 help
258 This option adds an alternative code sequence to work around ARM
259 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
260 to a coherent interconnect.
261
262 If a Cortex-A53 processor is executing a store or prefetch for
263 write instruction at the same time as a processor in another
264 cluster is executing a cache maintenance operation to the same
265 address, then this erratum might cause a clean cache line to be
266 incorrectly marked as dirty.
267
268 The workaround promotes data cache clean instructions to
269 data cache clean-and-invalidate.
270 Please note that this option does not necessarily enable the
271 workaround, as it depends on the alternative framework, which will
272 only patch the kernel if an affected CPU is detected.
273
274 If unsure, say Y.
275
276config ARM64_ERRATUM_819472
277 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
278 default y
279 help
280 This option adds an alternative code sequence to work around ARM
281 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
282 present when it is connected to a coherent interconnect.
283
284 If the processor is executing a load and store exclusive sequence at
285 the same time as a processor in another cluster is executing a cache
286 maintenance operation to the same address, then this erratum might
287 cause data corruption.
288
289 The workaround promotes data cache clean instructions to
290 data cache clean-and-invalidate.
291 Please note that this does not necessarily enable the workaround,
292 as it depends on the alternative framework, which will only patch
293 the kernel if an affected CPU is detected.
294
295 If unsure, say Y.
296
297config ARM64_ERRATUM_832075
298 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
299 default y
300 help
301 This option adds an alternative code sequence to work around ARM
302 erratum 832075 on Cortex-A57 parts up to r1p2.
303
304 Affected Cortex-A57 parts might deadlock when exclusive load/store
305 instructions to Write-Back memory are mixed with Device loads.
306
307 The workaround is to promote device loads to use Load-Acquire
308 semantics.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
312
313 If unsure, say Y.
314
315config ARM64_ERRATUM_845719
316 bool "Cortex-A53: 845719: a load might read incorrect data"
317 depends on COMPAT
318 default y
319 help
320 This option adds an alternative code sequence to work around ARM
321 erratum 845719 on Cortex-A53 parts up to r0p4.
322
323 When running a compat (AArch32) userspace on an affected Cortex-A53
324 part, a load at EL0 from a virtual address that matches the bottom 32
325 bits of the virtual address used by a recent load at (AArch64) EL1
326 might return incorrect data.
327
328 The workaround is to write the contextidr_el1 register on exception
329 return to a 32-bit task.
330 Please note that this does not necessarily enable the workaround,
331 as it depends on the alternative framework, which will only patch
332 the kernel if an affected CPU is detected.
333
334 If unsure, say Y.
335
336config ARM64_ERRATUM_843419
337 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
338 depends on MODULES
339 default y
340 help
341 This option builds kernel modules using the large memory model in
342 order to avoid the use of the ADRP instruction, which can cause
343 a subsequent memory access to use an incorrect address on Cortex-A53
344 parts up to r0p4.
345
346 Note that the kernel itself must be linked with a version of ld
347 which fixes potentially affected ADRP instructions through the
348 use of veneers.
349
350 If unsure, say Y.
351
352endmenu
353
354
355choice
356 prompt "Page size"
357 default ARM64_4K_PAGES
358 help
359 Page size (translation granule) configuration.
360
361config ARM64_4K_PAGES
362 bool "4KB"
363 help
364 This feature enables 4KB pages support.
365
366config ARM64_64K_PAGES
367 bool "64KB"
368 help
369 This feature enables 64KB pages support (4KB by default)
370 allowing only two levels of page tables and faster TLB
371 look-up. AArch32 emulation requires applications compiled
372 with 64K aligned segments.
373
374endchoice
375
376choice
377 prompt "Virtual address space size"
378 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
379 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
380 help
381 Allows choosing one of multiple possible virtual address
382 space sizes. The level of translation table is determined by
383 a combination of page size and virtual address space size.
384
385config ARM64_VA_BITS_39
386 bool "39-bit"
387 depends on ARM64_4K_PAGES
388
389config ARM64_VA_BITS_42
390 bool "42-bit"
391 depends on ARM64_64K_PAGES
392
393config ARM64_VA_BITS_48
394 bool "48-bit"
395
396endchoice
397
398config ARM64_VA_BITS
399 int
400 default 39 if ARM64_VA_BITS_39
401 default 42 if ARM64_VA_BITS_42
402 default 48 if ARM64_VA_BITS_48
403
404config CPU_BIG_ENDIAN
405 bool "Build big-endian kernel"
406 help
407 Say Y if you plan on running a kernel in big-endian mode.
408
409config SCHED_MC
410 bool "Multi-core scheduler support"
411 help
412 Multi-core scheduler support improves the CPU scheduler's decision
413 making when dealing with multi-core CPU chips at a cost of slightly
414 increased overhead in some places. If unsure say N here.
415
416config SCHED_SMT
417 bool "SMT scheduler support"
418 help
419 Improves the CPU scheduler's decision making when dealing with
420 MultiThreading at a cost of slightly increased overhead in some
421 places. If unsure say N here.
422
423config NR_CPUS
424 int "Maximum number of CPUs (2-4096)"
425 range 2 4096
426 # These have to remain sorted largest to smallest
427 default "64"
428
429config HOTPLUG_CPU
430 bool "Support for hot-pluggable CPUs"
431 select GENERIC_IRQ_MIGRATION
432 help
433 Say Y here to experiment with turning CPUs off and on. CPUs
434 can be controlled through /sys/devices/system/cpu.
435
436source kernel/Kconfig.preempt
437
438config HZ
439 int
440 default 100
441
442config ARCH_HAS_HOLES_MEMORYMODEL
443 def_bool y if SPARSEMEM
444
445config ARCH_SPARSEMEM_ENABLE
446 def_bool y
447 select SPARSEMEM_VMEMMAP_ENABLE
448
449config ARCH_SPARSEMEM_DEFAULT
450 def_bool ARCH_SPARSEMEM_ENABLE
451
452config ARCH_SELECT_MEMORY_MODEL
453 def_bool ARCH_SPARSEMEM_ENABLE
454
455config HAVE_ARCH_PFN_VALID
456 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
457
458config HW_PERF_EVENTS
459 def_bool y
460 depends on ARM_PMU
461
462config SYS_SUPPORTS_HUGETLBFS
463 def_bool y
464
465config ARCH_WANT_GENERAL_HUGETLB
466 def_bool y
467
468config ARCH_WANT_HUGE_PMD_SHARE
469 def_bool y if ARM64_4K_PAGES
470
471config HAVE_ARCH_TRANSPARENT_HUGEPAGE
472 def_bool y
473
474config ARCH_HAS_CACHE_LINE_SIZE
475 def_bool y
476
477source "mm/Kconfig"
478
479config SECCOMP
480 bool "Enable seccomp to safely compute untrusted bytecode"
481 ---help---
482 This kernel feature is useful for number crunching applications
483 that may need to compute untrusted bytecode during their
484 execution. By using pipes or other transports made available to
485 the process as file descriptors supporting the read/write
486 syscalls, it's possible to isolate those applications in
487 their own address space using seccomp. Once seccomp is
488 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
489 and the task is only allowed to execute a few safe syscalls
490 defined by each seccomp mode.
491
492config XEN_DOM0
493 def_bool y
494 depends on XEN
495
496config XEN
497 bool "Xen guest support on ARM64"
498 depends on ARM64 && OF
499 select SWIOTLB_XEN
500 help
501 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
502
503config FORCE_MAX_ZONEORDER
504 int
505 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
506 default "11"
507
508menuconfig ARMV8_DEPRECATED
509 bool "Emulate deprecated/obsolete ARMv8 instructions"
510 depends on COMPAT
511 help
512 Legacy software support may require certain instructions
513 that have been deprecated or obsoleted in the architecture.
514
515 Enable this config to enable selective emulation of these
516 features.
517
518 If unsure, say Y
519
520if ARMV8_DEPRECATED
521
522config SWP_EMULATION
523 bool "Emulate SWP/SWPB instructions"
524 help
525 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
526 they are always undefined. Say Y here to enable software
527 emulation of these instructions for userspace using LDXR/STXR.
528
529 In some older versions of glibc [<=2.8] SWP is used during futex
530 trylock() operations with the assumption that the code will not
531 be preempted. This invalid assumption may be more likely to fail
532 with SWP emulation enabled, leading to deadlock of the user
533 application.
534
535 NOTE: when accessing uncached shared regions, LDXR/STXR rely
536 on an external transaction monitoring block called a global
537 monitor to maintain update atomicity. If your system does not
538 implement a global monitor, this option can cause programs that
539 perform SWP operations to uncached memory to deadlock.
540
541 If unsure, say Y
542
543config CP15_BARRIER_EMULATION
544 bool "Emulate CP15 Barrier instructions"
545 help
546 The CP15 barrier instructions - CP15ISB, CP15DSB, and
547 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
548 strongly recommended to use the ISB, DSB, and DMB
549 instructions instead.
550
551 Say Y here to enable software emulation of these
552 instructions for AArch32 userspace code. When this option is
553 enabled, CP15 barrier usage is traced which can help
554 identify software that needs updating.
555
556 If unsure, say Y
557
558config SETEND_EMULATION
559 bool "Emulate SETEND instruction"
560 help
561 The SETEND instruction alters the data-endianness of the
562 AArch32 EL0, and is deprecated in ARMv8.
563
564 Say Y here to enable software emulation of the instruction
565 for AArch32 userspace code.
566
567 Note: All the cpus on the system must have mixed endian support at EL0
568 for this feature to be enabled. If a new CPU - which doesn't support mixed
569 endian - is hotplugged in after this feature has been enabled, there could
570 be unexpected results in the applications.
571
572 If unsure, say Y
573endif
574
575menu "ARMv8.1 architectural features"
576
577config ARM64_HW_AFDBM
578 bool "Support for hardware updates of the Access and Dirty page flags"
579 default y
580 help
581 The ARMv8.1 architecture extensions introduce support for
582 hardware updates of the access and dirty information in page
583 table entries. When enabled in TCR_EL1 (HA and HD bits) on
584 capable processors, accesses to pages with PTE_AF cleared will
585 set this bit instead of raising an access flag fault.
586 Similarly, writes to read-only pages with the DBM bit set will
587 clear the read-only bit (AP[2]) instead of raising a
588 permission fault.
589
590 Kernels built with this configuration option enabled continue
591 to work on pre-ARMv8.1 hardware and the performance impact is
592 minimal. If unsure, say Y.
593
594config ARM64_PAN
595 bool "Enable support for Privileged Access Never (PAN)"
596 default y
597 help
598 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
599 prevents the kernel or hypervisor from accessing user-space (EL0)
600 memory directly.
601
602 Choosing this option will cause any unprotected (not using
603 copy_to_user et al) memory access to fail with a permission fault.
604
605 The feature is detected at runtime, and will remain as a 'nop'
606 instruction if the cpu does not implement the feature.
607
608config ARM64_LSE_ATOMICS
609 bool "Atomic instructions"
610 help
611 As part of the Large System Extensions, ARMv8.1 introduces new
612 atomic instructions that are designed specifically to scale in
613 very large systems.
614
615 Say Y here to make use of these instructions for the in-kernel
616 atomic routines. This incurs a small overhead on CPUs that do
617 not support these instructions and requires the kernel to be
618 built with binutils >= 2.25.
619
620endmenu
621
622endmenu
623
624menu "Boot options"
625
626config CMDLINE
627 string "Default kernel command string"
628 default ""
629 help
630 Provide a set of default command-line options at build time by
631 entering them here. As a minimum, you should specify the the
632 root device (e.g. root=/dev/nfs).
633
634config CMDLINE_FORCE
635 bool "Always use the default kernel command string"
636 help
637 Always use the default kernel command string, even if the boot
638 loader passes other arguments to the kernel.
639 This is useful if you cannot or don't want to change the
640 command-line options your boot loader passes to the kernel.
641
642config EFI_STUB
643 bool
644
645config EFI
646 bool "UEFI runtime support"
647 depends on OF && !CPU_BIG_ENDIAN
648 select LIBFDT
649 select UCS2_STRING
650 select EFI_PARAMS_FROM_FDT
651 select EFI_RUNTIME_WRAPPERS
652 select EFI_STUB
653 select EFI_ARMSTUB
654 default y
655 help
656 This option provides support for runtime services provided
657 by UEFI firmware (such as non-volatile variables, realtime
658 clock, and platform reset). A UEFI stub is also provided to
659 allow the kernel to be booted as an EFI application. This
660 is only useful on systems that have UEFI firmware.
661
662config DMI
663 bool "Enable support for SMBIOS (DMI) tables"
664 depends on EFI
665 default y
666 help
667 This enables SMBIOS/DMI feature for systems.
668
669 This option is only useful on systems that have UEFI firmware.
670 However, even with this option, the resultant kernel should
671 continue to boot on existing non-UEFI platforms.
672
673endmenu
674
675menu "Userspace binary formats"
676
677source "fs/Kconfig.binfmt"
678
679config COMPAT
680 bool "Kernel support for 32-bit EL0"
681 depends on ARM64_4K_PAGES || EXPERT
682 select COMPAT_BINFMT_ELF
683 select HAVE_UID16
684 select OLD_SIGSUSPEND3
685 select COMPAT_OLD_SIGACTION
686 help
687 This option enables support for a 32-bit EL0 running under a 64-bit
688 kernel at EL1. AArch32-specific components such as system calls,
689 the user helper functions, VFP support and the ptrace interface are
690 handled appropriately by the kernel.
691
692 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
693 will only be able to execute AArch32 binaries that were compiled with
694 64k aligned segments.
695
696 If you want to execute 32-bit userspace applications, say Y.
697
698config SYSVIPC_COMPAT
699 def_bool y
700 depends on COMPAT && SYSVIPC
701
702endmenu
703
704menu "Power management options"
705
706source "kernel/power/Kconfig"
707
708config ARCH_SUSPEND_POSSIBLE
709 def_bool y
710
711endmenu
712
713menu "CPU Power Management"
714
715source "drivers/cpuidle/Kconfig"
716
717source "drivers/cpufreq/Kconfig"
718
719endmenu
720
721source "net/Kconfig"
722
723source "drivers/Kconfig"
724
725source "drivers/firmware/Kconfig"
726
727source "drivers/acpi/Kconfig"
728
729source "fs/Kconfig"
730
731source "arch/arm64/kvm/Kconfig"
732
733source "arch/arm64/Kconfig.debug"
734
735source "security/Kconfig"
736
737source "crypto/Kconfig"
738if CRYPTO
739source "arch/arm64/crypto/Kconfig"
740endif
741
742source "lib/Kconfig"