| 1 | /* |
| 2 | * TI DaVinci Power and Sleep Controller (PSC) |
| 3 | * |
| 4 | * Copyright (C) 2006 Texas Instruments. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | * |
| 20 | */ |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/io.h> |
| 24 | |
| 25 | #include <mach/cputype.h> |
| 26 | #include <mach/psc.h> |
| 27 | |
| 28 | #include "clock.h" |
| 29 | |
| 30 | /* Return nonzero iff the domain's clock is active */ |
| 31 | int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) |
| 32 | { |
| 33 | void __iomem *psc_base; |
| 34 | u32 mdstat; |
| 35 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 36 | |
| 37 | if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { |
| 38 | pr_warning("PSC: Bad psc data: 0x%x[%d]\n", |
| 39 | (int)soc_info->psc_bases, ctlr); |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); |
| 44 | mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); |
| 45 | iounmap(psc_base); |
| 46 | |
| 47 | /* if clocked, state can be "Enable" or "SyncReset" */ |
| 48 | return mdstat & BIT(12); |
| 49 | } |
| 50 | |
| 51 | /* Enable or disable a PSC domain */ |
| 52 | void davinci_psc_config(unsigned int domain, unsigned int ctlr, |
| 53 | unsigned int id, bool enable, u32 flags) |
| 54 | { |
| 55 | u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; |
| 56 | void __iomem *psc_base; |
| 57 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 58 | u32 next_state = PSC_STATE_ENABLE; |
| 59 | |
| 60 | if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { |
| 61 | pr_warning("PSC: Bad psc data: 0x%x[%d]\n", |
| 62 | (int)soc_info->psc_bases, ctlr); |
| 63 | return; |
| 64 | } |
| 65 | |
| 66 | psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); |
| 67 | |
| 68 | if (!enable) { |
| 69 | if (flags & PSC_SWRSTDISABLE) |
| 70 | next_state = PSC_STATE_SWRSTDISABLE; |
| 71 | else |
| 72 | next_state = PSC_STATE_DISABLE; |
| 73 | } |
| 74 | |
| 75 | mdctl = __raw_readl(psc_base + MDCTL + 4 * id); |
| 76 | mdctl &= ~MDSTAT_STATE_MASK; |
| 77 | mdctl |= next_state; |
| 78 | if (flags & PSC_FORCE) |
| 79 | mdctl |= MDCTL_FORCE; |
| 80 | __raw_writel(mdctl, psc_base + MDCTL + 4 * id); |
| 81 | |
| 82 | pdstat = __raw_readl(psc_base + PDSTAT); |
| 83 | if ((pdstat & 0x00000001) == 0) { |
| 84 | pdctl1 = __raw_readl(psc_base + PDCTL1); |
| 85 | pdctl1 |= 0x1; |
| 86 | __raw_writel(pdctl1, psc_base + PDCTL1); |
| 87 | |
| 88 | ptcmd = 1 << domain; |
| 89 | __raw_writel(ptcmd, psc_base + PTCMD); |
| 90 | |
| 91 | do { |
| 92 | epcpr = __raw_readl(psc_base + EPCPR); |
| 93 | } while ((((epcpr >> domain) & 1) == 0)); |
| 94 | |
| 95 | pdctl1 = __raw_readl(psc_base + PDCTL1); |
| 96 | pdctl1 |= 0x100; |
| 97 | __raw_writel(pdctl1, psc_base + PDCTL1); |
| 98 | } else { |
| 99 | ptcmd = 1 << domain; |
| 100 | __raw_writel(ptcmd, psc_base + PTCMD); |
| 101 | } |
| 102 | |
| 103 | do { |
| 104 | ptstat = __raw_readl(psc_base + PTSTAT); |
| 105 | } while (!(((ptstat >> domain) & 1) == 0)); |
| 106 | |
| 107 | do { |
| 108 | mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); |
| 109 | } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); |
| 110 | |
| 111 | iounmap(psc_base); |
| 112 | } |