| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | #include <dt-bindings/clock/tegra30-car.h> |
| 3 | #include <dt-bindings/gpio/tegra-gpio.h> |
| 4 | #include <dt-bindings/memory/tegra30-mc.h> |
| 5 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
| 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 7 | #include <dt-bindings/soc/tegra-pmc.h> |
| 8 | |
| 9 | / { |
| 10 | compatible = "nvidia,tegra30"; |
| 11 | interrupt-parent = <&lic>; |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; |
| 14 | |
| 15 | memory@80000000 { |
| 16 | device_type = "memory"; |
| 17 | reg = <0x80000000 0x0>; |
| 18 | }; |
| 19 | |
| 20 | pcie@3000 { |
| 21 | compatible = "nvidia,tegra30-pcie"; |
| 22 | device_type = "pci"; |
| 23 | reg = <0x00003000 0x00000800>, /* PADS registers */ |
| 24 | <0x00003800 0x00000200>, /* AFI registers */ |
| 25 | <0x10000000 0x10000000>; /* configuration space */ |
| 26 | reg-names = "pads", "afi", "cs"; |
| 27 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ |
| 28 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| 29 | interrupt-names = "intr", "msi"; |
| 30 | |
| 31 | #interrupt-cells = <1>; |
| 32 | interrupt-map-mask = <0 0 0 0>; |
| 33 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 34 | |
| 35 | bus-range = <0x00 0xff>; |
| 36 | #address-cells = <3>; |
| 37 | #size-cells = <2>; |
| 38 | |
| 39 | ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ |
| 40 | <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ |
| 41 | <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ |
| 42 | <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ |
| 43 | <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ |
| 44 | <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ |
| 45 | |
| 46 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, |
| 47 | <&tegra_car TEGRA30_CLK_AFI>, |
| 48 | <&tegra_car TEGRA30_CLK_PLL_E>, |
| 49 | <&tegra_car TEGRA30_CLK_CML0>; |
| 50 | clock-names = "pex", "afi", "pll_e", "cml"; |
| 51 | resets = <&tegra_car 70>, |
| 52 | <&tegra_car 72>, |
| 53 | <&tegra_car 74>; |
| 54 | reset-names = "pex", "afi", "pcie_x"; |
| 55 | status = "disabled"; |
| 56 | |
| 57 | pci@1,0 { |
| 58 | device_type = "pci"; |
| 59 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; |
| 60 | reg = <0x000800 0 0 0 0>; |
| 61 | bus-range = <0x00 0xff>; |
| 62 | status = "disabled"; |
| 63 | |
| 64 | #address-cells = <3>; |
| 65 | #size-cells = <2>; |
| 66 | ranges; |
| 67 | |
| 68 | nvidia,num-lanes = <2>; |
| 69 | }; |
| 70 | |
| 71 | pci@2,0 { |
| 72 | device_type = "pci"; |
| 73 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; |
| 74 | reg = <0x001000 0 0 0 0>; |
| 75 | bus-range = <0x00 0xff>; |
| 76 | status = "disabled"; |
| 77 | |
| 78 | #address-cells = <3>; |
| 79 | #size-cells = <2>; |
| 80 | ranges; |
| 81 | |
| 82 | nvidia,num-lanes = <2>; |
| 83 | }; |
| 84 | |
| 85 | pci@3,0 { |
| 86 | device_type = "pci"; |
| 87 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; |
| 88 | reg = <0x001800 0 0 0 0>; |
| 89 | bus-range = <0x00 0xff>; |
| 90 | status = "disabled"; |
| 91 | |
| 92 | #address-cells = <3>; |
| 93 | #size-cells = <2>; |
| 94 | ranges; |
| 95 | |
| 96 | nvidia,num-lanes = <2>; |
| 97 | }; |
| 98 | }; |
| 99 | |
| 100 | sram@40000000 { |
| 101 | compatible = "mmio-sram"; |
| 102 | reg = <0x40000000 0x40000>; |
| 103 | #address-cells = <1>; |
| 104 | #size-cells = <1>; |
| 105 | ranges = <0 0x40000000 0x40000>; |
| 106 | |
| 107 | vde_pool: sram@400 { |
| 108 | reg = <0x400 0x3fc00>; |
| 109 | pool; |
| 110 | }; |
| 111 | }; |
| 112 | |
| 113 | host1x@50000000 { |
| 114 | compatible = "nvidia,tegra30-host1x"; |
| 115 | reg = <0x50000000 0x00024000>; |
| 116 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 117 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
| 118 | interrupt-names = "syncpt", "host1x"; |
| 119 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
| 120 | clock-names = "host1x"; |
| 121 | resets = <&tegra_car 28>; |
| 122 | reset-names = "host1x"; |
| 123 | iommus = <&mc TEGRA_SWGROUP_HC>; |
| 124 | |
| 125 | #address-cells = <1>; |
| 126 | #size-cells = <1>; |
| 127 | |
| 128 | ranges = <0x54000000 0x54000000 0x04000000>; |
| 129 | |
| 130 | mpe@54040000 { |
| 131 | compatible = "nvidia,tegra30-mpe"; |
| 132 | reg = <0x54040000 0x00040000>; |
| 133 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| 134 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
| 135 | resets = <&tegra_car 60>; |
| 136 | reset-names = "mpe"; |
| 137 | |
| 138 | iommus = <&mc TEGRA_SWGROUP_MPE>; |
| 139 | }; |
| 140 | |
| 141 | vi@54080000 { |
| 142 | compatible = "nvidia,tegra30-vi"; |
| 143 | reg = <0x54080000 0x00040000>; |
| 144 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 145 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
| 146 | resets = <&tegra_car 20>; |
| 147 | reset-names = "vi"; |
| 148 | |
| 149 | iommus = <&mc TEGRA_SWGROUP_VI>; |
| 150 | }; |
| 151 | |
| 152 | epp@540c0000 { |
| 153 | compatible = "nvidia,tegra30-epp"; |
| 154 | reg = <0x540c0000 0x00040000>; |
| 155 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 156 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
| 157 | resets = <&tegra_car 19>; |
| 158 | reset-names = "epp"; |
| 159 | |
| 160 | iommus = <&mc TEGRA_SWGROUP_EPP>; |
| 161 | }; |
| 162 | |
| 163 | isp@54100000 { |
| 164 | compatible = "nvidia,tegra30-isp"; |
| 165 | reg = <0x54100000 0x00040000>; |
| 166 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 167 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
| 168 | resets = <&tegra_car 23>; |
| 169 | reset-names = "isp"; |
| 170 | |
| 171 | iommus = <&mc TEGRA_SWGROUP_ISP>; |
| 172 | }; |
| 173 | |
| 174 | gr2d@54140000 { |
| 175 | compatible = "nvidia,tegra30-gr2d"; |
| 176 | reg = <0x54140000 0x00040000>; |
| 177 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
| 179 | resets = <&tegra_car 21>; |
| 180 | reset-names = "2d"; |
| 181 | |
| 182 | iommus = <&mc TEGRA_SWGROUP_G2>; |
| 183 | }; |
| 184 | |
| 185 | gr3d@54180000 { |
| 186 | compatible = "nvidia,tegra30-gr3d"; |
| 187 | reg = <0x54180000 0x00040000>; |
| 188 | clocks = <&tegra_car TEGRA30_CLK_GR3D>, |
| 189 | <&tegra_car TEGRA30_CLK_GR3D2>; |
| 190 | clock-names = "3d", "3d2"; |
| 191 | resets = <&tegra_car 24>, |
| 192 | <&tegra_car 98>; |
| 193 | reset-names = "3d", "3d2"; |
| 194 | |
| 195 | iommus = <&mc TEGRA_SWGROUP_NV>, |
| 196 | <&mc TEGRA_SWGROUP_NV2>; |
| 197 | }; |
| 198 | |
| 199 | dc@54200000 { |
| 200 | compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; |
| 201 | reg = <0x54200000 0x00040000>; |
| 202 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 203 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
| 204 | <&tegra_car TEGRA30_CLK_PLL_P>; |
| 205 | clock-names = "dc", "parent"; |
| 206 | resets = <&tegra_car 27>; |
| 207 | reset-names = "dc"; |
| 208 | |
| 209 | iommus = <&mc TEGRA_SWGROUP_DC>; |
| 210 | |
| 211 | nvidia,head = <0>; |
| 212 | |
| 213 | rgb { |
| 214 | status = "disabled"; |
| 215 | }; |
| 216 | }; |
| 217 | |
| 218 | dc@54240000 { |
| 219 | compatible = "nvidia,tegra30-dc"; |
| 220 | reg = <0x54240000 0x00040000>; |
| 221 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 222 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
| 223 | <&tegra_car TEGRA30_CLK_PLL_P>; |
| 224 | clock-names = "dc", "parent"; |
| 225 | resets = <&tegra_car 26>; |
| 226 | reset-names = "dc"; |
| 227 | |
| 228 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
| 229 | |
| 230 | nvidia,head = <1>; |
| 231 | |
| 232 | rgb { |
| 233 | status = "disabled"; |
| 234 | }; |
| 235 | }; |
| 236 | |
| 237 | hdmi@54280000 { |
| 238 | compatible = "nvidia,tegra30-hdmi"; |
| 239 | reg = <0x54280000 0x00040000>; |
| 240 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 241 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
| 242 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; |
| 243 | clock-names = "hdmi", "parent"; |
| 244 | resets = <&tegra_car 51>; |
| 245 | reset-names = "hdmi"; |
| 246 | status = "disabled"; |
| 247 | }; |
| 248 | |
| 249 | tvo@542c0000 { |
| 250 | compatible = "nvidia,tegra30-tvo"; |
| 251 | reg = <0x542c0000 0x00040000>; |
| 252 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 253 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
| 257 | dsi@54300000 { |
| 258 | compatible = "nvidia,tegra30-dsi"; |
| 259 | reg = <0x54300000 0x00040000>; |
| 260 | clocks = <&tegra_car TEGRA30_CLK_DSIA>, |
| 261 | <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; |
| 262 | clock-names = "dsi", "parent"; |
| 263 | resets = <&tegra_car 48>; |
| 264 | reset-names = "dsi"; |
| 265 | status = "disabled"; |
| 266 | }; |
| 267 | }; |
| 268 | |
| 269 | timer@50040600 { |
| 270 | compatible = "arm,cortex-a9-twd-timer"; |
| 271 | reg = <0x50040600 0x20>; |
| 272 | interrupt-parent = <&intc>; |
| 273 | interrupts = <GIC_PPI 13 |
| 274 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
| 275 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
| 276 | }; |
| 277 | |
| 278 | intc: interrupt-controller@50041000 { |
| 279 | compatible = "arm,cortex-a9-gic"; |
| 280 | reg = <0x50041000 0x1000>, |
| 281 | <0x50040100 0x0100>; |
| 282 | interrupt-controller; |
| 283 | #interrupt-cells = <3>; |
| 284 | interrupt-parent = <&intc>; |
| 285 | }; |
| 286 | |
| 287 | cache-controller@50043000 { |
| 288 | compatible = "arm,pl310-cache"; |
| 289 | reg = <0x50043000 0x1000>; |
| 290 | arm,data-latency = <6 6 2>; |
| 291 | arm,tag-latency = <5 5 2>; |
| 292 | cache-unified; |
| 293 | cache-level = <2>; |
| 294 | }; |
| 295 | |
| 296 | lic: interrupt-controller@60004000 { |
| 297 | compatible = "nvidia,tegra30-ictlr"; |
| 298 | reg = <0x60004000 0x100>, |
| 299 | <0x60004100 0x50>, |
| 300 | <0x60004200 0x50>, |
| 301 | <0x60004300 0x50>, |
| 302 | <0x60004400 0x50>; |
| 303 | interrupt-controller; |
| 304 | #interrupt-cells = <3>; |
| 305 | interrupt-parent = <&intc>; |
| 306 | }; |
| 307 | |
| 308 | timer@60005000 { |
| 309 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
| 310 | reg = <0x60005000 0x400>; |
| 311 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 312 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 313 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 314 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 315 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 316 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
| 317 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
| 318 | }; |
| 319 | |
| 320 | tegra_car: clock@60006000 { |
| 321 | compatible = "nvidia,tegra30-car"; |
| 322 | reg = <0x60006000 0x1000>; |
| 323 | #clock-cells = <1>; |
| 324 | #reset-cells = <1>; |
| 325 | }; |
| 326 | |
| 327 | flow-controller@60007000 { |
| 328 | compatible = "nvidia,tegra30-flowctrl"; |
| 329 | reg = <0x60007000 0x1000>; |
| 330 | }; |
| 331 | |
| 332 | apbdma: dma@6000a000 { |
| 333 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| 334 | reg = <0x6000a000 0x1400>; |
| 335 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 336 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 337 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 338 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 339 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 340 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 341 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 342 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 343 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 344 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 345 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 346 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 347 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 348 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 349 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 350 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 351 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 352 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 353 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 354 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 355 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 356 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 357 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 358 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 359 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 360 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 361 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 362 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 363 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 364 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 365 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 366 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 367 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
| 368 | resets = <&tegra_car 34>; |
| 369 | reset-names = "dma"; |
| 370 | #dma-cells = <1>; |
| 371 | }; |
| 372 | |
| 373 | ahb: ahb@6000c000 { |
| 374 | compatible = "nvidia,tegra30-ahb"; |
| 375 | reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ |
| 376 | }; |
| 377 | |
| 378 | actmon@6000c800 { |
| 379 | compatible = "nvidia,tegra30-actmon"; |
| 380 | reg = <0x6000c800 0x400>; |
| 381 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 382 | clocks = <&tegra_car TEGRA30_CLK_ACTMON>, |
| 383 | <&tegra_car TEGRA30_CLK_EMC>; |
| 384 | clock-names = "actmon", "emc"; |
| 385 | resets = <&tegra_car TEGRA30_CLK_ACTMON>; |
| 386 | reset-names = "actmon"; |
| 387 | }; |
| 388 | |
| 389 | gpio: gpio@6000d000 { |
| 390 | compatible = "nvidia,tegra30-gpio"; |
| 391 | reg = <0x6000d000 0x1000>; |
| 392 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 393 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 394 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 395 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 396 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 397 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 398 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 399 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| 400 | #gpio-cells = <2>; |
| 401 | gpio-controller; |
| 402 | #interrupt-cells = <2>; |
| 403 | interrupt-controller; |
| 404 | /* |
| 405 | gpio-ranges = <&pinmux 0 0 248>; |
| 406 | */ |
| 407 | }; |
| 408 | |
| 409 | vde@6001a000 { |
| 410 | compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; |
| 411 | reg = <0x6001a000 0x1000>, /* Syntax Engine */ |
| 412 | <0x6001b000 0x1000>, /* Video Bitstream Engine */ |
| 413 | <0x6001c000 0x100>, /* Macroblock Engine */ |
| 414 | <0x6001c200 0x100>, /* Post-processing Engine */ |
| 415 | <0x6001c400 0x100>, /* Motion Compensation Engine */ |
| 416 | <0x6001c600 0x100>, /* Transform Engine */ |
| 417 | <0x6001c800 0x100>, /* Pixel prediction block */ |
| 418 | <0x6001ca00 0x100>, /* Video DMA */ |
| 419 | <0x6001d800 0x400>; /* Video frame controls */ |
| 420 | reg-names = "sxe", "bsev", "mbe", "ppe", "mce", |
| 421 | "tfe", "ppb", "vdma", "frameid"; |
| 422 | iram = <&vde_pool>; /* IRAM region */ |
| 423 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ |
| 424 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ |
| 425 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ |
| 426 | interrupt-names = "sync-token", "bsev", "sxe"; |
| 427 | clocks = <&tegra_car TEGRA30_CLK_VDE>; |
| 428 | reset-names = "vde", "mc"; |
| 429 | resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; |
| 430 | iommus = <&mc TEGRA_SWGROUP_VDE>; |
| 431 | }; |
| 432 | |
| 433 | apbmisc@70000800 { |
| 434 | compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; |
| 435 | reg = <0x70000800 0x64>, /* Chip revision */ |
| 436 | <0x70000008 0x04>; /* Strapping options */ |
| 437 | }; |
| 438 | |
| 439 | pinmux: pinmux@70000868 { |
| 440 | compatible = "nvidia,tegra30-pinmux"; |
| 441 | reg = <0x70000868 0x0d4>, /* Pad control registers */ |
| 442 | <0x70003000 0x3e4>; /* Mux registers */ |
| 443 | }; |
| 444 | |
| 445 | /* |
| 446 | * There are two serial driver i.e. 8250 based simple serial |
| 447 | * driver and APB DMA based serial driver for higher baudrate |
| 448 | * and performace. To enable the 8250 based driver, the compatible |
| 449 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable |
| 450 | * the APB DMA based serial driver, the compatible is |
| 451 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
| 452 | */ |
| 453 | uarta: serial@70006000 { |
| 454 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 455 | reg = <0x70006000 0x40>; |
| 456 | reg-shift = <2>; |
| 457 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 458 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
| 459 | resets = <&tegra_car 6>; |
| 460 | reset-names = "serial"; |
| 461 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 462 | dma-names = "rx", "tx"; |
| 463 | status = "disabled"; |
| 464 | }; |
| 465 | |
| 466 | uartb: serial@70006040 { |
| 467 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 468 | reg = <0x70006040 0x40>; |
| 469 | reg-shift = <2>; |
| 470 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 471 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
| 472 | resets = <&tegra_car 7>; |
| 473 | reset-names = "serial"; |
| 474 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 475 | dma-names = "rx", "tx"; |
| 476 | status = "disabled"; |
| 477 | }; |
| 478 | |
| 479 | uartc: serial@70006200 { |
| 480 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 481 | reg = <0x70006200 0x100>; |
| 482 | reg-shift = <2>; |
| 483 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 484 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
| 485 | resets = <&tegra_car 55>; |
| 486 | reset-names = "serial"; |
| 487 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 488 | dma-names = "rx", "tx"; |
| 489 | status = "disabled"; |
| 490 | }; |
| 491 | |
| 492 | uartd: serial@70006300 { |
| 493 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 494 | reg = <0x70006300 0x100>; |
| 495 | reg-shift = <2>; |
| 496 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| 497 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
| 498 | resets = <&tegra_car 65>; |
| 499 | reset-names = "serial"; |
| 500 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 501 | dma-names = "rx", "tx"; |
| 502 | status = "disabled"; |
| 503 | }; |
| 504 | |
| 505 | uarte: serial@70006400 { |
| 506 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 507 | reg = <0x70006400 0x100>; |
| 508 | reg-shift = <2>; |
| 509 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 510 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
| 511 | resets = <&tegra_car 66>; |
| 512 | reset-names = "serial"; |
| 513 | dmas = <&apbdma 20>, <&apbdma 20>; |
| 514 | dma-names = "rx", "tx"; |
| 515 | status = "disabled"; |
| 516 | }; |
| 517 | |
| 518 | gmi@70009000 { |
| 519 | compatible = "nvidia,tegra30-gmi"; |
| 520 | reg = <0x70009000 0x1000>; |
| 521 | #address-cells = <2>; |
| 522 | #size-cells = <1>; |
| 523 | ranges = <0 0 0x48000000 0x7ffffff>; |
| 524 | clocks = <&tegra_car TEGRA30_CLK_NOR>; |
| 525 | clock-names = "gmi"; |
| 526 | resets = <&tegra_car 42>; |
| 527 | reset-names = "gmi"; |
| 528 | status = "disabled"; |
| 529 | }; |
| 530 | |
| 531 | pwm: pwm@7000a000 { |
| 532 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
| 533 | reg = <0x7000a000 0x100>; |
| 534 | #pwm-cells = <2>; |
| 535 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
| 536 | resets = <&tegra_car 17>; |
| 537 | reset-names = "pwm"; |
| 538 | status = "disabled"; |
| 539 | }; |
| 540 | |
| 541 | rtc@7000e000 { |
| 542 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| 543 | reg = <0x7000e000 0x100>; |
| 544 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 545 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
| 546 | }; |
| 547 | |
| 548 | i2c@7000c000 { |
| 549 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 550 | reg = <0x7000c000 0x100>; |
| 551 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 552 | #address-cells = <1>; |
| 553 | #size-cells = <0>; |
| 554 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
| 555 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
| 556 | clock-names = "div-clk", "fast-clk"; |
| 557 | resets = <&tegra_car 12>; |
| 558 | reset-names = "i2c"; |
| 559 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 560 | dma-names = "rx", "tx"; |
| 561 | status = "disabled"; |
| 562 | }; |
| 563 | |
| 564 | i2c@7000c400 { |
| 565 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 566 | reg = <0x7000c400 0x100>; |
| 567 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 568 | #address-cells = <1>; |
| 569 | #size-cells = <0>; |
| 570 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
| 571 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
| 572 | clock-names = "div-clk", "fast-clk"; |
| 573 | resets = <&tegra_car 54>; |
| 574 | reset-names = "i2c"; |
| 575 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 576 | dma-names = "rx", "tx"; |
| 577 | status = "disabled"; |
| 578 | }; |
| 579 | |
| 580 | i2c@7000c500 { |
| 581 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 582 | reg = <0x7000c500 0x100>; |
| 583 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 584 | #address-cells = <1>; |
| 585 | #size-cells = <0>; |
| 586 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
| 587 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
| 588 | clock-names = "div-clk", "fast-clk"; |
| 589 | resets = <&tegra_car 67>; |
| 590 | reset-names = "i2c"; |
| 591 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 592 | dma-names = "rx", "tx"; |
| 593 | status = "disabled"; |
| 594 | }; |
| 595 | |
| 596 | i2c@7000c700 { |
| 597 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 598 | reg = <0x7000c700 0x100>; |
| 599 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 600 | #address-cells = <1>; |
| 601 | #size-cells = <0>; |
| 602 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
| 603 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
| 604 | resets = <&tegra_car 103>; |
| 605 | reset-names = "i2c"; |
| 606 | clock-names = "div-clk", "fast-clk"; |
| 607 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 608 | dma-names = "rx", "tx"; |
| 609 | status = "disabled"; |
| 610 | }; |
| 611 | |
| 612 | i2c@7000d000 { |
| 613 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 614 | reg = <0x7000d000 0x100>; |
| 615 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 616 | #address-cells = <1>; |
| 617 | #size-cells = <0>; |
| 618 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
| 619 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; |
| 620 | clock-names = "div-clk", "fast-clk"; |
| 621 | resets = <&tegra_car 47>; |
| 622 | reset-names = "i2c"; |
| 623 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 624 | dma-names = "rx", "tx"; |
| 625 | status = "disabled"; |
| 626 | }; |
| 627 | |
| 628 | spi@7000d400 { |
| 629 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 630 | reg = <0x7000d400 0x200>; |
| 631 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 632 | #address-cells = <1>; |
| 633 | #size-cells = <0>; |
| 634 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
| 635 | resets = <&tegra_car 41>; |
| 636 | reset-names = "spi"; |
| 637 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 638 | dma-names = "rx", "tx"; |
| 639 | status = "disabled"; |
| 640 | }; |
| 641 | |
| 642 | spi@7000d600 { |
| 643 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 644 | reg = <0x7000d600 0x200>; |
| 645 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 646 | #address-cells = <1>; |
| 647 | #size-cells = <0>; |
| 648 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
| 649 | resets = <&tegra_car 44>; |
| 650 | reset-names = "spi"; |
| 651 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 652 | dma-names = "rx", "tx"; |
| 653 | status = "disabled"; |
| 654 | }; |
| 655 | |
| 656 | spi@7000d800 { |
| 657 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 658 | reg = <0x7000d800 0x200>; |
| 659 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 660 | #address-cells = <1>; |
| 661 | #size-cells = <0>; |
| 662 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
| 663 | resets = <&tegra_car 46>; |
| 664 | reset-names = "spi"; |
| 665 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 666 | dma-names = "rx", "tx"; |
| 667 | status = "disabled"; |
| 668 | }; |
| 669 | |
| 670 | spi@7000da00 { |
| 671 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 672 | reg = <0x7000da00 0x200>; |
| 673 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 674 | #address-cells = <1>; |
| 675 | #size-cells = <0>; |
| 676 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
| 677 | resets = <&tegra_car 68>; |
| 678 | reset-names = "spi"; |
| 679 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 680 | dma-names = "rx", "tx"; |
| 681 | status = "disabled"; |
| 682 | }; |
| 683 | |
| 684 | spi@7000dc00 { |
| 685 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 686 | reg = <0x7000dc00 0x200>; |
| 687 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 688 | #address-cells = <1>; |
| 689 | #size-cells = <0>; |
| 690 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
| 691 | resets = <&tegra_car 104>; |
| 692 | reset-names = "spi"; |
| 693 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 694 | dma-names = "rx", "tx"; |
| 695 | status = "disabled"; |
| 696 | }; |
| 697 | |
| 698 | spi@7000de00 { |
| 699 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 700 | reg = <0x7000de00 0x200>; |
| 701 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 702 | #address-cells = <1>; |
| 703 | #size-cells = <0>; |
| 704 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
| 705 | resets = <&tegra_car 106>; |
| 706 | reset-names = "spi"; |
| 707 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 708 | dma-names = "rx", "tx"; |
| 709 | status = "disabled"; |
| 710 | }; |
| 711 | |
| 712 | kbc@7000e200 { |
| 713 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
| 714 | reg = <0x7000e200 0x100>; |
| 715 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 716 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
| 717 | resets = <&tegra_car 36>; |
| 718 | reset-names = "kbc"; |
| 719 | status = "disabled"; |
| 720 | }; |
| 721 | |
| 722 | tegra_pmc: pmc@7000e400 { |
| 723 | compatible = "nvidia,tegra30-pmc"; |
| 724 | reg = <0x7000e400 0x400>; |
| 725 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
| 726 | clock-names = "pclk", "clk32k_in"; |
| 727 | #clock-cells = <1>; |
| 728 | }; |
| 729 | |
| 730 | mc: memory-controller@7000f000 { |
| 731 | compatible = "nvidia,tegra30-mc"; |
| 732 | reg = <0x7000f000 0x400>; |
| 733 | clocks = <&tegra_car TEGRA30_CLK_MC>; |
| 734 | clock-names = "mc"; |
| 735 | |
| 736 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 737 | |
| 738 | #iommu-cells = <1>; |
| 739 | #reset-cells = <1>; |
| 740 | }; |
| 741 | |
| 742 | memory-controller@7000f400 { |
| 743 | compatible = "nvidia,tegra30-emc"; |
| 744 | reg = <0x7000f400 0x400>; |
| 745 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 746 | clocks = <&tegra_car TEGRA30_CLK_EMC>; |
| 747 | |
| 748 | nvidia,memory-controller = <&mc>; |
| 749 | }; |
| 750 | |
| 751 | fuse@7000f800 { |
| 752 | compatible = "nvidia,tegra30-efuse"; |
| 753 | reg = <0x7000f800 0x400>; |
| 754 | clocks = <&tegra_car TEGRA30_CLK_FUSE>; |
| 755 | clock-names = "fuse"; |
| 756 | resets = <&tegra_car 39>; |
| 757 | reset-names = "fuse"; |
| 758 | }; |
| 759 | |
| 760 | hda@70030000 { |
| 761 | compatible = "nvidia,tegra30-hda"; |
| 762 | reg = <0x70030000 0x10000>; |
| 763 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 764 | clocks = <&tegra_car TEGRA30_CLK_HDA>, |
| 765 | <&tegra_car TEGRA30_CLK_HDA2HDMI>, |
| 766 | <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; |
| 767 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; |
| 768 | resets = <&tegra_car 125>, /* hda */ |
| 769 | <&tegra_car 128>, /* hda2hdmi */ |
| 770 | <&tegra_car 111>; /* hda2codec_2x */ |
| 771 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; |
| 772 | status = "disabled"; |
| 773 | }; |
| 774 | |
| 775 | ahub@70080000 { |
| 776 | compatible = "nvidia,tegra30-ahub"; |
| 777 | reg = <0x70080000 0x200>, |
| 778 | <0x70080200 0x100>; |
| 779 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 780 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
| 781 | <&tegra_car TEGRA30_CLK_APBIF>; |
| 782 | clock-names = "d_audio", "apbif"; |
| 783 | resets = <&tegra_car 106>, /* d_audio */ |
| 784 | <&tegra_car 107>, /* apbif */ |
| 785 | <&tegra_car 30>, /* i2s0 */ |
| 786 | <&tegra_car 11>, /* i2s1 */ |
| 787 | <&tegra_car 18>, /* i2s2 */ |
| 788 | <&tegra_car 101>, /* i2s3 */ |
| 789 | <&tegra_car 102>, /* i2s4 */ |
| 790 | <&tegra_car 108>, /* dam0 */ |
| 791 | <&tegra_car 109>, /* dam1 */ |
| 792 | <&tegra_car 110>, /* dam2 */ |
| 793 | <&tegra_car 10>; /* spdif */ |
| 794 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 795 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 796 | "spdif"; |
| 797 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 798 | <&apbdma 2>, <&apbdma 2>, |
| 799 | <&apbdma 3>, <&apbdma 3>, |
| 800 | <&apbdma 4>, <&apbdma 4>; |
| 801 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 802 | "rx3", "tx3"; |
| 803 | ranges; |
| 804 | #address-cells = <1>; |
| 805 | #size-cells = <1>; |
| 806 | |
| 807 | tegra_i2s0: i2s@70080300 { |
| 808 | compatible = "nvidia,tegra30-i2s"; |
| 809 | reg = <0x70080300 0x100>; |
| 810 | nvidia,ahub-cif-ids = <4 4>; |
| 811 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
| 812 | resets = <&tegra_car 30>; |
| 813 | reset-names = "i2s"; |
| 814 | status = "disabled"; |
| 815 | }; |
| 816 | |
| 817 | tegra_i2s1: i2s@70080400 { |
| 818 | compatible = "nvidia,tegra30-i2s"; |
| 819 | reg = <0x70080400 0x100>; |
| 820 | nvidia,ahub-cif-ids = <5 5>; |
| 821 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
| 822 | resets = <&tegra_car 11>; |
| 823 | reset-names = "i2s"; |
| 824 | status = "disabled"; |
| 825 | }; |
| 826 | |
| 827 | tegra_i2s2: i2s@70080500 { |
| 828 | compatible = "nvidia,tegra30-i2s"; |
| 829 | reg = <0x70080500 0x100>; |
| 830 | nvidia,ahub-cif-ids = <6 6>; |
| 831 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
| 832 | resets = <&tegra_car 18>; |
| 833 | reset-names = "i2s"; |
| 834 | status = "disabled"; |
| 835 | }; |
| 836 | |
| 837 | tegra_i2s3: i2s@70080600 { |
| 838 | compatible = "nvidia,tegra30-i2s"; |
| 839 | reg = <0x70080600 0x100>; |
| 840 | nvidia,ahub-cif-ids = <7 7>; |
| 841 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
| 842 | resets = <&tegra_car 101>; |
| 843 | reset-names = "i2s"; |
| 844 | status = "disabled"; |
| 845 | }; |
| 846 | |
| 847 | tegra_i2s4: i2s@70080700 { |
| 848 | compatible = "nvidia,tegra30-i2s"; |
| 849 | reg = <0x70080700 0x100>; |
| 850 | nvidia,ahub-cif-ids = <8 8>; |
| 851 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
| 852 | resets = <&tegra_car 102>; |
| 853 | reset-names = "i2s"; |
| 854 | status = "disabled"; |
| 855 | }; |
| 856 | }; |
| 857 | |
| 858 | mmc@78000000 { |
| 859 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 860 | reg = <0x78000000 0x200>; |
| 861 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 862 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
| 863 | clock-names = "sdhci"; |
| 864 | resets = <&tegra_car 14>; |
| 865 | reset-names = "sdhci"; |
| 866 | status = "disabled"; |
| 867 | }; |
| 868 | |
| 869 | mmc@78000200 { |
| 870 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 871 | reg = <0x78000200 0x200>; |
| 872 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 873 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
| 874 | clock-names = "sdhci"; |
| 875 | resets = <&tegra_car 9>; |
| 876 | reset-names = "sdhci"; |
| 877 | status = "disabled"; |
| 878 | }; |
| 879 | |
| 880 | mmc@78000400 { |
| 881 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 882 | reg = <0x78000400 0x200>; |
| 883 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 884 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
| 885 | clock-names = "sdhci"; |
| 886 | resets = <&tegra_car 69>; |
| 887 | reset-names = "sdhci"; |
| 888 | status = "disabled"; |
| 889 | }; |
| 890 | |
| 891 | mmc@78000600 { |
| 892 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 893 | reg = <0x78000600 0x200>; |
| 894 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 895 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
| 896 | clock-names = "sdhci"; |
| 897 | resets = <&tegra_car 15>; |
| 898 | reset-names = "sdhci"; |
| 899 | status = "disabled"; |
| 900 | }; |
| 901 | |
| 902 | usb@7d000000 { |
| 903 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 904 | reg = <0x7d000000 0x4000>; |
| 905 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 906 | phy_type = "utmi"; |
| 907 | clocks = <&tegra_car TEGRA30_CLK_USBD>; |
| 908 | resets = <&tegra_car 22>; |
| 909 | reset-names = "usb"; |
| 910 | nvidia,needs-double-reset; |
| 911 | nvidia,phy = <&phy1>; |
| 912 | status = "disabled"; |
| 913 | }; |
| 914 | |
| 915 | phy1: usb-phy@7d000000 { |
| 916 | compatible = "nvidia,tegra30-usb-phy"; |
| 917 | reg = <0x7d000000 0x4000>, |
| 918 | <0x7d000000 0x4000>; |
| 919 | phy_type = "utmi"; |
| 920 | clocks = <&tegra_car TEGRA30_CLK_USBD>, |
| 921 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 922 | <&tegra_car TEGRA30_CLK_USBD>; |
| 923 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 924 | resets = <&tegra_car 22>, <&tegra_car 22>; |
| 925 | reset-names = "usb", "utmi-pads"; |
| 926 | #phy-cells = <0>; |
| 927 | nvidia,hssync-start-delay = <9>; |
| 928 | nvidia,idle-wait-delay = <17>; |
| 929 | nvidia,elastic-limit = <16>; |
| 930 | nvidia,term-range-adj = <6>; |
| 931 | nvidia,xcvr-setup = <51>; |
| 932 | nvidia,xcvr-setup-use-fuses; |
| 933 | nvidia,xcvr-lsfslew = <1>; |
| 934 | nvidia,xcvr-lsrslew = <1>; |
| 935 | nvidia,xcvr-hsslew = <32>; |
| 936 | nvidia,hssquelch-level = <2>; |
| 937 | nvidia,hsdiscon-level = <5>; |
| 938 | nvidia,has-utmi-pad-registers; |
| 939 | status = "disabled"; |
| 940 | }; |
| 941 | |
| 942 | usb@7d004000 { |
| 943 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 944 | reg = <0x7d004000 0x4000>; |
| 945 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 946 | phy_type = "utmi"; |
| 947 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
| 948 | resets = <&tegra_car 58>; |
| 949 | reset-names = "usb"; |
| 950 | nvidia,phy = <&phy2>; |
| 951 | status = "disabled"; |
| 952 | }; |
| 953 | |
| 954 | phy2: usb-phy@7d004000 { |
| 955 | compatible = "nvidia,tegra30-usb-phy"; |
| 956 | reg = <0x7d004000 0x4000>, |
| 957 | <0x7d000000 0x4000>; |
| 958 | phy_type = "utmi"; |
| 959 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
| 960 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 961 | <&tegra_car TEGRA30_CLK_USBD>; |
| 962 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 963 | resets = <&tegra_car 58>, <&tegra_car 22>; |
| 964 | reset-names = "usb", "utmi-pads"; |
| 965 | #phy-cells = <0>; |
| 966 | nvidia,hssync-start-delay = <9>; |
| 967 | nvidia,idle-wait-delay = <17>; |
| 968 | nvidia,elastic-limit = <16>; |
| 969 | nvidia,term-range-adj = <6>; |
| 970 | nvidia,xcvr-setup = <51>; |
| 971 | nvidia,xcvr-setup-use-fuses; |
| 972 | nvidia,xcvr-lsfslew = <2>; |
| 973 | nvidia,xcvr-lsrslew = <2>; |
| 974 | nvidia,xcvr-hsslew = <32>; |
| 975 | nvidia,hssquelch-level = <2>; |
| 976 | nvidia,hsdiscon-level = <5>; |
| 977 | status = "disabled"; |
| 978 | }; |
| 979 | |
| 980 | usb@7d008000 { |
| 981 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 982 | reg = <0x7d008000 0x4000>; |
| 983 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 984 | phy_type = "utmi"; |
| 985 | clocks = <&tegra_car TEGRA30_CLK_USB3>; |
| 986 | resets = <&tegra_car 59>; |
| 987 | reset-names = "usb"; |
| 988 | nvidia,phy = <&phy3>; |
| 989 | status = "disabled"; |
| 990 | }; |
| 991 | |
| 992 | phy3: usb-phy@7d008000 { |
| 993 | compatible = "nvidia,tegra30-usb-phy"; |
| 994 | reg = <0x7d008000 0x4000>, |
| 995 | <0x7d000000 0x4000>; |
| 996 | phy_type = "utmi"; |
| 997 | clocks = <&tegra_car TEGRA30_CLK_USB3>, |
| 998 | <&tegra_car TEGRA30_CLK_PLL_U>, |
| 999 | <&tegra_car TEGRA30_CLK_USBD>; |
| 1000 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 1001 | resets = <&tegra_car 59>, <&tegra_car 22>; |
| 1002 | reset-names = "usb", "utmi-pads"; |
| 1003 | #phy-cells = <0>; |
| 1004 | nvidia,hssync-start-delay = <0>; |
| 1005 | nvidia,idle-wait-delay = <17>; |
| 1006 | nvidia,elastic-limit = <16>; |
| 1007 | nvidia,term-range-adj = <6>; |
| 1008 | nvidia,xcvr-setup = <51>; |
| 1009 | nvidia,xcvr-setup-use-fuses; |
| 1010 | nvidia,xcvr-lsfslew = <2>; |
| 1011 | nvidia,xcvr-lsrslew = <2>; |
| 1012 | nvidia,xcvr-hsslew = <32>; |
| 1013 | nvidia,hssquelch-level = <2>; |
| 1014 | nvidia,hsdiscon-level = <5>; |
| 1015 | status = "disabled"; |
| 1016 | }; |
| 1017 | |
| 1018 | cpus { |
| 1019 | #address-cells = <1>; |
| 1020 | #size-cells = <0>; |
| 1021 | |
| 1022 | cpu@0 { |
| 1023 | device_type = "cpu"; |
| 1024 | compatible = "arm,cortex-a9"; |
| 1025 | reg = <0>; |
| 1026 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
| 1027 | }; |
| 1028 | |
| 1029 | cpu@1 { |
| 1030 | device_type = "cpu"; |
| 1031 | compatible = "arm,cortex-a9"; |
| 1032 | reg = <1>; |
| 1033 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
| 1034 | }; |
| 1035 | |
| 1036 | cpu@2 { |
| 1037 | device_type = "cpu"; |
| 1038 | compatible = "arm,cortex-a9"; |
| 1039 | reg = <2>; |
| 1040 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
| 1041 | }; |
| 1042 | |
| 1043 | cpu@3 { |
| 1044 | device_type = "cpu"; |
| 1045 | compatible = "arm,cortex-a9"; |
| 1046 | reg = <3>; |
| 1047 | clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; |
| 1048 | }; |
| 1049 | }; |
| 1050 | |
| 1051 | pmu { |
| 1052 | compatible = "arm,cortex-a9-pmu"; |
| 1053 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| 1054 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| 1055 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| 1056 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
| 1057 | interrupt-affinity = <&{/cpus/cpu@0}>, |
| 1058 | <&{/cpus/cpu@1}>, |
| 1059 | <&{/cpus/cpu@2}>, |
| 1060 | <&{/cpus/cpu@3}>; |
| 1061 | }; |
| 1062 | }; |