| 1 | #ifndef ARCH_PPC_H |
| 2 | #define ARCH_PPH_H |
| 3 | |
| 4 | #include <unistd.h> |
| 5 | #include <stdlib.h> |
| 6 | #include <sys/types.h> |
| 7 | #include <sys/wait.h> |
| 8 | |
| 9 | #define FIO_ARCH (arch_ppc) |
| 10 | |
| 11 | #ifndef __NR_ioprio_set |
| 12 | #define __NR_ioprio_set 273 |
| 13 | #define __NR_ioprio_get 274 |
| 14 | #endif |
| 15 | |
| 16 | #ifndef __NR_fadvise64 |
| 17 | #define __NR_fadvise64 233 |
| 18 | #endif |
| 19 | |
| 20 | #ifndef __NR_sys_splice |
| 21 | #define __NR_sys_splice 283 |
| 22 | #define __NR_sys_tee 284 |
| 23 | #define __NR_sys_vmsplice 285 |
| 24 | #endif |
| 25 | |
| 26 | #define nop do { } while (0) |
| 27 | |
| 28 | #ifdef __powerpc64__ |
| 29 | #define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory") |
| 30 | #else |
| 31 | #define read_barrier() __asm__ __volatile__ ("sync" : : : "memory") |
| 32 | #endif |
| 33 | |
| 34 | #define write_barrier() __asm__ __volatile__ ("sync" : : : "memory") |
| 35 | |
| 36 | static inline int __ilog2(unsigned long bitmask) |
| 37 | { |
| 38 | int lz; |
| 39 | |
| 40 | asm ("cntlzw %0,%1" : "=r" (lz) : "r" (bitmask)); |
| 41 | return 31 - lz; |
| 42 | } |
| 43 | |
| 44 | static inline int arch_ffz(unsigned long bitmask) |
| 45 | { |
| 46 | if ((bitmask = ~bitmask) == 0) |
| 47 | return 32; |
| 48 | return __ilog2(bitmask & -bitmask); |
| 49 | } |
| 50 | |
| 51 | static inline unsigned int mfspr(unsigned int reg) |
| 52 | { |
| 53 | unsigned int val; |
| 54 | |
| 55 | asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg)); |
| 56 | return val; |
| 57 | } |
| 58 | |
| 59 | #define SPRN_TBRL 0x10C /* Time Base Register Lower */ |
| 60 | #define SPRN_TBRU 0x10D /* Time Base Register Upper */ |
| 61 | #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ |
| 62 | #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ |
| 63 | |
| 64 | static inline unsigned long long get_cpu_clock(void) |
| 65 | { |
| 66 | unsigned int tbl, tbu0, tbu1; |
| 67 | unsigned long long ret; |
| 68 | |
| 69 | do { |
| 70 | if (arch_flags & ARCH_FLAG_1) { |
| 71 | tbu0 = mfspr(SPRN_ATBU); |
| 72 | tbl = mfspr(SPRN_ATBL); |
| 73 | tbu1 = mfspr(SPRN_ATBU); |
| 74 | } else { |
| 75 | tbu0 = mfspr(SPRN_TBRU); |
| 76 | tbl = mfspr(SPRN_TBRL); |
| 77 | tbu1 = mfspr(SPRN_TBRU); |
| 78 | } |
| 79 | } while (tbu0 != tbu1); |
| 80 | |
| 81 | ret = (((unsigned long long)tbu0) << 32) | tbl; |
| 82 | return ret; |
| 83 | } |
| 84 | |
| 85 | static void atb_child(void) |
| 86 | { |
| 87 | arch_flags |= ARCH_FLAG_1; |
| 88 | get_cpu_clock(); |
| 89 | _exit(0); |
| 90 | } |
| 91 | |
| 92 | static void atb_clocktest(void) |
| 93 | { |
| 94 | pid_t pid; |
| 95 | |
| 96 | pid = fork(); |
| 97 | if (!pid) |
| 98 | atb_child(); |
| 99 | else if (pid != -1) { |
| 100 | int status; |
| 101 | |
| 102 | pid = wait(&status); |
| 103 | if (pid == -1 || !WIFEXITED(status)) |
| 104 | arch_flags &= ~ARCH_FLAG_1; |
| 105 | else |
| 106 | arch_flags |= ARCH_FLAG_1; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | #define ARCH_HAVE_INIT |
| 111 | extern int tsc_reliable; |
| 112 | |
| 113 | static inline int arch_init(char *envp[]) |
| 114 | { |
| 115 | tsc_reliable = 1; |
| 116 | atb_clocktest(); |
| 117 | return 0; |
| 118 | } |
| 119 | |
| 120 | #define ARCH_HAVE_FFZ |
| 121 | #define ARCH_HAVE_CPU_CLOCK |
| 122 | |
| 123 | #endif |