Commit | Line | Data |
---|---|---|
1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
3 | * | |
4 | * MandrakeSoft S.A. | |
5 | * 43, rue d'Aboukir | |
6 | * 75002 Paris - France | |
7 | * http://www.linux-mandrake.com/ | |
8 | * http://www.mandrakesoft.com/ | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
25 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
26 | * Based on Xen 3.1 code. | |
27 | */ | |
28 | ||
edf88417 | 29 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
30 | #include <linux/kvm.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/highmem.h> | |
33 | #include <linux/smp.h> | |
34 | #include <linux/hrtimer.h> | |
35 | #include <linux/io.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1fd4f2a5 | 37 | #include <asm/processor.h> |
1fd4f2a5 ED |
38 | #include <asm/page.h> |
39 | #include <asm/current.h> | |
1000ff8d | 40 | #include <trace/events/kvm.h> |
82470196 ZX |
41 | |
42 | #include "ioapic.h" | |
43 | #include "lapic.h" | |
f5244726 | 44 | #include "irq.h" |
82470196 | 45 | |
e25e3ed5 LV |
46 | #if 0 |
47 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
48 | #else | |
1fd4f2a5 | 49 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 50 | #endif |
ff4b9df8 | 51 | static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq); |
1fd4f2a5 ED |
52 | |
53 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
54 | unsigned long addr, | |
55 | unsigned long length) | |
56 | { | |
57 | unsigned long result = 0; | |
58 | ||
59 | switch (ioapic->ioregsel) { | |
60 | case IOAPIC_REG_VERSION: | |
61 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
62 | | (IOAPIC_VERSION_ID & 0xff)); | |
63 | break; | |
64 | ||
65 | case IOAPIC_REG_APIC_ID: | |
66 | case IOAPIC_REG_ARB_ID: | |
67 | result = ((ioapic->id & 0xf) << 24); | |
68 | break; | |
69 | ||
70 | default: | |
71 | { | |
72 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
73 | u64 redir_content; | |
74 | ||
75 | ASSERT(redir_index < IOAPIC_NUM_PINS); | |
76 | ||
77 | redir_content = ioapic->redirtbl[redir_index].bits; | |
78 | result = (ioapic->ioregsel & 0x1) ? | |
79 | (redir_content >> 32) & 0xffffffff : | |
80 | redir_content & 0xffffffff; | |
81 | break; | |
82 | } | |
83 | } | |
84 | ||
85 | return result; | |
86 | } | |
87 | ||
4925663a | 88 | static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx) |
1fd4f2a5 | 89 | { |
cf9e4e15 | 90 | union kvm_ioapic_redirect_entry *pent; |
4925663a | 91 | int injected = -1; |
1fd4f2a5 ED |
92 | |
93 | pent = &ioapic->redirtbl[idx]; | |
94 | ||
95 | if (!pent->fields.mask) { | |
4925663a | 96 | injected = ioapic_deliver(ioapic, idx); |
ff4b9df8 | 97 | if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG) |
1fd4f2a5 ED |
98 | pent->fields.remote_irr = 1; |
99 | } | |
4925663a GN |
100 | |
101 | return injected; | |
1fd4f2a5 ED |
102 | } |
103 | ||
46a929bc AK |
104 | static void update_handled_vectors(struct kvm_ioapic *ioapic) |
105 | { | |
106 | DECLARE_BITMAP(handled_vectors, 256); | |
107 | int i; | |
108 | ||
109 | memset(handled_vectors, 0, sizeof(handled_vectors)); | |
110 | for (i = 0; i < IOAPIC_NUM_PINS; ++i) | |
111 | __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors); | |
112 | memcpy(ioapic->handled_vectors, handled_vectors, | |
113 | sizeof(handled_vectors)); | |
114 | smp_wmb(); | |
115 | } | |
116 | ||
1fd4f2a5 ED |
117 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
118 | { | |
119 | unsigned index; | |
75858a84 | 120 | bool mask_before, mask_after; |
70f93dae | 121 | union kvm_ioapic_redirect_entry *e; |
1fd4f2a5 ED |
122 | |
123 | switch (ioapic->ioregsel) { | |
124 | case IOAPIC_REG_VERSION: | |
125 | /* Writes are ignored. */ | |
126 | break; | |
127 | ||
128 | case IOAPIC_REG_APIC_ID: | |
129 | ioapic->id = (val >> 24) & 0xf; | |
130 | break; | |
131 | ||
132 | case IOAPIC_REG_ARB_ID: | |
133 | break; | |
134 | ||
135 | default: | |
136 | index = (ioapic->ioregsel - 0x10) >> 1; | |
137 | ||
e25e3ed5 | 138 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
139 | if (index >= IOAPIC_NUM_PINS) |
140 | return; | |
70f93dae GN |
141 | e = &ioapic->redirtbl[index]; |
142 | mask_before = e->fields.mask; | |
1fd4f2a5 | 143 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
144 | e->bits &= 0xffffffff; |
145 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 146 | } else { |
70f93dae GN |
147 | e->bits &= ~0xffffffffULL; |
148 | e->bits |= (u32) val; | |
149 | e->fields.remote_irr = 0; | |
1fd4f2a5 | 150 | } |
46a929bc | 151 | update_handled_vectors(ioapic); |
70f93dae | 152 | mask_after = e->fields.mask; |
75858a84 AK |
153 | if (mask_before != mask_after) |
154 | kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after); | |
70f93dae | 155 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG |
b4a2f5e7 | 156 | && ioapic->irr & (1 << index)) |
1fd4f2a5 ED |
157 | ioapic_service(ioapic, index); |
158 | break; | |
159 | } | |
160 | } | |
161 | ||
a53c17d2 GN |
162 | static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq) |
163 | { | |
58c2dde1 GN |
164 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
165 | struct kvm_lapic_irq irqe; | |
a53c17d2 GN |
166 | |
167 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " | |
168 | "vector=%x trig_mode=%x\n", | |
58c2dde1 GN |
169 | entry->fields.dest, entry->fields.dest_mode, |
170 | entry->fields.delivery_mode, entry->fields.vector, | |
171 | entry->fields.trig_mode); | |
172 | ||
173 | irqe.dest_id = entry->fields.dest_id; | |
174 | irqe.vector = entry->fields.vector; | |
175 | irqe.dest_mode = entry->fields.dest_mode; | |
176 | irqe.trig_mode = entry->fields.trig_mode; | |
177 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
178 | irqe.level = 1; | |
179 | irqe.shorthand = 0; | |
a53c17d2 GN |
180 | |
181 | #ifdef CONFIG_X86 | |
182 | /* Always delivery PIT interrupt to vcpu 0 */ | |
183 | if (irq == 0) { | |
58c2dde1 | 184 | irqe.dest_mode = 0; /* Physical mode. */ |
c5af89b6 GN |
185 | /* need to read apic_id from apic regiest since |
186 | * it can be rewritten */ | |
187 | irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id; | |
a53c17d2 GN |
188 | } |
189 | #endif | |
58c2dde1 | 190 | return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe); |
a53c17d2 GN |
191 | } |
192 | ||
4925663a | 193 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) |
1fd4f2a5 | 194 | { |
07dc7263 | 195 | u32 old_irr; |
1fd4f2a5 | 196 | u32 mask = 1 << irq; |
cf9e4e15 | 197 | union kvm_ioapic_redirect_entry entry; |
4925663a | 198 | int ret = 1; |
1fd4f2a5 | 199 | |
46a47b1e | 200 | spin_lock(&ioapic->lock); |
07dc7263 | 201 | old_irr = ioapic->irr; |
1fd4f2a5 ED |
202 | if (irq >= 0 && irq < IOAPIC_NUM_PINS) { |
203 | entry = ioapic->redirtbl[irq]; | |
204 | level ^= entry.fields.polarity; | |
205 | if (!level) | |
206 | ioapic->irr &= ~mask; | |
207 | else { | |
b4a2f5e7 | 208 | int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); |
1fd4f2a5 | 209 | ioapic->irr |= mask; |
b4a2f5e7 GN |
210 | if ((edge && old_irr != ioapic->irr) || |
211 | (!edge && !entry.fields.remote_irr)) | |
4925663a | 212 | ret = ioapic_service(ioapic, irq); |
65a82211 GN |
213 | else |
214 | ret = 0; /* report coalesced interrupt */ | |
1fd4f2a5 | 215 | } |
1000ff8d | 216 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); |
1fd4f2a5 | 217 | } |
46a47b1e | 218 | spin_unlock(&ioapic->lock); |
eba0226b | 219 | |
4925663a | 220 | return ret; |
1fd4f2a5 ED |
221 | } |
222 | ||
eba0226b GN |
223 | static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector, |
224 | int trigger_mode) | |
1fd4f2a5 | 225 | { |
eba0226b GN |
226 | int i; |
227 | ||
228 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
229 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
1fd4f2a5 | 230 | |
eba0226b GN |
231 | if (ent->fields.vector != vector) |
232 | continue; | |
1fd4f2a5 | 233 | |
eba0226b GN |
234 | /* |
235 | * We are dropping lock while calling ack notifiers because ack | |
236 | * notifier callbacks for assigned devices call into IOAPIC | |
237 | * recursively. Since remote_irr is cleared only after call | |
238 | * to notifiers if the same vector will be delivered while lock | |
239 | * is dropped it will be put into irr and will be delivered | |
240 | * after ack notifier returns. | |
241 | */ | |
46a47b1e | 242 | spin_unlock(&ioapic->lock); |
eba0226b | 243 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i); |
46a47b1e | 244 | spin_lock(&ioapic->lock); |
eba0226b GN |
245 | |
246 | if (trigger_mode != IOAPIC_LEVEL_TRIG) | |
247 | continue; | |
f5244726 | 248 | |
f5244726 MT |
249 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
250 | ent->fields.remote_irr = 0; | |
eba0226b GN |
251 | if (!ent->fields.mask && (ioapic->irr & (1 << i))) |
252 | ioapic_service(ioapic, i); | |
f5244726 | 253 | } |
1fd4f2a5 ED |
254 | } |
255 | ||
f5244726 | 256 | void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode) |
4fa6b9c5 AK |
257 | { |
258 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
4fa6b9c5 | 259 | |
46a929bc AK |
260 | smp_rmb(); |
261 | if (!test_bit(vector, ioapic->handled_vectors)) | |
262 | return; | |
46a47b1e | 263 | spin_lock(&ioapic->lock); |
eba0226b | 264 | __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode); |
46a47b1e | 265 | spin_unlock(&ioapic->lock); |
4fa6b9c5 AK |
266 | } |
267 | ||
d76685c4 GH |
268 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
269 | { | |
270 | return container_of(dev, struct kvm_ioapic, dev); | |
271 | } | |
272 | ||
bda9020e | 273 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 274 | { |
1fd4f2a5 ED |
275 | return ((addr >= ioapic->base_address && |
276 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
277 | } | |
278 | ||
bda9020e MT |
279 | static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, |
280 | void *val) | |
1fd4f2a5 | 281 | { |
d76685c4 | 282 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 283 | u32 result; |
bda9020e MT |
284 | if (!ioapic_in_range(ioapic, addr)) |
285 | return -EOPNOTSUPP; | |
1fd4f2a5 | 286 | |
e25e3ed5 | 287 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
288 | ASSERT(!(addr & 0xf)); /* check alignment */ |
289 | ||
290 | addr &= 0xff; | |
46a47b1e | 291 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
292 | switch (addr) { |
293 | case IOAPIC_REG_SELECT: | |
294 | result = ioapic->ioregsel; | |
295 | break; | |
296 | ||
297 | case IOAPIC_REG_WINDOW: | |
298 | result = ioapic_read_indirect(ioapic, addr, len); | |
299 | break; | |
300 | ||
301 | default: | |
302 | result = 0; | |
303 | break; | |
304 | } | |
46a47b1e | 305 | spin_unlock(&ioapic->lock); |
eba0226b | 306 | |
1fd4f2a5 ED |
307 | switch (len) { |
308 | case 8: | |
309 | *(u64 *) val = result; | |
310 | break; | |
311 | case 1: | |
312 | case 2: | |
313 | case 4: | |
314 | memcpy(val, (char *)&result, len); | |
315 | break; | |
316 | default: | |
317 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
318 | } | |
bda9020e | 319 | return 0; |
1fd4f2a5 ED |
320 | } |
321 | ||
bda9020e MT |
322 | static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, |
323 | const void *val) | |
1fd4f2a5 | 324 | { |
d76685c4 | 325 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 326 | u32 data; |
bda9020e MT |
327 | if (!ioapic_in_range(ioapic, addr)) |
328 | return -EOPNOTSUPP; | |
1fd4f2a5 | 329 | |
e25e3ed5 LV |
330 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
331 | (void*)addr, len, val); | |
1fd4f2a5 | 332 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 333 | |
1fd4f2a5 ED |
334 | if (len == 4 || len == 8) |
335 | data = *(u32 *) val; | |
336 | else { | |
337 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); | |
eba0226b | 338 | return 0; |
1fd4f2a5 ED |
339 | } |
340 | ||
341 | addr &= 0xff; | |
46a47b1e | 342 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
343 | switch (addr) { |
344 | case IOAPIC_REG_SELECT: | |
345 | ioapic->ioregsel = data; | |
346 | break; | |
347 | ||
348 | case IOAPIC_REG_WINDOW: | |
349 | ioapic_write_indirect(ioapic, data); | |
350 | break; | |
b1fd3d30 ZX |
351 | #ifdef CONFIG_IA64 |
352 | case IOAPIC_REG_EOI: | |
eba0226b | 353 | __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG); |
b1fd3d30 ZX |
354 | break; |
355 | #endif | |
1fd4f2a5 ED |
356 | |
357 | default: | |
358 | break; | |
359 | } | |
46a47b1e | 360 | spin_unlock(&ioapic->lock); |
bda9020e | 361 | return 0; |
1fd4f2a5 ED |
362 | } |
363 | ||
8c392696 ED |
364 | void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
365 | { | |
366 | int i; | |
367 | ||
368 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
369 | ioapic->redirtbl[i].fields.mask = 1; | |
370 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
371 | ioapic->ioregsel = 0; | |
372 | ioapic->irr = 0; | |
373 | ioapic->id = 0; | |
46a929bc | 374 | update_handled_vectors(ioapic); |
8c392696 ED |
375 | } |
376 | ||
d76685c4 GH |
377 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
378 | .read = ioapic_mmio_read, | |
379 | .write = ioapic_mmio_write, | |
d76685c4 GH |
380 | }; |
381 | ||
1fd4f2a5 ED |
382 | int kvm_ioapic_init(struct kvm *kvm) |
383 | { | |
384 | struct kvm_ioapic *ioapic; | |
090b7aff | 385 | int ret; |
1fd4f2a5 ED |
386 | |
387 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
388 | if (!ioapic) | |
389 | return -ENOMEM; | |
46a47b1e | 390 | spin_lock_init(&ioapic->lock); |
d7deeeb0 | 391 | kvm->arch.vioapic = ioapic; |
8c392696 | 392 | kvm_ioapic_reset(ioapic); |
d76685c4 | 393 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 394 | ioapic->kvm = kvm; |
79fac95e | 395 | mutex_lock(&kvm->slots_lock); |
e93f8a0f | 396 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); |
79fac95e | 397 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
398 | if (ret < 0) { |
399 | kvm->arch.vioapic = NULL; | |
090b7aff | 400 | kfree(ioapic); |
1ae77bad | 401 | } |
090b7aff GH |
402 | |
403 | return ret; | |
1fd4f2a5 | 404 | } |
75858a84 | 405 | |
72bb2fcd WY |
406 | void kvm_ioapic_destroy(struct kvm *kvm) |
407 | { | |
408 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
409 | ||
410 | if (ioapic) { | |
411 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); | |
412 | kvm->arch.vioapic = NULL; | |
413 | kfree(ioapic); | |
414 | } | |
415 | } | |
416 | ||
eba0226b GN |
417 | int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
418 | { | |
419 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
420 | if (!ioapic) | |
421 | return -EINVAL; | |
422 | ||
46a47b1e | 423 | spin_lock(&ioapic->lock); |
eba0226b | 424 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); |
46a47b1e | 425 | spin_unlock(&ioapic->lock); |
eba0226b GN |
426 | return 0; |
427 | } | |
428 | ||
429 | int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) | |
430 | { | |
431 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
432 | if (!ioapic) | |
433 | return -EINVAL; | |
434 | ||
46a47b1e | 435 | spin_lock(&ioapic->lock); |
eba0226b | 436 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); |
46a929bc | 437 | update_handled_vectors(ioapic); |
46a47b1e | 438 | spin_unlock(&ioapic->lock); |
eba0226b GN |
439 | return 0; |
440 | } |