[linux-2.6-block.git] / virt / kvm / arm / vgic / vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_NEW_H__
#define __KVM_ARM_VGIC_NEW_H__

#include <linux/irqchip/arm-gic-common.h>

#define PRODUCT_ID_KVM		0x4b	/* ASCII code K */
#define IMPLEMENTER_ARM		0x43b

#define VGIC_ADDR_UNDEF		(-1)
#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)

#define INTERRUPT_ID_BITS_SPIS	10
#define INTERRUPT_ID_BITS_ITS	16
#define VGIC_PRI_BITS		5

#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)

#define VGIC_AFFINITY_0_SHIFT 0
#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
#define VGIC_AFFINITY_1_SHIFT 8
#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
#define VGIC_AFFINITY_2_SHIFT 16
#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
#define VGIC_AFFINITY_3_SHIFT 24
#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)

#define VGIC_AFFINITY_LEVEL(reg, level) \
	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))

/*
 * The Userspace encodes the affinity differently from the MPIDR,
 * Below macro converts vgic userspace format to MPIDR reg format.
 */
#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
			    VGIC_AFFINITY_LEVEL(val, 1) | \
			    VGIC_AFFINITY_LEVEL(val, 2) | \
			    VGIC_AFFINITY_LEVEL(val, 3))

/*
 * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
 * below macros are defined for CPUREG encoding.
 */
#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT  14
#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT  11
#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT  7
#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT  3
#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT  0

#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)

static inline bool irq_is_pending(struct vgic_irq *irq)
{
	if (irq->config == VGIC_CONFIG_EDGE)
		return irq->pending_latch;
	else
		return irq->pending_latch || irq->line_level;
}

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
	/* Below member variable are valid only for GICv3 */
	u32	grpen0;
	u32	grpen1;
};

struct vgic_reg_attr {
	struct kvm_vcpu *vcpu;
	gpa_t addr;
};

int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
		       struct vgic_reg_attr *reg_attr);
int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
		       struct vgic_reg_attr *reg_attr);
const struct vgic_register_region *
vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
		     gpa_t addr, int len);
struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
			      u32 intid);
void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
void vgic_kick_vcpus(struct kvm *kvm);

int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
		      phys_addr_t addr, phys_addr_t alignment);

void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu);
void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			  int offset, u32 *val);
void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v2_enable(struct kvm_vcpu *vcpu);
int vgic_v2_probe(const struct gic_kvm_info *info);
int vgic_v2_map_resources(struct kvm *kvm);
int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
			     enum vgic_type);

static inline void vgic_get_irq_kref(struct vgic_irq *irq)
{
	if (irq->intid < VGIC_MIN_LPI)
		return;

	kref_get(&irq->refcount);
}

void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu);
void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_enable(struct kvm_vcpu *vcpu);
int vgic_v3_probe(const struct gic_kvm_info *info);
int vgic_v3_map_resources(struct kvm *kvm);
int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t dist_base_address);

int vgic_register_its_iodevs(struct kvm *kvm);
bool vgic_has_its(struct kvm *kvm);
int kvm_vgic_register_its_device(void);
void vgic_enable_lpis(struct kvm_vcpu *vcpu);
int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 u64 id, u64 *val);
int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
				u64 *reg);
int kvm_register_vgic_device(unsigned long type);
void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
int vgic_lazy_init(struct kvm *kvm);
int vgic_init(struct kvm *kvm);

int vgic_debug_init(struct kvm *kvm);
int vgic_debug_destroy(struct kvm *kvm);

#endif
Commit	Line	Data
64a959d6 CD	1	/*
	2	* Copyright (C) 2015, 2016 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __KVM_ARM_VGIC_NEW_H__
	17	#define __KVM_ARM_VGIC_NEW_H__
	18
90977732 EA	19	#include <linux/irqchip/arm-gic-common.h>
90977732 EA	20
2b0cda87 MZ	21	#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
	22	#define IMPLEMENTER_ARM 0x43b
	23
e2c1f9ab EA	24	#define VGIC_ADDR_UNDEF (-1)
	25	#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
	26
fd59ed3b	27	#define INTERRUPT_ID_BITS_SPIS 10
33d3bc95	28	#define INTERRUPT_ID_BITS_ITS 16
055658bf AP	29	#define VGIC_PRI_BITS 5
055658bf AP	30
0919e84c MZ	31	#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
0919e84c MZ	32
94574c94 VK	33	#define VGIC_AFFINITY_0_SHIFT 0
	34	#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
	35	#define VGIC_AFFINITY_1_SHIFT 8
	36	#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
	37	#define VGIC_AFFINITY_2_SHIFT 16
	38	#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
	39	#define VGIC_AFFINITY_3_SHIFT 24
	40	#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
	41
	42	#define VGIC_AFFINITY_LEVEL(reg, level) \
	43	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
	44	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
	45
	46	/*
	47	* The Userspace encodes the affinity differently from the MPIDR,
	48	* Below macro converts vgic userspace format to MPIDR reg format.
	49	*/
	50	#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) \| \
	51	VGIC_AFFINITY_LEVEL(val, 1) \| \
	52	VGIC_AFFINITY_LEVEL(val, 2) \| \
	53	VGIC_AFFINITY_LEVEL(val, 3))
	54
d017d7b0 VK	55	/*
	56	* As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
	57	* below macros are defined for CPUREG encoding.
	58	*/
	59	#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
	60	#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
	61	#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
	62	#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
	63	#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
	64	#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
	65	#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
	66	#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
	67	#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
	68	#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
	69
	70	#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK \| \
	71	KVM_REG_ARM_VGIC_SYSREG_OP1_MASK \| \
	72	KVM_REG_ARM_VGIC_SYSREG_CRN_MASK \| \
	73	KVM_REG_ARM_VGIC_SYSREG_CRM_MASK \| \
	74	KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
	75
8694e4da CD	76	static inline bool irq_is_pending(struct vgic_irq *irq)
	77	{
	78	if (irq->config == VGIC_CONFIG_EDGE)
	79	return irq->pending_latch;
	80	else
	81	return irq->pending_latch \|\| irq->line_level;
	82	}
	83
e4823a7a AP	84	struct vgic_vmcr {
	85	u32 ctlr;
	86	u32 abpr;
	87	u32 bpr;
	88	u32 pmr;
5fb247d7 VK	89	/* Below member variable are valid only for GICv3 */
	90	u32 grpen0;
	91	u32 grpen1;
e4823a7a AP	92	};
e4823a7a AP	93
94574c94 VK	94	struct vgic_reg_attr {
	95	struct kvm_vcpu *vcpu;
	96	gpa_t addr;
	97	};
	98
	99	int vgic_v3_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
	100	struct vgic_reg_attr *reg_attr);
	101	int vgic_v2_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
	102	struct vgic_reg_attr *reg_attr);
	103	const struct vgic_register_region *
	104	vgic_get_mmio_region(struct kvm_vcpu vcpu, struct vgic_io_device iodev,
	105	gpa_t addr, int len);
64a959d6 CD	106	struct vgic_irq vgic_get_irq(struct kvm kvm, struct kvm_vcpu *vcpu,
64a959d6 CD	107	u32 intid);
5dd4b924	108	void vgic_put_irq(struct kvm kvm, struct vgic_irq irq);
81eeb95d	109	bool vgic_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq);
2b0cda87	110	void vgic_kick_vcpus(struct kvm *kvm);
64a959d6	111
1085fdc6 AP	112	int vgic_check_ioaddr(struct kvm kvm, phys_addr_t ioaddr,
	113	phys_addr_t addr, phys_addr_t alignment);
	114
140b086d MZ	115	void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu);
	116	void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
	117	void vgic_v2_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr);
	118	void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
	119	void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
f94591e2	120	int vgic_v2_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr);
c3199f28 CD	121	int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
c3199f28 CD	122	int offset, u32 *val);
878c569e AP	123	int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
878c569e AP	124	int offset, u32 *val);
e4823a7a AP	125	void vgic_v2_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
e4823a7a AP	126	void vgic_v2_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
ad275b8b	127	void vgic_v2_enable(struct kvm_vcpu *vcpu);
90977732	128	int vgic_v2_probe(const struct gic_kvm_info *info);
b0442ee2	129	int vgic_v2_map_resources(struct kvm *kvm);
fb848db3 AP	130	int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
fb848db3 AP	131	enum vgic_type);
140b086d	132
d97594e6 MZ	133	static inline void vgic_get_irq_kref(struct vgic_irq *irq)
	134	{
	135	if (irq->intid < VGIC_MIN_LPI)
	136	return;
	137
	138	kref_get(&irq->refcount);
	139	}
	140
59529f69 MZ	141	void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu);
	142	void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
	143	void vgic_v3_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr);
	144	void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
	145	void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
e4823a7a AP	146	void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
e4823a7a AP	147	void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
ad275b8b	148	void vgic_v3_enable(struct kvm_vcpu *vcpu);
90977732	149	int vgic_v3_probe(const struct gic_kvm_info *info);
b0442ee2	150	int vgic_v3_map_resources(struct kvm *kvm);
ed9b8cef	151	int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t dist_base_address);
7a1ff708	152
c7735769	153	int vgic_register_its_iodevs(struct kvm *kvm);
59c5ab40	154	bool vgic_has_its(struct kvm *kvm);
0e4e82f1	155	int kvm_vgic_register_its_device(void);
33d3bc95	156	void vgic_enable_lpis(struct kvm_vcpu *vcpu);
2891a7df	157	int vgic_its_inject_msi(struct kvm kvm, struct kvm_msi msi);
94574c94 VK	158	int vgic_v3_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr);
	159	int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	160	int offset, u32 *val);
	161	int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	162	int offset, u32 *val);
d017d7b0 VK	163	int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	164	u64 id, u64 *val);
	165	int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
	166	u64 *reg);
42c8870f	167	int kvm_register_vgic_device(unsigned long type);
5fb247d7 VK	168	void vgic_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
5fb247d7 VK	169	void vgic_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
ad275b8b EA	170	int vgic_lazy_init(struct kvm *kvm);
ad275b8b EA	171	int vgic_init(struct kvm *kvm);
c86c7721	172
10f92c4c CD	173	int vgic_debug_init(struct kvm *kvm);
	174	int vgic_debug_destroy(struct kvm *kvm);
	175
64a959d6	176	#endif