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KVM: arm/arm64: Refactor vgic_register_redist_iodevs
[linux-2.6-block.git] / virt / kvm / arm / vgic / vgic.h
CommitLineData
64a959d6
CD		 1/*
2 * Copyright (C) 2015, 2016 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __KVM_ARM_VGIC_NEW_H__
17#define __KVM_ARM_VGIC_NEW_H__
18
90977732
EA		 19#include <linux/irqchip/arm-gic-common.h>
20
2b0cda87
MZ		 21#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
22#define IMPLEMENTER_ARM 0x43b
23
e2c1f9ab
EA		 24#define VGIC_ADDR_UNDEF (-1)
25#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
26
fd59ed3b 27#define INTERRUPT_ID_BITS_SPIS 10
33d3bc95 28#define INTERRUPT_ID_BITS_ITS 16
055658bf
AP		 29#define VGIC_PRI_BITS 5
30
0919e84c
MZ		 31#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
32
94574c94
VK		 33#define VGIC_AFFINITY_0_SHIFT 0
34#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
35#define VGIC_AFFINITY_1_SHIFT 8
36#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
37#define VGIC_AFFINITY_2_SHIFT 16
38#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
39#define VGIC_AFFINITY_3_SHIFT 24
40#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
41
42#define VGIC_AFFINITY_LEVEL(reg, level) \
43 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
44 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
45
46/*
47 * The Userspace encodes the affinity differently from the MPIDR,
48 * Below macro converts vgic userspace format to MPIDR reg format.
49 */
50#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
51 VGIC_AFFINITY_LEVEL(val, 1) | \
52 VGIC_AFFINITY_LEVEL(val, 2) | \
53 VGIC_AFFINITY_LEVEL(val, 3))
54
d017d7b0
VK		 55/*
56 * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
57 * below macros are defined for CPUREG encoding.
58 */
59#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
60#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
61#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
62#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
63#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
64#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
65#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
66#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
67#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
68#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
69
70#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
71 KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
72 KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
73 KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
74 KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
75
ea1ad53e
EA		 76/*
77 * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
78 * below macros are defined for ITS table entry encoding.
79 */
80#define KVM_ITS_CTE_VALID_SHIFT 63
81#define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
82#define KVM_ITS_CTE_RDBASE_SHIFT 16
83#define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
eff484e0
EA		 84#define KVM_ITS_ITE_NEXT_SHIFT 48
85#define KVM_ITS_ITE_PINTID_SHIFT 16
86#define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
87#define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
57a9a117
EA		 88#define KVM_ITS_DTE_VALID_SHIFT 63
89#define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
90#define KVM_ITS_DTE_NEXT_SHIFT 49
91#define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
92#define KVM_ITS_DTE_ITTADDR_SHIFT 5
93#define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
94#define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
95#define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
96/* we only support 64 kB translation table page size */
97#define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
ea1ad53e 98
8694e4da
CD		 99static inline bool irq_is_pending(struct vgic_irq *irq)
100{
101 if (irq->config == VGIC_CONFIG_EDGE)
102 return irq->pending_latch;
103 else
104 return irq->pending_latch || irq->line_level;
105}
106
e4823a7a
AP		 107struct vgic_vmcr {
108 u32 ctlr;
109 u32 abpr;
110 u32 bpr;
111 u32 pmr;
5fb247d7
VK		 112 /* Below member variable are valid only for GICv3 */
113 u32 grpen0;
114 u32 grpen1;
e4823a7a
AP		 115};
116
94574c94
VK		 117struct vgic_reg_attr {
118 struct kvm_vcpu *vcpu;
119 gpa_t addr;
120};
121
122int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
123 struct vgic_reg_attr *reg_attr);
124int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
125 struct vgic_reg_attr *reg_attr);
126const struct vgic_register_region *
127vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
128 gpa_t addr, int len);
64a959d6
CD		 129struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
130 u32 intid);
5dd4b924 131void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
81eeb95d 132bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
2b0cda87 133void vgic_kick_vcpus(struct kvm *kvm);
64a959d6 134
1085fdc6
AP		 135int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
136 phys_addr_t addr, phys_addr_t alignment);
137
140b086d
MZ		 138void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
139void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
140void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
141void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
f94591e2 142int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
c3199f28
CD		 143int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
144 int offset, u32 *val);
878c569e
AP		 145int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
146 int offset, u32 *val);
e4823a7a
AP		 147void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
148void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b 149void vgic_v2_enable(struct kvm_vcpu *vcpu);
90977732 150int vgic_v2_probe(const struct gic_kvm_info *info);
b0442ee2 151int vgic_v2_map_resources(struct kvm *kvm);
fb848db3
AP		 152int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
153 enum vgic_type);
140b086d 154
328e5664
CD		 155void vgic_v2_load(struct kvm_vcpu *vcpu);
156void vgic_v2_put(struct kvm_vcpu *vcpu);
157
d97594e6
MZ		 158static inline void vgic_get_irq_kref(struct vgic_irq *irq)
159{
160 if (irq->intid < VGIC_MIN_LPI)
161 return;
162
163 kref_get(&irq->refcount);
164}
165
59529f69
MZ		 166void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
167void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
168void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
169void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
e4823a7a
AP		 170void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
171void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b 172void vgic_v3_enable(struct kvm_vcpu *vcpu);
90977732 173int vgic_v3_probe(const struct gic_kvm_info *info);
b0442ee2 174int vgic_v3_map_resources(struct kvm *kvm);
44de9d68 175int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
28077125 176int vgic_v3_save_pending_tables(struct kvm *kvm);
7fadcd3a 177int vgic_register_redist_iodevs(struct kvm *kvm);
7a1ff708 178
328e5664
CD		 179void vgic_v3_load(struct kvm_vcpu *vcpu);
180void vgic_v3_put(struct kvm_vcpu *vcpu);
181
c7735769 182int vgic_register_its_iodevs(struct kvm *kvm);
59c5ab40 183bool vgic_has_its(struct kvm *kvm);
0e4e82f1 184int kvm_vgic_register_its_device(void);
33d3bc95 185void vgic_enable_lpis(struct kvm_vcpu *vcpu);
2891a7df 186int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
94574c94
VK		 187int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
188int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
189 int offset, u32 *val);
190int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
191 int offset, u32 *val);
d017d7b0
VK		 192int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
193 u64 id, u64 *val);
194int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
195 u64 *reg);
e96a006c
VK		 196int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
197 u32 intid, u64 *val);
42c8870f 198int kvm_register_vgic_device(unsigned long type);
5fb247d7
VK		 199void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
200void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b
EA		 201int vgic_lazy_init(struct kvm *kvm);
202int vgic_init(struct kvm *kvm);
c86c7721 203
10f92c4c
CD		 204int vgic_debug_init(struct kvm *kvm);
205int vgic_debug_destroy(struct kvm *kvm);
206
dfc99f85
EA		 207bool lock_all_vcpus(struct kvm *kvm);
208void unlock_all_vcpus(struct kvm *kvm);
209
64a959d6 210#endif
Linux 6.x block layer and io_uring tree(s)