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KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid
[linux-2.6-block.git] / virt / kvm / arm / vgic / vgic.h
CommitLineData
64a959d6
CD		 1/*
2 * Copyright (C) 2015, 2016 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __KVM_ARM_VGIC_NEW_H__
17#define __KVM_ARM_VGIC_NEW_H__
18
90977732
EA		 19#include <linux/irqchip/arm-gic-common.h>
20
2b0cda87
MZ		 21#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
22#define IMPLEMENTER_ARM 0x43b
23
e2c1f9ab
EA		 24#define VGIC_ADDR_UNDEF (-1)
25#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
26
fd59ed3b 27#define INTERRUPT_ID_BITS_SPIS 10
33d3bc95 28#define INTERRUPT_ID_BITS_ITS 16
055658bf
AP		 29#define VGIC_PRI_BITS 5
30
0919e84c
MZ		 31#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
32
94574c94
VK		 33#define VGIC_AFFINITY_0_SHIFT 0
34#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
35#define VGIC_AFFINITY_1_SHIFT 8
36#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
37#define VGIC_AFFINITY_2_SHIFT 16
38#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
39#define VGIC_AFFINITY_3_SHIFT 24
40#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
41
42#define VGIC_AFFINITY_LEVEL(reg, level) \
43 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
44 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
45
46/*
47 * The Userspace encodes the affinity differently from the MPIDR,
48 * Below macro converts vgic userspace format to MPIDR reg format.
49 */
50#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
51 VGIC_AFFINITY_LEVEL(val, 1) | \
52 VGIC_AFFINITY_LEVEL(val, 2) | \
53 VGIC_AFFINITY_LEVEL(val, 3))
54
d017d7b0
VK		 55/*
56 * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
57 * below macros are defined for CPUREG encoding.
58 */
59#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
60#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
61#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
62#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
63#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
64#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
65#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
66#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
67#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
68#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
69
70#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
71 KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
72 KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
73 KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
74 KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
75
ea1ad53e
EA		 76/*
77 * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
78 * below macros are defined for ITS table entry encoding.
79 */
80#define KVM_ITS_CTE_VALID_SHIFT 63
81#define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
82#define KVM_ITS_CTE_RDBASE_SHIFT 16
83#define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
eff484e0
EA		 84#define KVM_ITS_ITE_NEXT_SHIFT 48
85#define KVM_ITS_ITE_PINTID_SHIFT 16
86#define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
87#define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
57a9a117
EA		 88#define KVM_ITS_DTE_VALID_SHIFT 63
89#define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
90#define KVM_ITS_DTE_NEXT_SHIFT 49
91#define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
92#define KVM_ITS_DTE_ITTADDR_SHIFT 5
93#define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
94#define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
95#define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
96/* we only support 64 kB translation table page size */
97#define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
ea1ad53e 98
62b06f8f 99/* Requires the irq_lock to be held by the caller. */
8694e4da
CD		 100static inline bool irq_is_pending(struct vgic_irq *irq)
101{
102 if (irq->config == VGIC_CONFIG_EDGE)
103 return irq->pending_latch;
104 else
105 return irq->pending_latch || irq->line_level;
106}
107
e40cc57b
CD		 108static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
109{
110 return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
111}
112
6d56111c
CD		 113/*
114 * This struct provides an intermediate representation of the fields contained
115 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
116 * state to userspace can generate either GICv2 or GICv3 CPU interface
117 * registers regardless of the hardware backed GIC used.
118 */
e4823a7a 119struct vgic_vmcr {
28232a43
CD		 120 u32 grpen0;
121 u32 grpen1;
122
123 u32 ackctl;
124 u32 fiqen;
125 u32 cbpr;
126 u32 eoim;
127
e4823a7a
AP		 128 u32 abpr;
129 u32 bpr;
6d56111c
CD		 130 u32 pmr; /* Priority mask field in the GICC_PMR and
131 * ICC_PMR_EL1 priority field format */
e4823a7a
AP		 132};
133
94574c94
VK		 134struct vgic_reg_attr {
135 struct kvm_vcpu *vcpu;
136 gpa_t addr;
137};
138
139int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
140 struct vgic_reg_attr *reg_attr);
141int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
142 struct vgic_reg_attr *reg_attr);
143const struct vgic_register_region *
144vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
145 gpa_t addr, int len);
64a959d6
CD		 146struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
147 u32 intid);
5dd4b924 148void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
e40cc57b 149bool vgic_get_phys_line_level(struct vgic_irq *irq);
df635c5b 150void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
e40cc57b 151void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
006df0f3
CD		 152bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
153 unsigned long flags);
2b0cda87 154void vgic_kick_vcpus(struct kvm *kvm);
64a959d6 155
1085fdc6
AP		 156int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
157 phys_addr_t addr, phys_addr_t alignment);
158
140b086d
MZ		 159void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
160void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
161void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
162void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
16ca6a60 163void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
f94591e2 164int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
c3199f28
CD		 165int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
166 int offset, u32 *val);
878c569e
AP		 167int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
168 int offset, u32 *val);
e4823a7a
AP		 169void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
170void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b 171void vgic_v2_enable(struct kvm_vcpu *vcpu);
90977732 172int vgic_v2_probe(const struct gic_kvm_info *info);
b0442ee2 173int vgic_v2_map_resources(struct kvm *kvm);
fb848db3
AP		 174int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
175 enum vgic_type);
140b086d 176
5b0d2cc2 177void vgic_v2_init_lrs(void);
328e5664
CD		 178void vgic_v2_load(struct kvm_vcpu *vcpu);
179void vgic_v2_put(struct kvm_vcpu *vcpu);
5b0d2cc2 180
d97594e6
MZ		 181static inline void vgic_get_irq_kref(struct vgic_irq *irq)
182{
183 if (irq->intid < VGIC_MIN_LPI)
184 return;
185
186 kref_get(&irq->refcount);
187}
188
59529f69
MZ		 189void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
190void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
191void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
192void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
16ca6a60 193void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
e4823a7a
AP		 194void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
195void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b 196void vgic_v3_enable(struct kvm_vcpu *vcpu);
90977732 197int vgic_v3_probe(const struct gic_kvm_info *info);
b0442ee2 198int vgic_v3_map_resources(struct kvm *kvm);
44de9d68 199int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
28077125 200int vgic_v3_save_pending_tables(struct kvm *kvm);
1aab6f46
CD		 201int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr);
202int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
9a746d75 203bool vgic_v3_check_base(struct kvm *kvm);
7a1ff708 204
328e5664
CD		 205void vgic_v3_load(struct kvm_vcpu *vcpu);
206void vgic_v3_put(struct kvm_vcpu *vcpu);
207
59c5ab40 208bool vgic_has_its(struct kvm *kvm);
0e4e82f1 209int kvm_vgic_register_its_device(void);
33d3bc95 210void vgic_enable_lpis(struct kvm_vcpu *vcpu);
2891a7df 211int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
94574c94
VK		 212int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
213int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
214 int offset, u32 *val);
215int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
216 int offset, u32 *val);
d017d7b0
VK		 217int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
218 u64 id, u64 *val);
219int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
220 u64 *reg);
e96a006c
VK		 221int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
222 u32 intid, u64 *val);
42c8870f 223int kvm_register_vgic_device(unsigned long type);
5fb247d7
VK		 224void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
225void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b
EA		 226int vgic_lazy_init(struct kvm *kvm);
227int vgic_init(struct kvm *kvm);
c86c7721 228
10f92c4c
CD		 229int vgic_debug_init(struct kvm *kvm);
230int vgic_debug_destroy(struct kvm *kvm);
231
dfc99f85
EA		 232bool lock_all_vcpus(struct kvm *kvm);
233void unlock_all_vcpus(struct kvm *kvm);
234
50f5bd57
CD		 235static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
236{
237 struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
238
239 /*
240 * num_pri_bits are initialized with HW supported values.
241 * We can rely safely on num_pri_bits even if VM has not
242 * restored ICC_CTLR_EL1 before restoring APnR registers.
243 */
244 switch (cpu_if->num_pri_bits) {
245 case 7: return 3;
246 case 6: return 1;
247 default: return 0;
248 }
249}
250
bebfd2a2
MZ		 251int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
252 u32 devid, u32 eventid, struct vgic_irq **irq);
253struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
254
e7c48059 255bool vgic_supports_direct_msis(struct kvm *kvm);
74fe55dc
MZ		 256int vgic_v4_init(struct kvm *kvm);
257void vgic_v4_teardown(struct kvm *kvm);
62775797
MZ		 258int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu);
259int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu);
e7c48059 260
64a959d6 261#endif
Linux 6.x block layer and io_uring tree(s)