Commit | Line | Data |
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59529f69 MZ |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
13 | */ | |
14 | ||
15 | #include <linux/irqchip/arm-gic-v3.h> | |
16 | #include <linux/kvm.h> | |
17 | #include <linux/kvm_host.h> | |
90977732 | 18 | #include <kvm/arm_vgic.h> |
923a2e30 | 19 | #include <asm/kvm_hyp.h> |
90977732 EA |
20 | #include <asm/kvm_mmu.h> |
21 | #include <asm/kvm_asm.h> | |
59529f69 MZ |
22 | |
23 | #include "vgic.h" | |
24 | ||
abf55766 | 25 | static bool group0_trap; |
9c7bfc28 | 26 | static bool group1_trap; |
ff89511e | 27 | static bool common_trap; |
a7546054 | 28 | static bool gicv4_enable; |
9c7bfc28 | 29 | |
af061499 | 30 | void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) |
59529f69 MZ |
31 | { |
32 | struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | |
59529f69 | 33 | |
af061499 | 34 | cpuif->vgic_hcr |= ICH_HCR_UIE; |
59529f69 MZ |
35 | } |
36 | ||
af061499 | 37 | static bool lr_signals_eoi_mi(u64 lr_val) |
59529f69 | 38 | { |
af061499 CD |
39 | return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) && |
40 | !(lr_val & ICH_LR_HW); | |
59529f69 MZ |
41 | } |
42 | ||
43 | void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) | |
44 | { | |
8ac76ef4 CD |
45 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
46 | struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; | |
59529f69 MZ |
47 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
48 | int lr; | |
006df0f3 | 49 | unsigned long flags; |
59529f69 | 50 | |
53692908 | 51 | cpuif->vgic_hcr &= ~ICH_HCR_UIE; |
af061499 | 52 | |
8ac76ef4 | 53 | for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { |
59529f69 | 54 | u64 val = cpuif->vgic_lr[lr]; |
53692908 | 55 | u32 intid, cpuid; |
59529f69 | 56 | struct vgic_irq *irq; |
53692908 MZ |
57 | bool is_v2_sgi = false; |
58 | ||
59 | cpuid = val & GICH_LR_PHYSID_CPUID; | |
60 | cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; | |
59529f69 | 61 | |
53692908 | 62 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) { |
59529f69 | 63 | intid = val & ICH_LR_VIRTUAL_ID_MASK; |
53692908 | 64 | } else { |
59529f69 | 65 | intid = val & GICH_LR_VIRTUALID; |
53692908 MZ |
66 | is_v2_sgi = vgic_irq_is_sgi(intid); |
67 | } | |
af061499 CD |
68 | |
69 | /* Notify fds when the guest EOI'ed a level-triggered IRQ */ | |
70 | if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) | |
71 | kvm_notify_acked_irq(vcpu->kvm, 0, | |
72 | intid - VGIC_NR_PRIVATE_IRQS); | |
73 | ||
59529f69 | 74 | irq = vgic_get_irq(vcpu->kvm, vcpu, intid); |
3802411d AP |
75 | if (!irq) /* An LPI could have been unmapped. */ |
76 | continue; | |
59529f69 | 77 | |
006df0f3 | 78 | spin_lock_irqsave(&irq->irq_lock, flags); |
59529f69 MZ |
79 | |
80 | /* Always preserve the active bit */ | |
81 | irq->active = !!(val & ICH_LR_ACTIVE_BIT); | |
82 | ||
53692908 MZ |
83 | if (irq->active && is_v2_sgi) |
84 | irq->active_source = cpuid; | |
85 | ||
59529f69 MZ |
86 | /* Edge is the only case where we preserve the pending bit */ |
87 | if (irq->config == VGIC_CONFIG_EDGE && | |
88 | (val & ICH_LR_PENDING_BIT)) { | |
8694e4da | 89 | irq->pending_latch = true; |
59529f69 | 90 | |
53692908 | 91 | if (is_v2_sgi) |
59529f69 | 92 | irq->source |= (1 << cpuid); |
59529f69 MZ |
93 | } |
94 | ||
637d122b MZ |
95 | /* |
96 | * Clear soft pending state when level irqs have been acked. | |
637d122b | 97 | */ |
67b5b673 MZ |
98 | if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE)) |
99 | irq->pending_latch = false; | |
59529f69 | 100 | |
e40cc57b CD |
101 | /* |
102 | * Level-triggered mapped IRQs are special because we only | |
103 | * observe rising edges as input to the VGIC. | |
104 | * | |
105 | * If the guest never acked the interrupt we have to sample | |
106 | * the physical line and set the line level, because the | |
107 | * device state could have changed or we simply need to | |
108 | * process the still pending interrupt later. | |
109 | * | |
110 | * If this causes us to lower the level, we have to also clear | |
111 | * the physical active state, since we will otherwise never be | |
112 | * told when the interrupt becomes asserted again. | |
113 | */ | |
114 | if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT)) { | |
115 | irq->line_level = vgic_get_phys_line_level(irq); | |
116 | ||
117 | if (!irq->line_level) | |
118 | vgic_irq_set_phys_active(irq, false); | |
119 | } | |
120 | ||
006df0f3 | 121 | spin_unlock_irqrestore(&irq->irq_lock, flags); |
5dd4b924 | 122 | vgic_put_irq(vcpu->kvm, irq); |
59529f69 | 123 | } |
8ac76ef4 CD |
124 | |
125 | vgic_cpu->used_lrs = 0; | |
59529f69 MZ |
126 | } |
127 | ||
128 | /* Requires the irq to be locked already */ | |
129 | void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) | |
130 | { | |
131 | u32 model = vcpu->kvm->arch.vgic.vgic_model; | |
132 | u64 val = irq->intid; | |
53692908 | 133 | bool allow_pending = true, is_v2_sgi; |
67b5b673 | 134 | |
53692908 MZ |
135 | is_v2_sgi = (vgic_irq_is_sgi(irq->intid) && |
136 | model == KVM_DEV_TYPE_ARM_VGIC_V2); | |
137 | ||
138 | if (irq->active) { | |
67b5b673 | 139 | val |= ICH_LR_ACTIVE_BIT; |
53692908 MZ |
140 | if (is_v2_sgi) |
141 | val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT; | |
142 | if (vgic_irq_is_multi_sgi(irq)) { | |
143 | allow_pending = false; | |
144 | val |= ICH_LR_EOI; | |
145 | } | |
146 | } | |
67b5b673 MZ |
147 | |
148 | if (irq->hw) { | |
149 | val |= ICH_LR_HW; | |
150 | val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; | |
151 | /* | |
152 | * Never set pending+active on a HW interrupt, as the | |
153 | * pending state is kept at the physical distributor | |
154 | * level. | |
155 | */ | |
156 | if (irq->active) | |
157 | allow_pending = false; | |
158 | } else { | |
159 | if (irq->config == VGIC_CONFIG_LEVEL) { | |
160 | val |= ICH_LR_EOI; | |
59529f69 | 161 | |
67b5b673 MZ |
162 | /* |
163 | * Software resampling doesn't work very well | |
164 | * if we allow P+A, so let's not do that. | |
165 | */ | |
166 | if (irq->active) | |
167 | allow_pending = false; | |
168 | } | |
169 | } | |
170 | ||
171 | if (allow_pending && irq_is_pending(irq)) { | |
59529f69 MZ |
172 | val |= ICH_LR_PENDING_BIT; |
173 | ||
174 | if (irq->config == VGIC_CONFIG_EDGE) | |
8694e4da | 175 | irq->pending_latch = false; |
59529f69 MZ |
176 | |
177 | if (vgic_irq_is_sgi(irq->intid) && | |
178 | model == KVM_DEV_TYPE_ARM_VGIC_V2) { | |
179 | u32 src = ffs(irq->source); | |
180 | ||
181 | BUG_ON(!src); | |
182 | val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; | |
183 | irq->source &= ~(1 << (src - 1)); | |
53692908 | 184 | if (irq->source) { |
8694e4da | 185 | irq->pending_latch = true; |
53692908 MZ |
186 | val |= ICH_LR_EOI; |
187 | } | |
59529f69 MZ |
188 | } |
189 | } | |
190 | ||
e40cc57b CD |
191 | /* |
192 | * Level-triggered mapped IRQs are special because we only observe | |
193 | * rising edges as input to the VGIC. We therefore lower the line | |
194 | * level here, so that we can take new virtual IRQs. See | |
195 | * vgic_v3_fold_lr_state for more info. | |
196 | */ | |
197 | if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT)) | |
198 | irq->line_level = false; | |
199 | ||
59529f69 MZ |
200 | /* |
201 | * We currently only support Group1 interrupts, which is a | |
202 | * known defect. This needs to be addressed at some point. | |
203 | */ | |
204 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
205 | val |= ICH_LR_GROUP; | |
206 | ||
207 | val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; | |
208 | ||
209 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; | |
210 | } | |
211 | ||
212 | void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr) | |
213 | { | |
214 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0; | |
215 | } | |
e4823a7a AP |
216 | |
217 | void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
218 | { | |
328e5664 | 219 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; |
28232a43 | 220 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
e4823a7a AP |
221 | u32 vmcr; |
222 | ||
28232a43 CD |
223 | if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { |
224 | vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) & | |
225 | ICH_VMCR_ACK_CTL_MASK; | |
226 | vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) & | |
227 | ICH_VMCR_FIQ_EN_MASK; | |
228 | } else { | |
229 | /* | |
230 | * When emulating GICv3 on GICv3 with SRE=1 on the | |
231 | * VFIQEn bit is RES1 and the VAckCtl bit is RES0. | |
232 | */ | |
233 | vmcr = ICH_VMCR_FIQ_EN_MASK; | |
234 | } | |
235 | ||
236 | vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK; | |
237 | vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK; | |
e4823a7a AP |
238 | vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; |
239 | vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; | |
240 | vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; | |
5fb247d7 VK |
241 | vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK; |
242 | vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK; | |
e4823a7a | 243 | |
328e5664 | 244 | cpu_if->vgic_vmcr = vmcr; |
e4823a7a AP |
245 | } |
246 | ||
247 | void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
248 | { | |
328e5664 | 249 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; |
28232a43 | 250 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
328e5664 CD |
251 | u32 vmcr; |
252 | ||
253 | vmcr = cpu_if->vgic_vmcr; | |
e4823a7a | 254 | |
28232a43 CD |
255 | if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { |
256 | vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >> | |
257 | ICH_VMCR_ACK_CTL_SHIFT; | |
258 | vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >> | |
259 | ICH_VMCR_FIQ_EN_SHIFT; | |
260 | } else { | |
261 | /* | |
262 | * When emulating GICv3 on GICv3 with SRE=1 on the | |
263 | * VFIQEn bit is RES1 and the VAckCtl bit is RES0. | |
264 | */ | |
265 | vmcrp->fiqen = 1; | |
266 | vmcrp->ackctl = 0; | |
267 | } | |
268 | ||
269 | vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; | |
270 | vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT; | |
e4823a7a AP |
271 | vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; |
272 | vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; | |
273 | vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; | |
5fb247d7 VK |
274 | vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT; |
275 | vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT; | |
e4823a7a | 276 | } |
90977732 | 277 | |
0aa1de57 AP |
278 | #define INITIAL_PENDBASER_VALUE \ |
279 | (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \ | |
280 | GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \ | |
281 | GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)) | |
282 | ||
ad275b8b EA |
283 | void vgic_v3_enable(struct kvm_vcpu *vcpu) |
284 | { | |
f7b6985c EA |
285 | struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; |
286 | ||
287 | /* | |
288 | * By forcing VMCR to zero, the GIC will restore the binary | |
289 | * points to their reset values. Anything else resets to zero | |
290 | * anyway. | |
291 | */ | |
292 | vgic_v3->vgic_vmcr = 0; | |
f7b6985c EA |
293 | |
294 | /* | |
295 | * If we are emulating a GICv3, we do it in an non-GICv2-compatible | |
296 | * way, so we force SRE to 1 to demonstrate this to the guest. | |
4dfc0505 | 297 | * Also, we don't support any form of IRQ/FIQ bypass. |
f7b6985c EA |
298 | * This goes with the spec allowing the value to be RAO/WI. |
299 | */ | |
0aa1de57 | 300 | if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { |
4dfc0505 MZ |
301 | vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB | |
302 | ICC_SRE_EL1_DFB | | |
303 | ICC_SRE_EL1_SRE); | |
0aa1de57 AP |
304 | vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE; |
305 | } else { | |
f7b6985c | 306 | vgic_v3->vgic_sre = 0; |
0aa1de57 | 307 | } |
f7b6985c | 308 | |
d017d7b0 VK |
309 | vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 & |
310 | ICH_VTR_ID_BITS_MASK) >> | |
311 | ICH_VTR_ID_BITS_SHIFT; | |
312 | vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 & | |
313 | ICH_VTR_PRI_BITS_MASK) >> | |
314 | ICH_VTR_PRI_BITS_SHIFT) + 1; | |
315 | ||
f7b6985c EA |
316 | /* Get the show on the road... */ |
317 | vgic_v3->vgic_hcr = ICH_HCR_EN; | |
abf55766 MZ |
318 | if (group0_trap) |
319 | vgic_v3->vgic_hcr |= ICH_HCR_TALL0; | |
9c7bfc28 MZ |
320 | if (group1_trap) |
321 | vgic_v3->vgic_hcr |= ICH_HCR_TALL1; | |
ff89511e MZ |
322 | if (common_trap) |
323 | vgic_v3->vgic_hcr |= ICH_HCR_TC; | |
ad275b8b EA |
324 | } |
325 | ||
44de9d68 EA |
326 | int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq) |
327 | { | |
328 | struct kvm_vcpu *vcpu; | |
329 | int byte_offset, bit_nr; | |
330 | gpa_t pendbase, ptr; | |
331 | bool status; | |
332 | u8 val; | |
333 | int ret; | |
006df0f3 | 334 | unsigned long flags; |
44de9d68 EA |
335 | |
336 | retry: | |
337 | vcpu = irq->target_vcpu; | |
338 | if (!vcpu) | |
339 | return 0; | |
340 | ||
341 | pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); | |
342 | ||
343 | byte_offset = irq->intid / BITS_PER_BYTE; | |
344 | bit_nr = irq->intid % BITS_PER_BYTE; | |
345 | ptr = pendbase + byte_offset; | |
346 | ||
347 | ret = kvm_read_guest(kvm, ptr, &val, 1); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
351 | status = val & (1 << bit_nr); | |
352 | ||
006df0f3 | 353 | spin_lock_irqsave(&irq->irq_lock, flags); |
44de9d68 | 354 | if (irq->target_vcpu != vcpu) { |
006df0f3 | 355 | spin_unlock_irqrestore(&irq->irq_lock, flags); |
44de9d68 EA |
356 | goto retry; |
357 | } | |
358 | irq->pending_latch = status; | |
006df0f3 | 359 | vgic_queue_irq_unlock(vcpu->kvm, irq, flags); |
44de9d68 EA |
360 | |
361 | if (status) { | |
362 | /* clear consumed data */ | |
363 | val &= ~(1 << bit_nr); | |
364 | ret = kvm_write_guest(kvm, ptr, &val, 1); | |
365 | if (ret) | |
366 | return ret; | |
367 | } | |
368 | return 0; | |
369 | } | |
370 | ||
28077125 EA |
371 | /** |
372 | * vgic_its_save_pending_tables - Save the pending tables into guest RAM | |
373 | * kvm lock and all vcpu lock must be held | |
374 | */ | |
375 | int vgic_v3_save_pending_tables(struct kvm *kvm) | |
376 | { | |
377 | struct vgic_dist *dist = &kvm->arch.vgic; | |
378 | int last_byte_offset = -1; | |
379 | struct vgic_irq *irq; | |
380 | int ret; | |
ddb4b010 | 381 | u8 val; |
28077125 EA |
382 | |
383 | list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) { | |
384 | int byte_offset, bit_nr; | |
385 | struct kvm_vcpu *vcpu; | |
386 | gpa_t pendbase, ptr; | |
387 | bool stored; | |
28077125 EA |
388 | |
389 | vcpu = irq->target_vcpu; | |
390 | if (!vcpu) | |
391 | continue; | |
392 | ||
393 | pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); | |
394 | ||
395 | byte_offset = irq->intid / BITS_PER_BYTE; | |
396 | bit_nr = irq->intid % BITS_PER_BYTE; | |
397 | ptr = pendbase + byte_offset; | |
398 | ||
399 | if (byte_offset != last_byte_offset) { | |
400 | ret = kvm_read_guest(kvm, ptr, &val, 1); | |
401 | if (ret) | |
402 | return ret; | |
403 | last_byte_offset = byte_offset; | |
404 | } | |
405 | ||
406 | stored = val & (1U << bit_nr); | |
407 | if (stored == irq->pending_latch) | |
408 | continue; | |
409 | ||
410 | if (irq->pending_latch) | |
411 | val |= 1 << bit_nr; | |
412 | else | |
413 | val &= ~(1 << bit_nr); | |
414 | ||
415 | ret = kvm_write_guest(kvm, ptr, &val, 1); | |
416 | if (ret) | |
417 | return ret; | |
418 | } | |
419 | return 0; | |
420 | } | |
421 | ||
028bf278 EA |
422 | /** |
423 | * vgic_v3_rdist_overlap - check if a region overlaps with any | |
424 | * existing redistributor region | |
425 | * | |
426 | * @kvm: kvm handle | |
427 | * @base: base of the region | |
428 | * @size: size of region | |
429 | * | |
430 | * Return: true if there is an overlap | |
431 | */ | |
432 | bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size) | |
433 | { | |
434 | struct vgic_dist *d = &kvm->arch.vgic; | |
435 | struct vgic_redist_region *rdreg; | |
436 | ||
437 | list_for_each_entry(rdreg, &d->rd_regions, list) { | |
438 | if ((base + size > rdreg->base) && | |
439 | (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg))) | |
440 | return true; | |
441 | } | |
442 | return false; | |
443 | } | |
444 | ||
9a746d75 CD |
445 | /* |
446 | * Check for overlapping regions and for regions crossing the end of memory | |
447 | * for base addresses which have already been set. | |
448 | */ | |
449 | bool vgic_v3_check_base(struct kvm *kvm) | |
b0442ee2 EA |
450 | { |
451 | struct vgic_dist *d = &kvm->arch.vgic; | |
028bf278 | 452 | struct vgic_redist_region *rdreg; |
b0442ee2 | 453 | |
9a746d75 CD |
454 | if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && |
455 | d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base) | |
b0442ee2 | 456 | return false; |
9a746d75 | 457 | |
028bf278 EA |
458 | list_for_each_entry(rdreg, &d->rd_regions, list) { |
459 | if (rdreg->base + vgic_v3_rd_region_size(kvm, rdreg) < | |
460 | rdreg->base) | |
461 | return false; | |
462 | } | |
dbd9733a | 463 | |
028bf278 | 464 | if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base)) |
b0442ee2 EA |
465 | return true; |
466 | ||
028bf278 EA |
467 | return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base, |
468 | KVM_VGIC_V3_DIST_SIZE); | |
b0442ee2 EA |
469 | } |
470 | ||
dc524619 EA |
471 | /** |
472 | * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one | |
473 | * which has free space to put a new rdist region. | |
474 | * | |
475 | * @rd_regions: redistributor region list head | |
476 | * | |
477 | * A redistributor regions maps n redistributors, n = region size / (2 x 64kB). | |
478 | * Stride between redistributors is 0 and regions are filled in the index order. | |
479 | * | |
480 | * Return: the redist region handle, if any, that has space to map a new rdist | |
481 | * region. | |
482 | */ | |
483 | struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions) | |
484 | { | |
485 | struct vgic_redist_region *rdreg; | |
486 | ||
487 | list_for_each_entry(rdreg, rd_regions, list) { | |
488 | if (!vgic_v3_redist_region_full(rdreg)) | |
489 | return rdreg; | |
490 | } | |
491 | return NULL; | |
492 | } | |
493 | ||
b0442ee2 EA |
494 | int vgic_v3_map_resources(struct kvm *kvm) |
495 | { | |
496 | int ret = 0; | |
497 | struct vgic_dist *dist = &kvm->arch.vgic; | |
dbd9733a EA |
498 | struct vgic_redist_region *rdreg = |
499 | list_first_entry(&dist->rd_regions, | |
500 | struct vgic_redist_region, list); | |
b0442ee2 EA |
501 | |
502 | if (vgic_ready(kvm)) | |
503 | goto out; | |
504 | ||
dbd9733a | 505 | if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) || !rdreg) { |
b0442ee2 EA |
506 | kvm_err("Need to set vgic distributor addresses first\n"); |
507 | ret = -ENXIO; | |
508 | goto out; | |
509 | } | |
510 | ||
511 | if (!vgic_v3_check_base(kvm)) { | |
512 | kvm_err("VGIC redist and dist frames overlap\n"); | |
513 | ret = -EINVAL; | |
514 | goto out; | |
515 | } | |
516 | ||
517 | /* | |
518 | * For a VGICv3 we require the userland to explicitly initialize | |
519 | * the VGIC before we need to use it. | |
520 | */ | |
521 | if (!vgic_initialized(kvm)) { | |
522 | ret = -EBUSY; | |
523 | goto out; | |
524 | } | |
525 | ||
526 | ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3); | |
527 | if (ret) { | |
528 | kvm_err("Unable to register VGICv3 dist MMIO regions\n"); | |
529 | goto out; | |
530 | } | |
531 | ||
b0442ee2 EA |
532 | dist->ready = true; |
533 | ||
534 | out: | |
b0442ee2 EA |
535 | return ret; |
536 | } | |
537 | ||
59da1cbf MZ |
538 | DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap); |
539 | ||
e23f62f7 MZ |
540 | static int __init early_group0_trap_cfg(char *buf) |
541 | { | |
542 | return strtobool(buf, &group0_trap); | |
543 | } | |
544 | early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg); | |
545 | ||
182936ee MZ |
546 | static int __init early_group1_trap_cfg(char *buf) |
547 | { | |
548 | return strtobool(buf, &group1_trap); | |
549 | } | |
550 | early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg); | |
551 | ||
ff89511e MZ |
552 | static int __init early_common_trap_cfg(char *buf) |
553 | { | |
554 | return strtobool(buf, &common_trap); | |
555 | } | |
556 | early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg); | |
557 | ||
a7546054 MZ |
558 | static int __init early_gicv4_enable(char *buf) |
559 | { | |
560 | return strtobool(buf, &gicv4_enable); | |
561 | } | |
562 | early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable); | |
563 | ||
90977732 EA |
564 | /** |
565 | * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT | |
566 | * @node: pointer to the DT node | |
567 | * | |
568 | * Returns 0 if a GICv3 has been found, returns an error code otherwise | |
569 | */ | |
570 | int vgic_v3_probe(const struct gic_kvm_info *info) | |
571 | { | |
572 | u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2); | |
42c8870f | 573 | int ret; |
90977732 EA |
574 | |
575 | /* | |
576 | * The ListRegs field is 5 bits, but there is a architectural | |
577 | * maximum of 16 list registers. Just ignore bit 4... | |
578 | */ | |
579 | kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1; | |
580 | kvm_vgic_global_state.can_emulate_gicv2 = false; | |
d017d7b0 | 581 | kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2; |
90977732 | 582 | |
a7546054 MZ |
583 | /* GICv4 support? */ |
584 | if (info->has_v4) { | |
585 | kvm_vgic_global_state.has_gicv4 = gicv4_enable; | |
586 | kvm_info("GICv4 support %sabled\n", | |
587 | gicv4_enable ? "en" : "dis"); | |
588 | } | |
589 | ||
90977732 EA |
590 | if (!info->vcpu.start) { |
591 | kvm_info("GICv3: no GICV resource entry\n"); | |
592 | kvm_vgic_global_state.vcpu_base = 0; | |
593 | } else if (!PAGE_ALIGNED(info->vcpu.start)) { | |
594 | pr_warn("GICV physical address 0x%llx not page aligned\n", | |
595 | (unsigned long long)info->vcpu.start); | |
596 | kvm_vgic_global_state.vcpu_base = 0; | |
597 | } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) { | |
598 | pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n", | |
599 | (unsigned long long)resource_size(&info->vcpu), | |
600 | PAGE_SIZE); | |
601 | kvm_vgic_global_state.vcpu_base = 0; | |
602 | } else { | |
603 | kvm_vgic_global_state.vcpu_base = info->vcpu.start; | |
604 | kvm_vgic_global_state.can_emulate_gicv2 = true; | |
42c8870f AP |
605 | ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2); |
606 | if (ret) { | |
607 | kvm_err("Cannot register GICv2 KVM device.\n"); | |
608 | return ret; | |
609 | } | |
90977732 EA |
610 | kvm_info("vgic-v2@%llx\n", info->vcpu.start); |
611 | } | |
42c8870f AP |
612 | ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3); |
613 | if (ret) { | |
614 | kvm_err("Cannot register GICv3 KVM device.\n"); | |
615 | kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2); | |
616 | return ret; | |
617 | } | |
618 | ||
90977732 EA |
619 | if (kvm_vgic_global_state.vcpu_base == 0) |
620 | kvm_info("disabling GICv2 emulation\n"); | |
90977732 | 621 | |
690a3415 DD |
622 | #ifdef CONFIG_ARM64 |
623 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) { | |
624 | group0_trap = true; | |
625 | group1_trap = true; | |
626 | } | |
627 | #endif | |
628 | ||
ff89511e | 629 | if (group0_trap || group1_trap || common_trap) { |
2873b508 MZ |
630 | kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n", |
631 | group0_trap ? "G0" : "", | |
632 | group1_trap ? "G1" : "", | |
633 | common_trap ? "C" : ""); | |
182936ee MZ |
634 | static_branch_enable(&vgic_v3_cpuif_trap); |
635 | } | |
636 | ||
90977732 EA |
637 | kvm_vgic_global_state.vctrl_base = NULL; |
638 | kvm_vgic_global_state.type = VGIC_V3; | |
639 | kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS; | |
640 | ||
641 | return 0; | |
642 | } | |
328e5664 CD |
643 | |
644 | void vgic_v3_load(struct kvm_vcpu *vcpu) | |
645 | { | |
646 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
647 | ||
ff567614 MZ |
648 | /* |
649 | * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen | |
650 | * is dependent on ICC_SRE_EL1.SRE, and we have to perform the | |
651 | * VMCR_EL2 save/restore in the world switch. | |
652 | */ | |
653 | if (likely(cpu_if->vgic_sre)) | |
654 | kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr); | |
923a2e30 CD |
655 | |
656 | kvm_call_hyp(__vgic_v3_restore_aprs, vcpu); | |
2d0e63e0 CD |
657 | |
658 | if (has_vhe()) | |
659 | __vgic_v3_activate_traps(vcpu); | |
328e5664 CD |
660 | } |
661 | ||
662 | void vgic_v3_put(struct kvm_vcpu *vcpu) | |
663 | { | |
664 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
665 | ||
ff567614 MZ |
666 | if (likely(cpu_if->vgic_sre)) |
667 | cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr); | |
923a2e30 CD |
668 | |
669 | kvm_call_hyp(__vgic_v3_save_aprs, vcpu); | |
2d0e63e0 CD |
670 | |
671 | if (has_vhe()) | |
672 | __vgic_v3_deactivate_traps(vcpu); | |
328e5664 | 673 | } |