Commit | Line | Data |
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59529f69 MZ |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
13 | */ | |
14 | ||
15 | #include <linux/irqchip/arm-gic-v3.h> | |
16 | #include <linux/kvm.h> | |
17 | #include <linux/kvm_host.h> | |
90977732 EA |
18 | #include <kvm/arm_vgic.h> |
19 | #include <asm/kvm_mmu.h> | |
20 | #include <asm/kvm_asm.h> | |
59529f69 MZ |
21 | |
22 | #include "vgic.h" | |
23 | ||
abf55766 | 24 | static bool group0_trap; |
9c7bfc28 MZ |
25 | static bool group1_trap; |
26 | ||
af061499 | 27 | void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) |
59529f69 MZ |
28 | { |
29 | struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; | |
59529f69 | 30 | |
af061499 | 31 | cpuif->vgic_hcr |= ICH_HCR_UIE; |
59529f69 MZ |
32 | } |
33 | ||
af061499 | 34 | static bool lr_signals_eoi_mi(u64 lr_val) |
59529f69 | 35 | { |
af061499 CD |
36 | return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) && |
37 | !(lr_val & ICH_LR_HW); | |
59529f69 MZ |
38 | } |
39 | ||
40 | void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) | |
41 | { | |
8ac76ef4 CD |
42 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
43 | struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; | |
59529f69 MZ |
44 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
45 | int lr; | |
46 | ||
af061499 CD |
47 | cpuif->vgic_hcr &= ~ICH_HCR_UIE; |
48 | ||
8ac76ef4 | 49 | for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { |
59529f69 MZ |
50 | u64 val = cpuif->vgic_lr[lr]; |
51 | u32 intid; | |
52 | struct vgic_irq *irq; | |
53 | ||
54 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
55 | intid = val & ICH_LR_VIRTUAL_ID_MASK; | |
56 | else | |
57 | intid = val & GICH_LR_VIRTUALID; | |
af061499 CD |
58 | |
59 | /* Notify fds when the guest EOI'ed a level-triggered IRQ */ | |
60 | if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) | |
61 | kvm_notify_acked_irq(vcpu->kvm, 0, | |
62 | intid - VGIC_NR_PRIVATE_IRQS); | |
63 | ||
59529f69 | 64 | irq = vgic_get_irq(vcpu->kvm, vcpu, intid); |
3802411d AP |
65 | if (!irq) /* An LPI could have been unmapped. */ |
66 | continue; | |
59529f69 MZ |
67 | |
68 | spin_lock(&irq->irq_lock); | |
69 | ||
70 | /* Always preserve the active bit */ | |
71 | irq->active = !!(val & ICH_LR_ACTIVE_BIT); | |
72 | ||
73 | /* Edge is the only case where we preserve the pending bit */ | |
74 | if (irq->config == VGIC_CONFIG_EDGE && | |
75 | (val & ICH_LR_PENDING_BIT)) { | |
8694e4da | 76 | irq->pending_latch = true; |
59529f69 MZ |
77 | |
78 | if (vgic_irq_is_sgi(intid) && | |
79 | model == KVM_DEV_TYPE_ARM_VGIC_V2) { | |
80 | u32 cpuid = val & GICH_LR_PHYSID_CPUID; | |
81 | ||
82 | cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; | |
83 | irq->source |= (1 << cpuid); | |
84 | } | |
85 | } | |
86 | ||
637d122b MZ |
87 | /* |
88 | * Clear soft pending state when level irqs have been acked. | |
89 | * Always regenerate the pending state. | |
90 | */ | |
91 | if (irq->config == VGIC_CONFIG_LEVEL) { | |
92 | if (!(val & ICH_LR_PENDING_BIT)) | |
8694e4da | 93 | irq->pending_latch = false; |
59529f69 MZ |
94 | } |
95 | ||
96 | spin_unlock(&irq->irq_lock); | |
5dd4b924 | 97 | vgic_put_irq(vcpu->kvm, irq); |
59529f69 | 98 | } |
8ac76ef4 CD |
99 | |
100 | vgic_cpu->used_lrs = 0; | |
59529f69 MZ |
101 | } |
102 | ||
103 | /* Requires the irq to be locked already */ | |
104 | void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) | |
105 | { | |
106 | u32 model = vcpu->kvm->arch.vgic.vgic_model; | |
107 | u64 val = irq->intid; | |
108 | ||
8694e4da | 109 | if (irq_is_pending(irq)) { |
59529f69 MZ |
110 | val |= ICH_LR_PENDING_BIT; |
111 | ||
112 | if (irq->config == VGIC_CONFIG_EDGE) | |
8694e4da | 113 | irq->pending_latch = false; |
59529f69 MZ |
114 | |
115 | if (vgic_irq_is_sgi(irq->intid) && | |
116 | model == KVM_DEV_TYPE_ARM_VGIC_V2) { | |
117 | u32 src = ffs(irq->source); | |
118 | ||
119 | BUG_ON(!src); | |
120 | val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; | |
121 | irq->source &= ~(1 << (src - 1)); | |
122 | if (irq->source) | |
8694e4da | 123 | irq->pending_latch = true; |
59529f69 MZ |
124 | } |
125 | } | |
126 | ||
127 | if (irq->active) | |
128 | val |= ICH_LR_ACTIVE_BIT; | |
129 | ||
130 | if (irq->hw) { | |
131 | val |= ICH_LR_HW; | |
132 | val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; | |
3d6e77ad MZ |
133 | /* |
134 | * Never set pending+active on a HW interrupt, as the | |
135 | * pending state is kept at the physical distributor | |
136 | * level. | |
137 | */ | |
138 | if (irq->active && irq_is_pending(irq)) | |
139 | val &= ~ICH_LR_PENDING_BIT; | |
59529f69 MZ |
140 | } else { |
141 | if (irq->config == VGIC_CONFIG_LEVEL) | |
142 | val |= ICH_LR_EOI; | |
143 | } | |
144 | ||
145 | /* | |
146 | * We currently only support Group1 interrupts, which is a | |
147 | * known defect. This needs to be addressed at some point. | |
148 | */ | |
149 | if (model == KVM_DEV_TYPE_ARM_VGIC_V3) | |
150 | val |= ICH_LR_GROUP; | |
151 | ||
152 | val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; | |
153 | ||
154 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; | |
155 | } | |
156 | ||
157 | void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr) | |
158 | { | |
159 | vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0; | |
160 | } | |
e4823a7a AP |
161 | |
162 | void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
163 | { | |
328e5664 | 164 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; |
28232a43 | 165 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
e4823a7a AP |
166 | u32 vmcr; |
167 | ||
28232a43 CD |
168 | if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { |
169 | vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) & | |
170 | ICH_VMCR_ACK_CTL_MASK; | |
171 | vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) & | |
172 | ICH_VMCR_FIQ_EN_MASK; | |
173 | } else { | |
174 | /* | |
175 | * When emulating GICv3 on GICv3 with SRE=1 on the | |
176 | * VFIQEn bit is RES1 and the VAckCtl bit is RES0. | |
177 | */ | |
178 | vmcr = ICH_VMCR_FIQ_EN_MASK; | |
179 | } | |
180 | ||
181 | vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK; | |
182 | vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK; | |
e4823a7a AP |
183 | vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; |
184 | vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; | |
185 | vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; | |
5fb247d7 VK |
186 | vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK; |
187 | vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK; | |
e4823a7a | 188 | |
328e5664 | 189 | cpu_if->vgic_vmcr = vmcr; |
e4823a7a AP |
190 | } |
191 | ||
192 | void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
193 | { | |
328e5664 | 194 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; |
28232a43 | 195 | u32 model = vcpu->kvm->arch.vgic.vgic_model; |
328e5664 CD |
196 | u32 vmcr; |
197 | ||
198 | vmcr = cpu_if->vgic_vmcr; | |
e4823a7a | 199 | |
28232a43 CD |
200 | if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { |
201 | vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >> | |
202 | ICH_VMCR_ACK_CTL_SHIFT; | |
203 | vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >> | |
204 | ICH_VMCR_FIQ_EN_SHIFT; | |
205 | } else { | |
206 | /* | |
207 | * When emulating GICv3 on GICv3 with SRE=1 on the | |
208 | * VFIQEn bit is RES1 and the VAckCtl bit is RES0. | |
209 | */ | |
210 | vmcrp->fiqen = 1; | |
211 | vmcrp->ackctl = 0; | |
212 | } | |
213 | ||
214 | vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; | |
215 | vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT; | |
e4823a7a AP |
216 | vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; |
217 | vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; | |
218 | vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; | |
5fb247d7 VK |
219 | vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT; |
220 | vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT; | |
e4823a7a | 221 | } |
90977732 | 222 | |
0aa1de57 AP |
223 | #define INITIAL_PENDBASER_VALUE \ |
224 | (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \ | |
225 | GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \ | |
226 | GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)) | |
227 | ||
ad275b8b EA |
228 | void vgic_v3_enable(struct kvm_vcpu *vcpu) |
229 | { | |
f7b6985c EA |
230 | struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; |
231 | ||
232 | /* | |
233 | * By forcing VMCR to zero, the GIC will restore the binary | |
234 | * points to their reset values. Anything else resets to zero | |
235 | * anyway. | |
236 | */ | |
237 | vgic_v3->vgic_vmcr = 0; | |
238 | vgic_v3->vgic_elrsr = ~0; | |
239 | ||
240 | /* | |
241 | * If we are emulating a GICv3, we do it in an non-GICv2-compatible | |
242 | * way, so we force SRE to 1 to demonstrate this to the guest. | |
4dfc0505 | 243 | * Also, we don't support any form of IRQ/FIQ bypass. |
f7b6985c EA |
244 | * This goes with the spec allowing the value to be RAO/WI. |
245 | */ | |
0aa1de57 | 246 | if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { |
4dfc0505 MZ |
247 | vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB | |
248 | ICC_SRE_EL1_DFB | | |
249 | ICC_SRE_EL1_SRE); | |
0aa1de57 AP |
250 | vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE; |
251 | } else { | |
f7b6985c | 252 | vgic_v3->vgic_sre = 0; |
0aa1de57 | 253 | } |
f7b6985c | 254 | |
d017d7b0 VK |
255 | vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 & |
256 | ICH_VTR_ID_BITS_MASK) >> | |
257 | ICH_VTR_ID_BITS_SHIFT; | |
258 | vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 & | |
259 | ICH_VTR_PRI_BITS_MASK) >> | |
260 | ICH_VTR_PRI_BITS_SHIFT) + 1; | |
261 | ||
f7b6985c EA |
262 | /* Get the show on the road... */ |
263 | vgic_v3->vgic_hcr = ICH_HCR_EN; | |
abf55766 MZ |
264 | if (group0_trap) |
265 | vgic_v3->vgic_hcr |= ICH_HCR_TALL0; | |
9c7bfc28 MZ |
266 | if (group1_trap) |
267 | vgic_v3->vgic_hcr |= ICH_HCR_TALL1; | |
ad275b8b EA |
268 | } |
269 | ||
44de9d68 EA |
270 | int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq) |
271 | { | |
272 | struct kvm_vcpu *vcpu; | |
273 | int byte_offset, bit_nr; | |
274 | gpa_t pendbase, ptr; | |
275 | bool status; | |
276 | u8 val; | |
277 | int ret; | |
278 | ||
279 | retry: | |
280 | vcpu = irq->target_vcpu; | |
281 | if (!vcpu) | |
282 | return 0; | |
283 | ||
284 | pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); | |
285 | ||
286 | byte_offset = irq->intid / BITS_PER_BYTE; | |
287 | bit_nr = irq->intid % BITS_PER_BYTE; | |
288 | ptr = pendbase + byte_offset; | |
289 | ||
290 | ret = kvm_read_guest(kvm, ptr, &val, 1); | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
294 | status = val & (1 << bit_nr); | |
295 | ||
296 | spin_lock(&irq->irq_lock); | |
297 | if (irq->target_vcpu != vcpu) { | |
298 | spin_unlock(&irq->irq_lock); | |
299 | goto retry; | |
300 | } | |
301 | irq->pending_latch = status; | |
302 | vgic_queue_irq_unlock(vcpu->kvm, irq); | |
303 | ||
304 | if (status) { | |
305 | /* clear consumed data */ | |
306 | val &= ~(1 << bit_nr); | |
307 | ret = kvm_write_guest(kvm, ptr, &val, 1); | |
308 | if (ret) | |
309 | return ret; | |
310 | } | |
311 | return 0; | |
312 | } | |
313 | ||
28077125 EA |
314 | /** |
315 | * vgic_its_save_pending_tables - Save the pending tables into guest RAM | |
316 | * kvm lock and all vcpu lock must be held | |
317 | */ | |
318 | int vgic_v3_save_pending_tables(struct kvm *kvm) | |
319 | { | |
320 | struct vgic_dist *dist = &kvm->arch.vgic; | |
321 | int last_byte_offset = -1; | |
322 | struct vgic_irq *irq; | |
323 | int ret; | |
324 | ||
325 | list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) { | |
326 | int byte_offset, bit_nr; | |
327 | struct kvm_vcpu *vcpu; | |
328 | gpa_t pendbase, ptr; | |
329 | bool stored; | |
330 | u8 val; | |
331 | ||
332 | vcpu = irq->target_vcpu; | |
333 | if (!vcpu) | |
334 | continue; | |
335 | ||
336 | pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); | |
337 | ||
338 | byte_offset = irq->intid / BITS_PER_BYTE; | |
339 | bit_nr = irq->intid % BITS_PER_BYTE; | |
340 | ptr = pendbase + byte_offset; | |
341 | ||
342 | if (byte_offset != last_byte_offset) { | |
343 | ret = kvm_read_guest(kvm, ptr, &val, 1); | |
344 | if (ret) | |
345 | return ret; | |
346 | last_byte_offset = byte_offset; | |
347 | } | |
348 | ||
349 | stored = val & (1U << bit_nr); | |
350 | if (stored == irq->pending_latch) | |
351 | continue; | |
352 | ||
353 | if (irq->pending_latch) | |
354 | val |= 1 << bit_nr; | |
355 | else | |
356 | val &= ~(1 << bit_nr); | |
357 | ||
358 | ret = kvm_write_guest(kvm, ptr, &val, 1); | |
359 | if (ret) | |
360 | return ret; | |
361 | } | |
362 | return 0; | |
363 | } | |
364 | ||
9a746d75 CD |
365 | /* |
366 | * Check for overlapping regions and for regions crossing the end of memory | |
367 | * for base addresses which have already been set. | |
368 | */ | |
369 | bool vgic_v3_check_base(struct kvm *kvm) | |
b0442ee2 EA |
370 | { |
371 | struct vgic_dist *d = &kvm->arch.vgic; | |
372 | gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE; | |
373 | ||
374 | redist_size *= atomic_read(&kvm->online_vcpus); | |
375 | ||
9a746d75 CD |
376 | if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && |
377 | d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base) | |
b0442ee2 | 378 | return false; |
9a746d75 CD |
379 | |
380 | if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) && | |
381 | d->vgic_redist_base + redist_size < d->vgic_redist_base) | |
b0442ee2 EA |
382 | return false; |
383 | ||
9a746d75 CD |
384 | /* Both base addresses must be set to check if they overlap */ |
385 | if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) || | |
386 | IS_VGIC_ADDR_UNDEF(d->vgic_redist_base)) | |
387 | return true; | |
388 | ||
b0442ee2 EA |
389 | if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base) |
390 | return true; | |
391 | if (d->vgic_redist_base + redist_size <= d->vgic_dist_base) | |
392 | return true; | |
393 | ||
394 | return false; | |
395 | } | |
396 | ||
397 | int vgic_v3_map_resources(struct kvm *kvm) | |
398 | { | |
399 | int ret = 0; | |
400 | struct vgic_dist *dist = &kvm->arch.vgic; | |
401 | ||
402 | if (vgic_ready(kvm)) | |
403 | goto out; | |
404 | ||
405 | if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) || | |
406 | IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) { | |
407 | kvm_err("Need to set vgic distributor addresses first\n"); | |
408 | ret = -ENXIO; | |
409 | goto out; | |
410 | } | |
411 | ||
412 | if (!vgic_v3_check_base(kvm)) { | |
413 | kvm_err("VGIC redist and dist frames overlap\n"); | |
414 | ret = -EINVAL; | |
415 | goto out; | |
416 | } | |
417 | ||
418 | /* | |
419 | * For a VGICv3 we require the userland to explicitly initialize | |
420 | * the VGIC before we need to use it. | |
421 | */ | |
422 | if (!vgic_initialized(kvm)) { | |
423 | ret = -EBUSY; | |
424 | goto out; | |
425 | } | |
426 | ||
427 | ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3); | |
428 | if (ret) { | |
429 | kvm_err("Unable to register VGICv3 dist MMIO regions\n"); | |
430 | goto out; | |
431 | } | |
432 | ||
b0442ee2 EA |
433 | dist->ready = true; |
434 | ||
435 | out: | |
b0442ee2 EA |
436 | return ret; |
437 | } | |
438 | ||
59da1cbf MZ |
439 | DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap); |
440 | ||
182936ee MZ |
441 | static int __init early_group1_trap_cfg(char *buf) |
442 | { | |
443 | return strtobool(buf, &group1_trap); | |
444 | } | |
445 | early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg); | |
446 | ||
90977732 EA |
447 | /** |
448 | * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT | |
449 | * @node: pointer to the DT node | |
450 | * | |
451 | * Returns 0 if a GICv3 has been found, returns an error code otherwise | |
452 | */ | |
453 | int vgic_v3_probe(const struct gic_kvm_info *info) | |
454 | { | |
455 | u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2); | |
42c8870f | 456 | int ret; |
90977732 EA |
457 | |
458 | /* | |
459 | * The ListRegs field is 5 bits, but there is a architectural | |
460 | * maximum of 16 list registers. Just ignore bit 4... | |
461 | */ | |
462 | kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1; | |
463 | kvm_vgic_global_state.can_emulate_gicv2 = false; | |
d017d7b0 | 464 | kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2; |
90977732 EA |
465 | |
466 | if (!info->vcpu.start) { | |
467 | kvm_info("GICv3: no GICV resource entry\n"); | |
468 | kvm_vgic_global_state.vcpu_base = 0; | |
469 | } else if (!PAGE_ALIGNED(info->vcpu.start)) { | |
470 | pr_warn("GICV physical address 0x%llx not page aligned\n", | |
471 | (unsigned long long)info->vcpu.start); | |
472 | kvm_vgic_global_state.vcpu_base = 0; | |
473 | } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) { | |
474 | pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n", | |
475 | (unsigned long long)resource_size(&info->vcpu), | |
476 | PAGE_SIZE); | |
477 | kvm_vgic_global_state.vcpu_base = 0; | |
478 | } else { | |
479 | kvm_vgic_global_state.vcpu_base = info->vcpu.start; | |
480 | kvm_vgic_global_state.can_emulate_gicv2 = true; | |
42c8870f AP |
481 | ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2); |
482 | if (ret) { | |
483 | kvm_err("Cannot register GICv2 KVM device.\n"); | |
484 | return ret; | |
485 | } | |
90977732 EA |
486 | kvm_info("vgic-v2@%llx\n", info->vcpu.start); |
487 | } | |
42c8870f AP |
488 | ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3); |
489 | if (ret) { | |
490 | kvm_err("Cannot register GICv3 KVM device.\n"); | |
491 | kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2); | |
492 | return ret; | |
493 | } | |
494 | ||
90977732 EA |
495 | if (kvm_vgic_global_state.vcpu_base == 0) |
496 | kvm_info("disabling GICv2 emulation\n"); | |
90977732 | 497 | |
abf55766 | 498 | if (group0_trap || group1_trap) { |
182936ee MZ |
499 | kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n"); |
500 | static_branch_enable(&vgic_v3_cpuif_trap); | |
501 | } | |
502 | ||
90977732 EA |
503 | kvm_vgic_global_state.vctrl_base = NULL; |
504 | kvm_vgic_global_state.type = VGIC_V3; | |
505 | kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS; | |
506 | ||
507 | return 0; | |
508 | } | |
328e5664 CD |
509 | |
510 | void vgic_v3_load(struct kvm_vcpu *vcpu) | |
511 | { | |
512 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
513 | ||
ff567614 MZ |
514 | /* |
515 | * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen | |
516 | * is dependent on ICC_SRE_EL1.SRE, and we have to perform the | |
517 | * VMCR_EL2 save/restore in the world switch. | |
518 | */ | |
519 | if (likely(cpu_if->vgic_sre)) | |
520 | kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr); | |
328e5664 CD |
521 | } |
522 | ||
523 | void vgic_v3_put(struct kvm_vcpu *vcpu) | |
524 | { | |
525 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
526 | ||
ff567614 MZ |
527 | if (likely(cpu_if->vgic_sre)) |
528 | cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr); | |
328e5664 | 529 | } |