[linux-2.6-block.git] / virt / kvm / arm / vgic / vgic-v2.c

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/irqchip/arm-gic.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/arm_vgic.h>
#include <asm/kvm_mmu.h>

#include "vgic.h"

static inline void vgic_v2_write_lr(int lr, u32 val)
{
	void __iomem *base = kvm_vgic_global_state.vctrl_base;

	writel_relaxed(val, base + GICH_LR0 + (lr * 4));
}

void vgic_v2_init_lrs(void)
{
	int i;

	for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
		vgic_v2_write_lr(i, 0);
}

void vgic_v2_set_npie(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;

	cpuif->vgic_hcr |= GICH_HCR_NPIE;
}

void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;

	cpuif->vgic_hcr |= GICH_HCR_UIE;
}

static bool lr_signals_eoi_mi(u32 lr_val)
{
	return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
	       !(lr_val & GICH_LR_HW);
}

/*
 * transfer the content of the LRs back into the corresponding ap_list:
 * - active bit is transferred as is
 * - pending bit is
 *   - transferred as is in case of edge sensitive IRQs
 *   - set to the line-level (resample time) for level sensitive IRQs
 */
void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
{
	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
	struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
	int lr;
	unsigned long flags;

	cpuif->vgic_hcr &= ~(GICH_HCR_UIE | GICH_HCR_NPIE);

	for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
		u32 val = cpuif->vgic_lr[lr];
		u32 intid = val & GICH_LR_VIRTUALID;
		struct vgic_irq *irq;

		/* Notify fds when the guest EOI'ed a level-triggered SPI */
		if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
			kvm_notify_acked_irq(vcpu->kvm, 0,
					     intid - VGIC_NR_PRIVATE_IRQS);

		irq = vgic_get_irq(vcpu->kvm, vcpu, intid);

		spin_lock_irqsave(&irq->irq_lock, flags);

		/* Always preserve the active bit */
		irq->active = !!(val & GICH_LR_ACTIVE_BIT);

		/* Edge is the only case where we preserve the pending bit */
		if (irq->config == VGIC_CONFIG_EDGE &&
		    (val & GICH_LR_PENDING_BIT)) {
			irq->pending_latch = true;

			if (vgic_irq_is_sgi(intid)) {
				u32 cpuid = val & GICH_LR_PHYSID_CPUID;

				cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
				irq->source |= (1 << cpuid);
			}
		}

		/*
		 * Clear soft pending state when level irqs have been acked.
		 * Always regenerate the pending state.
		 */
		if (irq->config == VGIC_CONFIG_LEVEL) {
			if (!(val & GICH_LR_PENDING_BIT))
				irq->pending_latch = false;
		}

		/*
		 * Level-triggered mapped IRQs are special because we only
		 * observe rising edges as input to the VGIC.
		 *
		 * If the guest never acked the interrupt we have to sample
		 * the physical line and set the line level, because the
		 * device state could have changed or we simply need to
		 * process the still pending interrupt later.
		 *
		 * If this causes us to lower the level, we have to also clear
		 * the physical active state, since we will otherwise never be
		 * told when the interrupt becomes asserted again.
		 */
		if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
			irq->line_level = vgic_get_phys_line_level(irq);

			if (!irq->line_level)
				vgic_irq_set_phys_active(irq, false);
		}

		spin_unlock_irqrestore(&irq->irq_lock, flags);
		vgic_put_irq(vcpu->kvm, irq);
	}

	vgic_cpu->used_lrs = 0;
}

/*
 * Populates the particular LR with the state of a given IRQ:
 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 * - for a level sensitive IRQ the pending state value is unchanged;
 *   it is dictated directly by the input level
 *
 * If @irq describes an SGI with multiple sources, we choose the
 * lowest-numbered source VCPU and clear that bit in the source bitmap.
 *
 * The irq_lock must be held by the caller.
 */
void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
{
	u32 val = irq->intid;

	if (irq_is_pending(irq)) {
		val |= GICH_LR_PENDING_BIT;

		if (irq->config == VGIC_CONFIG_EDGE)
			irq->pending_latch = false;

		if (vgic_irq_is_sgi(irq->intid)) {
			u32 src = ffs(irq->source);

			BUG_ON(!src);
			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
			irq->source &= ~(1 << (src - 1));
			if (irq->source)
				irq->pending_latch = true;
		}
	}

	if (irq->active)
		val |= GICH_LR_ACTIVE_BIT;

	if (irq->hw) {
		val |= GICH_LR_HW;
		val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
		/*
		 * Never set pending+active on a HW interrupt, as the
		 * pending state is kept at the physical distributor
		 * level.
		 */
		if (irq->active && irq_is_pending(irq))
			val &= ~GICH_LR_PENDING_BIT;
	} else {
		if (irq->config == VGIC_CONFIG_LEVEL)
			val |= GICH_LR_EOI;
	}

	/*
	 * Level-triggered mapped IRQs are special because we only observe
	 * rising edges as input to the VGIC.  We therefore lower the line
	 * level here, so that we can take new virtual IRQs.  See
	 * vgic_v2_fold_lr_state for more info.
	 */
	if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
		irq->line_level = false;

	/* The GICv2 LR only holds five bits of priority. */
	val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;

	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
}

void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
{
	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
}

void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
	u32 vmcr;

	vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
		GICH_VMCR_ENABLE_GRP0_MASK;
	vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
		GICH_VMCR_ENABLE_GRP1_MASK;
	vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
		GICH_VMCR_ACK_CTL_MASK;
	vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
		GICH_VMCR_FIQ_EN_MASK;
	vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
		GICH_VMCR_CBPR_MASK;
	vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
		GICH_VMCR_EOI_MODE_MASK;
	vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
		GICH_VMCR_ALIAS_BINPOINT_MASK;
	vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
		GICH_VMCR_BINPOINT_MASK;
	vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
		 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;

	cpu_if->vgic_vmcr = vmcr;
}

void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
	u32 vmcr;

	vmcr = cpu_if->vgic_vmcr;

	vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
		GICH_VMCR_ENABLE_GRP0_SHIFT;
	vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
		GICH_VMCR_ENABLE_GRP1_SHIFT;
	vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
		GICH_VMCR_ACK_CTL_SHIFT;
	vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
		GICH_VMCR_FIQ_EN_SHIFT;
	vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
		GICH_VMCR_CBPR_SHIFT;
	vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
		GICH_VMCR_EOI_MODE_SHIFT;

	vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
			GICH_VMCR_ALIAS_BINPOINT_SHIFT;
	vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
			GICH_VMCR_BINPOINT_SHIFT;
	vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
			GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
}

void vgic_v2_enable(struct kvm_vcpu *vcpu)
{
	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;

	/* Get the show on the road... */
	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
}

/* check for overlapping regions and for regions crossing the end of memory */
static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
{
	if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
		return false;
	if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
		return false;

	if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
		return true;
	if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
		return true;

	return false;
}

int vgic_v2_map_resources(struct kvm *kvm)
{
	struct vgic_dist *dist = &kvm->arch.vgic;
	int ret = 0;

	if (vgic_ready(kvm))
		goto out;

	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
	    IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
		kvm_err("Need to set vgic cpu and dist addresses first\n");
		ret = -ENXIO;
		goto out;
	}

	if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
		kvm_err("VGIC CPU and dist frames overlap\n");
		ret = -EINVAL;
		goto out;
	}

	/*
	 * Initialize the vgic if this hasn't already been done on demand by
	 * accessing the vgic state from userspace.
	 */
	ret = vgic_init(kvm);
	if (ret) {
		kvm_err("Unable to initialize VGIC dynamic data structures\n");
		goto out;
	}

	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
	if (ret) {
		kvm_err("Unable to register VGIC MMIO regions\n");
		goto out;
	}

	if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
		ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
					    kvm_vgic_global_state.vcpu_base,
					    KVM_VGIC_V2_CPU_SIZE, true);
		if (ret) {
			kvm_err("Unable to remap VGIC CPU to VCPU\n");
			goto out;
		}
	}

	dist->ready = true;

out:
	return ret;
}

DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);

/**
 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 * @node:	pointer to the DT node
 *
 * Returns 0 if a GICv2 has been found, returns an error code otherwise
 */
int vgic_v2_probe(const struct gic_kvm_info *info)
{
	int ret;
	u32 vtr;

	if (!info->vctrl.start) {
		kvm_err("GICH not present in the firmware table\n");
		return -ENXIO;
	}

	if (!PAGE_ALIGNED(info->vcpu.start) ||
	    !PAGE_ALIGNED(resource_size(&info->vcpu))) {
		kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");

		ret = create_hyp_io_mappings(info->vcpu.start,
					     resource_size(&info->vcpu),
					     &kvm_vgic_global_state.vcpu_base_va,
					     &kvm_vgic_global_state.vcpu_hyp_va);
		if (ret) {
			kvm_err("Cannot map GICV into hyp\n");
			goto out;
		}

		static_branch_enable(&vgic_v2_cpuif_trap);
	}

	ret = create_hyp_io_mappings(info->vctrl.start,
				     resource_size(&info->vctrl),
				     &kvm_vgic_global_state.vctrl_base,
				     &kvm_vgic_global_state.vctrl_hyp);
	if (ret) {
		kvm_err("Cannot map VCTRL into hyp\n");
		goto out;
	}

	vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
	kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;

	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
	if (ret) {
		kvm_err("Cannot register GICv2 KVM device\n");
		goto out;
	}

	kvm_vgic_global_state.can_emulate_gicv2 = true;
	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	kvm_vgic_global_state.type = VGIC_V2;
	kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;

	kvm_debug("vgic-v2@%llx\n", info->vctrl.start);

	return 0;
out:
	if (kvm_vgic_global_state.vctrl_base)
		iounmap(kvm_vgic_global_state.vctrl_base);
	if (kvm_vgic_global_state.vcpu_base_va)
		iounmap(kvm_vgic_global_state.vcpu_base_va);

	return ret;
}

static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
{
	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
	u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
	u64 elrsr;
	int i;

	elrsr = readl_relaxed(base + GICH_ELRSR0);
	if (unlikely(used_lrs > 32))
		elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32;

	for (i = 0; i < used_lrs; i++) {
		if (elrsr & (1UL << i))
			cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
		else
			cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));

		writel_relaxed(0, base + GICH_LR0 + (i * 4));
	}
}

void vgic_v2_save_state(struct kvm_vcpu *vcpu)
{
	void __iomem *base = kvm_vgic_global_state.vctrl_base;
	u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;

	if (!base)
		return;

	if (used_lrs) {
		save_lrs(vcpu, base);
		writel_relaxed(0, base + GICH_HCR);
	}
}

void vgic_v2_restore_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
	void __iomem *base = kvm_vgic_global_state.vctrl_base;
	u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
	int i;

	if (!base)
		return;

	if (used_lrs) {
		writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
		for (i = 0; i < used_lrs; i++) {
			writel_relaxed(cpu_if->vgic_lr[i],
				       base + GICH_LR0 + (i * 4));
		}
	}
}

void vgic_v2_load(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;

	writel_relaxed(cpu_if->vgic_vmcr,
		       kvm_vgic_global_state.vctrl_base + GICH_VMCR);
	writel_relaxed(cpu_if->vgic_apr,
		       kvm_vgic_global_state.vctrl_base + GICH_APR);
}

void vgic_v2_put(struct kvm_vcpu *vcpu)
{
	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;

	cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
	cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
}
Commit	Line	Data
140b086d MZ	1	/*
	2	* Copyright (C) 2015, 2016 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/irqchip/arm-gic.h>
	18	#include <linux/kvm.h>
	19	#include <linux/kvm_host.h>
90977732 EA	20	#include <kvm/arm_vgic.h>
90977732 EA	21	#include <asm/kvm_mmu.h>
140b086d MZ	22
	23	#include "vgic.h"
	24
5b0d2cc2 CD	25	static inline void vgic_v2_write_lr(int lr, u32 val)
	26	{
	27	void __iomem *base = kvm_vgic_global_state.vctrl_base;
	28
	29	writel_relaxed(val, base + GICH_LR0 + (lr * 4));
	30	}
	31
	32	void vgic_v2_init_lrs(void)
	33	{
	34	int i;
	35
	36	for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
	37	vgic_v2_write_lr(i, 0);
	38	}
	39
16ca6a60 MZ	40	void vgic_v2_set_npie(struct kvm_vcpu *vcpu)
	41	{
	42	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
	43
	44	cpuif->vgic_hcr \|= GICH_HCR_NPIE;
	45	}
	46
af061499	47	void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
140b086d MZ	48	{
	49	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
	50
af061499	51	cpuif->vgic_hcr \|= GICH_HCR_UIE;
140b086d MZ	52	}
140b086d MZ	53
af061499	54	static bool lr_signals_eoi_mi(u32 lr_val)
140b086d	55	{
af061499 CD	56	return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
af061499 CD	57	!(lr_val & GICH_LR_HW);
140b086d MZ	58	}
	59
	60	/*
	61	* transfer the content of the LRs back into the corresponding ap_list:
	62	* - active bit is transferred as is
	63	* - pending bit is
	64	* - transferred as is in case of edge sensitive IRQs
	65	* - set to the line-level (resample time) for level sensitive IRQs
	66	*/
	67	void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
	68	{
8ac76ef4 CD	69	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
8ac76ef4 CD	70	struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
140b086d	71	int lr;
006df0f3	72	unsigned long flags;
140b086d	73
16ca6a60	74	cpuif->vgic_hcr &= ~(GICH_HCR_UIE \| GICH_HCR_NPIE);
af061499	75
8ac76ef4	76	for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
140b086d MZ	77	u32 val = cpuif->vgic_lr[lr];
	78	u32 intid = val & GICH_LR_VIRTUALID;
	79	struct vgic_irq *irq;
	80
af061499 CD	81	/* Notify fds when the guest EOI'ed a level-triggered SPI */
	82	if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
	83	kvm_notify_acked_irq(vcpu->kvm, 0,
	84	intid - VGIC_NR_PRIVATE_IRQS);
	85
140b086d MZ	86	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
140b086d MZ	87
006df0f3	88	spin_lock_irqsave(&irq->irq_lock, flags);
140b086d MZ	89
	90	/* Always preserve the active bit */
	91	irq->active = !!(val & GICH_LR_ACTIVE_BIT);
	92
	93	/* Edge is the only case where we preserve the pending bit */
	94	if (irq->config == VGIC_CONFIG_EDGE &&
	95	(val & GICH_LR_PENDING_BIT)) {
8694e4da	96	irq->pending_latch = true;
140b086d MZ	97
	98	if (vgic_irq_is_sgi(intid)) {
	99	u32 cpuid = val & GICH_LR_PHYSID_CPUID;
	100
	101	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
	102	irq->source \|= (1 << cpuid);
	103	}
	104	}
	105
df7942d1 MZ	106	/*
	107	* Clear soft pending state when level irqs have been acked.
	108	* Always regenerate the pending state.
	109	*/
	110	if (irq->config == VGIC_CONFIG_LEVEL) {
	111	if (!(val & GICH_LR_PENDING_BIT))
8694e4da	112	irq->pending_latch = false;
140b086d MZ	113	}
140b086d MZ	114
e40cc57b CD	115	/*
	116	* Level-triggered mapped IRQs are special because we only
	117	* observe rising edges as input to the VGIC.
	118	*
	119	* If the guest never acked the interrupt we have to sample
	120	* the physical line and set the line level, because the
	121	* device state could have changed or we simply need to
	122	* process the still pending interrupt later.
	123	*
	124	* If this causes us to lower the level, we have to also clear
	125	* the physical active state, since we will otherwise never be
	126	* told when the interrupt becomes asserted again.
	127	*/
	128	if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
	129	irq->line_level = vgic_get_phys_line_level(irq);
	130
	131	if (!irq->line_level)
	132	vgic_irq_set_phys_active(irq, false);
	133	}
	134
006df0f3	135	spin_unlock_irqrestore(&irq->irq_lock, flags);
5dd4b924	136	vgic_put_irq(vcpu->kvm, irq);
140b086d	137	}
8ac76ef4 CD	138
8ac76ef4 CD	139	vgic_cpu->used_lrs = 0;
140b086d MZ	140	}
	141
	142	/*
	143	* Populates the particular LR with the state of a given IRQ:
	144	* - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
	145	* - for a level sensitive IRQ the pending state value is unchanged;
	146	* it is dictated directly by the input level
	147	*
	148	* If @irq describes an SGI with multiple sources, we choose the
	149	* lowest-numbered source VCPU and clear that bit in the source bitmap.
	150	*
	151	* The irq_lock must be held by the caller.
	152	*/
	153	void vgic_v2_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr)
	154	{
	155	u32 val = irq->intid;
	156
8694e4da	157	if (irq_is_pending(irq)) {
140b086d MZ	158	val \|= GICH_LR_PENDING_BIT;
	159
	160	if (irq->config == VGIC_CONFIG_EDGE)
8694e4da	161	irq->pending_latch = false;
140b086d MZ	162
	163	if (vgic_irq_is_sgi(irq->intid)) {
	164	u32 src = ffs(irq->source);
	165
	166	BUG_ON(!src);
	167	val \|= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
	168	irq->source &= ~(1 << (src - 1));
	169	if (irq->source)
8694e4da	170	irq->pending_latch = true;
140b086d MZ	171	}
	172	}
	173
	174	if (irq->active)
	175	val \|= GICH_LR_ACTIVE_BIT;
	176
	177	if (irq->hw) {
	178	val \|= GICH_LR_HW;
	179	val \|= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
ddf42d06 MZ	180	/*
	181	* Never set pending+active on a HW interrupt, as the
	182	* pending state is kept at the physical distributor
	183	* level.
	184	*/
	185	if (irq->active && irq_is_pending(irq))
	186	val &= ~GICH_LR_PENDING_BIT;
140b086d MZ	187	} else {
	188	if (irq->config == VGIC_CONFIG_LEVEL)
	189	val \|= GICH_LR_EOI;
	190	}
	191
e40cc57b CD	192	/*
	193	* Level-triggered mapped IRQs are special because we only observe
	194	* rising edges as input to the VGIC. We therefore lower the line
	195	* level here, so that we can take new virtual IRQs. See
	196	* vgic_v2_fold_lr_state for more info.
	197	*/
	198	if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
	199	irq->line_level = false;
	200
140b086d MZ	201	/* The GICv2 LR only holds five bits of priority. */
	202	val \|= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
	203
	204	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
	205	}
	206
	207	void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
	208	{
	209	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
	210	}
e4823a7a AP	211
	212	void vgic_v2_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	213	{
328e5664	214	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
e4823a7a AP	215	u32 vmcr;
e4823a7a AP	216
28232a43 CD	217	vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
	218	GICH_VMCR_ENABLE_GRP0_MASK;
	219	vmcr \|= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
	220	GICH_VMCR_ENABLE_GRP1_MASK;
	221	vmcr \|= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
	222	GICH_VMCR_ACK_CTL_MASK;
	223	vmcr \|= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
	224	GICH_VMCR_FIQ_EN_MASK;
	225	vmcr \|= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
	226	GICH_VMCR_CBPR_MASK;
	227	vmcr \|= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
	228	GICH_VMCR_EOI_MODE_MASK;
e4823a7a AP	229	vmcr \|= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
	230	GICH_VMCR_ALIAS_BINPOINT_MASK;
	231	vmcr \|= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
	232	GICH_VMCR_BINPOINT_MASK;
6d56111c CD	233	vmcr \|= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
6d56111c CD	234	GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
e4823a7a	235
328e5664	236	cpu_if->vgic_vmcr = vmcr;
e4823a7a AP	237	}
	238
	239	void vgic_v2_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	240	{
328e5664 CD	241	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
	242	u32 vmcr;
	243
	244	vmcr = cpu_if->vgic_vmcr;
e4823a7a	245
28232a43 CD	246	vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
	247	GICH_VMCR_ENABLE_GRP0_SHIFT;
	248	vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
	249	GICH_VMCR_ENABLE_GRP1_SHIFT;
	250	vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
	251	GICH_VMCR_ACK_CTL_SHIFT;
	252	vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
	253	GICH_VMCR_FIQ_EN_SHIFT;
	254	vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
	255	GICH_VMCR_CBPR_SHIFT;
	256	vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
	257	GICH_VMCR_EOI_MODE_SHIFT;
	258
e4823a7a AP	259	vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
	260	GICH_VMCR_ALIAS_BINPOINT_SHIFT;
	261	vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
	262	GICH_VMCR_BINPOINT_SHIFT;
6d56111c CD	263	vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
6d56111c CD	264	GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
e4823a7a	265	}
90977732	266
ad275b8b EA	267	void vgic_v2_enable(struct kvm_vcpu *vcpu)
ad275b8b EA	268	{
f7b6985c EA	269	/*
	270	* By forcing VMCR to zero, the GIC will restore the binary
	271	* points to their reset values. Anything else resets to zero
	272	* anyway.
	273	*/
	274	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
f7b6985c EA	275
	276	/* Get the show on the road... */
	277	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
ad275b8b EA	278	}
ad275b8b EA	279
b0442ee2 EA	280	/* check for overlapping regions and for regions crossing the end of memory */
	281	static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
	282	{
	283	if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
	284	return false;
	285	if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
	286	return false;
	287
	288	if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
	289	return true;
	290	if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
	291	return true;
	292
	293	return false;
	294	}
	295
	296	int vgic_v2_map_resources(struct kvm *kvm)
	297	{
	298	struct vgic_dist *dist = &kvm->arch.vgic;
	299	int ret = 0;
	300
	301	if (vgic_ready(kvm))
	302	goto out;
	303
	304	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) \|\|
	305	IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
	306	kvm_err("Need to set vgic cpu and dist addresses first\n");
	307	ret = -ENXIO;
	308	goto out;
	309	}
	310
	311	if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
	312	kvm_err("VGIC CPU and dist frames overlap\n");
	313	ret = -EINVAL;
	314	goto out;
	315	}
	316
	317	/*
	318	* Initialize the vgic if this hasn't already been done on demand by
	319	* accessing the vgic state from userspace.
	320	*/
	321	ret = vgic_init(kvm);
	322	if (ret) {
	323	kvm_err("Unable to initialize VGIC dynamic data structures\n");
	324	goto out;
	325	}
	326
	327	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
	328	if (ret) {
	329	kvm_err("Unable to register VGIC MMIO regions\n");
	330	goto out;
	331	}
	332
a07d3b07 MZ	333	if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
	334	ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
	335	kvm_vgic_global_state.vcpu_base,
	336	KVM_VGIC_V2_CPU_SIZE, true);
	337	if (ret) {
	338	kvm_err("Unable to remap VGIC CPU to VCPU\n");
	339	goto out;
	340	}
b0442ee2 EA	341	}
	342
	343	dist->ready = true;
	344
	345	out:
b0442ee2 EA	346	return ret;
	347	}
	348
fb5ee369 MZ	349	DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
fb5ee369 MZ	350
90977732 EA	351	/**
	352	* vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
	353	* @node: pointer to the DT node
	354	*
	355	* Returns 0 if a GICv2 has been found, returns an error code otherwise
	356	*/
	357	int vgic_v2_probe(const struct gic_kvm_info *info)
	358	{
	359	int ret;
	360	u32 vtr;
	361
	362	if (!info->vctrl.start) {
	363	kvm_err("GICH not present in the firmware table\n");
	364	return -ENXIO;
	365	}
	366
a07d3b07 MZ	367	if (!PAGE_ALIGNED(info->vcpu.start) \|\|
	368	!PAGE_ALIGNED(resource_size(&info->vcpu))) {
	369	kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
90977732	370
807a3784 MZ	371	ret = create_hyp_io_mappings(info->vcpu.start,
807a3784 MZ	372	resource_size(&info->vcpu),
1bb32a44 MZ	373	&kvm_vgic_global_state.vcpu_base_va,
1bb32a44 MZ	374	&kvm_vgic_global_state.vcpu_hyp_va);
a07d3b07 MZ	375	if (ret) {
	376	kvm_err("Cannot map GICV into hyp\n");
	377	goto out;
	378	}
	379
	380	static_branch_enable(&vgic_v2_cpuif_trap);
90977732 EA	381	}
90977732 EA	382
807a3784 MZ	383	ret = create_hyp_io_mappings(info->vctrl.start,
807a3784 MZ	384	resource_size(&info->vctrl),
1bb32a44 MZ	385	&kvm_vgic_global_state.vctrl_base,
1bb32a44 MZ	386	&kvm_vgic_global_state.vctrl_hyp);
807a3784 MZ	387	if (ret) {
807a3784 MZ	388	kvm_err("Cannot map VCTRL into hyp\n");
a07d3b07	389	goto out;
90977732 EA	390	}
	391
	392	vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
	393	kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
	394
a07d3b07 MZ	395	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
	396	if (ret) {
	397	kvm_err("Cannot register GICv2 KVM device\n");
	398	goto out;
90977732 EA	399	}
	400
	401	kvm_vgic_global_state.can_emulate_gicv2 = true;
90977732 EA	402	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	403	kvm_vgic_global_state.type = VGIC_V2;
	404	kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
	405
76600428	406	kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
90977732 EA	407
90977732 EA	408	return 0;
a07d3b07 MZ	409	out:
	410	if (kvm_vgic_global_state.vctrl_base)
	411	iounmap(kvm_vgic_global_state.vctrl_base);
	412	if (kvm_vgic_global_state.vcpu_base_va)
	413	iounmap(kvm_vgic_global_state.vcpu_base_va);
	414
	415	return ret;
90977732	416	}
328e5664	417
75174ba6 CD	418	static void save_lrs(struct kvm_vcpu vcpu, void __iomem base)
	419	{
	420	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
	421	u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
	422	u64 elrsr;
	423	int i;
	424
	425	elrsr = readl_relaxed(base + GICH_ELRSR0);
	426	if (unlikely(used_lrs > 32))
	427	elrsr \|= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32;
	428
	429	for (i = 0; i < used_lrs; i++) {
	430	if (elrsr & (1UL << i))
	431	cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
	432	else
	433	cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
	434
	435	writel_relaxed(0, base + GICH_LR0 + (i * 4));
	436	}
	437	}
	438
	439	void vgic_v2_save_state(struct kvm_vcpu *vcpu)
	440	{
1bb32a44	441	void __iomem *base = kvm_vgic_global_state.vctrl_base;
75174ba6 CD	442	u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
	443
	444	if (!base)
	445	return;
	446
	447	if (used_lrs) {
75174ba6 CD	448	save_lrs(vcpu, base);
75174ba6 CD	449	writel_relaxed(0, base + GICH_HCR);
75174ba6 CD	450	}
	451	}
	452
	453	void vgic_v2_restore_state(struct kvm_vcpu *vcpu)
	454	{
75174ba6	455	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
1bb32a44	456	void __iomem *base = kvm_vgic_global_state.vctrl_base;
75174ba6 CD	457	u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
	458	int i;
	459
	460	if (!base)
	461	return;
	462
	463	if (used_lrs) {
	464	writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
75174ba6 CD	465	for (i = 0; i < used_lrs; i++) {
	466	writel_relaxed(cpu_if->vgic_lr[i],
	467	base + GICH_LR0 + (i * 4));
	468	}
	469	}
	470	}
	471
328e5664 CD	472	void vgic_v2_load(struct kvm_vcpu *vcpu)
	473	{
	474	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
328e5664	475
1bb32a44 MZ	476	writel_relaxed(cpu_if->vgic_vmcr,
	477	kvm_vgic_global_state.vctrl_base + GICH_VMCR);
	478	writel_relaxed(cpu_if->vgic_apr,
	479	kvm_vgic_global_state.vctrl_base + GICH_APR);
328e5664 CD	480	}
	481
	482	void vgic_v2_put(struct kvm_vcpu *vcpu)
	483	{
	484	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
328e5664	485
1bb32a44 MZ	486	cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
1bb32a44 MZ	487	cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
328e5664	488	}