Commit | Line | Data |
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140b086d MZ |
1 | /* |
2 | * Copyright (C) 2015, 2016 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/irqchip/arm-gic.h> | |
18 | #include <linux/kvm.h> | |
19 | #include <linux/kvm_host.h> | |
90977732 EA |
20 | #include <kvm/arm_vgic.h> |
21 | #include <asm/kvm_mmu.h> | |
140b086d MZ |
22 | |
23 | #include "vgic.h" | |
24 | ||
5b0d2cc2 CD |
25 | static inline void vgic_v2_write_lr(int lr, u32 val) |
26 | { | |
27 | void __iomem *base = kvm_vgic_global_state.vctrl_base; | |
28 | ||
29 | writel_relaxed(val, base + GICH_LR0 + (lr * 4)); | |
30 | } | |
31 | ||
32 | void vgic_v2_init_lrs(void) | |
33 | { | |
34 | int i; | |
35 | ||
36 | for (i = 0; i < kvm_vgic_global_state.nr_lr; i++) | |
37 | vgic_v2_write_lr(i, 0); | |
38 | } | |
39 | ||
af061499 | 40 | void vgic_v2_set_underflow(struct kvm_vcpu *vcpu) |
140b086d MZ |
41 | { |
42 | struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; | |
43 | ||
af061499 | 44 | cpuif->vgic_hcr |= GICH_HCR_UIE; |
140b086d MZ |
45 | } |
46 | ||
af061499 | 47 | static bool lr_signals_eoi_mi(u32 lr_val) |
140b086d | 48 | { |
af061499 CD |
49 | return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) && |
50 | !(lr_val & GICH_LR_HW); | |
140b086d MZ |
51 | } |
52 | ||
53 | /* | |
54 | * transfer the content of the LRs back into the corresponding ap_list: | |
55 | * - active bit is transferred as is | |
56 | * - pending bit is | |
57 | * - transferred as is in case of edge sensitive IRQs | |
58 | * - set to the line-level (resample time) for level sensitive IRQs | |
59 | */ | |
60 | void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) | |
61 | { | |
8ac76ef4 CD |
62 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
63 | struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2; | |
140b086d | 64 | int lr; |
006df0f3 | 65 | unsigned long flags; |
140b086d | 66 | |
53692908 | 67 | cpuif->vgic_hcr &= ~GICH_HCR_UIE; |
af061499 | 68 | |
8ac76ef4 | 69 | for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { |
140b086d | 70 | u32 val = cpuif->vgic_lr[lr]; |
53692908 | 71 | u32 cpuid, intid = val & GICH_LR_VIRTUALID; |
140b086d MZ |
72 | struct vgic_irq *irq; |
73 | ||
53692908 MZ |
74 | /* Extract the source vCPU id from the LR */ |
75 | cpuid = val & GICH_LR_PHYSID_CPUID; | |
76 | cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; | |
77 | cpuid &= 7; | |
78 | ||
af061499 CD |
79 | /* Notify fds when the guest EOI'ed a level-triggered SPI */ |
80 | if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) | |
81 | kvm_notify_acked_irq(vcpu->kvm, 0, | |
82 | intid - VGIC_NR_PRIVATE_IRQS); | |
83 | ||
140b086d MZ |
84 | irq = vgic_get_irq(vcpu->kvm, vcpu, intid); |
85 | ||
006df0f3 | 86 | spin_lock_irqsave(&irq->irq_lock, flags); |
140b086d MZ |
87 | |
88 | /* Always preserve the active bit */ | |
89 | irq->active = !!(val & GICH_LR_ACTIVE_BIT); | |
90 | ||
53692908 MZ |
91 | if (irq->active && vgic_irq_is_sgi(intid)) |
92 | irq->active_source = cpuid; | |
93 | ||
140b086d MZ |
94 | /* Edge is the only case where we preserve the pending bit */ |
95 | if (irq->config == VGIC_CONFIG_EDGE && | |
96 | (val & GICH_LR_PENDING_BIT)) { | |
8694e4da | 97 | irq->pending_latch = true; |
140b086d | 98 | |
53692908 | 99 | if (vgic_irq_is_sgi(intid)) |
140b086d | 100 | irq->source |= (1 << cpuid); |
140b086d MZ |
101 | } |
102 | ||
df7942d1 MZ |
103 | /* |
104 | * Clear soft pending state when level irqs have been acked. | |
df7942d1 | 105 | */ |
67b5b673 MZ |
106 | if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE)) |
107 | irq->pending_latch = false; | |
140b086d | 108 | |
e40cc57b CD |
109 | /* |
110 | * Level-triggered mapped IRQs are special because we only | |
111 | * observe rising edges as input to the VGIC. | |
112 | * | |
113 | * If the guest never acked the interrupt we have to sample | |
114 | * the physical line and set the line level, because the | |
115 | * device state could have changed or we simply need to | |
116 | * process the still pending interrupt later. | |
117 | * | |
118 | * If this causes us to lower the level, we have to also clear | |
119 | * the physical active state, since we will otherwise never be | |
120 | * told when the interrupt becomes asserted again. | |
121 | */ | |
122 | if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) { | |
123 | irq->line_level = vgic_get_phys_line_level(irq); | |
124 | ||
125 | if (!irq->line_level) | |
126 | vgic_irq_set_phys_active(irq, false); | |
127 | } | |
128 | ||
006df0f3 | 129 | spin_unlock_irqrestore(&irq->irq_lock, flags); |
5dd4b924 | 130 | vgic_put_irq(vcpu->kvm, irq); |
140b086d | 131 | } |
8ac76ef4 CD |
132 | |
133 | vgic_cpu->used_lrs = 0; | |
140b086d MZ |
134 | } |
135 | ||
136 | /* | |
137 | * Populates the particular LR with the state of a given IRQ: | |
138 | * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq | |
139 | * - for a level sensitive IRQ the pending state value is unchanged; | |
140 | * it is dictated directly by the input level | |
141 | * | |
142 | * If @irq describes an SGI with multiple sources, we choose the | |
143 | * lowest-numbered source VCPU and clear that bit in the source bitmap. | |
144 | * | |
145 | * The irq_lock must be held by the caller. | |
146 | */ | |
147 | void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) | |
148 | { | |
149 | u32 val = irq->intid; | |
67b5b673 MZ |
150 | bool allow_pending = true; |
151 | ||
53692908 | 152 | if (irq->active) { |
67b5b673 | 153 | val |= GICH_LR_ACTIVE_BIT; |
53692908 MZ |
154 | if (vgic_irq_is_sgi(irq->intid)) |
155 | val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT; | |
156 | if (vgic_irq_is_multi_sgi(irq)) { | |
157 | allow_pending = false; | |
158 | val |= GICH_LR_EOI; | |
159 | } | |
160 | } | |
67b5b673 MZ |
161 | |
162 | if (irq->hw) { | |
163 | val |= GICH_LR_HW; | |
164 | val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT; | |
165 | /* | |
166 | * Never set pending+active on a HW interrupt, as the | |
167 | * pending state is kept at the physical distributor | |
168 | * level. | |
169 | */ | |
170 | if (irq->active) | |
171 | allow_pending = false; | |
172 | } else { | |
173 | if (irq->config == VGIC_CONFIG_LEVEL) { | |
174 | val |= GICH_LR_EOI; | |
140b086d | 175 | |
67b5b673 MZ |
176 | /* |
177 | * Software resampling doesn't work very well | |
178 | * if we allow P+A, so let's not do that. | |
179 | */ | |
180 | if (irq->active) | |
181 | allow_pending = false; | |
182 | } | |
183 | } | |
184 | ||
185 | if (allow_pending && irq_is_pending(irq)) { | |
140b086d MZ |
186 | val |= GICH_LR_PENDING_BIT; |
187 | ||
188 | if (irq->config == VGIC_CONFIG_EDGE) | |
8694e4da | 189 | irq->pending_latch = false; |
140b086d MZ |
190 | |
191 | if (vgic_irq_is_sgi(irq->intid)) { | |
192 | u32 src = ffs(irq->source); | |
193 | ||
194 | BUG_ON(!src); | |
195 | val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; | |
196 | irq->source &= ~(1 << (src - 1)); | |
53692908 | 197 | if (irq->source) { |
8694e4da | 198 | irq->pending_latch = true; |
53692908 MZ |
199 | val |= GICH_LR_EOI; |
200 | } | |
140b086d MZ |
201 | } |
202 | } | |
203 | ||
e40cc57b CD |
204 | /* |
205 | * Level-triggered mapped IRQs are special because we only observe | |
206 | * rising edges as input to the VGIC. We therefore lower the line | |
207 | * level here, so that we can take new virtual IRQs. See | |
208 | * vgic_v2_fold_lr_state for more info. | |
209 | */ | |
210 | if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) | |
211 | irq->line_level = false; | |
212 | ||
140b086d MZ |
213 | /* The GICv2 LR only holds five bits of priority. */ |
214 | val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT; | |
215 | ||
216 | vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val; | |
217 | } | |
218 | ||
219 | void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr) | |
220 | { | |
221 | vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0; | |
222 | } | |
e4823a7a AP |
223 | |
224 | void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
225 | { | |
328e5664 | 226 | struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; |
e4823a7a AP |
227 | u32 vmcr; |
228 | ||
28232a43 CD |
229 | vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) & |
230 | GICH_VMCR_ENABLE_GRP0_MASK; | |
231 | vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) & | |
232 | GICH_VMCR_ENABLE_GRP1_MASK; | |
233 | vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) & | |
234 | GICH_VMCR_ACK_CTL_MASK; | |
235 | vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) & | |
236 | GICH_VMCR_FIQ_EN_MASK; | |
237 | vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) & | |
238 | GICH_VMCR_CBPR_MASK; | |
239 | vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) & | |
240 | GICH_VMCR_EOI_MODE_MASK; | |
e4823a7a AP |
241 | vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) & |
242 | GICH_VMCR_ALIAS_BINPOINT_MASK; | |
243 | vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) & | |
244 | GICH_VMCR_BINPOINT_MASK; | |
6d56111c CD |
245 | vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) << |
246 | GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK; | |
e4823a7a | 247 | |
328e5664 | 248 | cpu_if->vgic_vmcr = vmcr; |
e4823a7a AP |
249 | } |
250 | ||
251 | void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) | |
252 | { | |
328e5664 CD |
253 | struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; |
254 | u32 vmcr; | |
255 | ||
256 | vmcr = cpu_if->vgic_vmcr; | |
e4823a7a | 257 | |
28232a43 CD |
258 | vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >> |
259 | GICH_VMCR_ENABLE_GRP0_SHIFT; | |
260 | vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >> | |
261 | GICH_VMCR_ENABLE_GRP1_SHIFT; | |
262 | vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >> | |
263 | GICH_VMCR_ACK_CTL_SHIFT; | |
264 | vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >> | |
265 | GICH_VMCR_FIQ_EN_SHIFT; | |
266 | vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >> | |
267 | GICH_VMCR_CBPR_SHIFT; | |
268 | vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >> | |
269 | GICH_VMCR_EOI_MODE_SHIFT; | |
270 | ||
e4823a7a AP |
271 | vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >> |
272 | GICH_VMCR_ALIAS_BINPOINT_SHIFT; | |
273 | vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >> | |
274 | GICH_VMCR_BINPOINT_SHIFT; | |
6d56111c CD |
275 | vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >> |
276 | GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT; | |
e4823a7a | 277 | } |
90977732 | 278 | |
ad275b8b EA |
279 | void vgic_v2_enable(struct kvm_vcpu *vcpu) |
280 | { | |
f7b6985c EA |
281 | /* |
282 | * By forcing VMCR to zero, the GIC will restore the binary | |
283 | * points to their reset values. Anything else resets to zero | |
284 | * anyway. | |
285 | */ | |
286 | vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0; | |
f7b6985c EA |
287 | |
288 | /* Get the show on the road... */ | |
289 | vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN; | |
ad275b8b EA |
290 | } |
291 | ||
b0442ee2 EA |
292 | /* check for overlapping regions and for regions crossing the end of memory */ |
293 | static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base) | |
294 | { | |
295 | if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base) | |
296 | return false; | |
297 | if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base) | |
298 | return false; | |
299 | ||
300 | if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base) | |
301 | return true; | |
302 | if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base) | |
303 | return true; | |
304 | ||
305 | return false; | |
306 | } | |
307 | ||
308 | int vgic_v2_map_resources(struct kvm *kvm) | |
309 | { | |
310 | struct vgic_dist *dist = &kvm->arch.vgic; | |
311 | int ret = 0; | |
312 | ||
313 | if (vgic_ready(kvm)) | |
314 | goto out; | |
315 | ||
316 | if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) || | |
317 | IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) { | |
318 | kvm_err("Need to set vgic cpu and dist addresses first\n"); | |
319 | ret = -ENXIO; | |
320 | goto out; | |
321 | } | |
322 | ||
323 | if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) { | |
324 | kvm_err("VGIC CPU and dist frames overlap\n"); | |
325 | ret = -EINVAL; | |
326 | goto out; | |
327 | } | |
328 | ||
329 | /* | |
330 | * Initialize the vgic if this hasn't already been done on demand by | |
331 | * accessing the vgic state from userspace. | |
332 | */ | |
333 | ret = vgic_init(kvm); | |
334 | if (ret) { | |
335 | kvm_err("Unable to initialize VGIC dynamic data structures\n"); | |
336 | goto out; | |
337 | } | |
338 | ||
339 | ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2); | |
340 | if (ret) { | |
341 | kvm_err("Unable to register VGIC MMIO regions\n"); | |
342 | goto out; | |
343 | } | |
344 | ||
a07d3b07 MZ |
345 | if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) { |
346 | ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base, | |
347 | kvm_vgic_global_state.vcpu_base, | |
348 | KVM_VGIC_V2_CPU_SIZE, true); | |
349 | if (ret) { | |
350 | kvm_err("Unable to remap VGIC CPU to VCPU\n"); | |
351 | goto out; | |
352 | } | |
b0442ee2 EA |
353 | } |
354 | ||
355 | dist->ready = true; | |
356 | ||
357 | out: | |
b0442ee2 EA |
358 | return ret; |
359 | } | |
360 | ||
fb5ee369 MZ |
361 | DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap); |
362 | ||
90977732 EA |
363 | /** |
364 | * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT | |
365 | * @node: pointer to the DT node | |
366 | * | |
367 | * Returns 0 if a GICv2 has been found, returns an error code otherwise | |
368 | */ | |
369 | int vgic_v2_probe(const struct gic_kvm_info *info) | |
370 | { | |
371 | int ret; | |
372 | u32 vtr; | |
373 | ||
374 | if (!info->vctrl.start) { | |
375 | kvm_err("GICH not present in the firmware table\n"); | |
376 | return -ENXIO; | |
377 | } | |
378 | ||
a07d3b07 MZ |
379 | if (!PAGE_ALIGNED(info->vcpu.start) || |
380 | !PAGE_ALIGNED(resource_size(&info->vcpu))) { | |
381 | kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n"); | |
90977732 | 382 | |
807a3784 MZ |
383 | ret = create_hyp_io_mappings(info->vcpu.start, |
384 | resource_size(&info->vcpu), | |
1bb32a44 MZ |
385 | &kvm_vgic_global_state.vcpu_base_va, |
386 | &kvm_vgic_global_state.vcpu_hyp_va); | |
a07d3b07 MZ |
387 | if (ret) { |
388 | kvm_err("Cannot map GICV into hyp\n"); | |
389 | goto out; | |
390 | } | |
391 | ||
392 | static_branch_enable(&vgic_v2_cpuif_trap); | |
90977732 EA |
393 | } |
394 | ||
807a3784 MZ |
395 | ret = create_hyp_io_mappings(info->vctrl.start, |
396 | resource_size(&info->vctrl), | |
1bb32a44 MZ |
397 | &kvm_vgic_global_state.vctrl_base, |
398 | &kvm_vgic_global_state.vctrl_hyp); | |
807a3784 MZ |
399 | if (ret) { |
400 | kvm_err("Cannot map VCTRL into hyp\n"); | |
a07d3b07 | 401 | goto out; |
90977732 EA |
402 | } |
403 | ||
404 | vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR); | |
405 | kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1; | |
406 | ||
a07d3b07 MZ |
407 | ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2); |
408 | if (ret) { | |
409 | kvm_err("Cannot register GICv2 KVM device\n"); | |
410 | goto out; | |
90977732 EA |
411 | } |
412 | ||
413 | kvm_vgic_global_state.can_emulate_gicv2 = true; | |
90977732 EA |
414 | kvm_vgic_global_state.vcpu_base = info->vcpu.start; |
415 | kvm_vgic_global_state.type = VGIC_V2; | |
416 | kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS; | |
417 | ||
76600428 | 418 | kvm_debug("vgic-v2@%llx\n", info->vctrl.start); |
90977732 EA |
419 | |
420 | return 0; | |
a07d3b07 MZ |
421 | out: |
422 | if (kvm_vgic_global_state.vctrl_base) | |
423 | iounmap(kvm_vgic_global_state.vctrl_base); | |
424 | if (kvm_vgic_global_state.vcpu_base_va) | |
425 | iounmap(kvm_vgic_global_state.vcpu_base_va); | |
426 | ||
427 | return ret; | |
90977732 | 428 | } |
328e5664 | 429 | |
75174ba6 CD |
430 | static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base) |
431 | { | |
432 | struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; | |
433 | u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs; | |
434 | u64 elrsr; | |
435 | int i; | |
436 | ||
437 | elrsr = readl_relaxed(base + GICH_ELRSR0); | |
438 | if (unlikely(used_lrs > 32)) | |
439 | elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32; | |
440 | ||
441 | for (i = 0; i < used_lrs; i++) { | |
442 | if (elrsr & (1UL << i)) | |
443 | cpu_if->vgic_lr[i] &= ~GICH_LR_STATE; | |
444 | else | |
445 | cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4)); | |
446 | ||
447 | writel_relaxed(0, base + GICH_LR0 + (i * 4)); | |
448 | } | |
449 | } | |
450 | ||
451 | void vgic_v2_save_state(struct kvm_vcpu *vcpu) | |
452 | { | |
1bb32a44 | 453 | void __iomem *base = kvm_vgic_global_state.vctrl_base; |
75174ba6 CD |
454 | u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs; |
455 | ||
456 | if (!base) | |
457 | return; | |
458 | ||
459 | if (used_lrs) { | |
75174ba6 CD |
460 | save_lrs(vcpu, base); |
461 | writel_relaxed(0, base + GICH_HCR); | |
75174ba6 CD |
462 | } |
463 | } | |
464 | ||
465 | void vgic_v2_restore_state(struct kvm_vcpu *vcpu) | |
466 | { | |
75174ba6 | 467 | struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; |
1bb32a44 | 468 | void __iomem *base = kvm_vgic_global_state.vctrl_base; |
75174ba6 CD |
469 | u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs; |
470 | int i; | |
471 | ||
472 | if (!base) | |
473 | return; | |
474 | ||
475 | if (used_lrs) { | |
476 | writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR); | |
75174ba6 CD |
477 | for (i = 0; i < used_lrs; i++) { |
478 | writel_relaxed(cpu_if->vgic_lr[i], | |
479 | base + GICH_LR0 + (i * 4)); | |
480 | } | |
481 | } | |
482 | } | |
483 | ||
328e5664 CD |
484 | void vgic_v2_load(struct kvm_vcpu *vcpu) |
485 | { | |
486 | struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; | |
328e5664 | 487 | |
1bb32a44 MZ |
488 | writel_relaxed(cpu_if->vgic_vmcr, |
489 | kvm_vgic_global_state.vctrl_base + GICH_VMCR); | |
490 | writel_relaxed(cpu_if->vgic_apr, | |
491 | kvm_vgic_global_state.vctrl_base + GICH_APR); | |
328e5664 CD |
492 | } |
493 | ||
494 | void vgic_v2_put(struct kvm_vcpu *vcpu) | |
495 | { | |
496 | struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; | |
328e5664 | 497 | |
1bb32a44 MZ |
498 | cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR); |
499 | cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR); | |
328e5664 | 500 | } |