Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ed9b8cef AP |
2 | /* |
3 | * VGICv3 MMIO handling functions | |
ed9b8cef AP |
4 | */ |
5 | ||
2291ff2f | 6 | #include <linux/bitfield.h> |
ed9b8cef AP |
7 | #include <linux/irqchip/arm-gic-v3.h> |
8 | #include <linux/kvm.h> | |
9 | #include <linux/kvm_host.h> | |
ef1820be | 10 | #include <linux/interrupt.h> |
ed9b8cef AP |
11 | #include <kvm/iodev.h> |
12 | #include <kvm/arm_vgic.h> | |
13 | ||
14 | #include <asm/kvm_emulate.h> | |
94574c94 VK |
15 | #include <asm/kvm_arm.h> |
16 | #include <asm/kvm_mmu.h> | |
ed9b8cef AP |
17 | |
18 | #include "vgic.h" | |
19 | #include "vgic-mmio.h" | |
20 | ||
741972d8 | 21 | /* extract @num bytes at @offset bytes offset in data */ |
d7d0a11e | 22 | unsigned long extract_bytes(u64 data, unsigned int offset, |
424c3383 | 23 | unsigned int num) |
741972d8 AP |
24 | { |
25 | return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); | |
26 | } | |
27 | ||
0aa1de57 | 28 | /* allows updates of any half of a 64-bit register (or the whole thing) */ |
424c3383 AP |
29 | u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, |
30 | unsigned long val) | |
0aa1de57 AP |
31 | { |
32 | int lower = (offset & 4) * 8; | |
33 | int upper = lower + 8 * len - 1; | |
34 | ||
35 | reg &= ~GENMASK_ULL(upper, lower); | |
36 | val &= GENMASK_ULL(len * 8 - 1, 0); | |
37 | ||
38 | return reg | ((u64)val << lower); | |
39 | } | |
40 | ||
59c5ab40 AP |
41 | bool vgic_has_its(struct kvm *kvm) |
42 | { | |
43 | struct vgic_dist *dist = &kvm->arch.vgic; | |
44 | ||
45 | if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) | |
46 | return false; | |
47 | ||
1085fdc6 | 48 | return dist->has_its; |
59c5ab40 AP |
49 | } |
50 | ||
e7c48059 MZ |
51 | bool vgic_supports_direct_msis(struct kvm *kvm) |
52 | { | |
53 | return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm); | |
54 | } | |
55 | ||
d53c2c29 CD |
56 | /* |
57 | * The Revision field in the IIDR have the following meanings: | |
58 | * | |
59 | * Revision 2: Interrupt groups are guest-configurable and signaled using | |
60 | * their configured groups. | |
61 | */ | |
62 | ||
fd59ed3b AP |
63 | static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, |
64 | gpa_t addr, unsigned int len) | |
65 | { | |
aa075b0f | 66 | struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; |
fd59ed3b AP |
67 | u32 value = 0; |
68 | ||
69 | switch (addr & 0x0c) { | |
70 | case GICD_CTLR: | |
aa075b0f | 71 | if (vgic->enabled) |
fd59ed3b AP |
72 | value |= GICD_CTLR_ENABLE_SS_G1; |
73 | value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; | |
2291ff2f MZ |
74 | if (vgic->nassgireq) |
75 | value |= GICD_CTLR_nASSGIreq; | |
fd59ed3b AP |
76 | break; |
77 | case GICD_TYPER: | |
aa075b0f | 78 | value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS; |
fd59ed3b | 79 | value = (value >> 5) - 1; |
0e4e82f1 AP |
80 | if (vgic_has_its(vcpu->kvm)) { |
81 | value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; | |
82 | value |= GICD_TYPER_LPIS; | |
83 | } else { | |
84 | value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; | |
85 | } | |
fd59ed3b | 86 | break; |
2291ff2f MZ |
87 | case GICD_TYPER2: |
88 | if (kvm_vgic_global_state.has_gicv4_1) | |
89 | value = GICD_TYPER2_nASSGIcap; | |
90 | break; | |
fd59ed3b | 91 | case GICD_IIDR: |
a2dca217 | 92 | value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | |
aa075b0f | 93 | (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) | |
a2dca217 | 94 | (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); |
fd59ed3b AP |
95 | break; |
96 | default: | |
97 | return 0; | |
98 | } | |
99 | ||
100 | return value; | |
101 | } | |
102 | ||
103 | static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, | |
104 | gpa_t addr, unsigned int len, | |
105 | unsigned long val) | |
106 | { | |
107 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
fd59ed3b AP |
108 | |
109 | switch (addr & 0x0c) { | |
2291ff2f MZ |
110 | case GICD_CTLR: { |
111 | bool was_enabled, is_hwsgi; | |
112 | ||
113 | mutex_lock(&vcpu->kvm->lock); | |
114 | ||
115 | was_enabled = dist->enabled; | |
116 | is_hwsgi = dist->nassgireq; | |
117 | ||
fd59ed3b AP |
118 | dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; |
119 | ||
2291ff2f MZ |
120 | /* Not a GICv4.1? No HW SGIs */ |
121 | if (!kvm_vgic_global_state.has_gicv4_1) | |
122 | val &= ~GICD_CTLR_nASSGIreq; | |
123 | ||
124 | /* Dist stays enabled? nASSGIreq is RO */ | |
125 | if (was_enabled && dist->enabled) { | |
126 | val &= ~GICD_CTLR_nASSGIreq; | |
127 | val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); | |
128 | } | |
129 | ||
130 | /* Switching HW SGIs? */ | |
131 | dist->nassgireq = val & GICD_CTLR_nASSGIreq; | |
132 | if (is_hwsgi != dist->nassgireq) | |
133 | vgic_v4_configure_vsgis(vcpu->kvm); | |
134 | ||
d9c3872c MZ |
135 | if (kvm_vgic_global_state.has_gicv4_1 && |
136 | was_enabled != dist->enabled) | |
137 | kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); | |
138 | else if (!was_enabled && dist->enabled) | |
fd59ed3b | 139 | vgic_kick_vcpus(vcpu->kvm); |
2291ff2f MZ |
140 | |
141 | mutex_unlock(&vcpu->kvm->lock); | |
fd59ed3b | 142 | break; |
2291ff2f | 143 | } |
fd59ed3b | 144 | case GICD_TYPER: |
2291ff2f | 145 | case GICD_TYPER2: |
fd59ed3b | 146 | case GICD_IIDR: |
2291ff2f | 147 | /* This is at best for documentation purposes... */ |
fd59ed3b AP |
148 | return; |
149 | } | |
150 | } | |
151 | ||
b489edc3 CD |
152 | static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, |
153 | gpa_t addr, unsigned int len, | |
154 | unsigned long val) | |
155 | { | |
2291ff2f MZ |
156 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
157 | ||
b489edc3 | 158 | switch (addr & 0x0c) { |
2291ff2f | 159 | case GICD_TYPER2: |
b489edc3 CD |
160 | case GICD_IIDR: |
161 | if (val != vgic_mmio_read_v3_misc(vcpu, addr, len)) | |
162 | return -EINVAL; | |
2291ff2f MZ |
163 | return 0; |
164 | case GICD_CTLR: | |
165 | /* Not a GICv4.1? No HW SGIs */ | |
166 | if (!kvm_vgic_global_state.has_gicv4_1) | |
167 | val &= ~GICD_CTLR_nASSGIreq; | |
168 | ||
169 | dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; | |
170 | dist->nassgireq = val & GICD_CTLR_nASSGIreq; | |
171 | return 0; | |
b489edc3 CD |
172 | } |
173 | ||
174 | vgic_mmio_write_v3_misc(vcpu, addr, len, val); | |
175 | return 0; | |
176 | } | |
177 | ||
78a714ab AP |
178 | static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu, |
179 | gpa_t addr, unsigned int len) | |
180 | { | |
181 | int intid = VGIC_ADDR_TO_INTID(addr, 64); | |
182 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid); | |
5dd4b924 | 183 | unsigned long ret = 0; |
78a714ab AP |
184 | |
185 | if (!irq) | |
186 | return 0; | |
187 | ||
188 | /* The upper word is RAZ for us. */ | |
5dd4b924 AP |
189 | if (!(addr & 4)) |
190 | ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); | |
78a714ab | 191 | |
5dd4b924 AP |
192 | vgic_put_irq(vcpu->kvm, irq); |
193 | return ret; | |
78a714ab AP |
194 | } |
195 | ||
196 | static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, | |
197 | gpa_t addr, unsigned int len, | |
198 | unsigned long val) | |
199 | { | |
200 | int intid = VGIC_ADDR_TO_INTID(addr, 64); | |
5dd4b924 | 201 | struct vgic_irq *irq; |
006df0f3 | 202 | unsigned long flags; |
78a714ab AP |
203 | |
204 | /* The upper word is WI for us since we don't implement Aff3. */ | |
205 | if (addr & 4) | |
206 | return; | |
207 | ||
5dd4b924 AP |
208 | irq = vgic_get_irq(vcpu->kvm, NULL, intid); |
209 | ||
210 | if (!irq) | |
211 | return; | |
212 | ||
8fa3adb8 | 213 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
78a714ab AP |
214 | |
215 | /* We only care about and preserve Aff0, Aff1 and Aff2. */ | |
216 | irq->mpidr = val & GENMASK(23, 0); | |
217 | irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); | |
218 | ||
8fa3adb8 | 219 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
5dd4b924 | 220 | vgic_put_irq(vcpu->kvm, irq); |
78a714ab AP |
221 | } |
222 | ||
59c5ab40 AP |
223 | static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu, |
224 | gpa_t addr, unsigned int len) | |
225 | { | |
226 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
227 | ||
228 | return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0; | |
229 | } | |
230 | ||
231 | ||
232 | static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, | |
233 | gpa_t addr, unsigned int len, | |
234 | unsigned long val) | |
235 | { | |
236 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
237 | bool was_enabled = vgic_cpu->lpis_enabled; | |
238 | ||
239 | if (!vgic_has_its(vcpu->kvm)) | |
240 | return; | |
241 | ||
242 | vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS; | |
243 | ||
b4931afc | 244 | if (was_enabled && !vgic_cpu->lpis_enabled) { |
96085b94 | 245 | vgic_flush_pending_lpis(vcpu); |
b4931afc MZ |
246 | vgic_its_invalidate_cache(vcpu->kvm); |
247 | } | |
96085b94 | 248 | |
0e4e82f1 AP |
249 | if (!was_enabled && vgic_cpu->lpis_enabled) |
250 | vgic_enable_lpis(vcpu); | |
59c5ab40 AP |
251 | } |
252 | ||
741972d8 AP |
253 | static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, |
254 | gpa_t addr, unsigned int len) | |
255 | { | |
256 | unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); | |
ba7b3f12 EA |
257 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
258 | struct vgic_redist_region *rdreg = vgic_cpu->rdreg; | |
741972d8 | 259 | int target_vcpu_id = vcpu->vcpu_id; |
ba7b3f12 EA |
260 | gpa_t last_rdist_typer = rdreg->base + GICR_TYPER + |
261 | (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE; | |
741972d8 AP |
262 | u64 value; |
263 | ||
e533a37f | 264 | value = (u64)(mpidr & GENMASK(23, 0)) << 32; |
741972d8 | 265 | value |= ((target_vcpu_id & 0xffff) << 8); |
ba7b3f12 EA |
266 | |
267 | if (addr == last_rdist_typer) | |
741972d8 | 268 | value |= GICR_TYPER_LAST; |
0e4e82f1 AP |
269 | if (vgic_has_its(vcpu->kvm)) |
270 | value |= GICR_TYPER_PLPIS; | |
741972d8 AP |
271 | |
272 | return extract_bytes(value, addr & 7, len); | |
273 | } | |
274 | ||
275 | static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu, | |
276 | gpa_t addr, unsigned int len) | |
277 | { | |
278 | return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
279 | } | |
280 | ||
54f59d2b AP |
281 | static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, |
282 | gpa_t addr, unsigned int len) | |
283 | { | |
284 | switch (addr & 0xffff) { | |
285 | case GICD_PIDR2: | |
286 | /* report a GICv3 compliant implementation */ | |
287 | return 0x3b; | |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
2df903a8 VK |
293 | static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu, |
294 | gpa_t addr, unsigned int len) | |
295 | { | |
296 | u32 intid = VGIC_ADDR_TO_INTID(addr, 1); | |
297 | u32 value = 0; | |
298 | int i; | |
299 | ||
300 | /* | |
301 | * pending state of interrupt is latched in pending_latch variable. | |
302 | * Userspace will save and restore pending state and line_level | |
303 | * separately. | |
2f5947df | 304 | * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.txt |
2df903a8 VK |
305 | * for handling of ISPENDR and ICPENDR. |
306 | */ | |
307 | for (i = 0; i < len * 8; i++) { | |
308 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
ef1820be | 309 | bool state = irq->pending_latch; |
2df903a8 | 310 | |
ef1820be MZ |
311 | if (irq->hw && vgic_irq_is_sgi(irq->intid)) { |
312 | int err; | |
313 | ||
314 | err = irq_get_irqchip_state(irq->host_irq, | |
315 | IRQCHIP_STATE_PENDING, | |
316 | &state); | |
317 | WARN_ON(err); | |
318 | } | |
319 | ||
320 | if (state) | |
2df903a8 VK |
321 | value |= (1U << i); |
322 | ||
323 | vgic_put_irq(vcpu->kvm, irq); | |
324 | } | |
325 | ||
326 | return value; | |
327 | } | |
328 | ||
c6e0917b CD |
329 | static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, |
330 | gpa_t addr, unsigned int len, | |
331 | unsigned long val) | |
2df903a8 VK |
332 | { |
333 | u32 intid = VGIC_ADDR_TO_INTID(addr, 1); | |
334 | int i; | |
006df0f3 | 335 | unsigned long flags; |
2df903a8 VK |
336 | |
337 | for (i = 0; i < len * 8; i++) { | |
338 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
339 | ||
8fa3adb8 | 340 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
2df903a8 VK |
341 | if (test_bit(i, &val)) { |
342 | /* | |
343 | * pending_latch is set irrespective of irq type | |
344 | * (level or edge) to avoid dependency that VM should | |
345 | * restore irq config before pending info. | |
346 | */ | |
347 | irq->pending_latch = true; | |
006df0f3 | 348 | vgic_queue_irq_unlock(vcpu->kvm, irq, flags); |
2df903a8 VK |
349 | } else { |
350 | irq->pending_latch = false; | |
8fa3adb8 | 351 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
2df903a8 VK |
352 | } |
353 | ||
354 | vgic_put_irq(vcpu->kvm, irq); | |
355 | } | |
c6e0917b CD |
356 | |
357 | return 0; | |
2df903a8 VK |
358 | } |
359 | ||
0aa1de57 AP |
360 | /* We want to avoid outer shareable. */ |
361 | u64 vgic_sanitise_shareability(u64 field) | |
362 | { | |
363 | switch (field) { | |
364 | case GIC_BASER_OuterShareable: | |
365 | return GIC_BASER_InnerShareable; | |
366 | default: | |
367 | return field; | |
368 | } | |
369 | } | |
370 | ||
371 | /* Avoid any inner non-cacheable mapping. */ | |
372 | u64 vgic_sanitise_inner_cacheability(u64 field) | |
373 | { | |
374 | switch (field) { | |
375 | case GIC_BASER_CACHE_nCnB: | |
376 | case GIC_BASER_CACHE_nC: | |
377 | return GIC_BASER_CACHE_RaWb; | |
378 | default: | |
379 | return field; | |
380 | } | |
381 | } | |
382 | ||
383 | /* Non-cacheable or same-as-inner are OK. */ | |
384 | u64 vgic_sanitise_outer_cacheability(u64 field) | |
385 | { | |
386 | switch (field) { | |
387 | case GIC_BASER_CACHE_SameAsInner: | |
388 | case GIC_BASER_CACHE_nC: | |
389 | return field; | |
390 | default: | |
391 | return GIC_BASER_CACHE_nC; | |
392 | } | |
393 | } | |
394 | ||
395 | u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, | |
396 | u64 (*sanitise_fn)(u64)) | |
397 | { | |
398 | u64 field = (reg & field_mask) >> field_shift; | |
399 | ||
400 | field = sanitise_fn(field) << field_shift; | |
401 | return (reg & ~field_mask) | field; | |
402 | } | |
403 | ||
404 | #define PROPBASER_RES0_MASK \ | |
405 | (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) | |
406 | #define PENDBASER_RES0_MASK \ | |
407 | (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ | |
408 | GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) | |
409 | ||
410 | static u64 vgic_sanitise_pendbaser(u64 reg) | |
411 | { | |
412 | reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, | |
413 | GICR_PENDBASER_SHAREABILITY_SHIFT, | |
414 | vgic_sanitise_shareability); | |
415 | reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, | |
416 | GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, | |
417 | vgic_sanitise_inner_cacheability); | |
418 | reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, | |
419 | GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, | |
420 | vgic_sanitise_outer_cacheability); | |
421 | ||
422 | reg &= ~PENDBASER_RES0_MASK; | |
0aa1de57 AP |
423 | |
424 | return reg; | |
425 | } | |
426 | ||
427 | static u64 vgic_sanitise_propbaser(u64 reg) | |
428 | { | |
429 | reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, | |
430 | GICR_PROPBASER_SHAREABILITY_SHIFT, | |
431 | vgic_sanitise_shareability); | |
432 | reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, | |
433 | GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, | |
434 | vgic_sanitise_inner_cacheability); | |
435 | reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, | |
436 | GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, | |
437 | vgic_sanitise_outer_cacheability); | |
438 | ||
439 | reg &= ~PROPBASER_RES0_MASK; | |
0aa1de57 AP |
440 | return reg; |
441 | } | |
442 | ||
443 | static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, | |
444 | gpa_t addr, unsigned int len) | |
445 | { | |
446 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
447 | ||
448 | return extract_bytes(dist->propbaser, addr & 7, len); | |
449 | } | |
450 | ||
451 | static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, | |
452 | gpa_t addr, unsigned int len, | |
453 | unsigned long val) | |
454 | { | |
455 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
456 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
d9ae449b | 457 | u64 old_propbaser, propbaser; |
0aa1de57 AP |
458 | |
459 | /* Storing a value with LPIs already enabled is undefined */ | |
460 | if (vgic_cpu->lpis_enabled) | |
461 | return; | |
462 | ||
d9ae449b | 463 | do { |
3af4e414 | 464 | old_propbaser = READ_ONCE(dist->propbaser); |
d9ae449b CD |
465 | propbaser = old_propbaser; |
466 | propbaser = update_64bit_reg(propbaser, addr & 4, len, val); | |
467 | propbaser = vgic_sanitise_propbaser(propbaser); | |
468 | } while (cmpxchg64(&dist->propbaser, old_propbaser, | |
469 | propbaser) != old_propbaser); | |
0aa1de57 AP |
470 | } |
471 | ||
472 | static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, | |
473 | gpa_t addr, unsigned int len) | |
474 | { | |
475 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
5f675c56 | 476 | u64 value = vgic_cpu->pendbaser; |
0aa1de57 | 477 | |
5f675c56 ZY |
478 | value &= ~GICR_PENDBASER_PTZ; |
479 | ||
480 | return extract_bytes(value, addr & 7, len); | |
0aa1de57 AP |
481 | } |
482 | ||
483 | static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, | |
484 | gpa_t addr, unsigned int len, | |
485 | unsigned long val) | |
486 | { | |
487 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
d9ae449b | 488 | u64 old_pendbaser, pendbaser; |
0aa1de57 AP |
489 | |
490 | /* Storing a value with LPIs already enabled is undefined */ | |
491 | if (vgic_cpu->lpis_enabled) | |
492 | return; | |
493 | ||
d9ae449b | 494 | do { |
3af4e414 | 495 | old_pendbaser = READ_ONCE(vgic_cpu->pendbaser); |
d9ae449b CD |
496 | pendbaser = old_pendbaser; |
497 | pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); | |
498 | pendbaser = vgic_sanitise_pendbaser(pendbaser); | |
499 | } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, | |
500 | pendbaser) != old_pendbaser); | |
0aa1de57 AP |
501 | } |
502 | ||
ed9b8cef AP |
503 | /* |
504 | * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the | |
505 | * redistributors, while SPIs are covered by registers in the distributor | |
506 | * block. Trying to set private IRQs in this block gets ignored. | |
507 | * We take some special care here to fix the calculation of the register | |
508 | * offset. | |
509 | */ | |
2df903a8 | 510 | #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \ |
ed9b8cef AP |
511 | { \ |
512 | .reg_offset = off, \ | |
513 | .bits_per_irq = bpi, \ | |
514 | .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ | |
515 | .access_flags = acc, \ | |
516 | .read = vgic_mmio_read_raz, \ | |
517 | .write = vgic_mmio_write_wi, \ | |
518 | }, { \ | |
519 | .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ | |
520 | .bits_per_irq = bpi, \ | |
521 | .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \ | |
522 | .access_flags = acc, \ | |
523 | .read = rd, \ | |
524 | .write = wr, \ | |
2df903a8 VK |
525 | .uaccess_read = ur, \ |
526 | .uaccess_write = uw, \ | |
ed9b8cef AP |
527 | } |
528 | ||
529 | static const struct vgic_register_region vgic_v3_dist_registers[] = { | |
b489edc3 CD |
530 | REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR, |
531 | vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, | |
532 | NULL, vgic_mmio_uaccess_write_v3_misc, | |
533 | 16, VGIC_ACCESS_32bit), | |
94574c94 VK |
534 | REGISTER_DESC_WITH_LENGTH(GICD_STATUSR, |
535 | vgic_mmio_read_rao, vgic_mmio_write_wi, 4, | |
536 | VGIC_ACCESS_32bit), | |
ed9b8cef | 537 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR, |
d53c2c29 | 538 | vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1, |
ed9b8cef AP |
539 | VGIC_ACCESS_32bit), |
540 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER, | |
2df903a8 | 541 | vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1, |
ed9b8cef AP |
542 | VGIC_ACCESS_32bit), |
543 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER, | |
2df903a8 | 544 | vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1, |
ed9b8cef AP |
545 | VGIC_ACCESS_32bit), |
546 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR, | |
2df903a8 VK |
547 | vgic_mmio_read_pending, vgic_mmio_write_spending, |
548 | vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1, | |
ed9b8cef AP |
549 | VGIC_ACCESS_32bit), |
550 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR, | |
2df903a8 | 551 | vgic_mmio_read_pending, vgic_mmio_write_cpending, |
c6e0917b | 552 | vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1, |
ed9b8cef AP |
553 | VGIC_ACCESS_32bit), |
554 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER, | |
3197191e CD |
555 | vgic_mmio_read_active, vgic_mmio_write_sactive, |
556 | NULL, vgic_mmio_uaccess_write_sactive, 1, | |
ed9b8cef AP |
557 | VGIC_ACCESS_32bit), |
558 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER, | |
3197191e CD |
559 | vgic_mmio_read_active, vgic_mmio_write_cactive, |
560 | NULL, vgic_mmio_uaccess_write_cactive, | |
561 | 1, VGIC_ACCESS_32bit), | |
ed9b8cef | 562 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR, |
2df903a8 VK |
563 | vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, |
564 | 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), | |
ed9b8cef | 565 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR, |
2df903a8 | 566 | vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, |
ed9b8cef AP |
567 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), |
568 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR, | |
2df903a8 | 569 | vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, |
ed9b8cef AP |
570 | VGIC_ACCESS_32bit), |
571 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR, | |
2df903a8 | 572 | vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, |
ed9b8cef AP |
573 | VGIC_ACCESS_32bit), |
574 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER, | |
2df903a8 | 575 | vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64, |
ed9b8cef AP |
576 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
577 | REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, | |
54f59d2b | 578 | vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, |
ed9b8cef AP |
579 | VGIC_ACCESS_32bit), |
580 | }; | |
581 | ||
3109741a EA |
582 | static const struct vgic_register_region vgic_v3_rd_registers[] = { |
583 | /* RD_base registers */ | |
ed9b8cef | 584 | REGISTER_DESC_WITH_LENGTH(GICR_CTLR, |
59c5ab40 | 585 | vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4, |
ed9b8cef | 586 | VGIC_ACCESS_32bit), |
94574c94 VK |
587 | REGISTER_DESC_WITH_LENGTH(GICR_STATUSR, |
588 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, | |
589 | VGIC_ACCESS_32bit), | |
ed9b8cef | 590 | REGISTER_DESC_WITH_LENGTH(GICR_IIDR, |
741972d8 | 591 | vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4, |
ed9b8cef AP |
592 | VGIC_ACCESS_32bit), |
593 | REGISTER_DESC_WITH_LENGTH(GICR_TYPER, | |
741972d8 | 594 | vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8, |
ed9b8cef | 595 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
94574c94 VK |
596 | REGISTER_DESC_WITH_LENGTH(GICR_WAKER, |
597 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, | |
598 | VGIC_ACCESS_32bit), | |
ed9b8cef | 599 | REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, |
0aa1de57 | 600 | vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, |
ed9b8cef AP |
601 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
602 | REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, | |
0aa1de57 | 603 | vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, |
ed9b8cef AP |
604 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
605 | REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, | |
54f59d2b | 606 | vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, |
ed9b8cef | 607 | VGIC_ACCESS_32bit), |
3109741a EA |
608 | /* SGI_base registers */ |
609 | REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0, | |
d53c2c29 | 610 | vgic_mmio_read_group, vgic_mmio_write_group, 4, |
ed9b8cef | 611 | VGIC_ACCESS_32bit), |
3109741a | 612 | REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISENABLER0, |
ed9b8cef AP |
613 | vgic_mmio_read_enable, vgic_mmio_write_senable, 4, |
614 | VGIC_ACCESS_32bit), | |
3109741a | 615 | REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICENABLER0, |
ed9b8cef AP |
616 | vgic_mmio_read_enable, vgic_mmio_write_cenable, 4, |
617 | VGIC_ACCESS_32bit), | |
3109741a | 618 | REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0, |
2df903a8 VK |
619 | vgic_mmio_read_pending, vgic_mmio_write_spending, |
620 | vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4, | |
ed9b8cef | 621 | VGIC_ACCESS_32bit), |
3109741a | 622 | REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0, |
2df903a8 | 623 | vgic_mmio_read_pending, vgic_mmio_write_cpending, |
c6e0917b | 624 | vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4, |
ed9b8cef | 625 | VGIC_ACCESS_32bit), |
3109741a | 626 | REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0, |
0710f9a6 CD |
627 | vgic_mmio_read_active, vgic_mmio_write_sactive, |
628 | NULL, vgic_mmio_uaccess_write_sactive, | |
629 | 4, VGIC_ACCESS_32bit), | |
3109741a | 630 | REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0, |
0710f9a6 CD |
631 | vgic_mmio_read_active, vgic_mmio_write_cactive, |
632 | NULL, vgic_mmio_uaccess_write_cactive, | |
633 | 4, VGIC_ACCESS_32bit), | |
3109741a | 634 | REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0, |
ed9b8cef AP |
635 | vgic_mmio_read_priority, vgic_mmio_write_priority, 32, |
636 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), | |
3109741a | 637 | REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0, |
ed9b8cef AP |
638 | vgic_mmio_read_config, vgic_mmio_write_config, 8, |
639 | VGIC_ACCESS_32bit), | |
3109741a | 640 | REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0, |
ed9b8cef AP |
641 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, |
642 | VGIC_ACCESS_32bit), | |
3109741a | 643 | REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, |
ed9b8cef AP |
644 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, |
645 | VGIC_ACCESS_32bit), | |
646 | }; | |
647 | ||
648 | unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev) | |
649 | { | |
650 | dev->regions = vgic_v3_dist_registers; | |
651 | dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); | |
652 | ||
653 | kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); | |
654 | ||
655 | return SZ_64K; | |
656 | } | |
657 | ||
7fadcd3a CD |
658 | /** |
659 | * vgic_register_redist_iodev - register a single redist iodev | |
660 | * @vcpu: The VCPU to which the redistributor belongs | |
661 | * | |
662 | * Register a KVM iodev for this VCPU's redistributor using the address | |
663 | * provided. | |
664 | * | |
665 | * Return 0 on success, -ERRNO otherwise. | |
666 | */ | |
1aab6f46 | 667 | int vgic_register_redist_iodev(struct kvm_vcpu *vcpu) |
7fadcd3a CD |
668 | { |
669 | struct kvm *kvm = vcpu->kvm; | |
670 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
dbd9733a | 671 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
7fadcd3a | 672 | struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; |
dbd9733a | 673 | struct vgic_redist_region *rdreg; |
3109741a | 674 | gpa_t rd_base; |
7fadcd3a CD |
675 | int ret; |
676 | ||
c011f4ea EA |
677 | if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) |
678 | return 0; | |
679 | ||
1aab6f46 CD |
680 | /* |
681 | * We may be creating VCPUs before having set the base address for the | |
682 | * redistributor region, in which case we will come back to this | |
683 | * function for all VCPUs when the base address is set. Just return | |
684 | * without doing any work for now. | |
685 | */ | |
dc524619 | 686 | rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions); |
dbd9733a | 687 | if (!rdreg) |
1aab6f46 CD |
688 | return 0; |
689 | ||
690 | if (!vgic_v3_check_base(kvm)) | |
691 | return -EINVAL; | |
692 | ||
dbd9733a EA |
693 | vgic_cpu->rdreg = rdreg; |
694 | ||
695 | rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; | |
7fadcd3a CD |
696 | |
697 | kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops); | |
698 | rd_dev->base_addr = rd_base; | |
699 | rd_dev->iodev_type = IODEV_REDIST; | |
3109741a EA |
700 | rd_dev->regions = vgic_v3_rd_registers; |
701 | rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); | |
7fadcd3a CD |
702 | rd_dev->redist_vcpu = vcpu; |
703 | ||
704 | mutex_lock(&kvm->slots_lock); | |
705 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base, | |
3109741a | 706 | 2 * SZ_64K, &rd_dev->dev); |
7fadcd3a CD |
707 | mutex_unlock(&kvm->slots_lock); |
708 | ||
709 | if (ret) | |
710 | return ret; | |
711 | ||
dbd9733a | 712 | rdreg->free_index++; |
3109741a | 713 | return 0; |
7fadcd3a CD |
714 | } |
715 | ||
716 | static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu) | |
717 | { | |
718 | struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; | |
7fadcd3a CD |
719 | |
720 | kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev); | |
7fadcd3a CD |
721 | } |
722 | ||
1aab6f46 | 723 | static int vgic_register_all_redist_iodevs(struct kvm *kvm) |
ed9b8cef | 724 | { |
ed9b8cef | 725 | struct kvm_vcpu *vcpu; |
ed9b8cef AP |
726 | int c, ret = 0; |
727 | ||
ed9b8cef | 728 | kvm_for_each_vcpu(c, vcpu, kvm) { |
7fadcd3a | 729 | ret = vgic_register_redist_iodev(vcpu); |
ed9b8cef AP |
730 | if (ret) |
731 | break; | |
ed9b8cef AP |
732 | } |
733 | ||
734 | if (ret) { | |
735 | /* The current c failed, so we start with the previous one. */ | |
fa472fa9 | 736 | mutex_lock(&kvm->slots_lock); |
ed9b8cef | 737 | for (c--; c >= 0; c--) { |
8f6cdc1c | 738 | vcpu = kvm_get_vcpu(kvm, c); |
7fadcd3a | 739 | vgic_unregister_redist_iodev(vcpu); |
ed9b8cef | 740 | } |
fa472fa9 | 741 | mutex_unlock(&kvm->slots_lock); |
ed9b8cef AP |
742 | } |
743 | ||
744 | return ret; | |
745 | } | |
621ecd8d | 746 | |
ccc27bf5 EA |
747 | /** |
748 | * vgic_v3_insert_redist_region - Insert a new redistributor region | |
749 | * | |
750 | * Performs various checks before inserting the rdist region in the list. | |
751 | * Those tests depend on whether the size of the rdist region is known | |
752 | * (ie. count != 0). The list is sorted by rdist region index. | |
753 | * | |
754 | * @kvm: kvm handle | |
755 | * @index: redist region index | |
756 | * @base: base of the new rdist region | |
757 | * @count: number of redistributors the region is made of (0 in the old style | |
758 | * single region, whose size is induced from the number of vcpus) | |
759 | * | |
760 | * Return 0 on success, < 0 otherwise | |
761 | */ | |
762 | static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index, | |
763 | gpa_t base, uint32_t count) | |
1aab6f46 | 764 | { |
ccc27bf5 | 765 | struct vgic_dist *d = &kvm->arch.vgic; |
dbd9733a | 766 | struct vgic_redist_region *rdreg; |
ccc27bf5 EA |
767 | struct list_head *rd_regions = &d->rd_regions; |
768 | size_t size = count * KVM_VGIC_V3_REDIST_SIZE; | |
1aab6f46 CD |
769 | int ret; |
770 | ||
ccc27bf5 EA |
771 | /* single rdist region already set ?*/ |
772 | if (!count && !list_empty(rd_regions)) | |
773 | return -EINVAL; | |
774 | ||
775 | /* cross the end of memory ? */ | |
776 | if (base + size < base) | |
777 | return -EINVAL; | |
778 | ||
779 | if (list_empty(rd_regions)) { | |
780 | if (index != 0) | |
781 | return -EINVAL; | |
782 | } else { | |
783 | rdreg = list_last_entry(rd_regions, | |
784 | struct vgic_redist_region, list); | |
785 | if (index != rdreg->index + 1) | |
786 | return -EINVAL; | |
787 | ||
788 | /* Cannot add an explicitly sized regions after legacy region */ | |
789 | if (!rdreg->count) | |
790 | return -EINVAL; | |
791 | } | |
792 | ||
793 | /* | |
794 | * For legacy single-region redistributor regions (!count), | |
795 | * check that the redistributor region does not overlap with the | |
796 | * distributor's address space. | |
797 | */ | |
798 | if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && | |
799 | vgic_dist_overlap(kvm, base, size)) | |
800 | return -EINVAL; | |
801 | ||
802 | /* collision with any other rdist region? */ | |
803 | if (vgic_v3_rdist_overlap(kvm, base, size)) | |
dbd9733a EA |
804 | return -EINVAL; |
805 | ||
806 | rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL); | |
807 | if (!rdreg) | |
808 | return -ENOMEM; | |
809 | ||
810 | rdreg->base = VGIC_ADDR_UNDEF; | |
811 | ||
ccc27bf5 | 812 | ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K); |
1aab6f46 | 813 | if (ret) |
ccc27bf5 | 814 | goto free; |
1aab6f46 | 815 | |
ccc27bf5 EA |
816 | rdreg->base = base; |
817 | rdreg->count = count; | |
818 | rdreg->free_index = 0; | |
819 | rdreg->index = index; | |
1aab6f46 | 820 | |
ccc27bf5 EA |
821 | list_add_tail(&rdreg->list, rd_regions); |
822 | return 0; | |
823 | free: | |
824 | kfree(rdreg); | |
825 | return ret; | |
826 | } | |
827 | ||
04c11093 | 828 | int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count) |
ccc27bf5 EA |
829 | { |
830 | int ret; | |
831 | ||
04c11093 | 832 | ret = vgic_v3_insert_redist_region(kvm, index, addr, count); |
ccc27bf5 EA |
833 | if (ret) |
834 | return ret; | |
dbd9733a | 835 | |
1aab6f46 CD |
836 | /* |
837 | * Register iodevs for each existing VCPU. Adding more VCPUs | |
838 | * afterwards will register the iodevs when needed. | |
839 | */ | |
840 | ret = vgic_register_all_redist_iodevs(kvm); | |
841 | if (ret) | |
842 | return ret; | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
94574c94 VK |
847 | int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) |
848 | { | |
849 | const struct vgic_register_region *region; | |
850 | struct vgic_io_device iodev; | |
851 | struct vgic_reg_attr reg_attr; | |
852 | struct kvm_vcpu *vcpu; | |
853 | gpa_t addr; | |
854 | int ret; | |
855 | ||
856 | ret = vgic_v3_parse_attr(dev, attr, ®_attr); | |
857 | if (ret) | |
858 | return ret; | |
859 | ||
860 | vcpu = reg_attr.vcpu; | |
861 | addr = reg_attr.addr; | |
862 | ||
863 | switch (attr->group) { | |
864 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
865 | iodev.regions = vgic_v3_dist_registers; | |
866 | iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); | |
867 | iodev.base_addr = 0; | |
868 | break; | |
869 | case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{ | |
3109741a EA |
870 | iodev.regions = vgic_v3_rd_registers; |
871 | iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); | |
94574c94 VK |
872 | iodev.base_addr = 0; |
873 | break; | |
874 | } | |
d017d7b0 VK |
875 | case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: { |
876 | u64 reg, id; | |
877 | ||
878 | id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK); | |
879 | return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®); | |
880 | } | |
94574c94 VK |
881 | default: |
882 | return -ENXIO; | |
883 | } | |
884 | ||
885 | /* We only support aligned 32-bit accesses. */ | |
886 | if (addr & 3) | |
887 | return -ENXIO; | |
888 | ||
889 | region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); | |
890 | if (!region) | |
891 | return -ENXIO; | |
892 | ||
893 | return 0; | |
894 | } | |
621ecd8d AP |
895 | /* |
896 | * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI | |
897 | * generation register ICC_SGI1R_EL1) with a given VCPU. | |
898 | * If the VCPU's MPIDR matches, return the level0 affinity, otherwise | |
899 | * return -1. | |
900 | */ | |
901 | static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu) | |
902 | { | |
903 | unsigned long affinity; | |
904 | int level0; | |
905 | ||
906 | /* | |
907 | * Split the current VCPU's MPIDR into affinity level 0 and the | |
908 | * rest as this is what we have to compare against. | |
909 | */ | |
910 | affinity = kvm_vcpu_get_mpidr_aff(vcpu); | |
911 | level0 = MPIDR_AFFINITY_LEVEL(affinity, 0); | |
912 | affinity &= ~MPIDR_LEVEL_MASK; | |
913 | ||
914 | /* bail out if the upper three levels don't match */ | |
915 | if (sgi_aff != affinity) | |
916 | return -1; | |
917 | ||
918 | /* Is this VCPU's bit set in the mask ? */ | |
919 | if (!(sgi_cpu_mask & BIT(level0))) | |
920 | return -1; | |
921 | ||
922 | return level0; | |
923 | } | |
924 | ||
925 | /* | |
926 | * The ICC_SGI* registers encode the affinity differently from the MPIDR, | |
927 | * so provide a wrapper to use the existing defines to isolate a certain | |
928 | * affinity level. | |
929 | */ | |
930 | #define SGI_AFFINITY_LEVEL(reg, level) \ | |
931 | ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ | |
932 | >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) | |
933 | ||
934 | /** | |
935 | * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs | |
936 | * @vcpu: The VCPU requesting a SGI | |
6249f2a4 MZ |
937 | * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU |
938 | * @allow_group1: Does the sysreg access allow generation of G1 SGIs | |
621ecd8d AP |
939 | * |
940 | * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register. | |
941 | * This will trap in sys_regs.c and call this function. | |
942 | * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the | |
943 | * target processors as well as a bitmask of 16 Aff0 CPUs. | |
944 | * If the interrupt routing mode bit is not set, we iterate over all VCPUs to | |
945 | * check for matching ones. If this bit is set, we signal all, but not the | |
946 | * calling VCPU. | |
947 | */ | |
6249f2a4 | 948 | void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) |
621ecd8d AP |
949 | { |
950 | struct kvm *kvm = vcpu->kvm; | |
951 | struct kvm_vcpu *c_vcpu; | |
952 | u16 target_cpus; | |
953 | u64 mpidr; | |
954 | int sgi, c; | |
955 | int vcpu_id = vcpu->vcpu_id; | |
956 | bool broadcast; | |
006df0f3 | 957 | unsigned long flags; |
621ecd8d AP |
958 | |
959 | sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT; | |
e533a37f | 960 | broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT); |
621ecd8d AP |
961 | target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT; |
962 | mpidr = SGI_AFFINITY_LEVEL(reg, 3); | |
963 | mpidr |= SGI_AFFINITY_LEVEL(reg, 2); | |
964 | mpidr |= SGI_AFFINITY_LEVEL(reg, 1); | |
965 | ||
966 | /* | |
967 | * We iterate over all VCPUs to find the MPIDRs matching the request. | |
968 | * If we have handled one CPU, we clear its bit to detect early | |
969 | * if we are already finished. This avoids iterating through all | |
970 | * VCPUs when most of the times we just signal a single VCPU. | |
971 | */ | |
972 | kvm_for_each_vcpu(c, c_vcpu, kvm) { | |
973 | struct vgic_irq *irq; | |
974 | ||
975 | /* Exit early if we have dealt with all requested CPUs */ | |
976 | if (!broadcast && target_cpus == 0) | |
977 | break; | |
978 | ||
979 | /* Don't signal the calling VCPU */ | |
980 | if (broadcast && c == vcpu_id) | |
981 | continue; | |
982 | ||
983 | if (!broadcast) { | |
984 | int level0; | |
985 | ||
986 | level0 = match_mpidr(mpidr, target_cpus, c_vcpu); | |
987 | if (level0 == -1) | |
988 | continue; | |
989 | ||
990 | /* remove this matching VCPU from the mask */ | |
991 | target_cpus &= ~BIT(level0); | |
992 | } | |
993 | ||
994 | irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi); | |
995 | ||
8fa3adb8 | 996 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
621ecd8d | 997 | |
6249f2a4 MZ |
998 | /* |
999 | * An access targetting Group0 SGIs can only generate | |
1000 | * those, while an access targetting Group1 SGIs can | |
1001 | * generate interrupts of either group. | |
1002 | */ | |
1003 | if (!irq->group || allow_group1) { | |
ef1820be MZ |
1004 | if (!irq->hw) { |
1005 | irq->pending_latch = true; | |
1006 | vgic_queue_irq_unlock(vcpu->kvm, irq, flags); | |
1007 | } else { | |
1008 | /* HW SGI? Ask the GIC to inject it */ | |
1009 | int err; | |
1010 | err = irq_set_irqchip_state(irq->host_irq, | |
1011 | IRQCHIP_STATE_PENDING, | |
1012 | true); | |
1013 | WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); | |
1014 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); | |
1015 | } | |
6249f2a4 | 1016 | } else { |
8fa3adb8 | 1017 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
6249f2a4 MZ |
1018 | } |
1019 | ||
5dd4b924 | 1020 | vgic_put_irq(vcpu->kvm, irq); |
621ecd8d AP |
1021 | } |
1022 | } | |
94574c94 VK |
1023 | |
1024 | int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, | |
1025 | int offset, u32 *val) | |
1026 | { | |
1027 | struct vgic_io_device dev = { | |
1028 | .regions = vgic_v3_dist_registers, | |
1029 | .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers), | |
1030 | }; | |
1031 | ||
1032 | return vgic_uaccess(vcpu, &dev, is_write, offset, val); | |
1033 | } | |
1034 | ||
1035 | int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, | |
1036 | int offset, u32 *val) | |
1037 | { | |
1038 | struct vgic_io_device rd_dev = { | |
3109741a EA |
1039 | .regions = vgic_v3_rd_registers, |
1040 | .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers), | |
94574c94 VK |
1041 | }; |
1042 | ||
3109741a | 1043 | return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); |
94574c94 | 1044 | } |
e96a006c VK |
1045 | |
1046 | int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, | |
1047 | u32 intid, u64 *val) | |
1048 | { | |
1049 | if (intid % 32) | |
1050 | return -EINVAL; | |
1051 | ||
1052 | if (is_write) | |
1053 | vgic_write_irq_line_level_info(vcpu, intid, *val); | |
1054 | else | |
1055 | *val = vgic_read_irq_line_level_info(vcpu, intid); | |
1056 | ||
1057 | return 0; | |
1058 | } |