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KVM: arm/arm64: vgic: Return error on incompatible uaccess GICD_IIDR writes
[linux-2.6-block.git] / virt / kvm / arm / vgic / vgic-mmio-v3.c
CommitLineData
ed9b8cef
AP		 1/*
2 * VGICv3 MMIO handling functions
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/irqchip/arm-gic-v3.h>
15#include <linux/kvm.h>
16#include <linux/kvm_host.h>
17#include <kvm/iodev.h>
18#include <kvm/arm_vgic.h>
19
20#include <asm/kvm_emulate.h>
94574c94
VK		 21#include <asm/kvm_arm.h>
22#include <asm/kvm_mmu.h>
ed9b8cef
AP		 23
24#include "vgic.h"
25#include "vgic-mmio.h"
26
741972d8 27/* extract @num bytes at @offset bytes offset in data */
d7d0a11e 28unsigned long extract_bytes(u64 data, unsigned int offset,
424c3383 29 unsigned int num)
741972d8
AP		 30{
31 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
32}
33
0aa1de57 34/* allows updates of any half of a 64-bit register (or the whole thing) */
424c3383
AP		 35u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
36 unsigned long val)
0aa1de57
AP		 37{
38 int lower = (offset & 4) * 8;
39 int upper = lower + 8 * len - 1;
40
41 reg &= ~GENMASK_ULL(upper, lower);
42 val &= GENMASK_ULL(len * 8 - 1, 0);
43
44 return reg | ((u64)val << lower);
45}
46
59c5ab40
AP		 47bool vgic_has_its(struct kvm *kvm)
48{
49 struct vgic_dist *dist = &kvm->arch.vgic;
50
51 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
52 return false;
53
1085fdc6 54 return dist->has_its;
59c5ab40
AP		 55}
56
e7c48059
MZ		 57bool vgic_supports_direct_msis(struct kvm *kvm)
58{
59 return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
60}
61
fd59ed3b
AP		 62static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
63 gpa_t addr, unsigned int len)
64{
aa075b0f 65 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
fd59ed3b
AP		 66 u32 value = 0;
67
68 switch (addr & 0x0c) {
69 case GICD_CTLR:
aa075b0f 70 if (vgic->enabled)
fd59ed3b
AP		 71 value |= GICD_CTLR_ENABLE_SS_G1;
72 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
73 break;
74 case GICD_TYPER:
aa075b0f 75 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
fd59ed3b 76 value = (value >> 5) - 1;
0e4e82f1
AP		 77 if (vgic_has_its(vcpu->kvm)) {
78 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
79 value |= GICD_TYPER_LPIS;
80 } else {
81 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
82 }
fd59ed3b
AP		 83 break;
84 case GICD_IIDR:
a2dca217 85 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
aa075b0f 86 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
a2dca217 87 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
fd59ed3b
AP		 88 break;
89 default:
90 return 0;
91 }
92
93 return value;
94}
95
96static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
97 gpa_t addr, unsigned int len,
98 unsigned long val)
99{
100 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
101 bool was_enabled = dist->enabled;
102
103 switch (addr & 0x0c) {
104 case GICD_CTLR:
105 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
106
107 if (!was_enabled && dist->enabled)
108 vgic_kick_vcpus(vcpu->kvm);
109 break;
110 case GICD_TYPER:
111 case GICD_IIDR:
112 return;
113 }
114}
115
b489edc3
CD		 116static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
117 gpa_t addr, unsigned int len,
118 unsigned long val)
119{
120 switch (addr & 0x0c) {
121 case GICD_IIDR:
122 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
123 return -EINVAL;
124 }
125
126 vgic_mmio_write_v3_misc(vcpu, addr, len, val);
127 return 0;
128}
129
78a714ab
AP		 130static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
131 gpa_t addr, unsigned int len)
132{
133 int intid = VGIC_ADDR_TO_INTID(addr, 64);
134 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
5dd4b924 135 unsigned long ret = 0;
78a714ab
AP		 136
137 if (!irq)
138 return 0;
139
140 /* The upper word is RAZ for us. */
5dd4b924
AP		 141 if (!(addr & 4))
142 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
78a714ab 143
5dd4b924
AP		 144 vgic_put_irq(vcpu->kvm, irq);
145 return ret;
78a714ab
AP		 146}
147
148static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
149 gpa_t addr, unsigned int len,
150 unsigned long val)
151{
152 int intid = VGIC_ADDR_TO_INTID(addr, 64);
5dd4b924 153 struct vgic_irq *irq;
006df0f3 154 unsigned long flags;
78a714ab
AP		 155
156 /* The upper word is WI for us since we don't implement Aff3. */
157 if (addr & 4)
158 return;
159
5dd4b924
AP		 160 irq = vgic_get_irq(vcpu->kvm, NULL, intid);
161
162 if (!irq)
163 return;
164
006df0f3 165 spin_lock_irqsave(&irq->irq_lock, flags);
78a714ab
AP		 166
167 /* We only care about and preserve Aff0, Aff1 and Aff2. */
168 irq->mpidr = val & GENMASK(23, 0);
169 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
170
006df0f3 171 spin_unlock_irqrestore(&irq->irq_lock, flags);
5dd4b924 172 vgic_put_irq(vcpu->kvm, irq);
78a714ab
AP		 173}
174
59c5ab40
AP		 175static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
176 gpa_t addr, unsigned int len)
177{
178 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
179
180 return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
181}
182
183
184static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
185 gpa_t addr, unsigned int len,
186 unsigned long val)
187{
188 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
189 bool was_enabled = vgic_cpu->lpis_enabled;
190
191 if (!vgic_has_its(vcpu->kvm))
192 return;
193
194 vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
195
0e4e82f1
AP		 196 if (!was_enabled && vgic_cpu->lpis_enabled)
197 vgic_enable_lpis(vcpu);
59c5ab40
AP		 198}
199
741972d8
AP		 200static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
201 gpa_t addr, unsigned int len)
202{
203 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
ba7b3f12
EA		 204 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
205 struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
741972d8 206 int target_vcpu_id = vcpu->vcpu_id;
ba7b3f12
EA		 207 gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
208 (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
741972d8
AP		 209 u64 value;
210
e533a37f 211 value = (u64)(mpidr & GENMASK(23, 0)) << 32;
741972d8 212 value |= ((target_vcpu_id & 0xffff) << 8);
ba7b3f12
EA		 213
214 if (addr == last_rdist_typer)
741972d8 215 value |= GICR_TYPER_LAST;
0e4e82f1
AP		 216 if (vgic_has_its(vcpu->kvm))
217 value |= GICR_TYPER_PLPIS;
741972d8
AP		 218
219 return extract_bytes(value, addr & 7, len);
220}
221
222static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
223 gpa_t addr, unsigned int len)
224{
225 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
226}
227
54f59d2b
AP		 228static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
229 gpa_t addr, unsigned int len)
230{
231 switch (addr & 0xffff) {
232 case GICD_PIDR2:
233 /* report a GICv3 compliant implementation */
234 return 0x3b;
235 }
236
237 return 0;
238}
239
2df903a8
VK		 240static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
241 gpa_t addr, unsigned int len)
242{
243 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
244 u32 value = 0;
245 int i;
246
247 /*
248 * pending state of interrupt is latched in pending_latch variable.
249 * Userspace will save and restore pending state and line_level
250 * separately.
251 * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
252 * for handling of ISPENDR and ICPENDR.
253 */
254 for (i = 0; i < len * 8; i++) {
255 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
256
257 if (irq->pending_latch)
258 value |= (1U << i);
259
260 vgic_put_irq(vcpu->kvm, irq);
261 }
262
263 return value;
264}
265
c6e0917b
CD		 266static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
267 gpa_t addr, unsigned int len,
268 unsigned long val)
2df903a8
VK		 269{
270 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
271 int i;
006df0f3 272 unsigned long flags;
2df903a8
VK		 273
274 for (i = 0; i < len * 8; i++) {
275 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
276
006df0f3 277 spin_lock_irqsave(&irq->irq_lock, flags);
2df903a8
VK		 278 if (test_bit(i, &val)) {
279 /*
280 * pending_latch is set irrespective of irq type
281 * (level or edge) to avoid dependency that VM should
282 * restore irq config before pending info.
283 */
284 irq->pending_latch = true;
006df0f3 285 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
2df903a8
VK		 286 } else {
287 irq->pending_latch = false;
006df0f3 288 spin_unlock_irqrestore(&irq->irq_lock, flags);
2df903a8
VK		 289 }
290
291 vgic_put_irq(vcpu->kvm, irq);
292 }
c6e0917b
CD		 293
294 return 0;
2df903a8
VK		 295}
296
0aa1de57
AP		 297/* We want to avoid outer shareable. */
298u64 vgic_sanitise_shareability(u64 field)
299{
300 switch (field) {
301 case GIC_BASER_OuterShareable:
302 return GIC_BASER_InnerShareable;
303 default:
304 return field;
305 }
306}
307
308/* Avoid any inner non-cacheable mapping. */
309u64 vgic_sanitise_inner_cacheability(u64 field)
310{
311 switch (field) {
312 case GIC_BASER_CACHE_nCnB:
313 case GIC_BASER_CACHE_nC:
314 return GIC_BASER_CACHE_RaWb;
315 default:
316 return field;
317 }
318}
319
320/* Non-cacheable or same-as-inner are OK. */
321u64 vgic_sanitise_outer_cacheability(u64 field)
322{
323 switch (field) {
324 case GIC_BASER_CACHE_SameAsInner:
325 case GIC_BASER_CACHE_nC:
326 return field;
327 default:
328 return GIC_BASER_CACHE_nC;
329 }
330}
331
332u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
333 u64 (*sanitise_fn)(u64))
334{
335 u64 field = (reg & field_mask) >> field_shift;
336
337 field = sanitise_fn(field) << field_shift;
338 return (reg & ~field_mask) | field;
339}
340
341#define PROPBASER_RES0_MASK \
342 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
343#define PENDBASER_RES0_MASK \
344 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
345 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
346
347static u64 vgic_sanitise_pendbaser(u64 reg)
348{
349 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
350 GICR_PENDBASER_SHAREABILITY_SHIFT,
351 vgic_sanitise_shareability);
352 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
353 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
354 vgic_sanitise_inner_cacheability);
355 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
356 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
357 vgic_sanitise_outer_cacheability);
358
359 reg &= ~PENDBASER_RES0_MASK;
360 reg &= ~GENMASK_ULL(51, 48);
361
362 return reg;
363}
364
365static u64 vgic_sanitise_propbaser(u64 reg)
366{
367 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
368 GICR_PROPBASER_SHAREABILITY_SHIFT,
369 vgic_sanitise_shareability);
370 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
371 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
372 vgic_sanitise_inner_cacheability);
373 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
374 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
375 vgic_sanitise_outer_cacheability);
376
377 reg &= ~PROPBASER_RES0_MASK;
378 reg &= ~GENMASK_ULL(51, 48);
379 return reg;
380}
381
382static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
383 gpa_t addr, unsigned int len)
384{
385 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
386
387 return extract_bytes(dist->propbaser, addr & 7, len);
388}
389
390static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
391 gpa_t addr, unsigned int len,
392 unsigned long val)
393{
394 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
395 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
d9ae449b 396 u64 old_propbaser, propbaser;
0aa1de57
AP		 397
398 /* Storing a value with LPIs already enabled is undefined */
399 if (vgic_cpu->lpis_enabled)
400 return;
401
d9ae449b 402 do {
3af4e414 403 old_propbaser = READ_ONCE(dist->propbaser);
d9ae449b
CD		 404 propbaser = old_propbaser;
405 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
406 propbaser = vgic_sanitise_propbaser(propbaser);
407 } while (cmpxchg64(&dist->propbaser, old_propbaser,
408 propbaser) != old_propbaser);
0aa1de57
AP		 409}
410
411static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
412 gpa_t addr, unsigned int len)
413{
414 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
415
416 return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
417}
418
419static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
420 gpa_t addr, unsigned int len,
421 unsigned long val)
422{
423 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
d9ae449b 424 u64 old_pendbaser, pendbaser;
0aa1de57
AP		 425
426 /* Storing a value with LPIs already enabled is undefined */
427 if (vgic_cpu->lpis_enabled)
428 return;
429
d9ae449b 430 do {
3af4e414 431 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
d9ae449b
CD		 432 pendbaser = old_pendbaser;
433 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
434 pendbaser = vgic_sanitise_pendbaser(pendbaser);
435 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
436 pendbaser) != old_pendbaser);
0aa1de57
AP		 437}
438
ed9b8cef
AP		 439/*
440 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
441 * redistributors, while SPIs are covered by registers in the distributor
442 * block. Trying to set private IRQs in this block gets ignored.
443 * We take some special care here to fix the calculation of the register
444 * offset.
445 */
2df903a8 446#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
ed9b8cef
AP		 447 { \
448 .reg_offset = off, \
449 .bits_per_irq = bpi, \
450 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
451 .access_flags = acc, \
452 .read = vgic_mmio_read_raz, \
453 .write = vgic_mmio_write_wi, \
454 }, { \
455 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
456 .bits_per_irq = bpi, \
457 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
458 .access_flags = acc, \
459 .read = rd, \
460 .write = wr, \
2df903a8
VK		 461 .uaccess_read = ur, \
462 .uaccess_write = uw, \
ed9b8cef
AP		 463 }
464
465static const struct vgic_register_region vgic_v3_dist_registers[] = {
b489edc3
CD		 466 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
467 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
468 NULL, vgic_mmio_uaccess_write_v3_misc,
469 16, VGIC_ACCESS_32bit),
94574c94
VK		 470 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
471 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
472 VGIC_ACCESS_32bit),
ed9b8cef 473 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
2df903a8 474 vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
ed9b8cef
AP		 475 VGIC_ACCESS_32bit),
476 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
2df903a8 477 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
ed9b8cef
AP		 478 VGIC_ACCESS_32bit),
479 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
2df903a8 480 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
ed9b8cef
AP		 481 VGIC_ACCESS_32bit),
482 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
2df903a8
VK		 483 vgic_mmio_read_pending, vgic_mmio_write_spending,
484 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
ed9b8cef
AP		 485 VGIC_ACCESS_32bit),
486 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
2df903a8 487 vgic_mmio_read_pending, vgic_mmio_write_cpending,
c6e0917b 488 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
ed9b8cef
AP		 489 VGIC_ACCESS_32bit),
490 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
3197191e
CD		 491 vgic_mmio_read_active, vgic_mmio_write_sactive,
492 NULL, vgic_mmio_uaccess_write_sactive, 1,
ed9b8cef
AP		 493 VGIC_ACCESS_32bit),
494 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
3197191e
CD		 495 vgic_mmio_read_active, vgic_mmio_write_cactive,
496 NULL, vgic_mmio_uaccess_write_cactive,
497 1, VGIC_ACCESS_32bit),
ed9b8cef 498 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
2df903a8
VK		 499 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
500 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
ed9b8cef 501 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
2df903a8 502 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
ed9b8cef
AP		 503 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
504 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
2df903a8 505 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
ed9b8cef
AP		 506 VGIC_ACCESS_32bit),
507 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
2df903a8 508 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
ed9b8cef
AP		 509 VGIC_ACCESS_32bit),
510 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
2df903a8 511 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
ed9b8cef
AP		 512 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
513 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
54f59d2b 514 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef
AP		 515 VGIC_ACCESS_32bit),
516};
517
518static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
519 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
59c5ab40 520 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
ed9b8cef 521 VGIC_ACCESS_32bit),
94574c94
VK		 522 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
523 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
524 VGIC_ACCESS_32bit),
ed9b8cef 525 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
741972d8 526 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
ed9b8cef
AP		 527 VGIC_ACCESS_32bit),
528 REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
741972d8 529 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
ed9b8cef 530 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
94574c94
VK		 531 REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
532 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
533 VGIC_ACCESS_32bit),
ed9b8cef 534 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
0aa1de57 535 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
ed9b8cef
AP		 536 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
537 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
0aa1de57 538 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
ed9b8cef
AP		 539 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
540 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
54f59d2b 541 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef
AP		 542 VGIC_ACCESS_32bit),
543};
544
545static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
546 REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
547 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
548 VGIC_ACCESS_32bit),
549 REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
550 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
551 VGIC_ACCESS_32bit),
552 REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
553 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
554 VGIC_ACCESS_32bit),
2df903a8
VK		 555 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
556 vgic_mmio_read_pending, vgic_mmio_write_spending,
557 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
ed9b8cef 558 VGIC_ACCESS_32bit),
2df903a8
VK		 559 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
560 vgic_mmio_read_pending, vgic_mmio_write_cpending,
c6e0917b 561 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
ed9b8cef 562 VGIC_ACCESS_32bit),
0710f9a6
CD		 563 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISACTIVER0,
564 vgic_mmio_read_active, vgic_mmio_write_sactive,
565 NULL, vgic_mmio_uaccess_write_sactive,
566 4, VGIC_ACCESS_32bit),
567 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICACTIVER0,
568 vgic_mmio_read_active, vgic_mmio_write_cactive,
569 NULL, vgic_mmio_uaccess_write_cactive,
570 4, VGIC_ACCESS_32bit),
ed9b8cef
AP		 571 REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
572 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
573 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
574 REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
575 vgic_mmio_read_config, vgic_mmio_write_config, 8,
576 VGIC_ACCESS_32bit),
577 REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
578 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
579 VGIC_ACCESS_32bit),
580 REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
581 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
582 VGIC_ACCESS_32bit),
583};
584
585unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
586{
587 dev->regions = vgic_v3_dist_registers;
588 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
589
590 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
591
592 return SZ_64K;
593}
594
7fadcd3a
CD		 595/**
596 * vgic_register_redist_iodev - register a single redist iodev
597 * @vcpu: The VCPU to which the redistributor belongs
598 *
599 * Register a KVM iodev for this VCPU's redistributor using the address
600 * provided.
601 *
602 * Return 0 on success, -ERRNO otherwise.
603 */
1aab6f46 604int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
7fadcd3a
CD		 605{
606 struct kvm *kvm = vcpu->kvm;
607 struct vgic_dist *vgic = &kvm->arch.vgic;
dbd9733a 608 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
7fadcd3a
CD		 609 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
610 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
dbd9733a 611 struct vgic_redist_region *rdreg;
7fadcd3a
CD		 612 gpa_t rd_base, sgi_base;
613 int ret;
614
c011f4ea
EA		 615 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
616 return 0;
617
1aab6f46
CD		 618 /*
619 * We may be creating VCPUs before having set the base address for the
620 * redistributor region, in which case we will come back to this
621 * function for all VCPUs when the base address is set. Just return
622 * without doing any work for now.
623 */
dc524619 624 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
dbd9733a 625 if (!rdreg)
1aab6f46
CD		 626 return 0;
627
628 if (!vgic_v3_check_base(kvm))
629 return -EINVAL;
630
dbd9733a
EA		 631 vgic_cpu->rdreg = rdreg;
632
633 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
7fadcd3a
CD		 634 sgi_base = rd_base + SZ_64K;
635
636 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
637 rd_dev->base_addr = rd_base;
638 rd_dev->iodev_type = IODEV_REDIST;
639 rd_dev->regions = vgic_v3_rdbase_registers;
640 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
641 rd_dev->redist_vcpu = vcpu;
642
643 mutex_lock(&kvm->slots_lock);
644 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
645 SZ_64K, &rd_dev->dev);
646 mutex_unlock(&kvm->slots_lock);
647
648 if (ret)
649 return ret;
650
651 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
652 sgi_dev->base_addr = sgi_base;
653 sgi_dev->iodev_type = IODEV_REDIST;
654 sgi_dev->regions = vgic_v3_sgibase_registers;
655 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
656 sgi_dev->redist_vcpu = vcpu;
657
658 mutex_lock(&kvm->slots_lock);
659 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
660 SZ_64K, &sgi_dev->dev);
552c9f47 661 if (ret) {
7fadcd3a
CD		 662 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
663 &rd_dev->dev);
fa472fa9 664 goto out;
552c9f47 665 }
7fadcd3a 666
dbd9733a 667 rdreg->free_index++;
fa472fa9
CD		 668out:
669 mutex_unlock(&kvm->slots_lock);
7fadcd3a
CD		 670 return ret;
671}
672
673static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
674{
675 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
676 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
677
678 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
679 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &sgi_dev->dev);
680}
681
1aab6f46 682static int vgic_register_all_redist_iodevs(struct kvm *kvm)
ed9b8cef 683{
ed9b8cef 684 struct kvm_vcpu *vcpu;
ed9b8cef
AP		 685 int c, ret = 0;
686
ed9b8cef 687 kvm_for_each_vcpu(c, vcpu, kvm) {
7fadcd3a 688 ret = vgic_register_redist_iodev(vcpu);
ed9b8cef
AP		 689 if (ret)
690 break;
ed9b8cef
AP		 691 }
692
693 if (ret) {
694 /* The current c failed, so we start with the previous one. */
fa472fa9 695 mutex_lock(&kvm->slots_lock);
ed9b8cef 696 for (c--; c >= 0; c--) {
8f6cdc1c 697 vcpu = kvm_get_vcpu(kvm, c);
7fadcd3a 698 vgic_unregister_redist_iodev(vcpu);
ed9b8cef 699 }
fa472fa9 700 mutex_unlock(&kvm->slots_lock);
ed9b8cef
AP		 701 }
702
703 return ret;
704}
621ecd8d 705
ccc27bf5
EA		 706/**
707 * vgic_v3_insert_redist_region - Insert a new redistributor region
708 *
709 * Performs various checks before inserting the rdist region in the list.
710 * Those tests depend on whether the size of the rdist region is known
711 * (ie. count != 0). The list is sorted by rdist region index.
712 *
713 * @kvm: kvm handle
714 * @index: redist region index
715 * @base: base of the new rdist region
716 * @count: number of redistributors the region is made of (0 in the old style
717 * single region, whose size is induced from the number of vcpus)
718 *
719 * Return 0 on success, < 0 otherwise
720 */
721static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
722 gpa_t base, uint32_t count)
1aab6f46 723{
ccc27bf5 724 struct vgic_dist *d = &kvm->arch.vgic;
dbd9733a 725 struct vgic_redist_region *rdreg;
ccc27bf5
EA		 726 struct list_head *rd_regions = &d->rd_regions;
727 size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
1aab6f46
CD		 728 int ret;
729
ccc27bf5
EA		 730 /* single rdist region already set ?*/
731 if (!count && !list_empty(rd_regions))
732 return -EINVAL;
733
734 /* cross the end of memory ? */
735 if (base + size < base)
736 return -EINVAL;
737
738 if (list_empty(rd_regions)) {
739 if (index != 0)
740 return -EINVAL;
741 } else {
742 rdreg = list_last_entry(rd_regions,
743 struct vgic_redist_region, list);
744 if (index != rdreg->index + 1)
745 return -EINVAL;
746
747 /* Cannot add an explicitly sized regions after legacy region */
748 if (!rdreg->count)
749 return -EINVAL;
750 }
751
752 /*
753 * For legacy single-region redistributor regions (!count),
754 * check that the redistributor region does not overlap with the
755 * distributor's address space.
756 */
757 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
758 vgic_dist_overlap(kvm, base, size))
759 return -EINVAL;
760
761 /* collision with any other rdist region? */
762 if (vgic_v3_rdist_overlap(kvm, base, size))
dbd9733a
EA		 763 return -EINVAL;
764
765 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
766 if (!rdreg)
767 return -ENOMEM;
768
769 rdreg->base = VGIC_ADDR_UNDEF;
770
ccc27bf5 771 ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
1aab6f46 772 if (ret)
ccc27bf5 773 goto free;
1aab6f46 774
ccc27bf5
EA		 775 rdreg->base = base;
776 rdreg->count = count;
777 rdreg->free_index = 0;
778 rdreg->index = index;
1aab6f46 779
ccc27bf5
EA		 780 list_add_tail(&rdreg->list, rd_regions);
781 return 0;
782free:
783 kfree(rdreg);
784 return ret;
785}
786
04c11093 787int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
ccc27bf5
EA		 788{
789 int ret;
790
04c11093 791 ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
ccc27bf5
EA		 792 if (ret)
793 return ret;
dbd9733a 794
1aab6f46
CD		 795 /*
796 * Register iodevs for each existing VCPU. Adding more VCPUs
797 * afterwards will register the iodevs when needed.
798 */
799 ret = vgic_register_all_redist_iodevs(kvm);
800 if (ret)
801 return ret;
802
803 return 0;
804}
805
94574c94
VK		 806int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
807{
808 const struct vgic_register_region *region;
809 struct vgic_io_device iodev;
810 struct vgic_reg_attr reg_attr;
811 struct kvm_vcpu *vcpu;
812 gpa_t addr;
813 int ret;
814
815 ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
816 if (ret)
817 return ret;
818
819 vcpu = reg_attr.vcpu;
820 addr = reg_attr.addr;
821
822 switch (attr->group) {
823 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
824 iodev.regions = vgic_v3_dist_registers;
825 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
826 iodev.base_addr = 0;
827 break;
828 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
829 iodev.regions = vgic_v3_rdbase_registers;
830 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
831 iodev.base_addr = 0;
832 break;
833 }
d017d7b0
VK		 834 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
835 u64 reg, id;
836
837 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
838 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, &reg);
839 }
94574c94
VK		 840 default:
841 return -ENXIO;
842 }
843
844 /* We only support aligned 32-bit accesses. */
845 if (addr & 3)
846 return -ENXIO;
847
848 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
849 if (!region)
850 return -ENXIO;
851
852 return 0;
853}
621ecd8d
AP		 854/*
855 * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
856 * generation register ICC_SGI1R_EL1) with a given VCPU.
857 * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
858 * return -1.
859 */
860static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
861{
862 unsigned long affinity;
863 int level0;
864
865 /*
866 * Split the current VCPU's MPIDR into affinity level 0 and the
867 * rest as this is what we have to compare against.
868 */
869 affinity = kvm_vcpu_get_mpidr_aff(vcpu);
870 level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
871 affinity &= ~MPIDR_LEVEL_MASK;
872
873 /* bail out if the upper three levels don't match */
874 if (sgi_aff != affinity)
875 return -1;
876
877 /* Is this VCPU's bit set in the mask ? */
878 if (!(sgi_cpu_mask & BIT(level0)))
879 return -1;
880
881 return level0;
882}
883
884/*
885 * The ICC_SGI* registers encode the affinity differently from the MPIDR,
886 * so provide a wrapper to use the existing defines to isolate a certain
887 * affinity level.
888 */
889#define SGI_AFFINITY_LEVEL(reg, level) \
890 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
891 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
892
893/**
894 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
895 * @vcpu: The VCPU requesting a SGI
896 * @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
897 *
898 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
899 * This will trap in sys_regs.c and call this function.
900 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
901 * target processors as well as a bitmask of 16 Aff0 CPUs.
902 * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
903 * check for matching ones. If this bit is set, we signal all, but not the
904 * calling VCPU.
905 */
906void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
907{
908 struct kvm *kvm = vcpu->kvm;
909 struct kvm_vcpu *c_vcpu;
910 u16 target_cpus;
911 u64 mpidr;
912 int sgi, c;
913 int vcpu_id = vcpu->vcpu_id;
914 bool broadcast;
006df0f3 915 unsigned long flags;
621ecd8d
AP		 916
917 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
e533a37f 918 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
621ecd8d
AP		 919 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
920 mpidr = SGI_AFFINITY_LEVEL(reg, 3);
921 mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
922 mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
923
924 /*
925 * We iterate over all VCPUs to find the MPIDRs matching the request.
926 * If we have handled one CPU, we clear its bit to detect early
927 * if we are already finished. This avoids iterating through all
928 * VCPUs when most of the times we just signal a single VCPU.
929 */
930 kvm_for_each_vcpu(c, c_vcpu, kvm) {
931 struct vgic_irq *irq;
932
933 /* Exit early if we have dealt with all requested CPUs */
934 if (!broadcast && target_cpus == 0)
935 break;
936
937 /* Don't signal the calling VCPU */
938 if (broadcast && c == vcpu_id)
939 continue;
940
941 if (!broadcast) {
942 int level0;
943
944 level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
945 if (level0 == -1)
946 continue;
947
948 /* remove this matching VCPU from the mask */
949 target_cpus &= ~BIT(level0);
950 }
951
952 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
953
006df0f3 954 spin_lock_irqsave(&irq->irq_lock, flags);
8694e4da 955 irq->pending_latch = true;
621ecd8d 956
006df0f3 957 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
5dd4b924 958 vgic_put_irq(vcpu->kvm, irq);
621ecd8d
AP		 959 }
960}
94574c94
VK		 961
962int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
963 int offset, u32 *val)
964{
965 struct vgic_io_device dev = {
966 .regions = vgic_v3_dist_registers,
967 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
968 };
969
970 return vgic_uaccess(vcpu, &dev, is_write, offset, val);
971}
972
973int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
974 int offset, u32 *val)
975{
976 struct vgic_io_device rd_dev = {
977 .regions = vgic_v3_rdbase_registers,
978 .nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
979 };
980
981 struct vgic_io_device sgi_dev = {
982 .regions = vgic_v3_sgibase_registers,
983 .nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
984 };
985
986 /* SGI_base is the next 64K frame after RD_base */
987 if (offset >= SZ_64K)
988 return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
989 val);
990 else
991 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
992}
e96a006c
VK		 993
994int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
995 u32 intid, u64 *val)
996{
997 if (intid % 32)
998 return -EINVAL;
999
1000 if (is_write)
1001 vgic_write_irq_line_level_info(vcpu, intid, *val);
1002 else
1003 *val = vgic_read_irq_line_level_info(vcpu, intid);
1004
1005 return 0;
1006}
Linux 6.x block layer and io_uring tree(s)