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KVM: arm/arm64: vgic: Implement support for userspace access
[linux-2.6-block.git] / virt / kvm / arm / vgic / vgic-mmio-v3.c
CommitLineData
ed9b8cef
AP		 1/*
2 * VGICv3 MMIO handling functions
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/irqchip/arm-gic-v3.h>
15#include <linux/kvm.h>
16#include <linux/kvm_host.h>
17#include <kvm/iodev.h>
18#include <kvm/arm_vgic.h>
19
20#include <asm/kvm_emulate.h>
21
22#include "vgic.h"
23#include "vgic-mmio.h"
24
741972d8 25/* extract @num bytes at @offset bytes offset in data */
d7d0a11e 26unsigned long extract_bytes(u64 data, unsigned int offset,
424c3383 27 unsigned int num)
741972d8
AP		 28{
29 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
30}
31
0aa1de57 32/* allows updates of any half of a 64-bit register (or the whole thing) */
424c3383
AP		 33u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
34 unsigned long val)
0aa1de57
AP		 35{
36 int lower = (offset & 4) * 8;
37 int upper = lower + 8 * len - 1;
38
39 reg &= ~GENMASK_ULL(upper, lower);
40 val &= GENMASK_ULL(len * 8 - 1, 0);
41
42 return reg | ((u64)val << lower);
43}
44
59c5ab40
AP		 45bool vgic_has_its(struct kvm *kvm)
46{
47 struct vgic_dist *dist = &kvm->arch.vgic;
48
49 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
50 return false;
51
1085fdc6 52 return dist->has_its;
59c5ab40
AP		 53}
54
fd59ed3b
AP		 55static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
56 gpa_t addr, unsigned int len)
57{
58 u32 value = 0;
59
60 switch (addr & 0x0c) {
61 case GICD_CTLR:
62 if (vcpu->kvm->arch.vgic.enabled)
63 value |= GICD_CTLR_ENABLE_SS_G1;
64 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
65 break;
66 case GICD_TYPER:
67 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
68 value = (value >> 5) - 1;
0e4e82f1
AP		 69 if (vgic_has_its(vcpu->kvm)) {
70 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
71 value |= GICD_TYPER_LPIS;
72 } else {
73 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
74 }
fd59ed3b
AP		 75 break;
76 case GICD_IIDR:
77 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
78 break;
79 default:
80 return 0;
81 }
82
83 return value;
84}
85
86static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
87 gpa_t addr, unsigned int len,
88 unsigned long val)
89{
90 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
91 bool was_enabled = dist->enabled;
92
93 switch (addr & 0x0c) {
94 case GICD_CTLR:
95 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
96
97 if (!was_enabled && dist->enabled)
98 vgic_kick_vcpus(vcpu->kvm);
99 break;
100 case GICD_TYPER:
101 case GICD_IIDR:
102 return;
103 }
104}
105
78a714ab
AP		 106static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
107 gpa_t addr, unsigned int len)
108{
109 int intid = VGIC_ADDR_TO_INTID(addr, 64);
110 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
5dd4b924 111 unsigned long ret = 0;
78a714ab
AP		 112
113 if (!irq)
114 return 0;
115
116 /* The upper word is RAZ for us. */
5dd4b924
AP		 117 if (!(addr & 4))
118 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
78a714ab 119
5dd4b924
AP		 120 vgic_put_irq(vcpu->kvm, irq);
121 return ret;
78a714ab
AP		 122}
123
124static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
125 gpa_t addr, unsigned int len,
126 unsigned long val)
127{
128 int intid = VGIC_ADDR_TO_INTID(addr, 64);
5dd4b924 129 struct vgic_irq *irq;
78a714ab
AP		 130
131 /* The upper word is WI for us since we don't implement Aff3. */
132 if (addr & 4)
133 return;
134
5dd4b924
AP		 135 irq = vgic_get_irq(vcpu->kvm, NULL, intid);
136
137 if (!irq)
138 return;
139
78a714ab
AP		 140 spin_lock(&irq->irq_lock);
141
142 /* We only care about and preserve Aff0, Aff1 and Aff2. */
143 irq->mpidr = val & GENMASK(23, 0);
144 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
145
146 spin_unlock(&irq->irq_lock);
5dd4b924 147 vgic_put_irq(vcpu->kvm, irq);
78a714ab
AP		 148}
149
59c5ab40
AP		 150static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
151 gpa_t addr, unsigned int len)
152{
153 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
154
155 return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
156}
157
158
159static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
160 gpa_t addr, unsigned int len,
161 unsigned long val)
162{
163 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
164 bool was_enabled = vgic_cpu->lpis_enabled;
165
166 if (!vgic_has_its(vcpu->kvm))
167 return;
168
169 vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
170
0e4e82f1
AP		 171 if (!was_enabled && vgic_cpu->lpis_enabled)
172 vgic_enable_lpis(vcpu);
59c5ab40
AP		 173}
174
741972d8
AP		 175static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
176 gpa_t addr, unsigned int len)
177{
178 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
179 int target_vcpu_id = vcpu->vcpu_id;
180 u64 value;
181
e533a37f 182 value = (u64)(mpidr & GENMASK(23, 0)) << 32;
741972d8
AP		 183 value |= ((target_vcpu_id & 0xffff) << 8);
184 if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
185 value |= GICR_TYPER_LAST;
0e4e82f1
AP		 186 if (vgic_has_its(vcpu->kvm))
187 value |= GICR_TYPER_PLPIS;
741972d8
AP		 188
189 return extract_bytes(value, addr & 7, len);
190}
191
192static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
193 gpa_t addr, unsigned int len)
194{
195 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
196}
197
54f59d2b
AP		 198static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
199 gpa_t addr, unsigned int len)
200{
201 switch (addr & 0xffff) {
202 case GICD_PIDR2:
203 /* report a GICv3 compliant implementation */
204 return 0x3b;
205 }
206
207 return 0;
208}
209
2df903a8
VK		 210static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
211 gpa_t addr, unsigned int len)
212{
213 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
214 u32 value = 0;
215 int i;
216
217 /*
218 * pending state of interrupt is latched in pending_latch variable.
219 * Userspace will save and restore pending state and line_level
220 * separately.
221 * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
222 * for handling of ISPENDR and ICPENDR.
223 */
224 for (i = 0; i < len * 8; i++) {
225 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
226
227 if (irq->pending_latch)
228 value |= (1U << i);
229
230 vgic_put_irq(vcpu->kvm, irq);
231 }
232
233 return value;
234}
235
236static void vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
237 gpa_t addr, unsigned int len,
238 unsigned long val)
239{
240 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
241 int i;
242
243 for (i = 0; i < len * 8; i++) {
244 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
245
246 spin_lock(&irq->irq_lock);
247 if (test_bit(i, &val)) {
248 /*
249 * pending_latch is set irrespective of irq type
250 * (level or edge) to avoid dependency that VM should
251 * restore irq config before pending info.
252 */
253 irq->pending_latch = true;
254 vgic_queue_irq_unlock(vcpu->kvm, irq);
255 } else {
256 irq->pending_latch = false;
257 spin_unlock(&irq->irq_lock);
258 }
259
260 vgic_put_irq(vcpu->kvm, irq);
261 }
262}
263
0aa1de57
AP		 264/* We want to avoid outer shareable. */
265u64 vgic_sanitise_shareability(u64 field)
266{
267 switch (field) {
268 case GIC_BASER_OuterShareable:
269 return GIC_BASER_InnerShareable;
270 default:
271 return field;
272 }
273}
274
275/* Avoid any inner non-cacheable mapping. */
276u64 vgic_sanitise_inner_cacheability(u64 field)
277{
278 switch (field) {
279 case GIC_BASER_CACHE_nCnB:
280 case GIC_BASER_CACHE_nC:
281 return GIC_BASER_CACHE_RaWb;
282 default:
283 return field;
284 }
285}
286
287/* Non-cacheable or same-as-inner are OK. */
288u64 vgic_sanitise_outer_cacheability(u64 field)
289{
290 switch (field) {
291 case GIC_BASER_CACHE_SameAsInner:
292 case GIC_BASER_CACHE_nC:
293 return field;
294 default:
295 return GIC_BASER_CACHE_nC;
296 }
297}
298
299u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
300 u64 (*sanitise_fn)(u64))
301{
302 u64 field = (reg & field_mask) >> field_shift;
303
304 field = sanitise_fn(field) << field_shift;
305 return (reg & ~field_mask) | field;
306}
307
308#define PROPBASER_RES0_MASK \
309 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
310#define PENDBASER_RES0_MASK \
311 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
312 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
313
314static u64 vgic_sanitise_pendbaser(u64 reg)
315{
316 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
317 GICR_PENDBASER_SHAREABILITY_SHIFT,
318 vgic_sanitise_shareability);
319 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
320 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
321 vgic_sanitise_inner_cacheability);
322 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
323 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
324 vgic_sanitise_outer_cacheability);
325
326 reg &= ~PENDBASER_RES0_MASK;
327 reg &= ~GENMASK_ULL(51, 48);
328
329 return reg;
330}
331
332static u64 vgic_sanitise_propbaser(u64 reg)
333{
334 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
335 GICR_PROPBASER_SHAREABILITY_SHIFT,
336 vgic_sanitise_shareability);
337 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
338 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
339 vgic_sanitise_inner_cacheability);
340 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
341 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
342 vgic_sanitise_outer_cacheability);
343
344 reg &= ~PROPBASER_RES0_MASK;
345 reg &= ~GENMASK_ULL(51, 48);
346 return reg;
347}
348
349static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
350 gpa_t addr, unsigned int len)
351{
352 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
353
354 return extract_bytes(dist->propbaser, addr & 7, len);
355}
356
357static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
358 gpa_t addr, unsigned int len,
359 unsigned long val)
360{
361 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
362 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
d9ae449b 363 u64 old_propbaser, propbaser;
0aa1de57
AP		 364
365 /* Storing a value with LPIs already enabled is undefined */
366 if (vgic_cpu->lpis_enabled)
367 return;
368
d9ae449b
CD		 369 do {
370 old_propbaser = dist->propbaser;
371 propbaser = old_propbaser;
372 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
373 propbaser = vgic_sanitise_propbaser(propbaser);
374 } while (cmpxchg64(&dist->propbaser, old_propbaser,
375 propbaser) != old_propbaser);
0aa1de57
AP		 376}
377
378static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
379 gpa_t addr, unsigned int len)
380{
381 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
382
383 return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
384}
385
386static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
387 gpa_t addr, unsigned int len,
388 unsigned long val)
389{
390 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
d9ae449b 391 u64 old_pendbaser, pendbaser;
0aa1de57
AP		 392
393 /* Storing a value with LPIs already enabled is undefined */
394 if (vgic_cpu->lpis_enabled)
395 return;
396
d9ae449b
CD		 397 do {
398 old_pendbaser = vgic_cpu->pendbaser;
399 pendbaser = old_pendbaser;
400 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
401 pendbaser = vgic_sanitise_pendbaser(pendbaser);
402 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
403 pendbaser) != old_pendbaser);
0aa1de57
AP		 404}
405
ed9b8cef
AP		 406/*
407 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
408 * redistributors, while SPIs are covered by registers in the distributor
409 * block. Trying to set private IRQs in this block gets ignored.
410 * We take some special care here to fix the calculation of the register
411 * offset.
412 */
2df903a8 413#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
ed9b8cef
AP		 414 { \
415 .reg_offset = off, \
416 .bits_per_irq = bpi, \
417 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
418 .access_flags = acc, \
419 .read = vgic_mmio_read_raz, \
420 .write = vgic_mmio_write_wi, \
421 }, { \
422 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
423 .bits_per_irq = bpi, \
424 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
425 .access_flags = acc, \
426 .read = rd, \
427 .write = wr, \
2df903a8
VK		 428 .uaccess_read = ur, \
429 .uaccess_write = uw, \
ed9b8cef
AP		 430 }
431
432static const struct vgic_register_region vgic_v3_dist_registers[] = {
433 REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
fd59ed3b 434 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
ed9b8cef
AP		 435 VGIC_ACCESS_32bit),
436 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
2df903a8 437 vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
ed9b8cef
AP		 438 VGIC_ACCESS_32bit),
439 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
2df903a8 440 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
ed9b8cef
AP		 441 VGIC_ACCESS_32bit),
442 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
2df903a8 443 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
ed9b8cef
AP		 444 VGIC_ACCESS_32bit),
445 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
2df903a8
VK		 446 vgic_mmio_read_pending, vgic_mmio_write_spending,
447 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
ed9b8cef
AP		 448 VGIC_ACCESS_32bit),
449 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
2df903a8
VK		 450 vgic_mmio_read_pending, vgic_mmio_write_cpending,
451 vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
ed9b8cef
AP		 452 VGIC_ACCESS_32bit),
453 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
2df903a8 454 vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
ed9b8cef
AP		 455 VGIC_ACCESS_32bit),
456 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
2df903a8 457 vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
ed9b8cef
AP		 458 VGIC_ACCESS_32bit),
459 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
2df903a8
VK		 460 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
461 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
ed9b8cef 462 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
2df903a8 463 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
ed9b8cef
AP		 464 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
465 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
2df903a8 466 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
ed9b8cef
AP		 467 VGIC_ACCESS_32bit),
468 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
2df903a8 469 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
ed9b8cef
AP		 470 VGIC_ACCESS_32bit),
471 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
2df903a8 472 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
ed9b8cef
AP		 473 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
474 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
54f59d2b 475 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef
AP		 476 VGIC_ACCESS_32bit),
477};
478
479static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
480 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
59c5ab40 481 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
ed9b8cef
AP		 482 VGIC_ACCESS_32bit),
483 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
741972d8 484 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
ed9b8cef
AP		 485 VGIC_ACCESS_32bit),
486 REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
741972d8 487 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
ed9b8cef
AP		 488 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
489 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
0aa1de57 490 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
ed9b8cef
AP		 491 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
492 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
0aa1de57 493 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
ed9b8cef
AP		 494 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
495 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
54f59d2b 496 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
ed9b8cef
AP		 497 VGIC_ACCESS_32bit),
498};
499
500static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
501 REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
502 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
503 VGIC_ACCESS_32bit),
504 REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
505 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
506 VGIC_ACCESS_32bit),
507 REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
508 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
509 VGIC_ACCESS_32bit),
2df903a8
VK		 510 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
511 vgic_mmio_read_pending, vgic_mmio_write_spending,
512 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
ed9b8cef 513 VGIC_ACCESS_32bit),
2df903a8
VK		 514 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
515 vgic_mmio_read_pending, vgic_mmio_write_cpending,
516 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
ed9b8cef
AP		 517 VGIC_ACCESS_32bit),
518 REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
519 vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
520 VGIC_ACCESS_32bit),
521 REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
522 vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
523 VGIC_ACCESS_32bit),
524 REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
525 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
526 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
527 REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
528 vgic_mmio_read_config, vgic_mmio_write_config, 8,
529 VGIC_ACCESS_32bit),
530 REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
531 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
532 VGIC_ACCESS_32bit),
533 REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
534 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
535 VGIC_ACCESS_32bit),
536};
537
538unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
539{
540 dev->regions = vgic_v3_dist_registers;
541 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
542
543 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
544
545 return SZ_64K;
546}
547
548int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
549{
ed9b8cef 550 struct kvm_vcpu *vcpu;
ed9b8cef
AP		 551 int c, ret = 0;
552
ed9b8cef
AP		 553 kvm_for_each_vcpu(c, vcpu, kvm) {
554 gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
555 gpa_t sgi_base = rd_base + SZ_64K;
8f6cdc1c
AP		 556 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
557 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
ed9b8cef
AP		 558
559 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
560 rd_dev->base_addr = rd_base;
59c5ab40 561 rd_dev->iodev_type = IODEV_REDIST;
ed9b8cef
AP		 562 rd_dev->regions = vgic_v3_rdbase_registers;
563 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
564 rd_dev->redist_vcpu = vcpu;
565
566 mutex_lock(&kvm->slots_lock);
567 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
568 SZ_64K, &rd_dev->dev);
569 mutex_unlock(&kvm->slots_lock);
570
571 if (ret)
572 break;
573
574 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
575 sgi_dev->base_addr = sgi_base;
59c5ab40 576 sgi_dev->iodev_type = IODEV_REDIST;
ed9b8cef
AP		 577 sgi_dev->regions = vgic_v3_sgibase_registers;
578 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
579 sgi_dev->redist_vcpu = vcpu;
580
581 mutex_lock(&kvm->slots_lock);
582 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
583 SZ_64K, &sgi_dev->dev);
584 mutex_unlock(&kvm->slots_lock);
585 if (ret) {
586 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
587 &rd_dev->dev);
588 break;
589 }
590 }
591
592 if (ret) {
593 /* The current c failed, so we start with the previous one. */
594 for (c--; c >= 0; c--) {
8f6cdc1c
AP		 595 struct vgic_cpu *vgic_cpu;
596
597 vcpu = kvm_get_vcpu(kvm, c);
598 vgic_cpu = &vcpu->arch.vgic_cpu;
ed9b8cef 599 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
8f6cdc1c 600 &vgic_cpu->rd_iodev.dev);
ed9b8cef 601 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
8f6cdc1c 602 &vgic_cpu->sgi_iodev.dev);
ed9b8cef 603 }
ed9b8cef
AP		 604 }
605
606 return ret;
607}
621ecd8d
AP		 608
609/*
610 * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
611 * generation register ICC_SGI1R_EL1) with a given VCPU.
612 * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
613 * return -1.
614 */
615static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
616{
617 unsigned long affinity;
618 int level0;
619
620 /*
621 * Split the current VCPU's MPIDR into affinity level 0 and the
622 * rest as this is what we have to compare against.
623 */
624 affinity = kvm_vcpu_get_mpidr_aff(vcpu);
625 level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
626 affinity &= ~MPIDR_LEVEL_MASK;
627
628 /* bail out if the upper three levels don't match */
629 if (sgi_aff != affinity)
630 return -1;
631
632 /* Is this VCPU's bit set in the mask ? */
633 if (!(sgi_cpu_mask & BIT(level0)))
634 return -1;
635
636 return level0;
637}
638
639/*
640 * The ICC_SGI* registers encode the affinity differently from the MPIDR,
641 * so provide a wrapper to use the existing defines to isolate a certain
642 * affinity level.
643 */
644#define SGI_AFFINITY_LEVEL(reg, level) \
645 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
646 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
647
648/**
649 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
650 * @vcpu: The VCPU requesting a SGI
651 * @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
652 *
653 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
654 * This will trap in sys_regs.c and call this function.
655 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
656 * target processors as well as a bitmask of 16 Aff0 CPUs.
657 * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
658 * check for matching ones. If this bit is set, we signal all, but not the
659 * calling VCPU.
660 */
661void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
662{
663 struct kvm *kvm = vcpu->kvm;
664 struct kvm_vcpu *c_vcpu;
665 u16 target_cpus;
666 u64 mpidr;
667 int sgi, c;
668 int vcpu_id = vcpu->vcpu_id;
669 bool broadcast;
670
671 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
e533a37f 672 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
621ecd8d
AP		 673 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
674 mpidr = SGI_AFFINITY_LEVEL(reg, 3);
675 mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
676 mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
677
678 /*
679 * We iterate over all VCPUs to find the MPIDRs matching the request.
680 * If we have handled one CPU, we clear its bit to detect early
681 * if we are already finished. This avoids iterating through all
682 * VCPUs when most of the times we just signal a single VCPU.
683 */
684 kvm_for_each_vcpu(c, c_vcpu, kvm) {
685 struct vgic_irq *irq;
686
687 /* Exit early if we have dealt with all requested CPUs */
688 if (!broadcast && target_cpus == 0)
689 break;
690
691 /* Don't signal the calling VCPU */
692 if (broadcast && c == vcpu_id)
693 continue;
694
695 if (!broadcast) {
696 int level0;
697
698 level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
699 if (level0 == -1)
700 continue;
701
702 /* remove this matching VCPU from the mask */
703 target_cpus &= ~BIT(level0);
704 }
705
706 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
707
708 spin_lock(&irq->irq_lock);
8694e4da 709 irq->pending_latch = true;
621ecd8d
AP		 710
711 vgic_queue_irq_unlock(vcpu->kvm, irq);
5dd4b924 712 vgic_put_irq(vcpu->kvm, irq);
621ecd8d
AP		 713 }
714}
Linux 6.x block layer and io_uring tree(s)