Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ed9b8cef AP |
2 | /* |
3 | * VGICv3 MMIO handling functions | |
ed9b8cef AP |
4 | */ |
5 | ||
6 | #include <linux/irqchip/arm-gic-v3.h> | |
7 | #include <linux/kvm.h> | |
8 | #include <linux/kvm_host.h> | |
9 | #include <kvm/iodev.h> | |
10 | #include <kvm/arm_vgic.h> | |
11 | ||
12 | #include <asm/kvm_emulate.h> | |
94574c94 VK |
13 | #include <asm/kvm_arm.h> |
14 | #include <asm/kvm_mmu.h> | |
ed9b8cef AP |
15 | |
16 | #include "vgic.h" | |
17 | #include "vgic-mmio.h" | |
18 | ||
741972d8 | 19 | /* extract @num bytes at @offset bytes offset in data */ |
d7d0a11e | 20 | unsigned long extract_bytes(u64 data, unsigned int offset, |
424c3383 | 21 | unsigned int num) |
741972d8 AP |
22 | { |
23 | return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); | |
24 | } | |
25 | ||
0aa1de57 | 26 | /* allows updates of any half of a 64-bit register (or the whole thing) */ |
424c3383 AP |
27 | u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, |
28 | unsigned long val) | |
0aa1de57 AP |
29 | { |
30 | int lower = (offset & 4) * 8; | |
31 | int upper = lower + 8 * len - 1; | |
32 | ||
33 | reg &= ~GENMASK_ULL(upper, lower); | |
34 | val &= GENMASK_ULL(len * 8 - 1, 0); | |
35 | ||
36 | return reg | ((u64)val << lower); | |
37 | } | |
38 | ||
59c5ab40 AP |
39 | bool vgic_has_its(struct kvm *kvm) |
40 | { | |
41 | struct vgic_dist *dist = &kvm->arch.vgic; | |
42 | ||
43 | if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) | |
44 | return false; | |
45 | ||
1085fdc6 | 46 | return dist->has_its; |
59c5ab40 AP |
47 | } |
48 | ||
e7c48059 MZ |
49 | bool vgic_supports_direct_msis(struct kvm *kvm) |
50 | { | |
51 | return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm); | |
52 | } | |
53 | ||
d53c2c29 CD |
54 | /* |
55 | * The Revision field in the IIDR have the following meanings: | |
56 | * | |
57 | * Revision 2: Interrupt groups are guest-configurable and signaled using | |
58 | * their configured groups. | |
59 | */ | |
60 | ||
fd59ed3b AP |
61 | static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, |
62 | gpa_t addr, unsigned int len) | |
63 | { | |
aa075b0f | 64 | struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; |
fd59ed3b AP |
65 | u32 value = 0; |
66 | ||
67 | switch (addr & 0x0c) { | |
68 | case GICD_CTLR: | |
aa075b0f | 69 | if (vgic->enabled) |
fd59ed3b AP |
70 | value |= GICD_CTLR_ENABLE_SS_G1; |
71 | value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; | |
72 | break; | |
73 | case GICD_TYPER: | |
aa075b0f | 74 | value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS; |
fd59ed3b | 75 | value = (value >> 5) - 1; |
0e4e82f1 AP |
76 | if (vgic_has_its(vcpu->kvm)) { |
77 | value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; | |
78 | value |= GICD_TYPER_LPIS; | |
79 | } else { | |
80 | value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; | |
81 | } | |
fd59ed3b AP |
82 | break; |
83 | case GICD_IIDR: | |
a2dca217 | 84 | value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | |
aa075b0f | 85 | (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) | |
a2dca217 | 86 | (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); |
fd59ed3b AP |
87 | break; |
88 | default: | |
89 | return 0; | |
90 | } | |
91 | ||
92 | return value; | |
93 | } | |
94 | ||
95 | static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, | |
96 | gpa_t addr, unsigned int len, | |
97 | unsigned long val) | |
98 | { | |
99 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
100 | bool was_enabled = dist->enabled; | |
101 | ||
102 | switch (addr & 0x0c) { | |
103 | case GICD_CTLR: | |
104 | dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; | |
105 | ||
106 | if (!was_enabled && dist->enabled) | |
107 | vgic_kick_vcpus(vcpu->kvm); | |
108 | break; | |
109 | case GICD_TYPER: | |
110 | case GICD_IIDR: | |
111 | return; | |
112 | } | |
113 | } | |
114 | ||
b489edc3 CD |
115 | static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, |
116 | gpa_t addr, unsigned int len, | |
117 | unsigned long val) | |
118 | { | |
119 | switch (addr & 0x0c) { | |
120 | case GICD_IIDR: | |
121 | if (val != vgic_mmio_read_v3_misc(vcpu, addr, len)) | |
122 | return -EINVAL; | |
123 | } | |
124 | ||
125 | vgic_mmio_write_v3_misc(vcpu, addr, len, val); | |
126 | return 0; | |
127 | } | |
128 | ||
78a714ab AP |
129 | static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu, |
130 | gpa_t addr, unsigned int len) | |
131 | { | |
132 | int intid = VGIC_ADDR_TO_INTID(addr, 64); | |
133 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid); | |
5dd4b924 | 134 | unsigned long ret = 0; |
78a714ab AP |
135 | |
136 | if (!irq) | |
137 | return 0; | |
138 | ||
139 | /* The upper word is RAZ for us. */ | |
5dd4b924 AP |
140 | if (!(addr & 4)) |
141 | ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); | |
78a714ab | 142 | |
5dd4b924 AP |
143 | vgic_put_irq(vcpu->kvm, irq); |
144 | return ret; | |
78a714ab AP |
145 | } |
146 | ||
147 | static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, | |
148 | gpa_t addr, unsigned int len, | |
149 | unsigned long val) | |
150 | { | |
151 | int intid = VGIC_ADDR_TO_INTID(addr, 64); | |
5dd4b924 | 152 | struct vgic_irq *irq; |
006df0f3 | 153 | unsigned long flags; |
78a714ab AP |
154 | |
155 | /* The upper word is WI for us since we don't implement Aff3. */ | |
156 | if (addr & 4) | |
157 | return; | |
158 | ||
5dd4b924 AP |
159 | irq = vgic_get_irq(vcpu->kvm, NULL, intid); |
160 | ||
161 | if (!irq) | |
162 | return; | |
163 | ||
8fa3adb8 | 164 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
78a714ab AP |
165 | |
166 | /* We only care about and preserve Aff0, Aff1 and Aff2. */ | |
167 | irq->mpidr = val & GENMASK(23, 0); | |
168 | irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); | |
169 | ||
8fa3adb8 | 170 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
5dd4b924 | 171 | vgic_put_irq(vcpu->kvm, irq); |
78a714ab AP |
172 | } |
173 | ||
59c5ab40 AP |
174 | static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu, |
175 | gpa_t addr, unsigned int len) | |
176 | { | |
177 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
178 | ||
179 | return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0; | |
180 | } | |
181 | ||
182 | ||
183 | static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, | |
184 | gpa_t addr, unsigned int len, | |
185 | unsigned long val) | |
186 | { | |
187 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
188 | bool was_enabled = vgic_cpu->lpis_enabled; | |
189 | ||
190 | if (!vgic_has_its(vcpu->kvm)) | |
191 | return; | |
192 | ||
193 | vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS; | |
194 | ||
96085b94 MZ |
195 | if (was_enabled && !vgic_cpu->lpis_enabled) |
196 | vgic_flush_pending_lpis(vcpu); | |
197 | ||
0e4e82f1 AP |
198 | if (!was_enabled && vgic_cpu->lpis_enabled) |
199 | vgic_enable_lpis(vcpu); | |
59c5ab40 AP |
200 | } |
201 | ||
741972d8 AP |
202 | static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, |
203 | gpa_t addr, unsigned int len) | |
204 | { | |
205 | unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); | |
ba7b3f12 EA |
206 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
207 | struct vgic_redist_region *rdreg = vgic_cpu->rdreg; | |
741972d8 | 208 | int target_vcpu_id = vcpu->vcpu_id; |
ba7b3f12 EA |
209 | gpa_t last_rdist_typer = rdreg->base + GICR_TYPER + |
210 | (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE; | |
741972d8 AP |
211 | u64 value; |
212 | ||
e533a37f | 213 | value = (u64)(mpidr & GENMASK(23, 0)) << 32; |
741972d8 | 214 | value |= ((target_vcpu_id & 0xffff) << 8); |
ba7b3f12 EA |
215 | |
216 | if (addr == last_rdist_typer) | |
741972d8 | 217 | value |= GICR_TYPER_LAST; |
0e4e82f1 AP |
218 | if (vgic_has_its(vcpu->kvm)) |
219 | value |= GICR_TYPER_PLPIS; | |
741972d8 AP |
220 | |
221 | return extract_bytes(value, addr & 7, len); | |
222 | } | |
223 | ||
224 | static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu, | |
225 | gpa_t addr, unsigned int len) | |
226 | { | |
227 | return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
228 | } | |
229 | ||
54f59d2b AP |
230 | static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, |
231 | gpa_t addr, unsigned int len) | |
232 | { | |
233 | switch (addr & 0xffff) { | |
234 | case GICD_PIDR2: | |
235 | /* report a GICv3 compliant implementation */ | |
236 | return 0x3b; | |
237 | } | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
2df903a8 VK |
242 | static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu, |
243 | gpa_t addr, unsigned int len) | |
244 | { | |
245 | u32 intid = VGIC_ADDR_TO_INTID(addr, 1); | |
246 | u32 value = 0; | |
247 | int i; | |
248 | ||
249 | /* | |
250 | * pending state of interrupt is latched in pending_latch variable. | |
251 | * Userspace will save and restore pending state and line_level | |
252 | * separately. | |
253 | * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt | |
254 | * for handling of ISPENDR and ICPENDR. | |
255 | */ | |
256 | for (i = 0; i < len * 8; i++) { | |
257 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
258 | ||
259 | if (irq->pending_latch) | |
260 | value |= (1U << i); | |
261 | ||
262 | vgic_put_irq(vcpu->kvm, irq); | |
263 | } | |
264 | ||
265 | return value; | |
266 | } | |
267 | ||
c6e0917b CD |
268 | static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, |
269 | gpa_t addr, unsigned int len, | |
270 | unsigned long val) | |
2df903a8 VK |
271 | { |
272 | u32 intid = VGIC_ADDR_TO_INTID(addr, 1); | |
273 | int i; | |
006df0f3 | 274 | unsigned long flags; |
2df903a8 VK |
275 | |
276 | for (i = 0; i < len * 8; i++) { | |
277 | struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); | |
278 | ||
8fa3adb8 | 279 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
2df903a8 VK |
280 | if (test_bit(i, &val)) { |
281 | /* | |
282 | * pending_latch is set irrespective of irq type | |
283 | * (level or edge) to avoid dependency that VM should | |
284 | * restore irq config before pending info. | |
285 | */ | |
286 | irq->pending_latch = true; | |
006df0f3 | 287 | vgic_queue_irq_unlock(vcpu->kvm, irq, flags); |
2df903a8 VK |
288 | } else { |
289 | irq->pending_latch = false; | |
8fa3adb8 | 290 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
2df903a8 VK |
291 | } |
292 | ||
293 | vgic_put_irq(vcpu->kvm, irq); | |
294 | } | |
c6e0917b CD |
295 | |
296 | return 0; | |
2df903a8 VK |
297 | } |
298 | ||
0aa1de57 AP |
299 | /* We want to avoid outer shareable. */ |
300 | u64 vgic_sanitise_shareability(u64 field) | |
301 | { | |
302 | switch (field) { | |
303 | case GIC_BASER_OuterShareable: | |
304 | return GIC_BASER_InnerShareable; | |
305 | default: | |
306 | return field; | |
307 | } | |
308 | } | |
309 | ||
310 | /* Avoid any inner non-cacheable mapping. */ | |
311 | u64 vgic_sanitise_inner_cacheability(u64 field) | |
312 | { | |
313 | switch (field) { | |
314 | case GIC_BASER_CACHE_nCnB: | |
315 | case GIC_BASER_CACHE_nC: | |
316 | return GIC_BASER_CACHE_RaWb; | |
317 | default: | |
318 | return field; | |
319 | } | |
320 | } | |
321 | ||
322 | /* Non-cacheable or same-as-inner are OK. */ | |
323 | u64 vgic_sanitise_outer_cacheability(u64 field) | |
324 | { | |
325 | switch (field) { | |
326 | case GIC_BASER_CACHE_SameAsInner: | |
327 | case GIC_BASER_CACHE_nC: | |
328 | return field; | |
329 | default: | |
330 | return GIC_BASER_CACHE_nC; | |
331 | } | |
332 | } | |
333 | ||
334 | u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, | |
335 | u64 (*sanitise_fn)(u64)) | |
336 | { | |
337 | u64 field = (reg & field_mask) >> field_shift; | |
338 | ||
339 | field = sanitise_fn(field) << field_shift; | |
340 | return (reg & ~field_mask) | field; | |
341 | } | |
342 | ||
343 | #define PROPBASER_RES0_MASK \ | |
344 | (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) | |
345 | #define PENDBASER_RES0_MASK \ | |
346 | (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ | |
347 | GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) | |
348 | ||
349 | static u64 vgic_sanitise_pendbaser(u64 reg) | |
350 | { | |
351 | reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, | |
352 | GICR_PENDBASER_SHAREABILITY_SHIFT, | |
353 | vgic_sanitise_shareability); | |
354 | reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, | |
355 | GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, | |
356 | vgic_sanitise_inner_cacheability); | |
357 | reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, | |
358 | GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, | |
359 | vgic_sanitise_outer_cacheability); | |
360 | ||
361 | reg &= ~PENDBASER_RES0_MASK; | |
0aa1de57 AP |
362 | |
363 | return reg; | |
364 | } | |
365 | ||
366 | static u64 vgic_sanitise_propbaser(u64 reg) | |
367 | { | |
368 | reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, | |
369 | GICR_PROPBASER_SHAREABILITY_SHIFT, | |
370 | vgic_sanitise_shareability); | |
371 | reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, | |
372 | GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, | |
373 | vgic_sanitise_inner_cacheability); | |
374 | reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, | |
375 | GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, | |
376 | vgic_sanitise_outer_cacheability); | |
377 | ||
378 | reg &= ~PROPBASER_RES0_MASK; | |
0aa1de57 AP |
379 | return reg; |
380 | } | |
381 | ||
382 | static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, | |
383 | gpa_t addr, unsigned int len) | |
384 | { | |
385 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
386 | ||
387 | return extract_bytes(dist->propbaser, addr & 7, len); | |
388 | } | |
389 | ||
390 | static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, | |
391 | gpa_t addr, unsigned int len, | |
392 | unsigned long val) | |
393 | { | |
394 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
395 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
d9ae449b | 396 | u64 old_propbaser, propbaser; |
0aa1de57 AP |
397 | |
398 | /* Storing a value with LPIs already enabled is undefined */ | |
399 | if (vgic_cpu->lpis_enabled) | |
400 | return; | |
401 | ||
d9ae449b | 402 | do { |
3af4e414 | 403 | old_propbaser = READ_ONCE(dist->propbaser); |
d9ae449b CD |
404 | propbaser = old_propbaser; |
405 | propbaser = update_64bit_reg(propbaser, addr & 4, len, val); | |
406 | propbaser = vgic_sanitise_propbaser(propbaser); | |
407 | } while (cmpxchg64(&dist->propbaser, old_propbaser, | |
408 | propbaser) != old_propbaser); | |
0aa1de57 AP |
409 | } |
410 | ||
411 | static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, | |
412 | gpa_t addr, unsigned int len) | |
413 | { | |
414 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
415 | ||
416 | return extract_bytes(vgic_cpu->pendbaser, addr & 7, len); | |
417 | } | |
418 | ||
419 | static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, | |
420 | gpa_t addr, unsigned int len, | |
421 | unsigned long val) | |
422 | { | |
423 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
d9ae449b | 424 | u64 old_pendbaser, pendbaser; |
0aa1de57 AP |
425 | |
426 | /* Storing a value with LPIs already enabled is undefined */ | |
427 | if (vgic_cpu->lpis_enabled) | |
428 | return; | |
429 | ||
d9ae449b | 430 | do { |
3af4e414 | 431 | old_pendbaser = READ_ONCE(vgic_cpu->pendbaser); |
d9ae449b CD |
432 | pendbaser = old_pendbaser; |
433 | pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); | |
434 | pendbaser = vgic_sanitise_pendbaser(pendbaser); | |
435 | } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, | |
436 | pendbaser) != old_pendbaser); | |
0aa1de57 AP |
437 | } |
438 | ||
ed9b8cef AP |
439 | /* |
440 | * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the | |
441 | * redistributors, while SPIs are covered by registers in the distributor | |
442 | * block. Trying to set private IRQs in this block gets ignored. | |
443 | * We take some special care here to fix the calculation of the register | |
444 | * offset. | |
445 | */ | |
2df903a8 | 446 | #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \ |
ed9b8cef AP |
447 | { \ |
448 | .reg_offset = off, \ | |
449 | .bits_per_irq = bpi, \ | |
450 | .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ | |
451 | .access_flags = acc, \ | |
452 | .read = vgic_mmio_read_raz, \ | |
453 | .write = vgic_mmio_write_wi, \ | |
454 | }, { \ | |
455 | .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ | |
456 | .bits_per_irq = bpi, \ | |
457 | .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \ | |
458 | .access_flags = acc, \ | |
459 | .read = rd, \ | |
460 | .write = wr, \ | |
2df903a8 VK |
461 | .uaccess_read = ur, \ |
462 | .uaccess_write = uw, \ | |
ed9b8cef AP |
463 | } |
464 | ||
465 | static const struct vgic_register_region vgic_v3_dist_registers[] = { | |
b489edc3 CD |
466 | REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR, |
467 | vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, | |
468 | NULL, vgic_mmio_uaccess_write_v3_misc, | |
469 | 16, VGIC_ACCESS_32bit), | |
94574c94 VK |
470 | REGISTER_DESC_WITH_LENGTH(GICD_STATUSR, |
471 | vgic_mmio_read_rao, vgic_mmio_write_wi, 4, | |
472 | VGIC_ACCESS_32bit), | |
ed9b8cef | 473 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR, |
d53c2c29 | 474 | vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1, |
ed9b8cef AP |
475 | VGIC_ACCESS_32bit), |
476 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER, | |
2df903a8 | 477 | vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1, |
ed9b8cef AP |
478 | VGIC_ACCESS_32bit), |
479 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER, | |
2df903a8 | 480 | vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1, |
ed9b8cef AP |
481 | VGIC_ACCESS_32bit), |
482 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR, | |
2df903a8 VK |
483 | vgic_mmio_read_pending, vgic_mmio_write_spending, |
484 | vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1, | |
ed9b8cef AP |
485 | VGIC_ACCESS_32bit), |
486 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR, | |
2df903a8 | 487 | vgic_mmio_read_pending, vgic_mmio_write_cpending, |
c6e0917b | 488 | vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1, |
ed9b8cef AP |
489 | VGIC_ACCESS_32bit), |
490 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER, | |
3197191e CD |
491 | vgic_mmio_read_active, vgic_mmio_write_sactive, |
492 | NULL, vgic_mmio_uaccess_write_sactive, 1, | |
ed9b8cef AP |
493 | VGIC_ACCESS_32bit), |
494 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER, | |
3197191e CD |
495 | vgic_mmio_read_active, vgic_mmio_write_cactive, |
496 | NULL, vgic_mmio_uaccess_write_cactive, | |
497 | 1, VGIC_ACCESS_32bit), | |
ed9b8cef | 498 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR, |
2df903a8 VK |
499 | vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, |
500 | 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), | |
ed9b8cef | 501 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR, |
2df903a8 | 502 | vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, |
ed9b8cef AP |
503 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), |
504 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR, | |
2df903a8 | 505 | vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, |
ed9b8cef AP |
506 | VGIC_ACCESS_32bit), |
507 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR, | |
2df903a8 | 508 | vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, |
ed9b8cef AP |
509 | VGIC_ACCESS_32bit), |
510 | REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER, | |
2df903a8 | 511 | vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64, |
ed9b8cef AP |
512 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
513 | REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, | |
54f59d2b | 514 | vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, |
ed9b8cef AP |
515 | VGIC_ACCESS_32bit), |
516 | }; | |
517 | ||
518 | static const struct vgic_register_region vgic_v3_rdbase_registers[] = { | |
519 | REGISTER_DESC_WITH_LENGTH(GICR_CTLR, | |
59c5ab40 | 520 | vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4, |
ed9b8cef | 521 | VGIC_ACCESS_32bit), |
94574c94 VK |
522 | REGISTER_DESC_WITH_LENGTH(GICR_STATUSR, |
523 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, | |
524 | VGIC_ACCESS_32bit), | |
ed9b8cef | 525 | REGISTER_DESC_WITH_LENGTH(GICR_IIDR, |
741972d8 | 526 | vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4, |
ed9b8cef AP |
527 | VGIC_ACCESS_32bit), |
528 | REGISTER_DESC_WITH_LENGTH(GICR_TYPER, | |
741972d8 | 529 | vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8, |
ed9b8cef | 530 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
94574c94 VK |
531 | REGISTER_DESC_WITH_LENGTH(GICR_WAKER, |
532 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, | |
533 | VGIC_ACCESS_32bit), | |
ed9b8cef | 534 | REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, |
0aa1de57 | 535 | vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, |
ed9b8cef AP |
536 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
537 | REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, | |
0aa1de57 | 538 | vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, |
ed9b8cef AP |
539 | VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), |
540 | REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, | |
54f59d2b | 541 | vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, |
ed9b8cef AP |
542 | VGIC_ACCESS_32bit), |
543 | }; | |
544 | ||
545 | static const struct vgic_register_region vgic_v3_sgibase_registers[] = { | |
546 | REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0, | |
d53c2c29 | 547 | vgic_mmio_read_group, vgic_mmio_write_group, 4, |
ed9b8cef AP |
548 | VGIC_ACCESS_32bit), |
549 | REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0, | |
550 | vgic_mmio_read_enable, vgic_mmio_write_senable, 4, | |
551 | VGIC_ACCESS_32bit), | |
552 | REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0, | |
553 | vgic_mmio_read_enable, vgic_mmio_write_cenable, 4, | |
554 | VGIC_ACCESS_32bit), | |
2df903a8 VK |
555 | REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0, |
556 | vgic_mmio_read_pending, vgic_mmio_write_spending, | |
557 | vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4, | |
ed9b8cef | 558 | VGIC_ACCESS_32bit), |
2df903a8 VK |
559 | REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0, |
560 | vgic_mmio_read_pending, vgic_mmio_write_cpending, | |
c6e0917b | 561 | vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4, |
ed9b8cef | 562 | VGIC_ACCESS_32bit), |
0710f9a6 CD |
563 | REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISACTIVER0, |
564 | vgic_mmio_read_active, vgic_mmio_write_sactive, | |
565 | NULL, vgic_mmio_uaccess_write_sactive, | |
566 | 4, VGIC_ACCESS_32bit), | |
567 | REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICACTIVER0, | |
568 | vgic_mmio_read_active, vgic_mmio_write_cactive, | |
569 | NULL, vgic_mmio_uaccess_write_cactive, | |
570 | 4, VGIC_ACCESS_32bit), | |
ed9b8cef AP |
571 | REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0, |
572 | vgic_mmio_read_priority, vgic_mmio_write_priority, 32, | |
573 | VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), | |
574 | REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0, | |
575 | vgic_mmio_read_config, vgic_mmio_write_config, 8, | |
576 | VGIC_ACCESS_32bit), | |
577 | REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0, | |
578 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, | |
579 | VGIC_ACCESS_32bit), | |
580 | REGISTER_DESC_WITH_LENGTH(GICR_NSACR, | |
581 | vgic_mmio_read_raz, vgic_mmio_write_wi, 4, | |
582 | VGIC_ACCESS_32bit), | |
583 | }; | |
584 | ||
585 | unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev) | |
586 | { | |
587 | dev->regions = vgic_v3_dist_registers; | |
588 | dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); | |
589 | ||
590 | kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); | |
591 | ||
592 | return SZ_64K; | |
593 | } | |
594 | ||
7fadcd3a CD |
595 | /** |
596 | * vgic_register_redist_iodev - register a single redist iodev | |
597 | * @vcpu: The VCPU to which the redistributor belongs | |
598 | * | |
599 | * Register a KVM iodev for this VCPU's redistributor using the address | |
600 | * provided. | |
601 | * | |
602 | * Return 0 on success, -ERRNO otherwise. | |
603 | */ | |
1aab6f46 | 604 | int vgic_register_redist_iodev(struct kvm_vcpu *vcpu) |
7fadcd3a CD |
605 | { |
606 | struct kvm *kvm = vcpu->kvm; | |
607 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
dbd9733a | 608 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
7fadcd3a CD |
609 | struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; |
610 | struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev; | |
dbd9733a | 611 | struct vgic_redist_region *rdreg; |
7fadcd3a CD |
612 | gpa_t rd_base, sgi_base; |
613 | int ret; | |
614 | ||
c011f4ea EA |
615 | if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) |
616 | return 0; | |
617 | ||
1aab6f46 CD |
618 | /* |
619 | * We may be creating VCPUs before having set the base address for the | |
620 | * redistributor region, in which case we will come back to this | |
621 | * function for all VCPUs when the base address is set. Just return | |
622 | * without doing any work for now. | |
623 | */ | |
dc524619 | 624 | rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions); |
dbd9733a | 625 | if (!rdreg) |
1aab6f46 CD |
626 | return 0; |
627 | ||
628 | if (!vgic_v3_check_base(kvm)) | |
629 | return -EINVAL; | |
630 | ||
dbd9733a EA |
631 | vgic_cpu->rdreg = rdreg; |
632 | ||
633 | rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; | |
7fadcd3a CD |
634 | sgi_base = rd_base + SZ_64K; |
635 | ||
636 | kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops); | |
637 | rd_dev->base_addr = rd_base; | |
638 | rd_dev->iodev_type = IODEV_REDIST; | |
639 | rd_dev->regions = vgic_v3_rdbase_registers; | |
640 | rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers); | |
641 | rd_dev->redist_vcpu = vcpu; | |
642 | ||
643 | mutex_lock(&kvm->slots_lock); | |
644 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base, | |
645 | SZ_64K, &rd_dev->dev); | |
646 | mutex_unlock(&kvm->slots_lock); | |
647 | ||
648 | if (ret) | |
649 | return ret; | |
650 | ||
651 | kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops); | |
652 | sgi_dev->base_addr = sgi_base; | |
653 | sgi_dev->iodev_type = IODEV_REDIST; | |
654 | sgi_dev->regions = vgic_v3_sgibase_registers; | |
655 | sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers); | |
656 | sgi_dev->redist_vcpu = vcpu; | |
657 | ||
658 | mutex_lock(&kvm->slots_lock); | |
659 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base, | |
660 | SZ_64K, &sgi_dev->dev); | |
552c9f47 | 661 | if (ret) { |
7fadcd3a CD |
662 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, |
663 | &rd_dev->dev); | |
fa472fa9 | 664 | goto out; |
552c9f47 | 665 | } |
7fadcd3a | 666 | |
dbd9733a | 667 | rdreg->free_index++; |
fa472fa9 CD |
668 | out: |
669 | mutex_unlock(&kvm->slots_lock); | |
7fadcd3a CD |
670 | return ret; |
671 | } | |
672 | ||
673 | static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu) | |
674 | { | |
675 | struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; | |
676 | struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev; | |
677 | ||
678 | kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev); | |
679 | kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &sgi_dev->dev); | |
680 | } | |
681 | ||
1aab6f46 | 682 | static int vgic_register_all_redist_iodevs(struct kvm *kvm) |
ed9b8cef | 683 | { |
ed9b8cef | 684 | struct kvm_vcpu *vcpu; |
ed9b8cef AP |
685 | int c, ret = 0; |
686 | ||
ed9b8cef | 687 | kvm_for_each_vcpu(c, vcpu, kvm) { |
7fadcd3a | 688 | ret = vgic_register_redist_iodev(vcpu); |
ed9b8cef AP |
689 | if (ret) |
690 | break; | |
ed9b8cef AP |
691 | } |
692 | ||
693 | if (ret) { | |
694 | /* The current c failed, so we start with the previous one. */ | |
fa472fa9 | 695 | mutex_lock(&kvm->slots_lock); |
ed9b8cef | 696 | for (c--; c >= 0; c--) { |
8f6cdc1c | 697 | vcpu = kvm_get_vcpu(kvm, c); |
7fadcd3a | 698 | vgic_unregister_redist_iodev(vcpu); |
ed9b8cef | 699 | } |
fa472fa9 | 700 | mutex_unlock(&kvm->slots_lock); |
ed9b8cef AP |
701 | } |
702 | ||
703 | return ret; | |
704 | } | |
621ecd8d | 705 | |
ccc27bf5 EA |
706 | /** |
707 | * vgic_v3_insert_redist_region - Insert a new redistributor region | |
708 | * | |
709 | * Performs various checks before inserting the rdist region in the list. | |
710 | * Those tests depend on whether the size of the rdist region is known | |
711 | * (ie. count != 0). The list is sorted by rdist region index. | |
712 | * | |
713 | * @kvm: kvm handle | |
714 | * @index: redist region index | |
715 | * @base: base of the new rdist region | |
716 | * @count: number of redistributors the region is made of (0 in the old style | |
717 | * single region, whose size is induced from the number of vcpus) | |
718 | * | |
719 | * Return 0 on success, < 0 otherwise | |
720 | */ | |
721 | static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index, | |
722 | gpa_t base, uint32_t count) | |
1aab6f46 | 723 | { |
ccc27bf5 | 724 | struct vgic_dist *d = &kvm->arch.vgic; |
dbd9733a | 725 | struct vgic_redist_region *rdreg; |
ccc27bf5 EA |
726 | struct list_head *rd_regions = &d->rd_regions; |
727 | size_t size = count * KVM_VGIC_V3_REDIST_SIZE; | |
1aab6f46 CD |
728 | int ret; |
729 | ||
ccc27bf5 EA |
730 | /* single rdist region already set ?*/ |
731 | if (!count && !list_empty(rd_regions)) | |
732 | return -EINVAL; | |
733 | ||
734 | /* cross the end of memory ? */ | |
735 | if (base + size < base) | |
736 | return -EINVAL; | |
737 | ||
738 | if (list_empty(rd_regions)) { | |
739 | if (index != 0) | |
740 | return -EINVAL; | |
741 | } else { | |
742 | rdreg = list_last_entry(rd_regions, | |
743 | struct vgic_redist_region, list); | |
744 | if (index != rdreg->index + 1) | |
745 | return -EINVAL; | |
746 | ||
747 | /* Cannot add an explicitly sized regions after legacy region */ | |
748 | if (!rdreg->count) | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | /* | |
753 | * For legacy single-region redistributor regions (!count), | |
754 | * check that the redistributor region does not overlap with the | |
755 | * distributor's address space. | |
756 | */ | |
757 | if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && | |
758 | vgic_dist_overlap(kvm, base, size)) | |
759 | return -EINVAL; | |
760 | ||
761 | /* collision with any other rdist region? */ | |
762 | if (vgic_v3_rdist_overlap(kvm, base, size)) | |
dbd9733a EA |
763 | return -EINVAL; |
764 | ||
765 | rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL); | |
766 | if (!rdreg) | |
767 | return -ENOMEM; | |
768 | ||
769 | rdreg->base = VGIC_ADDR_UNDEF; | |
770 | ||
ccc27bf5 | 771 | ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K); |
1aab6f46 | 772 | if (ret) |
ccc27bf5 | 773 | goto free; |
1aab6f46 | 774 | |
ccc27bf5 EA |
775 | rdreg->base = base; |
776 | rdreg->count = count; | |
777 | rdreg->free_index = 0; | |
778 | rdreg->index = index; | |
1aab6f46 | 779 | |
ccc27bf5 EA |
780 | list_add_tail(&rdreg->list, rd_regions); |
781 | return 0; | |
782 | free: | |
783 | kfree(rdreg); | |
784 | return ret; | |
785 | } | |
786 | ||
04c11093 | 787 | int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count) |
ccc27bf5 EA |
788 | { |
789 | int ret; | |
790 | ||
04c11093 | 791 | ret = vgic_v3_insert_redist_region(kvm, index, addr, count); |
ccc27bf5 EA |
792 | if (ret) |
793 | return ret; | |
dbd9733a | 794 | |
1aab6f46 CD |
795 | /* |
796 | * Register iodevs for each existing VCPU. Adding more VCPUs | |
797 | * afterwards will register the iodevs when needed. | |
798 | */ | |
799 | ret = vgic_register_all_redist_iodevs(kvm); | |
800 | if (ret) | |
801 | return ret; | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
94574c94 VK |
806 | int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) |
807 | { | |
808 | const struct vgic_register_region *region; | |
809 | struct vgic_io_device iodev; | |
810 | struct vgic_reg_attr reg_attr; | |
811 | struct kvm_vcpu *vcpu; | |
812 | gpa_t addr; | |
813 | int ret; | |
814 | ||
815 | ret = vgic_v3_parse_attr(dev, attr, ®_attr); | |
816 | if (ret) | |
817 | return ret; | |
818 | ||
819 | vcpu = reg_attr.vcpu; | |
820 | addr = reg_attr.addr; | |
821 | ||
822 | switch (attr->group) { | |
823 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
824 | iodev.regions = vgic_v3_dist_registers; | |
825 | iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); | |
826 | iodev.base_addr = 0; | |
827 | break; | |
828 | case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{ | |
829 | iodev.regions = vgic_v3_rdbase_registers; | |
830 | iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers); | |
831 | iodev.base_addr = 0; | |
832 | break; | |
833 | } | |
d017d7b0 VK |
834 | case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: { |
835 | u64 reg, id; | |
836 | ||
837 | id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK); | |
838 | return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®); | |
839 | } | |
94574c94 VK |
840 | default: |
841 | return -ENXIO; | |
842 | } | |
843 | ||
844 | /* We only support aligned 32-bit accesses. */ | |
845 | if (addr & 3) | |
846 | return -ENXIO; | |
847 | ||
848 | region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); | |
849 | if (!region) | |
850 | return -ENXIO; | |
851 | ||
852 | return 0; | |
853 | } | |
621ecd8d AP |
854 | /* |
855 | * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI | |
856 | * generation register ICC_SGI1R_EL1) with a given VCPU. | |
857 | * If the VCPU's MPIDR matches, return the level0 affinity, otherwise | |
858 | * return -1. | |
859 | */ | |
860 | static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu) | |
861 | { | |
862 | unsigned long affinity; | |
863 | int level0; | |
864 | ||
865 | /* | |
866 | * Split the current VCPU's MPIDR into affinity level 0 and the | |
867 | * rest as this is what we have to compare against. | |
868 | */ | |
869 | affinity = kvm_vcpu_get_mpidr_aff(vcpu); | |
870 | level0 = MPIDR_AFFINITY_LEVEL(affinity, 0); | |
871 | affinity &= ~MPIDR_LEVEL_MASK; | |
872 | ||
873 | /* bail out if the upper three levels don't match */ | |
874 | if (sgi_aff != affinity) | |
875 | return -1; | |
876 | ||
877 | /* Is this VCPU's bit set in the mask ? */ | |
878 | if (!(sgi_cpu_mask & BIT(level0))) | |
879 | return -1; | |
880 | ||
881 | return level0; | |
882 | } | |
883 | ||
884 | /* | |
885 | * The ICC_SGI* registers encode the affinity differently from the MPIDR, | |
886 | * so provide a wrapper to use the existing defines to isolate a certain | |
887 | * affinity level. | |
888 | */ | |
889 | #define SGI_AFFINITY_LEVEL(reg, level) \ | |
890 | ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ | |
891 | >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) | |
892 | ||
893 | /** | |
894 | * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs | |
895 | * @vcpu: The VCPU requesting a SGI | |
6249f2a4 MZ |
896 | * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU |
897 | * @allow_group1: Does the sysreg access allow generation of G1 SGIs | |
621ecd8d AP |
898 | * |
899 | * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register. | |
900 | * This will trap in sys_regs.c and call this function. | |
901 | * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the | |
902 | * target processors as well as a bitmask of 16 Aff0 CPUs. | |
903 | * If the interrupt routing mode bit is not set, we iterate over all VCPUs to | |
904 | * check for matching ones. If this bit is set, we signal all, but not the | |
905 | * calling VCPU. | |
906 | */ | |
6249f2a4 | 907 | void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) |
621ecd8d AP |
908 | { |
909 | struct kvm *kvm = vcpu->kvm; | |
910 | struct kvm_vcpu *c_vcpu; | |
911 | u16 target_cpus; | |
912 | u64 mpidr; | |
913 | int sgi, c; | |
914 | int vcpu_id = vcpu->vcpu_id; | |
915 | bool broadcast; | |
006df0f3 | 916 | unsigned long flags; |
621ecd8d AP |
917 | |
918 | sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT; | |
e533a37f | 919 | broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT); |
621ecd8d AP |
920 | target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT; |
921 | mpidr = SGI_AFFINITY_LEVEL(reg, 3); | |
922 | mpidr |= SGI_AFFINITY_LEVEL(reg, 2); | |
923 | mpidr |= SGI_AFFINITY_LEVEL(reg, 1); | |
924 | ||
925 | /* | |
926 | * We iterate over all VCPUs to find the MPIDRs matching the request. | |
927 | * If we have handled one CPU, we clear its bit to detect early | |
928 | * if we are already finished. This avoids iterating through all | |
929 | * VCPUs when most of the times we just signal a single VCPU. | |
930 | */ | |
931 | kvm_for_each_vcpu(c, c_vcpu, kvm) { | |
932 | struct vgic_irq *irq; | |
933 | ||
934 | /* Exit early if we have dealt with all requested CPUs */ | |
935 | if (!broadcast && target_cpus == 0) | |
936 | break; | |
937 | ||
938 | /* Don't signal the calling VCPU */ | |
939 | if (broadcast && c == vcpu_id) | |
940 | continue; | |
941 | ||
942 | if (!broadcast) { | |
943 | int level0; | |
944 | ||
945 | level0 = match_mpidr(mpidr, target_cpus, c_vcpu); | |
946 | if (level0 == -1) | |
947 | continue; | |
948 | ||
949 | /* remove this matching VCPU from the mask */ | |
950 | target_cpus &= ~BIT(level0); | |
951 | } | |
952 | ||
953 | irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi); | |
954 | ||
8fa3adb8 | 955 | raw_spin_lock_irqsave(&irq->irq_lock, flags); |
621ecd8d | 956 | |
6249f2a4 MZ |
957 | /* |
958 | * An access targetting Group0 SGIs can only generate | |
959 | * those, while an access targetting Group1 SGIs can | |
960 | * generate interrupts of either group. | |
961 | */ | |
962 | if (!irq->group || allow_group1) { | |
963 | irq->pending_latch = true; | |
964 | vgic_queue_irq_unlock(vcpu->kvm, irq, flags); | |
965 | } else { | |
8fa3adb8 | 966 | raw_spin_unlock_irqrestore(&irq->irq_lock, flags); |
6249f2a4 MZ |
967 | } |
968 | ||
5dd4b924 | 969 | vgic_put_irq(vcpu->kvm, irq); |
621ecd8d AP |
970 | } |
971 | } | |
94574c94 VK |
972 | |
973 | int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, | |
974 | int offset, u32 *val) | |
975 | { | |
976 | struct vgic_io_device dev = { | |
977 | .regions = vgic_v3_dist_registers, | |
978 | .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers), | |
979 | }; | |
980 | ||
981 | return vgic_uaccess(vcpu, &dev, is_write, offset, val); | |
982 | } | |
983 | ||
984 | int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, | |
985 | int offset, u32 *val) | |
986 | { | |
987 | struct vgic_io_device rd_dev = { | |
988 | .regions = vgic_v3_rdbase_registers, | |
989 | .nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers), | |
990 | }; | |
991 | ||
992 | struct vgic_io_device sgi_dev = { | |
993 | .regions = vgic_v3_sgibase_registers, | |
994 | .nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers), | |
995 | }; | |
996 | ||
997 | /* SGI_base is the next 64K frame after RD_base */ | |
998 | if (offset >= SZ_64K) | |
999 | return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K, | |
1000 | val); | |
1001 | else | |
1002 | return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); | |
1003 | } | |
e96a006c VK |
1004 | |
1005 | int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, | |
1006 | u32 intid, u64 *val) | |
1007 | { | |
1008 | if (intid % 32) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | if (is_write) | |
1012 | vgic_write_irq_line_level_info(vcpu, intid, *val); | |
1013 | else | |
1014 | *val = vgic_read_irq_line_level_info(vcpu, intid); | |
1015 | ||
1016 | return 0; | |
1017 | } |