arm64: KVM: Annotate guest entry/exit as a single function
[linux-block.git] / virt / kvm / arm / mmu.c
CommitLineData
d94d71cb 1// SPDX-License-Identifier: GPL-2.0-only
749cf76c
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2/*
3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
4 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
749cf76c 5 */
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6
7#include <linux/mman.h>
8#include <linux/kvm_host.h>
9#include <linux/io.h>
ad361f09 10#include <linux/hugetlb.h>
196f878a 11#include <linux/sched/signal.h>
45e96ea6 12#include <trace/events/kvm.h>
342cd0ab 13#include <asm/pgalloc.h>
94f8e641 14#include <asm/cacheflush.h>
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15#include <asm/kvm_arm.h>
16#include <asm/kvm_mmu.h>
0db5e022 17#include <asm/kvm_ras.h>
d5d8184d 18#include <asm/kvm_asm.h>
94f8e641 19#include <asm/kvm_emulate.h>
1e947bad 20#include <asm/virt.h>
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21
22#include "trace.h"
342cd0ab 23
5a677ce0 24static pgd_t *boot_hyp_pgd;
2fb41059 25static pgd_t *hyp_pgd;
e4c5a685 26static pgd_t *merged_hyp_pgd;
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27static DEFINE_MUTEX(kvm_hyp_pgd_mutex);
28
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29static unsigned long hyp_idmap_start;
30static unsigned long hyp_idmap_end;
31static phys_addr_t hyp_idmap_vector;
32
e3f019b3
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33static unsigned long io_map_base;
34
38f791a4 35#define hyp_pgd_order get_order(PTRS_PER_PGD * sizeof(pgd_t))
5d4e08c4 36
15a49a44
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37#define KVM_S2PTE_FLAG_IS_IOMAP (1UL << 0)
38#define KVM_S2_FLAG_LOGGING_ACTIVE (1UL << 1)
39
6d674e28
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40static bool is_iomap(unsigned long flags)
41{
42 return flags & KVM_S2PTE_FLAG_IS_IOMAP;
43}
44
15a49a44
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45static bool memslot_is_logging(struct kvm_memory_slot *memslot)
46{
15a49a44 47 return memslot->dirty_bitmap && !(memslot->flags & KVM_MEM_READONLY);
7276030a
MS
48}
49
50/**
51 * kvm_flush_remote_tlbs() - flush all VM TLB entries for v7/8
52 * @kvm: pointer to kvm structure.
53 *
54 * Interface to HYP function to flush all VM TLB entries
55 */
56void kvm_flush_remote_tlbs(struct kvm *kvm)
57{
58 kvm_call_hyp(__kvm_tlb_flush_vmid, kvm);
15a49a44 59}
ad361f09 60
48762767 61static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
d5d8184d 62{
8684e701 63 kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
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64}
65
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66/*
67 * D-Cache management functions. They take the page table entries by
68 * value, as they are flushing the cache using the kernel mapping (or
69 * kmap on 32bit).
70 */
71static void kvm_flush_dcache_pte(pte_t pte)
72{
73 __kvm_flush_dcache_pte(pte);
74}
75
76static void kvm_flush_dcache_pmd(pmd_t pmd)
77{
78 __kvm_flush_dcache_pmd(pmd);
79}
80
81static void kvm_flush_dcache_pud(pud_t pud)
82{
83 __kvm_flush_dcache_pud(pud);
84}
85
e6fab544
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86static bool kvm_is_device_pfn(unsigned long pfn)
87{
88 return !pfn_valid(pfn);
89}
90
15a49a44
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91/**
92 * stage2_dissolve_pmd() - clear and flush huge PMD entry
93 * @kvm: pointer to kvm structure.
94 * @addr: IPA
95 * @pmd: pmd pointer for IPA
96 *
8324c3d5 97 * Function clears a PMD entry, flushes addr 1st and 2nd stage TLBs.
15a49a44
MS
98 */
99static void stage2_dissolve_pmd(struct kvm *kvm, phys_addr_t addr, pmd_t *pmd)
100{
bbb3b6b3 101 if (!pmd_thp_or_huge(*pmd))
15a49a44
MS
102 return;
103
104 pmd_clear(pmd);
105 kvm_tlb_flush_vmid_ipa(kvm, addr);
106 put_page(virt_to_page(pmd));
107}
108
b8e0ba7c
PA
109/**
110 * stage2_dissolve_pud() - clear and flush huge PUD entry
111 * @kvm: pointer to kvm structure.
112 * @addr: IPA
113 * @pud: pud pointer for IPA
114 *
8324c3d5 115 * Function clears a PUD entry, flushes addr 1st and 2nd stage TLBs.
b8e0ba7c
PA
116 */
117static void stage2_dissolve_pud(struct kvm *kvm, phys_addr_t addr, pud_t *pudp)
118{
119 if (!stage2_pud_huge(kvm, *pudp))
120 return;
121
122 stage2_pud_clear(kvm, pudp);
123 kvm_tlb_flush_vmid_ipa(kvm, addr);
124 put_page(virt_to_page(pudp));
125}
126
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127static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
128 int min, int max)
129{
130 void *page;
131
132 BUG_ON(max > KVM_NR_MEM_OBJS);
133 if (cache->nobjs >= min)
134 return 0;
135 while (cache->nobjs < max) {
50f11a8a 136 page = (void *)__get_free_page(GFP_PGTABLE_USER);
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137 if (!page)
138 return -ENOMEM;
139 cache->objects[cache->nobjs++] = page;
140 }
141 return 0;
142}
143
144static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
145{
146 while (mc->nobjs)
147 free_page((unsigned long)mc->objects[--mc->nobjs]);
148}
149
150static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
151{
152 void *p;
153
154 BUG_ON(!mc || !mc->nobjs);
155 p = mc->objects[--mc->nobjs];
156 return p;
157}
158
7a1c831e 159static void clear_stage2_pgd_entry(struct kvm *kvm, pgd_t *pgd, phys_addr_t addr)
979acd5e 160{
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SP
161 pud_t *pud_table __maybe_unused = stage2_pud_offset(kvm, pgd, 0UL);
162 stage2_pgd_clear(kvm, pgd);
4f853a71 163 kvm_tlb_flush_vmid_ipa(kvm, addr);
e55cac5b 164 stage2_pud_free(kvm, pud_table);
4f853a71 165 put_page(virt_to_page(pgd));
979acd5e
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166}
167
7a1c831e 168static void clear_stage2_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr)
342cd0ab 169{
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170 pmd_t *pmd_table __maybe_unused = stage2_pmd_offset(kvm, pud, 0);
171 VM_BUG_ON(stage2_pud_huge(kvm, *pud));
172 stage2_pud_clear(kvm, pud);
4f853a71 173 kvm_tlb_flush_vmid_ipa(kvm, addr);
e55cac5b 174 stage2_pmd_free(kvm, pmd_table);
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175 put_page(virt_to_page(pud));
176}
342cd0ab 177
7a1c831e 178static void clear_stage2_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
4f728276 179{
4f853a71 180 pte_t *pte_table = pte_offset_kernel(pmd, 0);
bbb3b6b3 181 VM_BUG_ON(pmd_thp_or_huge(*pmd));
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182 pmd_clear(pmd);
183 kvm_tlb_flush_vmid_ipa(kvm, addr);
14b94d07 184 free_page((unsigned long)pte_table);
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185 put_page(virt_to_page(pmd));
186}
187
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188static inline void kvm_set_pte(pte_t *ptep, pte_t new_pte)
189{
190 WRITE_ONCE(*ptep, new_pte);
191 dsb(ishst);
192}
193
194static inline void kvm_set_pmd(pmd_t *pmdp, pmd_t new_pmd)
195{
196 WRITE_ONCE(*pmdp, new_pmd);
197 dsb(ishst);
198}
199
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200static inline void kvm_pmd_populate(pmd_t *pmdp, pte_t *ptep)
201{
202 kvm_set_pmd(pmdp, kvm_mk_pmd(ptep));
203}
204
205static inline void kvm_pud_populate(pud_t *pudp, pmd_t *pmdp)
206{
207 WRITE_ONCE(*pudp, kvm_mk_pud(pmdp));
208 dsb(ishst);
209}
210
211static inline void kvm_pgd_populate(pgd_t *pgdp, pud_t *pudp)
212{
213 WRITE_ONCE(*pgdp, kvm_mk_pgd(pudp));
214 dsb(ishst);
215}
216
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217/*
218 * Unmapping vs dcache management:
219 *
220 * If a guest maps certain memory pages as uncached, all writes will
221 * bypass the data cache and go directly to RAM. However, the CPUs
222 * can still speculate reads (not writes) and fill cache lines with
223 * data.
224 *
225 * Those cache lines will be *clean* cache lines though, so a
226 * clean+invalidate operation is equivalent to an invalidate
227 * operation, because no cache lines are marked dirty.
228 *
229 * Those clean cache lines could be filled prior to an uncached write
230 * by the guest, and the cache coherent IO subsystem would therefore
231 * end up writing old data to disk.
232 *
233 * This is why right after unmapping a page/section and invalidating
234 * the corresponding TLBs, we call kvm_flush_dcache_p*() to make sure
235 * the IO subsystem will never hit in the cache.
e48d53a9
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236 *
237 * This is all avoided on systems that have ARM64_HAS_STAGE2_FWB, as
238 * we then fully enforce cacheability of RAM, no matter what the guest
239 * does.
363ef89f 240 */
7a1c831e 241static void unmap_stage2_ptes(struct kvm *kvm, pmd_t *pmd,
4f853a71 242 phys_addr_t addr, phys_addr_t end)
4f728276 243{
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244 phys_addr_t start_addr = addr;
245 pte_t *pte, *start_pte;
246
247 start_pte = pte = pte_offset_kernel(pmd, addr);
248 do {
249 if (!pte_none(*pte)) {
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250 pte_t old_pte = *pte;
251
4f853a71 252 kvm_set_pte(pte, __pte(0));
4f853a71 253 kvm_tlb_flush_vmid_ipa(kvm, addr);
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254
255 /* No need to invalidate the cache for device mappings */
0de58f85 256 if (!kvm_is_device_pfn(pte_pfn(old_pte)))
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257 kvm_flush_dcache_pte(old_pte);
258
259 put_page(virt_to_page(pte));
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260 }
261 } while (pte++, addr += PAGE_SIZE, addr != end);
262
e55cac5b 263 if (stage2_pte_table_empty(kvm, start_pte))
7a1c831e 264 clear_stage2_pmd_entry(kvm, pmd, start_addr);
342cd0ab
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265}
266
7a1c831e 267static void unmap_stage2_pmds(struct kvm *kvm, pud_t *pud,
4f853a71 268 phys_addr_t addr, phys_addr_t end)
000d3996 269{
4f853a71
CD
270 phys_addr_t next, start_addr = addr;
271 pmd_t *pmd, *start_pmd;
000d3996 272
e55cac5b 273 start_pmd = pmd = stage2_pmd_offset(kvm, pud, addr);
4f853a71 274 do {
e55cac5b 275 next = stage2_pmd_addr_end(kvm, addr, end);
4f853a71 276 if (!pmd_none(*pmd)) {
bbb3b6b3 277 if (pmd_thp_or_huge(*pmd)) {
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278 pmd_t old_pmd = *pmd;
279
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280 pmd_clear(pmd);
281 kvm_tlb_flush_vmid_ipa(kvm, addr);
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282
283 kvm_flush_dcache_pmd(old_pmd);
284
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285 put_page(virt_to_page(pmd));
286 } else {
7a1c831e 287 unmap_stage2_ptes(kvm, pmd, addr, next);
4f853a71 288 }
ad361f09 289 }
4f853a71 290 } while (pmd++, addr = next, addr != end);
ad361f09 291
e55cac5b 292 if (stage2_pmd_table_empty(kvm, start_pmd))
7a1c831e 293 clear_stage2_pud_entry(kvm, pud, start_addr);
4f853a71 294}
000d3996 295
7a1c831e 296static void unmap_stage2_puds(struct kvm *kvm, pgd_t *pgd,
4f853a71
CD
297 phys_addr_t addr, phys_addr_t end)
298{
299 phys_addr_t next, start_addr = addr;
300 pud_t *pud, *start_pud;
4f728276 301
e55cac5b 302 start_pud = pud = stage2_pud_offset(kvm, pgd, addr);
4f853a71 303 do {
e55cac5b
SP
304 next = stage2_pud_addr_end(kvm, addr, end);
305 if (!stage2_pud_none(kvm, *pud)) {
306 if (stage2_pud_huge(kvm, *pud)) {
363ef89f
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307 pud_t old_pud = *pud;
308
e55cac5b 309 stage2_pud_clear(kvm, pud);
4f853a71 310 kvm_tlb_flush_vmid_ipa(kvm, addr);
363ef89f 311 kvm_flush_dcache_pud(old_pud);
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CD
312 put_page(virt_to_page(pud));
313 } else {
7a1c831e 314 unmap_stage2_pmds(kvm, pud, addr, next);
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315 }
316 }
4f853a71 317 } while (pud++, addr = next, addr != end);
4f728276 318
e55cac5b 319 if (stage2_pud_table_empty(kvm, start_pud))
7a1c831e 320 clear_stage2_pgd_entry(kvm, pgd, start_addr);
4f853a71
CD
321}
322
7a1c831e
SP
323/**
324 * unmap_stage2_range -- Clear stage2 page table entries to unmap a range
325 * @kvm: The VM pointer
326 * @start: The intermediate physical base address of the range to unmap
327 * @size: The size of the area to unmap
328 *
329 * Clear a range of stage-2 mappings, lowering the various ref-counts. Must
330 * be called while holding mmu_lock (unless for freeing the stage2 pgd before
331 * destroying the VM), otherwise another faulting VCPU may come in and mess
332 * with things behind our backs.
333 */
334static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
4f853a71
CD
335{
336 pgd_t *pgd;
337 phys_addr_t addr = start, end = start + size;
338 phys_addr_t next;
339
8b3405e3 340 assert_spin_locked(&kvm->mmu_lock);
47a91b72
JH
341 WARN_ON(size & ~PAGE_MASK);
342
e55cac5b 343 pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr);
4f853a71 344 do {
0c428a6a
SP
345 /*
346 * Make sure the page table is still active, as another thread
347 * could have possibly freed the page table, while we released
348 * the lock.
349 */
350 if (!READ_ONCE(kvm->arch.pgd))
351 break;
e55cac5b
SP
352 next = stage2_pgd_addr_end(kvm, addr, end);
353 if (!stage2_pgd_none(kvm, *pgd))
7a1c831e 354 unmap_stage2_puds(kvm, pgd, addr, next);
8b3405e3
SP
355 /*
356 * If the range is too large, release the kvm->mmu_lock
357 * to prevent starvation and lockup detector warnings.
358 */
359 if (next != end)
360 cond_resched_lock(&kvm->mmu_lock);
4f853a71 361 } while (pgd++, addr = next, addr != end);
000d3996
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362}
363
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364static void stage2_flush_ptes(struct kvm *kvm, pmd_t *pmd,
365 phys_addr_t addr, phys_addr_t end)
366{
367 pte_t *pte;
368
369 pte = pte_offset_kernel(pmd, addr);
370 do {
0de58f85 371 if (!pte_none(*pte) && !kvm_is_device_pfn(pte_pfn(*pte)))
363ef89f 372 kvm_flush_dcache_pte(*pte);
9d218a1f
MZ
373 } while (pte++, addr += PAGE_SIZE, addr != end);
374}
375
376static void stage2_flush_pmds(struct kvm *kvm, pud_t *pud,
377 phys_addr_t addr, phys_addr_t end)
378{
379 pmd_t *pmd;
380 phys_addr_t next;
381
e55cac5b 382 pmd = stage2_pmd_offset(kvm, pud, addr);
9d218a1f 383 do {
e55cac5b 384 next = stage2_pmd_addr_end(kvm, addr, end);
9d218a1f 385 if (!pmd_none(*pmd)) {
bbb3b6b3 386 if (pmd_thp_or_huge(*pmd))
363ef89f
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387 kvm_flush_dcache_pmd(*pmd);
388 else
9d218a1f 389 stage2_flush_ptes(kvm, pmd, addr, next);
9d218a1f
MZ
390 }
391 } while (pmd++, addr = next, addr != end);
392}
393
394static void stage2_flush_puds(struct kvm *kvm, pgd_t *pgd,
395 phys_addr_t addr, phys_addr_t end)
396{
397 pud_t *pud;
398 phys_addr_t next;
399
e55cac5b 400 pud = stage2_pud_offset(kvm, pgd, addr);
9d218a1f 401 do {
e55cac5b
SP
402 next = stage2_pud_addr_end(kvm, addr, end);
403 if (!stage2_pud_none(kvm, *pud)) {
404 if (stage2_pud_huge(kvm, *pud))
363ef89f
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405 kvm_flush_dcache_pud(*pud);
406 else
9d218a1f 407 stage2_flush_pmds(kvm, pud, addr, next);
9d218a1f
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408 }
409 } while (pud++, addr = next, addr != end);
410}
411
412static void stage2_flush_memslot(struct kvm *kvm,
413 struct kvm_memory_slot *memslot)
414{
415 phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT;
416 phys_addr_t end = addr + PAGE_SIZE * memslot->npages;
417 phys_addr_t next;
418 pgd_t *pgd;
419
e55cac5b 420 pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr);
9d218a1f 421 do {
e55cac5b
SP
422 next = stage2_pgd_addr_end(kvm, addr, end);
423 if (!stage2_pgd_none(kvm, *pgd))
d2db7773 424 stage2_flush_puds(kvm, pgd, addr, next);
9d218a1f
MZ
425 } while (pgd++, addr = next, addr != end);
426}
427
428/**
429 * stage2_flush_vm - Invalidate cache for pages mapped in stage 2
430 * @kvm: The struct kvm pointer
431 *
432 * Go through the stage 2 page tables and invalidate any cache lines
433 * backing memory already mapped to the VM.
434 */
3c1e7165 435static void stage2_flush_vm(struct kvm *kvm)
9d218a1f
MZ
436{
437 struct kvm_memslots *slots;
438 struct kvm_memory_slot *memslot;
439 int idx;
440
441 idx = srcu_read_lock(&kvm->srcu);
442 spin_lock(&kvm->mmu_lock);
443
444 slots = kvm_memslots(kvm);
445 kvm_for_each_memslot(memslot, slots)
446 stage2_flush_memslot(kvm, memslot);
447
448 spin_unlock(&kvm->mmu_lock);
449 srcu_read_unlock(&kvm->srcu, idx);
450}
451
64f32497
SP
452static void clear_hyp_pgd_entry(pgd_t *pgd)
453{
454 pud_t *pud_table __maybe_unused = pud_offset(pgd, 0UL);
455 pgd_clear(pgd);
456 pud_free(NULL, pud_table);
457 put_page(virt_to_page(pgd));
458}
459
460static void clear_hyp_pud_entry(pud_t *pud)
461{
462 pmd_t *pmd_table __maybe_unused = pmd_offset(pud, 0);
463 VM_BUG_ON(pud_huge(*pud));
464 pud_clear(pud);
465 pmd_free(NULL, pmd_table);
466 put_page(virt_to_page(pud));
467}
468
469static void clear_hyp_pmd_entry(pmd_t *pmd)
470{
471 pte_t *pte_table = pte_offset_kernel(pmd, 0);
472 VM_BUG_ON(pmd_thp_or_huge(*pmd));
473 pmd_clear(pmd);
474 pte_free_kernel(NULL, pte_table);
475 put_page(virt_to_page(pmd));
476}
477
478static void unmap_hyp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end)
479{
480 pte_t *pte, *start_pte;
481
482 start_pte = pte = pte_offset_kernel(pmd, addr);
483 do {
484 if (!pte_none(*pte)) {
485 kvm_set_pte(pte, __pte(0));
486 put_page(virt_to_page(pte));
487 }
488 } while (pte++, addr += PAGE_SIZE, addr != end);
489
490 if (hyp_pte_table_empty(start_pte))
491 clear_hyp_pmd_entry(pmd);
492}
493
494static void unmap_hyp_pmds(pud_t *pud, phys_addr_t addr, phys_addr_t end)
495{
496 phys_addr_t next;
497 pmd_t *pmd, *start_pmd;
498
499 start_pmd = pmd = pmd_offset(pud, addr);
500 do {
501 next = pmd_addr_end(addr, end);
502 /* Hyp doesn't use huge pmds */
503 if (!pmd_none(*pmd))
504 unmap_hyp_ptes(pmd, addr, next);
505 } while (pmd++, addr = next, addr != end);
506
507 if (hyp_pmd_table_empty(start_pmd))
508 clear_hyp_pud_entry(pud);
509}
510
511static void unmap_hyp_puds(pgd_t *pgd, phys_addr_t addr, phys_addr_t end)
512{
513 phys_addr_t next;
514 pud_t *pud, *start_pud;
515
516 start_pud = pud = pud_offset(pgd, addr);
517 do {
518 next = pud_addr_end(addr, end);
519 /* Hyp doesn't use huge puds */
520 if (!pud_none(*pud))
521 unmap_hyp_pmds(pud, addr, next);
522 } while (pud++, addr = next, addr != end);
523
524 if (hyp_pud_table_empty(start_pud))
525 clear_hyp_pgd_entry(pgd);
526}
527
3ddd4556
MZ
528static unsigned int kvm_pgd_index(unsigned long addr, unsigned int ptrs_per_pgd)
529{
530 return (addr >> PGDIR_SHIFT) & (ptrs_per_pgd - 1);
531}
532
533static void __unmap_hyp_range(pgd_t *pgdp, unsigned long ptrs_per_pgd,
534 phys_addr_t start, u64 size)
64f32497
SP
535{
536 pgd_t *pgd;
537 phys_addr_t addr = start, end = start + size;
538 phys_addr_t next;
539
540 /*
541 * We don't unmap anything from HYP, except at the hyp tear down.
542 * Hence, we don't have to invalidate the TLBs here.
543 */
3ddd4556 544 pgd = pgdp + kvm_pgd_index(addr, ptrs_per_pgd);
64f32497
SP
545 do {
546 next = pgd_addr_end(addr, end);
547 if (!pgd_none(*pgd))
548 unmap_hyp_puds(pgd, addr, next);
549 } while (pgd++, addr = next, addr != end);
550}
551
3ddd4556
MZ
552static void unmap_hyp_range(pgd_t *pgdp, phys_addr_t start, u64 size)
553{
554 __unmap_hyp_range(pgdp, PTRS_PER_PGD, start, size);
555}
556
557static void unmap_hyp_idmap_range(pgd_t *pgdp, phys_addr_t start, u64 size)
558{
559 __unmap_hyp_range(pgdp, __kvm_idmap_ptrs_per_pgd(), start, size);
560}
561
342cd0ab 562/**
4f728276 563 * free_hyp_pgds - free Hyp-mode page tables
342cd0ab 564 *
5a677ce0
MZ
565 * Assumes hyp_pgd is a page table used strictly in Hyp-mode and
566 * therefore contains either mappings in the kernel memory area (above
e3f019b3 567 * PAGE_OFFSET), or device mappings in the idmap range.
5a677ce0 568 *
e3f019b3
MZ
569 * boot_hyp_pgd should only map the idmap range, and is only used in
570 * the extended idmap case.
342cd0ab 571 */
4f728276 572void free_hyp_pgds(void)
342cd0ab 573{
e3f019b3
MZ
574 pgd_t *id_pgd;
575
d157f4a5 576 mutex_lock(&kvm_hyp_pgd_mutex);
5a677ce0 577
e3f019b3
MZ
578 id_pgd = boot_hyp_pgd ? boot_hyp_pgd : hyp_pgd;
579
580 if (id_pgd) {
581 /* In case we never called hyp_mmu_init() */
582 if (!io_map_base)
583 io_map_base = hyp_idmap_start;
584 unmap_hyp_idmap_range(id_pgd, io_map_base,
585 hyp_idmap_start + PAGE_SIZE - io_map_base);
586 }
587
26781f9c 588 if (boot_hyp_pgd) {
26781f9c
MZ
589 free_pages((unsigned long)boot_hyp_pgd, hyp_pgd_order);
590 boot_hyp_pgd = NULL;
591 }
592
4f728276 593 if (hyp_pgd) {
7839c672
MZ
594 unmap_hyp_range(hyp_pgd, kern_hyp_va(PAGE_OFFSET),
595 (uintptr_t)high_memory - PAGE_OFFSET);
d4cb9df5 596
38f791a4 597 free_pages((unsigned long)hyp_pgd, hyp_pgd_order);
d157f4a5 598 hyp_pgd = NULL;
4f728276 599 }
e4c5a685
AB
600 if (merged_hyp_pgd) {
601 clear_page(merged_hyp_pgd);
602 free_page((unsigned long)merged_hyp_pgd);
603 merged_hyp_pgd = NULL;
604 }
4f728276 605
342cd0ab
CD
606 mutex_unlock(&kvm_hyp_pgd_mutex);
607}
608
609static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
6060df84
MZ
610 unsigned long end, unsigned long pfn,
611 pgprot_t prot)
342cd0ab
CD
612{
613 pte_t *pte;
614 unsigned long addr;
342cd0ab 615
3562c76d
MZ
616 addr = start;
617 do {
6060df84 618 pte = pte_offset_kernel(pmd, addr);
f8df7338 619 kvm_set_pte(pte, kvm_pfn_pte(pfn, prot));
4f728276 620 get_page(virt_to_page(pte));
6060df84 621 pfn++;
3562c76d 622 } while (addr += PAGE_SIZE, addr != end);
342cd0ab
CD
623}
624
625static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
6060df84
MZ
626 unsigned long end, unsigned long pfn,
627 pgprot_t prot)
342cd0ab
CD
628{
629 pmd_t *pmd;
630 pte_t *pte;
631 unsigned long addr, next;
632
3562c76d
MZ
633 addr = start;
634 do {
6060df84 635 pmd = pmd_offset(pud, addr);
342cd0ab
CD
636
637 BUG_ON(pmd_sect(*pmd));
638
639 if (pmd_none(*pmd)) {
4cf58924 640 pte = pte_alloc_one_kernel(NULL);
342cd0ab
CD
641 if (!pte) {
642 kvm_err("Cannot allocate Hyp pte\n");
643 return -ENOMEM;
644 }
0db9dd8a 645 kvm_pmd_populate(pmd, pte);
4f728276 646 get_page(virt_to_page(pmd));
342cd0ab
CD
647 }
648
649 next = pmd_addr_end(addr, end);
650
6060df84
MZ
651 create_hyp_pte_mappings(pmd, addr, next, pfn, prot);
652 pfn += (next - addr) >> PAGE_SHIFT;
3562c76d 653 } while (addr = next, addr != end);
342cd0ab
CD
654
655 return 0;
656}
657
38f791a4
CD
658static int create_hyp_pud_mappings(pgd_t *pgd, unsigned long start,
659 unsigned long end, unsigned long pfn,
660 pgprot_t prot)
661{
662 pud_t *pud;
663 pmd_t *pmd;
664 unsigned long addr, next;
665 int ret;
666
667 addr = start;
668 do {
669 pud = pud_offset(pgd, addr);
670
671 if (pud_none_or_clear_bad(pud)) {
672 pmd = pmd_alloc_one(NULL, addr);
673 if (!pmd) {
674 kvm_err("Cannot allocate Hyp pmd\n");
675 return -ENOMEM;
676 }
0db9dd8a 677 kvm_pud_populate(pud, pmd);
38f791a4 678 get_page(virt_to_page(pud));
38f791a4
CD
679 }
680
681 next = pud_addr_end(addr, end);
682 ret = create_hyp_pmd_mappings(pud, addr, next, pfn, prot);
683 if (ret)
684 return ret;
685 pfn += (next - addr) >> PAGE_SHIFT;
686 } while (addr = next, addr != end);
687
688 return 0;
689}
690
98732d1b 691static int __create_hyp_mappings(pgd_t *pgdp, unsigned long ptrs_per_pgd,
6060df84
MZ
692 unsigned long start, unsigned long end,
693 unsigned long pfn, pgprot_t prot)
342cd0ab 694{
342cd0ab
CD
695 pgd_t *pgd;
696 pud_t *pud;
342cd0ab
CD
697 unsigned long addr, next;
698 int err = 0;
699
342cd0ab 700 mutex_lock(&kvm_hyp_pgd_mutex);
3562c76d
MZ
701 addr = start & PAGE_MASK;
702 end = PAGE_ALIGN(end);
703 do {
3ddd4556 704 pgd = pgdp + kvm_pgd_index(addr, ptrs_per_pgd);
342cd0ab 705
38f791a4
CD
706 if (pgd_none(*pgd)) {
707 pud = pud_alloc_one(NULL, addr);
708 if (!pud) {
709 kvm_err("Cannot allocate Hyp pud\n");
342cd0ab
CD
710 err = -ENOMEM;
711 goto out;
712 }
0db9dd8a 713 kvm_pgd_populate(pgd, pud);
38f791a4 714 get_page(virt_to_page(pgd));
342cd0ab
CD
715 }
716
717 next = pgd_addr_end(addr, end);
38f791a4 718 err = create_hyp_pud_mappings(pgd, addr, next, pfn, prot);
342cd0ab
CD
719 if (err)
720 goto out;
6060df84 721 pfn += (next - addr) >> PAGE_SHIFT;
3562c76d 722 } while (addr = next, addr != end);
342cd0ab
CD
723out:
724 mutex_unlock(&kvm_hyp_pgd_mutex);
725 return err;
726}
727
40c2729b
CD
728static phys_addr_t kvm_kaddr_to_phys(void *kaddr)
729{
730 if (!is_vmalloc_addr(kaddr)) {
731 BUG_ON(!virt_addr_valid(kaddr));
732 return __pa(kaddr);
733 } else {
734 return page_to_phys(vmalloc_to_page(kaddr)) +
735 offset_in_page(kaddr);
736 }
737}
738
342cd0ab 739/**
06e8c3b0 740 * create_hyp_mappings - duplicate a kernel virtual address range in Hyp mode
342cd0ab
CD
741 * @from: The virtual kernel start address of the range
742 * @to: The virtual kernel end address of the range (exclusive)
c8dddecd 743 * @prot: The protection to be applied to this range
342cd0ab 744 *
06e8c3b0
MZ
745 * The same virtual address as the kernel virtual address is also used
746 * in Hyp-mode mapping (modulo HYP_PAGE_OFFSET) to the same underlying
747 * physical pages.
342cd0ab 748 */
c8dddecd 749int create_hyp_mappings(void *from, void *to, pgprot_t prot)
342cd0ab 750{
40c2729b
CD
751 phys_addr_t phys_addr;
752 unsigned long virt_addr;
6c41a413
MZ
753 unsigned long start = kern_hyp_va((unsigned long)from);
754 unsigned long end = kern_hyp_va((unsigned long)to);
6060df84 755
1e947bad
MZ
756 if (is_kernel_in_hyp_mode())
757 return 0;
758
40c2729b
CD
759 start = start & PAGE_MASK;
760 end = PAGE_ALIGN(end);
6060df84 761
40c2729b
CD
762 for (virt_addr = start; virt_addr < end; virt_addr += PAGE_SIZE) {
763 int err;
6060df84 764
40c2729b 765 phys_addr = kvm_kaddr_to_phys(from + virt_addr - start);
98732d1b
KM
766 err = __create_hyp_mappings(hyp_pgd, PTRS_PER_PGD,
767 virt_addr, virt_addr + PAGE_SIZE,
40c2729b 768 __phys_to_pfn(phys_addr),
c8dddecd 769 prot);
40c2729b
CD
770 if (err)
771 return err;
772 }
773
774 return 0;
342cd0ab
CD
775}
776
dc2e4633
MZ
777static int __create_hyp_private_mapping(phys_addr_t phys_addr, size_t size,
778 unsigned long *haddr, pgprot_t prot)
342cd0ab 779{
e3f019b3
MZ
780 pgd_t *pgd = hyp_pgd;
781 unsigned long base;
782 int ret = 0;
6060df84 783
e3f019b3 784 mutex_lock(&kvm_hyp_pgd_mutex);
6060df84 785
e3f019b3
MZ
786 /*
787 * This assumes that we we have enough space below the idmap
788 * page to allocate our VAs. If not, the check below will
789 * kick. A potential alternative would be to detect that
790 * overflow and switch to an allocation above the idmap.
791 *
792 * The allocated size is always a multiple of PAGE_SIZE.
793 */
794 size = PAGE_ALIGN(size + offset_in_page(phys_addr));
795 base = io_map_base - size;
1bb32a44 796
e3f019b3
MZ
797 /*
798 * Verify that BIT(VA_BITS - 1) hasn't been flipped by
799 * allocating the new area, as it would indicate we've
800 * overflowed the idmap/IO address range.
801 */
802 if ((base ^ io_map_base) & BIT(VA_BITS - 1))
803 ret = -ENOMEM;
804 else
805 io_map_base = base;
806
807 mutex_unlock(&kvm_hyp_pgd_mutex);
808
809 if (ret)
810 goto out;
811
812 if (__kvm_cpu_uses_extended_idmap())
813 pgd = boot_hyp_pgd;
814
815 ret = __create_hyp_mappings(pgd, __kvm_idmap_ptrs_per_pgd(),
816 base, base + size,
dc2e4633 817 __phys_to_pfn(phys_addr), prot);
e3f019b3
MZ
818 if (ret)
819 goto out;
820
dc2e4633 821 *haddr = base + offset_in_page(phys_addr);
e3f019b3
MZ
822
823out:
dc2e4633
MZ
824 return ret;
825}
826
827/**
828 * create_hyp_io_mappings - Map IO into both kernel and HYP
829 * @phys_addr: The physical start address which gets mapped
830 * @size: Size of the region being mapped
831 * @kaddr: Kernel VA for this mapping
832 * @haddr: HYP VA for this mapping
833 */
834int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
835 void __iomem **kaddr,
836 void __iomem **haddr)
837{
838 unsigned long addr;
839 int ret;
840
841 *kaddr = ioremap(phys_addr, size);
842 if (!*kaddr)
843 return -ENOMEM;
844
845 if (is_kernel_in_hyp_mode()) {
846 *haddr = *kaddr;
847 return 0;
848 }
849
850 ret = __create_hyp_private_mapping(phys_addr, size,
851 &addr, PAGE_HYP_DEVICE);
1bb32a44
MZ
852 if (ret) {
853 iounmap(*kaddr);
854 *kaddr = NULL;
dc2e4633
MZ
855 *haddr = NULL;
856 return ret;
857 }
858
859 *haddr = (void __iomem *)addr;
860 return 0;
861}
862
863/**
864 * create_hyp_exec_mappings - Map an executable range into HYP
865 * @phys_addr: The physical start address which gets mapped
866 * @size: Size of the region being mapped
867 * @haddr: HYP VA for this mapping
868 */
869int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
870 void **haddr)
871{
872 unsigned long addr;
873 int ret;
874
875 BUG_ON(is_kernel_in_hyp_mode());
876
877 ret = __create_hyp_private_mapping(phys_addr, size,
878 &addr, PAGE_HYP_EXEC);
879 if (ret) {
880 *haddr = NULL;
1bb32a44
MZ
881 return ret;
882 }
883
dc2e4633 884 *haddr = (void *)addr;
1bb32a44 885 return 0;
342cd0ab
CD
886}
887
d5d8184d
CD
888/**
889 * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation.
890 * @kvm: The KVM struct pointer for the VM.
891 *
8324c3d5
ZY
892 * Allocates only the stage-2 HW PGD level table(s) of size defined by
893 * stage2_pgd_size(kvm).
d5d8184d
CD
894 *
895 * Note we don't need locking here as this is only called when the VM is
896 * created, which can only be done once.
897 */
898int kvm_alloc_stage2_pgd(struct kvm *kvm)
899{
e329fb75 900 phys_addr_t pgd_phys;
d5d8184d
CD
901 pgd_t *pgd;
902
903 if (kvm->arch.pgd != NULL) {
904 kvm_err("kvm_arch already initialized?\n");
905 return -EINVAL;
906 }
907
9163ee23 908 /* Allocate the HW PGD, making sure that each page gets its own refcount */
e55cac5b 909 pgd = alloc_pages_exact(stage2_pgd_size(kvm), GFP_KERNEL | __GFP_ZERO);
9163ee23 910 if (!pgd)
a987370f
MZ
911 return -ENOMEM;
912
e329fb75
CD
913 pgd_phys = virt_to_phys(pgd);
914 if (WARN_ON(pgd_phys & ~kvm_vttbr_baddr_mask(kvm)))
915 return -EINVAL;
916
d5d8184d 917 kvm->arch.pgd = pgd;
e329fb75 918 kvm->arch.pgd_phys = pgd_phys;
d5d8184d
CD
919 return 0;
920}
921
957db105
CD
922static void stage2_unmap_memslot(struct kvm *kvm,
923 struct kvm_memory_slot *memslot)
924{
925 hva_t hva = memslot->userspace_addr;
926 phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT;
927 phys_addr_t size = PAGE_SIZE * memslot->npages;
928 hva_t reg_end = hva + size;
929
930 /*
931 * A memory region could potentially cover multiple VMAs, and any holes
932 * between them, so iterate over all of them to find out if we should
933 * unmap any of them.
934 *
935 * +--------------------------------------------+
936 * +---------------+----------------+ +----------------+
937 * | : VMA 1 | VMA 2 | | VMA 3 : |
938 * +---------------+----------------+ +----------------+
939 * | memory region |
940 * +--------------------------------------------+
941 */
942 do {
943 struct vm_area_struct *vma = find_vma(current->mm, hva);
944 hva_t vm_start, vm_end;
945
946 if (!vma || vma->vm_start >= reg_end)
947 break;
948
949 /*
950 * Take the intersection of this VMA with the memory region
951 */
952 vm_start = max(hva, vma->vm_start);
953 vm_end = min(reg_end, vma->vm_end);
954
955 if (!(vma->vm_flags & VM_PFNMAP)) {
956 gpa_t gpa = addr + (vm_start - memslot->userspace_addr);
957 unmap_stage2_range(kvm, gpa, vm_end - vm_start);
958 }
959 hva = vm_end;
960 } while (hva < reg_end);
961}
962
963/**
964 * stage2_unmap_vm - Unmap Stage-2 RAM mappings
965 * @kvm: The struct kvm pointer
966 *
967 * Go through the memregions and unmap any reguler RAM
968 * backing memory already mapped to the VM.
969 */
970void stage2_unmap_vm(struct kvm *kvm)
971{
972 struct kvm_memslots *slots;
973 struct kvm_memory_slot *memslot;
974 int idx;
975
976 idx = srcu_read_lock(&kvm->srcu);
90f6e150 977 down_read(&current->mm->mmap_sem);
957db105
CD
978 spin_lock(&kvm->mmu_lock);
979
980 slots = kvm_memslots(kvm);
981 kvm_for_each_memslot(memslot, slots)
982 stage2_unmap_memslot(kvm, memslot);
983
984 spin_unlock(&kvm->mmu_lock);
90f6e150 985 up_read(&current->mm->mmap_sem);
957db105
CD
986 srcu_read_unlock(&kvm->srcu, idx);
987}
988
d5d8184d
CD
989/**
990 * kvm_free_stage2_pgd - free all stage-2 tables
991 * @kvm: The KVM struct pointer for the VM.
992 *
993 * Walks the level-1 page table pointed to by kvm->arch.pgd and frees all
994 * underlying level-2 and level-3 tables before freeing the actual level-1 table
995 * and setting the struct pointer to NULL.
d5d8184d
CD
996 */
997void kvm_free_stage2_pgd(struct kvm *kvm)
998{
6c0d706b 999 void *pgd = NULL;
d5d8184d 1000
8b3405e3 1001 spin_lock(&kvm->mmu_lock);
6c0d706b 1002 if (kvm->arch.pgd) {
e55cac5b 1003 unmap_stage2_range(kvm, 0, kvm_phys_size(kvm));
2952a607 1004 pgd = READ_ONCE(kvm->arch.pgd);
6c0d706b 1005 kvm->arch.pgd = NULL;
e329fb75 1006 kvm->arch.pgd_phys = 0;
6c0d706b 1007 }
8b3405e3
SP
1008 spin_unlock(&kvm->mmu_lock);
1009
9163ee23 1010 /* Free the HW pgd, one page at a time */
6c0d706b 1011 if (pgd)
e55cac5b 1012 free_pages_exact(pgd, stage2_pgd_size(kvm));
d5d8184d
CD
1013}
1014
38f791a4 1015static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
ad361f09 1016 phys_addr_t addr)
d5d8184d
CD
1017{
1018 pgd_t *pgd;
1019 pud_t *pud;
d5d8184d 1020
e55cac5b
SP
1021 pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr);
1022 if (stage2_pgd_none(kvm, *pgd)) {
38f791a4
CD
1023 if (!cache)
1024 return NULL;
1025 pud = mmu_memory_cache_alloc(cache);
e55cac5b 1026 stage2_pgd_populate(kvm, pgd, pud);
38f791a4
CD
1027 get_page(virt_to_page(pgd));
1028 }
1029
e55cac5b 1030 return stage2_pud_offset(kvm, pgd, addr);
38f791a4
CD
1031}
1032
1033static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
1034 phys_addr_t addr)
1035{
1036 pud_t *pud;
1037 pmd_t *pmd;
1038
1039 pud = stage2_get_pud(kvm, cache, addr);
b8e0ba7c 1040 if (!pud || stage2_pud_huge(kvm, *pud))
d6dbdd3c
MZ
1041 return NULL;
1042
e55cac5b 1043 if (stage2_pud_none(kvm, *pud)) {
d5d8184d 1044 if (!cache)
ad361f09 1045 return NULL;
d5d8184d 1046 pmd = mmu_memory_cache_alloc(cache);
e55cac5b 1047 stage2_pud_populate(kvm, pud, pmd);
d5d8184d 1048 get_page(virt_to_page(pud));
c62ee2b2
MZ
1049 }
1050
e55cac5b 1051 return stage2_pmd_offset(kvm, pud, addr);
ad361f09
CD
1052}
1053
1054static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache
1055 *cache, phys_addr_t addr, const pmd_t *new_pmd)
1056{
1057 pmd_t *pmd, old_pmd;
1058
3c3736cd 1059retry:
ad361f09
CD
1060 pmd = stage2_get_pmd(kvm, cache, addr);
1061 VM_BUG_ON(!pmd);
d5d8184d 1062
ad361f09 1063 old_pmd = *pmd;
3c3736cd
SP
1064 /*
1065 * Multiple vcpus faulting on the same PMD entry, can
1066 * lead to them sequentially updating the PMD with the
1067 * same value. Following the break-before-make
1068 * (pmd_clear() followed by tlb_flush()) process can
1069 * hinder forward progress due to refaults generated
1070 * on missing translations.
1071 *
1072 * Skip updating the page table if the entry is
1073 * unchanged.
1074 */
1075 if (pmd_val(old_pmd) == pmd_val(*new_pmd))
1076 return 0;
1077
d4b9e079 1078 if (pmd_present(old_pmd)) {
86658b81 1079 /*
3c3736cd
SP
1080 * If we already have PTE level mapping for this block,
1081 * we must unmap it to avoid inconsistent TLB state and
1082 * leaking the table page. We could end up in this situation
1083 * if the memory slot was marked for dirty logging and was
1084 * reverted, leaving PTE level mappings for the pages accessed
1085 * during the period. So, unmap the PTE level mapping for this
1086 * block and retry, as we could have released the upper level
1087 * table in the process.
86658b81 1088 *
3c3736cd
SP
1089 * Normal THP split/merge follows mmu_notifier callbacks and do
1090 * get handled accordingly.
86658b81 1091 */
3c3736cd
SP
1092 if (!pmd_thp_or_huge(old_pmd)) {
1093 unmap_stage2_range(kvm, addr & S2_PMD_MASK, S2_PMD_SIZE);
1094 goto retry;
1095 }
86658b81
PA
1096 /*
1097 * Mapping in huge pages should only happen through a
1098 * fault. If a page is merged into a transparent huge
1099 * page, the individual subpages of that huge page
1100 * should be unmapped through MMU notifiers before we
1101 * get here.
1102 *
1103 * Merging of CompoundPages is not supported; they
1104 * should become splitting first, unmapped, merged,
1105 * and mapped back in on-demand.
1106 */
3c3736cd 1107 WARN_ON_ONCE(pmd_pfn(old_pmd) != pmd_pfn(*new_pmd));
d4b9e079 1108 pmd_clear(pmd);
ad361f09 1109 kvm_tlb_flush_vmid_ipa(kvm, addr);
d4b9e079 1110 } else {
ad361f09 1111 get_page(virt_to_page(pmd));
d4b9e079
MZ
1112 }
1113
1114 kvm_set_pmd(pmd, *new_pmd);
ad361f09
CD
1115 return 0;
1116}
1117
b8e0ba7c
PA
1118static int stage2_set_pud_huge(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
1119 phys_addr_t addr, const pud_t *new_pudp)
1120{
1121 pud_t *pudp, old_pud;
1122
3c3736cd 1123retry:
b8e0ba7c
PA
1124 pudp = stage2_get_pud(kvm, cache, addr);
1125 VM_BUG_ON(!pudp);
1126
1127 old_pud = *pudp;
1128
1129 /*
1130 * A large number of vcpus faulting on the same stage 2 entry,
3c3736cd
SP
1131 * can lead to a refault due to the stage2_pud_clear()/tlb_flush().
1132 * Skip updating the page tables if there is no change.
b8e0ba7c
PA
1133 */
1134 if (pud_val(old_pud) == pud_val(*new_pudp))
1135 return 0;
1136
1137 if (stage2_pud_present(kvm, old_pud)) {
3c3736cd
SP
1138 /*
1139 * If we already have table level mapping for this block, unmap
1140 * the range for this block and retry.
1141 */
1142 if (!stage2_pud_huge(kvm, old_pud)) {
1143 unmap_stage2_range(kvm, addr & S2_PUD_MASK, S2_PUD_SIZE);
1144 goto retry;
1145 }
1146
1147 WARN_ON_ONCE(kvm_pud_pfn(old_pud) != kvm_pud_pfn(*new_pudp));
b8e0ba7c
PA
1148 stage2_pud_clear(kvm, pudp);
1149 kvm_tlb_flush_vmid_ipa(kvm, addr);
1150 } else {
1151 get_page(virt_to_page(pudp));
1152 }
1153
1154 kvm_set_pud(pudp, *new_pudp);
1155 return 0;
1156}
1157
86d1c55e
PA
1158/*
1159 * stage2_get_leaf_entry - walk the stage2 VM page tables and return
1160 * true if a valid and present leaf-entry is found. A pointer to the
1161 * leaf-entry is returned in the appropriate level variable - pudpp,
1162 * pmdpp, ptepp.
1163 */
1164static bool stage2_get_leaf_entry(struct kvm *kvm, phys_addr_t addr,
1165 pud_t **pudpp, pmd_t **pmdpp, pte_t **ptepp)
7a3796d2 1166{
86d1c55e 1167 pud_t *pudp;
7a3796d2
MZ
1168 pmd_t *pmdp;
1169 pte_t *ptep;
1170
86d1c55e
PA
1171 *pudpp = NULL;
1172 *pmdpp = NULL;
1173 *ptepp = NULL;
1174
1175 pudp = stage2_get_pud(kvm, NULL, addr);
1176 if (!pudp || stage2_pud_none(kvm, *pudp) || !stage2_pud_present(kvm, *pudp))
1177 return false;
1178
1179 if (stage2_pud_huge(kvm, *pudp)) {
1180 *pudpp = pudp;
1181 return true;
1182 }
1183
1184 pmdp = stage2_pmd_offset(kvm, pudp, addr);
7a3796d2
MZ
1185 if (!pmdp || pmd_none(*pmdp) || !pmd_present(*pmdp))
1186 return false;
1187
86d1c55e
PA
1188 if (pmd_thp_or_huge(*pmdp)) {
1189 *pmdpp = pmdp;
1190 return true;
1191 }
7a3796d2
MZ
1192
1193 ptep = pte_offset_kernel(pmdp, addr);
1194 if (!ptep || pte_none(*ptep) || !pte_present(*ptep))
1195 return false;
1196
86d1c55e
PA
1197 *ptepp = ptep;
1198 return true;
1199}
1200
1201static bool stage2_is_exec(struct kvm *kvm, phys_addr_t addr)
1202{
1203 pud_t *pudp;
1204 pmd_t *pmdp;
1205 pte_t *ptep;
1206 bool found;
1207
1208 found = stage2_get_leaf_entry(kvm, addr, &pudp, &pmdp, &ptep);
1209 if (!found)
1210 return false;
1211
1212 if (pudp)
1213 return kvm_s2pud_exec(pudp);
1214 else if (pmdp)
1215 return kvm_s2pmd_exec(pmdp);
1216 else
1217 return kvm_s2pte_exec(ptep);
7a3796d2
MZ
1218}
1219
ad361f09 1220static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
15a49a44
MS
1221 phys_addr_t addr, const pte_t *new_pte,
1222 unsigned long flags)
ad361f09 1223{
b8e0ba7c 1224 pud_t *pud;
ad361f09
CD
1225 pmd_t *pmd;
1226 pte_t *pte, old_pte;
15a49a44
MS
1227 bool iomap = flags & KVM_S2PTE_FLAG_IS_IOMAP;
1228 bool logging_active = flags & KVM_S2_FLAG_LOGGING_ACTIVE;
1229
1230 VM_BUG_ON(logging_active && !cache);
ad361f09 1231
38f791a4 1232 /* Create stage-2 page table mapping - Levels 0 and 1 */
b8e0ba7c
PA
1233 pud = stage2_get_pud(kvm, cache, addr);
1234 if (!pud) {
1235 /*
1236 * Ignore calls from kvm_set_spte_hva for unallocated
1237 * address ranges.
1238 */
1239 return 0;
1240 }
1241
1242 /*
1243 * While dirty page logging - dissolve huge PUD, then continue
1244 * on to allocate page.
1245 */
1246 if (logging_active)
1247 stage2_dissolve_pud(kvm, addr, pud);
1248
1249 if (stage2_pud_none(kvm, *pud)) {
1250 if (!cache)
1251 return 0; /* ignore calls from kvm_set_spte_hva */
1252 pmd = mmu_memory_cache_alloc(cache);
1253 stage2_pud_populate(kvm, pud, pmd);
1254 get_page(virt_to_page(pud));
1255 }
1256
1257 pmd = stage2_pmd_offset(kvm, pud, addr);
ad361f09
CD
1258 if (!pmd) {
1259 /*
1260 * Ignore calls from kvm_set_spte_hva for unallocated
1261 * address ranges.
1262 */
1263 return 0;
1264 }
1265
15a49a44
MS
1266 /*
1267 * While dirty page logging - dissolve huge PMD, then continue on to
1268 * allocate page.
1269 */
1270 if (logging_active)
1271 stage2_dissolve_pmd(kvm, addr, pmd);
1272
ad361f09 1273 /* Create stage-2 page mappings - Level 2 */
d5d8184d
CD
1274 if (pmd_none(*pmd)) {
1275 if (!cache)
1276 return 0; /* ignore calls from kvm_set_spte_hva */
1277 pte = mmu_memory_cache_alloc(cache);
0db9dd8a 1278 kvm_pmd_populate(pmd, pte);
d5d8184d 1279 get_page(virt_to_page(pmd));
c62ee2b2
MZ
1280 }
1281
1282 pte = pte_offset_kernel(pmd, addr);
d5d8184d
CD
1283
1284 if (iomap && pte_present(*pte))
1285 return -EFAULT;
1286
1287 /* Create 2nd stage page table mapping - Level 3 */
1288 old_pte = *pte;
d4b9e079 1289 if (pte_present(old_pte)) {
976d34e2
PA
1290 /* Skip page table update if there is no change */
1291 if (pte_val(old_pte) == pte_val(*new_pte))
1292 return 0;
1293
d4b9e079 1294 kvm_set_pte(pte, __pte(0));
48762767 1295 kvm_tlb_flush_vmid_ipa(kvm, addr);
d4b9e079 1296 } else {
d5d8184d 1297 get_page(virt_to_page(pte));
d4b9e079 1298 }
d5d8184d 1299
d4b9e079 1300 kvm_set_pte(pte, *new_pte);
d5d8184d
CD
1301 return 0;
1302}
d5d8184d 1303
06485053
CM
1304#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1305static int stage2_ptep_test_and_clear_young(pte_t *pte)
1306{
1307 if (pte_young(*pte)) {
1308 *pte = pte_mkold(*pte);
1309 return 1;
1310 }
d5d8184d
CD
1311 return 0;
1312}
06485053
CM
1313#else
1314static int stage2_ptep_test_and_clear_young(pte_t *pte)
1315{
1316 return __ptep_test_and_clear_young(pte);
1317}
1318#endif
1319
1320static int stage2_pmdp_test_and_clear_young(pmd_t *pmd)
1321{
1322 return stage2_ptep_test_and_clear_young((pte_t *)pmd);
1323}
d5d8184d 1324
35a63966
PA
1325static int stage2_pudp_test_and_clear_young(pud_t *pud)
1326{
1327 return stage2_ptep_test_and_clear_young((pte_t *)pud);
1328}
1329
d5d8184d
CD
1330/**
1331 * kvm_phys_addr_ioremap - map a device range to guest IPA
1332 *
1333 * @kvm: The KVM pointer
1334 * @guest_ipa: The IPA at which to insert the mapping
1335 * @pa: The physical address of the device
1336 * @size: The size of the mapping
1337 */
1338int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
c40f2f8f 1339 phys_addr_t pa, unsigned long size, bool writable)
d5d8184d
CD
1340{
1341 phys_addr_t addr, end;
1342 int ret = 0;
1343 unsigned long pfn;
1344 struct kvm_mmu_memory_cache cache = { 0, };
1345
1346 end = (guest_ipa + size + PAGE_SIZE - 1) & PAGE_MASK;
1347 pfn = __phys_to_pfn(pa);
1348
1349 for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
f8df7338 1350 pte_t pte = kvm_pfn_pte(pfn, PAGE_S2_DEVICE);
d5d8184d 1351
c40f2f8f 1352 if (writable)
06485053 1353 pte = kvm_s2pte_mkwrite(pte);
c40f2f8f 1354
e55cac5b
SP
1355 ret = mmu_topup_memory_cache(&cache,
1356 kvm_mmu_cache_min_pages(kvm),
1357 KVM_NR_MEM_OBJS);
d5d8184d
CD
1358 if (ret)
1359 goto out;
1360 spin_lock(&kvm->mmu_lock);
15a49a44
MS
1361 ret = stage2_set_pte(kvm, &cache, addr, &pte,
1362 KVM_S2PTE_FLAG_IS_IOMAP);
d5d8184d
CD
1363 spin_unlock(&kvm->mmu_lock);
1364 if (ret)
1365 goto out;
1366
1367 pfn++;
1368 }
1369
1370out:
1371 mmu_free_memory_cache(&cache);
1372 return ret;
1373}
1374
ba049e93 1375static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap)
9b5fdb97 1376{
ba049e93 1377 kvm_pfn_t pfn = *pfnp;
9b5fdb97 1378 gfn_t gfn = *ipap >> PAGE_SHIFT;
fd2ef358 1379 struct page *page = pfn_to_page(pfn);
9b5fdb97 1380
fd2ef358 1381 /*
6992195c 1382 * PageTransCompoundMap() returns true for THP and
fd2ef358
PA
1383 * hugetlbfs. Make sure the adjustment is done only for THP
1384 * pages.
1385 */
1386 if (!PageHuge(page) && PageTransCompoundMap(page)) {
9b5fdb97
CD
1387 unsigned long mask;
1388 /*
1389 * The address we faulted on is backed by a transparent huge
1390 * page. However, because we map the compound huge page and
1391 * not the individual tail page, we need to transfer the
1392 * refcount to the head page. We have to be careful that the
1393 * THP doesn't start to split while we are adjusting the
1394 * refcounts.
1395 *
1396 * We are sure this doesn't happen, because mmu_notifier_retry
1397 * was successful and we are holding the mmu_lock, so if this
1398 * THP is trying to split, it will be blocked in the mmu
1399 * notifier before touching any of the pages, specifically
1400 * before being able to call __split_huge_page_refcount().
1401 *
1402 * We can therefore safely transfer the refcount from PG_tail
1403 * to PG_head and switch the pfn from a tail page to the head
1404 * page accordingly.
1405 */
1406 mask = PTRS_PER_PMD - 1;
1407 VM_BUG_ON((gfn & mask) != (pfn & mask));
1408 if (pfn & mask) {
1409 *ipap &= PMD_MASK;
1410 kvm_release_pfn_clean(pfn);
1411 pfn &= ~mask;
1412 kvm_get_pfn(pfn);
1413 *pfnp = pfn;
1414 }
1415
1416 return true;
1417 }
1418
1419 return false;
1420}
1421
c6473555
MS
1422/**
1423 * stage2_wp_ptes - write protect PMD range
1424 * @pmd: pointer to pmd entry
1425 * @addr: range start address
1426 * @end: range end address
1427 */
1428static void stage2_wp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end)
1429{
1430 pte_t *pte;
1431
1432 pte = pte_offset_kernel(pmd, addr);
1433 do {
1434 if (!pte_none(*pte)) {
1435 if (!kvm_s2pte_readonly(pte))
1436 kvm_set_s2pte_readonly(pte);
1437 }
1438 } while (pte++, addr += PAGE_SIZE, addr != end);
1439}
1440
1441/**
1442 * stage2_wp_pmds - write protect PUD range
e55cac5b 1443 * kvm: kvm instance for the VM
c6473555
MS
1444 * @pud: pointer to pud entry
1445 * @addr: range start address
1446 * @end: range end address
1447 */
e55cac5b
SP
1448static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud,
1449 phys_addr_t addr, phys_addr_t end)
c6473555
MS
1450{
1451 pmd_t *pmd;
1452 phys_addr_t next;
1453
e55cac5b 1454 pmd = stage2_pmd_offset(kvm, pud, addr);
c6473555
MS
1455
1456 do {
e55cac5b 1457 next = stage2_pmd_addr_end(kvm, addr, end);
c6473555 1458 if (!pmd_none(*pmd)) {
bbb3b6b3 1459 if (pmd_thp_or_huge(*pmd)) {
c6473555
MS
1460 if (!kvm_s2pmd_readonly(pmd))
1461 kvm_set_s2pmd_readonly(pmd);
1462 } else {
1463 stage2_wp_ptes(pmd, addr, next);
1464 }
1465 }
1466 } while (pmd++, addr = next, addr != end);
1467}
1468
1469/**
8324c3d5
ZY
1470 * stage2_wp_puds - write protect PGD range
1471 * @pgd: pointer to pgd entry
1472 * @addr: range start address
1473 * @end: range end address
1474 */
e55cac5b
SP
1475static void stage2_wp_puds(struct kvm *kvm, pgd_t *pgd,
1476 phys_addr_t addr, phys_addr_t end)
c6473555
MS
1477{
1478 pud_t *pud;
1479 phys_addr_t next;
1480
e55cac5b 1481 pud = stage2_pud_offset(kvm, pgd, addr);
c6473555 1482 do {
e55cac5b
SP
1483 next = stage2_pud_addr_end(kvm, addr, end);
1484 if (!stage2_pud_none(kvm, *pud)) {
4ea5af53
PA
1485 if (stage2_pud_huge(kvm, *pud)) {
1486 if (!kvm_s2pud_readonly(pud))
1487 kvm_set_s2pud_readonly(pud);
1488 } else {
1489 stage2_wp_pmds(kvm, pud, addr, next);
1490 }
c6473555
MS
1491 }
1492 } while (pud++, addr = next, addr != end);
1493}
1494
1495/**
1496 * stage2_wp_range() - write protect stage2 memory region range
1497 * @kvm: The KVM pointer
1498 * @addr: Start address of range
1499 * @end: End address of range
1500 */
1501static void stage2_wp_range(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)
1502{
1503 pgd_t *pgd;
1504 phys_addr_t next;
1505
e55cac5b 1506 pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr);
c6473555
MS
1507 do {
1508 /*
1509 * Release kvm_mmu_lock periodically if the memory region is
1510 * large. Otherwise, we may see kernel panics with
227ea818
CD
1511 * CONFIG_DETECT_HUNG_TASK, CONFIG_LOCKUP_DETECTOR,
1512 * CONFIG_LOCKDEP. Additionally, holding the lock too long
0c428a6a
SP
1513 * will also starve other vCPUs. We have to also make sure
1514 * that the page tables are not freed while we released
1515 * the lock.
c6473555 1516 */
0c428a6a
SP
1517 cond_resched_lock(&kvm->mmu_lock);
1518 if (!READ_ONCE(kvm->arch.pgd))
1519 break;
e55cac5b
SP
1520 next = stage2_pgd_addr_end(kvm, addr, end);
1521 if (stage2_pgd_present(kvm, *pgd))
1522 stage2_wp_puds(kvm, pgd, addr, next);
c6473555
MS
1523 } while (pgd++, addr = next, addr != end);
1524}
1525
1526/**
1527 * kvm_mmu_wp_memory_region() - write protect stage 2 entries for memory slot
1528 * @kvm: The KVM pointer
1529 * @slot: The memory slot to write protect
1530 *
1531 * Called to start logging dirty pages after memory region
1532 * KVM_MEM_LOG_DIRTY_PAGES operation is called. After this function returns
4ea5af53 1533 * all present PUD, PMD and PTEs are write protected in the memory region.
c6473555
MS
1534 * Afterwards read of dirty page log can be called.
1535 *
1536 * Acquires kvm_mmu_lock. Called with kvm->slots_lock mutex acquired,
1537 * serializing operations for VM memory regions.
1538 */
1539void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot)
1540{
9f6b8029
PB
1541 struct kvm_memslots *slots = kvm_memslots(kvm);
1542 struct kvm_memory_slot *memslot = id_to_memslot(slots, slot);
c6473555
MS
1543 phys_addr_t start = memslot->base_gfn << PAGE_SHIFT;
1544 phys_addr_t end = (memslot->base_gfn + memslot->npages) << PAGE_SHIFT;
1545
1546 spin_lock(&kvm->mmu_lock);
1547 stage2_wp_range(kvm, start, end);
1548 spin_unlock(&kvm->mmu_lock);
1549 kvm_flush_remote_tlbs(kvm);
1550}
53c810c3
MS
1551
1552/**
3b0f1d01 1553 * kvm_mmu_write_protect_pt_masked() - write protect dirty pages
53c810c3
MS
1554 * @kvm: The KVM pointer
1555 * @slot: The memory slot associated with mask
1556 * @gfn_offset: The gfn offset in memory slot
1557 * @mask: The mask of dirty pages at offset 'gfn_offset' in this memory
1558 * slot to be write protected
1559 *
1560 * Walks bits set in mask write protects the associated pte's. Caller must
1561 * acquire kvm_mmu_lock.
1562 */
3b0f1d01 1563static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
53c810c3
MS
1564 struct kvm_memory_slot *slot,
1565 gfn_t gfn_offset, unsigned long mask)
1566{
1567 phys_addr_t base_gfn = slot->base_gfn + gfn_offset;
1568 phys_addr_t start = (base_gfn + __ffs(mask)) << PAGE_SHIFT;
1569 phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT;
1570
1571 stage2_wp_range(kvm, start, end);
1572}
c6473555 1573
3b0f1d01
KH
1574/*
1575 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1576 * dirty pages.
1577 *
1578 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1579 * enable dirty logging for them.
1580 */
1581void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1582 struct kvm_memory_slot *slot,
1583 gfn_t gfn_offset, unsigned long mask)
1584{
1585 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1586}
1587
17ab9d57 1588static void clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)
0d3e4d4f 1589{
17ab9d57 1590 __clean_dcache_guest_page(pfn, size);
a15f6939
MZ
1591}
1592
17ab9d57 1593static void invalidate_icache_guest_page(kvm_pfn_t pfn, unsigned long size)
a15f6939 1594{
17ab9d57 1595 __invalidate_icache_guest_page(pfn, size);
0d3e4d4f
MZ
1596}
1597
1559b758 1598static void kvm_send_hwpoison_signal(unsigned long address, short lsb)
196f878a 1599{
795a8371 1600 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, lsb, current);
196f878a
JM
1601}
1602
a80868f3
SP
1603static bool fault_supports_stage2_huge_mapping(struct kvm_memory_slot *memslot,
1604 unsigned long hva,
1605 unsigned long map_size)
6794ad54 1606{
c2be79a0 1607 gpa_t gpa_start;
6794ad54
CD
1608 hva_t uaddr_start, uaddr_end;
1609 size_t size;
1610
1611 size = memslot->npages * PAGE_SIZE;
1612
1613 gpa_start = memslot->base_gfn << PAGE_SHIFT;
6794ad54
CD
1614
1615 uaddr_start = memslot->userspace_addr;
1616 uaddr_end = uaddr_start + size;
1617
1618 /*
1619 * Pages belonging to memslots that don't have the same alignment
a80868f3
SP
1620 * within a PMD/PUD for userspace and IPA cannot be mapped with stage-2
1621 * PMD/PUD entries, because we'll end up mapping the wrong pages.
6794ad54
CD
1622 *
1623 * Consider a layout like the following:
1624 *
1625 * memslot->userspace_addr:
1626 * +-----+--------------------+--------------------+---+
a80868f3 1627 * |abcde|fgh Stage-1 block | Stage-1 block tv|xyz|
6794ad54
CD
1628 * +-----+--------------------+--------------------+---+
1629 *
1630 * memslot->base_gfn << PAGE_SIZE:
1631 * +---+--------------------+--------------------+-----+
a80868f3 1632 * |abc|def Stage-2 block | Stage-2 block |tvxyz|
6794ad54
CD
1633 * +---+--------------------+--------------------+-----+
1634 *
a80868f3 1635 * If we create those stage-2 blocks, we'll end up with this incorrect
6794ad54
CD
1636 * mapping:
1637 * d -> f
1638 * e -> g
1639 * f -> h
1640 */
a80868f3 1641 if ((gpa_start & (map_size - 1)) != (uaddr_start & (map_size - 1)))
6794ad54
CD
1642 return false;
1643
1644 /*
1645 * Next, let's make sure we're not trying to map anything not covered
a80868f3
SP
1646 * by the memslot. This means we have to prohibit block size mappings
1647 * for the beginning and end of a non-block aligned and non-block sized
6794ad54
CD
1648 * memory slot (illustrated by the head and tail parts of the
1649 * userspace view above containing pages 'abcde' and 'xyz',
1650 * respectively).
1651 *
1652 * Note that it doesn't matter if we do the check using the
1653 * userspace_addr or the base_gfn, as both are equally aligned (per
1654 * the check above) and equally sized.
1655 */
a80868f3
SP
1656 return (hva & ~(map_size - 1)) >= uaddr_start &&
1657 (hva & ~(map_size - 1)) + map_size <= uaddr_end;
6794ad54
CD
1658}
1659
94f8e641 1660static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
98047888 1661 struct kvm_memory_slot *memslot, unsigned long hva,
94f8e641
CD
1662 unsigned long fault_status)
1663{
94f8e641 1664 int ret;
6396b852
PA
1665 bool write_fault, writable, force_pte = false;
1666 bool exec_fault, needs_exec;
94f8e641 1667 unsigned long mmu_seq;
ad361f09 1668 gfn_t gfn = fault_ipa >> PAGE_SHIFT;
ad361f09 1669 struct kvm *kvm = vcpu->kvm;
94f8e641 1670 struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
ad361f09 1671 struct vm_area_struct *vma;
1559b758 1672 short vma_shift;
ba049e93 1673 kvm_pfn_t pfn;
b8865767 1674 pgprot_t mem_type = PAGE_S2;
15a49a44 1675 bool logging_active = memslot_is_logging(memslot);
3f58bf63 1676 unsigned long vma_pagesize, flags = 0;
94f8e641 1677
a7d079ce 1678 write_fault = kvm_is_write_fault(vcpu);
d0e22b4a
MZ
1679 exec_fault = kvm_vcpu_trap_is_iabt(vcpu);
1680 VM_BUG_ON(write_fault && exec_fault);
1681
1682 if (fault_status == FSC_PERM && !write_fault && !exec_fault) {
94f8e641
CD
1683 kvm_err("Unexpected L2 read permission error\n");
1684 return -EFAULT;
1685 }
1686
ad361f09
CD
1687 /* Let's check if we will get back a huge page backed by hugetlbfs */
1688 down_read(&current->mm->mmap_sem);
1689 vma = find_vma_intersection(current->mm, hva, hva + 1);
37b54408
AB
1690 if (unlikely(!vma)) {
1691 kvm_err("Failed to find VMA for hva 0x%lx\n", hva);
1692 up_read(&current->mm->mmap_sem);
1693 return -EFAULT;
1694 }
1695
1559b758
JM
1696 if (is_vm_hugetlb_page(vma))
1697 vma_shift = huge_page_shift(hstate_vma(vma));
1698 else
1699 vma_shift = PAGE_SHIFT;
1700
1701 vma_pagesize = 1ULL << vma_shift;
a80868f3 1702 if (logging_active ||
6d674e28 1703 (vma->vm_flags & VM_PFNMAP) ||
a80868f3
SP
1704 !fault_supports_stage2_huge_mapping(memslot, hva, vma_pagesize)) {
1705 force_pte = true;
1706 vma_pagesize = PAGE_SIZE;
1707 }
1708
b8e0ba7c 1709 /*
280cebfd
SP
1710 * The stage2 has a minimum of 2 level table (For arm64 see
1711 * kvm_arm_setup_stage2()). Hence, we are guaranteed that we can
1712 * use PMD_SIZE huge mappings (even when the PMD is folded into PGD).
1713 * As for PUD huge maps, we must make sure that we have at least
1714 * 3 levels, i.e, PMD is not folded.
b8e0ba7c 1715 */
a80868f3
SP
1716 if (vma_pagesize == PMD_SIZE ||
1717 (vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm)))
b8e0ba7c 1718 gfn = (fault_ipa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT;
ad361f09
CD
1719 up_read(&current->mm->mmap_sem);
1720
94f8e641 1721 /* We need minimum second+third level pages */
e55cac5b 1722 ret = mmu_topup_memory_cache(memcache, kvm_mmu_cache_min_pages(kvm),
38f791a4 1723 KVM_NR_MEM_OBJS);
94f8e641
CD
1724 if (ret)
1725 return ret;
1726
1727 mmu_seq = vcpu->kvm->mmu_notifier_seq;
1728 /*
1729 * Ensure the read of mmu_notifier_seq happens before we call
1730 * gfn_to_pfn_prot (which calls get_user_pages), so that we don't risk
1731 * the page we just got a reference to gets unmapped before we have a
1732 * chance to grab the mmu_lock, which ensure that if the page gets
1733 * unmapped afterwards, the call to kvm_unmap_hva will take it away
1734 * from us again properly. This smp_rmb() interacts with the smp_wmb()
1735 * in kvm_mmu_notifier_invalidate_<page|range_end>.
1736 */
1737 smp_rmb();
1738
ad361f09 1739 pfn = gfn_to_pfn_prot(kvm, gfn, write_fault, &writable);
196f878a 1740 if (pfn == KVM_PFN_ERR_HWPOISON) {
1559b758 1741 kvm_send_hwpoison_signal(hva, vma_shift);
196f878a
JM
1742 return 0;
1743 }
9ac71595 1744 if (is_error_noslot_pfn(pfn))
94f8e641
CD
1745 return -EFAULT;
1746
15a49a44 1747 if (kvm_is_device_pfn(pfn)) {
b8865767 1748 mem_type = PAGE_S2_DEVICE;
15a49a44
MS
1749 flags |= KVM_S2PTE_FLAG_IS_IOMAP;
1750 } else if (logging_active) {
1751 /*
1752 * Faults on pages in a memslot with logging enabled
1753 * should not be mapped with huge pages (it introduces churn
1754 * and performance degradation), so force a pte mapping.
1755 */
15a49a44
MS
1756 flags |= KVM_S2_FLAG_LOGGING_ACTIVE;
1757
1758 /*
1759 * Only actually map the page as writable if this was a write
1760 * fault.
1761 */
1762 if (!write_fault)
1763 writable = false;
1764 }
b8865767 1765
6d674e28
MZ
1766 if (exec_fault && is_iomap(flags))
1767 return -ENOEXEC;
1768
ad361f09
CD
1769 spin_lock(&kvm->mmu_lock);
1770 if (mmu_notifier_retry(kvm, mmu_seq))
94f8e641 1771 goto out_unlock;
15a49a44 1772
3f58bf63
PA
1773 if (vma_pagesize == PAGE_SIZE && !force_pte) {
1774 /*
1775 * Only PMD_SIZE transparent hugepages(THP) are
1776 * currently supported. This code will need to be
1777 * updated to support other THP sizes.
2e8010bb
SP
1778 *
1779 * Make sure the host VA and the guest IPA are sufficiently
1780 * aligned and that the block is contained within the memslot.
3f58bf63 1781 */
2e8010bb
SP
1782 if (fault_supports_stage2_huge_mapping(memslot, hva, PMD_SIZE) &&
1783 transparent_hugepage_adjust(&pfn, &fault_ipa))
3f58bf63
PA
1784 vma_pagesize = PMD_SIZE;
1785 }
1786
1787 if (writable)
1788 kvm_set_pfn_dirty(pfn);
ad361f09 1789
6d674e28 1790 if (fault_status != FSC_PERM && !is_iomap(flags))
3f58bf63
PA
1791 clean_dcache_guest_page(pfn, vma_pagesize);
1792
1793 if (exec_fault)
1794 invalidate_icache_guest_page(pfn, vma_pagesize);
1795
6396b852
PA
1796 /*
1797 * If we took an execution fault we have made the
1798 * icache/dcache coherent above and should now let the s2
1799 * mapping be executable.
1800 *
1801 * Write faults (!exec_fault && FSC_PERM) are orthogonal to
1802 * execute permissions, and we preserve whatever we have.
1803 */
1804 needs_exec = exec_fault ||
1805 (fault_status == FSC_PERM && stage2_is_exec(kvm, fault_ipa));
1806
b8e0ba7c
PA
1807 if (vma_pagesize == PUD_SIZE) {
1808 pud_t new_pud = kvm_pfn_pud(pfn, mem_type);
1809
1810 new_pud = kvm_pud_mkhuge(new_pud);
1811 if (writable)
1812 new_pud = kvm_s2pud_mkwrite(new_pud);
1813
1814 if (needs_exec)
1815 new_pud = kvm_s2pud_mkexec(new_pud);
1816
1817 ret = stage2_set_pud_huge(kvm, memcache, fault_ipa, &new_pud);
1818 } else if (vma_pagesize == PMD_SIZE) {
f8df7338
PA
1819 pmd_t new_pmd = kvm_pfn_pmd(pfn, mem_type);
1820
1821 new_pmd = kvm_pmd_mkhuge(new_pmd);
1822
3f58bf63 1823 if (writable)
06485053 1824 new_pmd = kvm_s2pmd_mkwrite(new_pmd);
d0e22b4a 1825
6396b852 1826 if (needs_exec)
d0e22b4a 1827 new_pmd = kvm_s2pmd_mkexec(new_pmd);
a15f6939 1828
ad361f09
CD
1829 ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);
1830 } else {
f8df7338 1831 pte_t new_pte = kvm_pfn_pte(pfn, mem_type);
15a49a44 1832
ad361f09 1833 if (writable) {
06485053 1834 new_pte = kvm_s2pte_mkwrite(new_pte);
15a49a44 1835 mark_page_dirty(kvm, gfn);
ad361f09 1836 }
a9c0e12e 1837
6396b852 1838 if (needs_exec)
d0e22b4a 1839 new_pte = kvm_s2pte_mkexec(new_pte);
a15f6939 1840
15a49a44 1841 ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, flags);
94f8e641 1842 }
ad361f09 1843
94f8e641 1844out_unlock:
ad361f09 1845 spin_unlock(&kvm->mmu_lock);
35307b9a 1846 kvm_set_pfn_accessed(pfn);
94f8e641 1847 kvm_release_pfn_clean(pfn);
ad361f09 1848 return ret;
94f8e641
CD
1849}
1850
aeda9130
MZ
1851/*
1852 * Resolve the access fault by making the page young again.
1853 * Note that because the faulting entry is guaranteed not to be
1854 * cached in the TLB, we don't need to invalidate anything.
06485053
CM
1855 * Only the HW Access Flag updates are supported for Stage 2 (no DBM),
1856 * so there is no need for atomic (pte|pmd)_mkyoung operations.
aeda9130
MZ
1857 */
1858static void handle_access_fault(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa)
1859{
eb3f0624 1860 pud_t *pud;
aeda9130
MZ
1861 pmd_t *pmd;
1862 pte_t *pte;
ba049e93 1863 kvm_pfn_t pfn;
aeda9130
MZ
1864 bool pfn_valid = false;
1865
1866 trace_kvm_access_fault(fault_ipa);
1867
1868 spin_lock(&vcpu->kvm->mmu_lock);
1869
eb3f0624 1870 if (!stage2_get_leaf_entry(vcpu->kvm, fault_ipa, &pud, &pmd, &pte))
aeda9130
MZ
1871 goto out;
1872
eb3f0624
PA
1873 if (pud) { /* HugeTLB */
1874 *pud = kvm_s2pud_mkyoung(*pud);
1875 pfn = kvm_pud_pfn(*pud);
1876 pfn_valid = true;
1877 } else if (pmd) { /* THP, HugeTLB */
aeda9130
MZ
1878 *pmd = pmd_mkyoung(*pmd);
1879 pfn = pmd_pfn(*pmd);
1880 pfn_valid = true;
eb3f0624
PA
1881 } else {
1882 *pte = pte_mkyoung(*pte); /* Just a page... */
1883 pfn = pte_pfn(*pte);
1884 pfn_valid = true;
aeda9130
MZ
1885 }
1886
aeda9130
MZ
1887out:
1888 spin_unlock(&vcpu->kvm->mmu_lock);
1889 if (pfn_valid)
1890 kvm_set_pfn_accessed(pfn);
1891}
1892
94f8e641
CD
1893/**
1894 * kvm_handle_guest_abort - handles all 2nd stage aborts
1895 * @vcpu: the VCPU pointer
1896 * @run: the kvm_run structure
1897 *
1898 * Any abort that gets to the host is almost guaranteed to be caused by a
1899 * missing second stage translation table entry, which can mean that either the
1900 * guest simply needs more memory and we must allocate an appropriate page or it
1901 * can mean that the guest tried to access I/O memory, which is emulated by user
1902 * space. The distinction is based on the IPA causing the fault and whether this
1903 * memory region has been registered as standard RAM by user space.
1904 */
342cd0ab
CD
1905int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
1906{
94f8e641
CD
1907 unsigned long fault_status;
1908 phys_addr_t fault_ipa;
1909 struct kvm_memory_slot *memslot;
98047888
CD
1910 unsigned long hva;
1911 bool is_iabt, write_fault, writable;
94f8e641
CD
1912 gfn_t gfn;
1913 int ret, idx;
1914
621f48e4
TB
1915 fault_status = kvm_vcpu_trap_get_fault_type(vcpu);
1916
1917 fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
bb428921 1918 is_iabt = kvm_vcpu_trap_is_iabt(vcpu);
621f48e4 1919
bb428921
JM
1920 /* Synchronous External Abort? */
1921 if (kvm_vcpu_dabt_isextabt(vcpu)) {
1922 /*
1923 * For RAS the host kernel may handle this abort.
1924 * There is no need to pass the error into the guest.
1925 */
0db5e022 1926 if (!kvm_handle_guest_sea(fault_ipa, kvm_vcpu_get_hsr(vcpu)))
621f48e4 1927 return 1;
621f48e4 1928
bb428921
JM
1929 if (unlikely(!is_iabt)) {
1930 kvm_inject_vabt(vcpu);
1931 return 1;
1932 }
4055710b
MZ
1933 }
1934
7393b599
MZ
1935 trace_kvm_guest_fault(*vcpu_pc(vcpu), kvm_vcpu_get_hsr(vcpu),
1936 kvm_vcpu_get_hfar(vcpu), fault_ipa);
94f8e641
CD
1937
1938 /* Check the stage-2 fault is trans. fault or write fault */
35307b9a
MZ
1939 if (fault_status != FSC_FAULT && fault_status != FSC_PERM &&
1940 fault_status != FSC_ACCESS) {
0496daa5
CD
1941 kvm_err("Unsupported FSC: EC=%#x xFSC=%#lx ESR_EL2=%#lx\n",
1942 kvm_vcpu_trap_get_class(vcpu),
1943 (unsigned long)kvm_vcpu_trap_get_fault(vcpu),
1944 (unsigned long)kvm_vcpu_get_hsr(vcpu));
94f8e641
CD
1945 return -EFAULT;
1946 }
1947
1948 idx = srcu_read_lock(&vcpu->kvm->srcu);
1949
1950 gfn = fault_ipa >> PAGE_SHIFT;
98047888
CD
1951 memslot = gfn_to_memslot(vcpu->kvm, gfn);
1952 hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable);
a7d079ce 1953 write_fault = kvm_is_write_fault(vcpu);
98047888 1954 if (kvm_is_error_hva(hva) || (write_fault && !writable)) {
94f8e641
CD
1955 if (is_iabt) {
1956 /* Prefetch Abort on I/O address */
6d674e28
MZ
1957 ret = -ENOEXEC;
1958 goto out;
94f8e641
CD
1959 }
1960
57c841f1
MZ
1961 /*
1962 * Check for a cache maintenance operation. Since we
1963 * ended-up here, we know it is outside of any memory
1964 * slot. But we can't find out if that is for a device,
1965 * or if the guest is just being stupid. The only thing
1966 * we know for sure is that this range cannot be cached.
1967 *
1968 * So let's assume that the guest is just being
1969 * cautious, and skip the instruction.
1970 */
1971 if (kvm_vcpu_dabt_is_cm(vcpu)) {
1972 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1973 ret = 1;
1974 goto out_unlock;
1975 }
1976
cfe3950c
MZ
1977 /*
1978 * The IPA is reported as [MAX:12], so we need to
1979 * complement it with the bottom 12 bits from the
1980 * faulting VA. This is always 12 bits, irrespective
1981 * of the page size.
1982 */
1983 fault_ipa |= kvm_vcpu_get_hfar(vcpu) & ((1 << 12) - 1);
45e96ea6 1984 ret = io_mem_abort(vcpu, run, fault_ipa);
94f8e641
CD
1985 goto out_unlock;
1986 }
1987
c3058d5d 1988 /* Userspace should not be able to register out-of-bounds IPAs */
e55cac5b 1989 VM_BUG_ON(fault_ipa >= kvm_phys_size(vcpu->kvm));
c3058d5d 1990
aeda9130
MZ
1991 if (fault_status == FSC_ACCESS) {
1992 handle_access_fault(vcpu, fault_ipa);
1993 ret = 1;
1994 goto out_unlock;
1995 }
1996
98047888 1997 ret = user_mem_abort(vcpu, fault_ipa, memslot, hva, fault_status);
94f8e641
CD
1998 if (ret == 0)
1999 ret = 1;
6d674e28
MZ
2000out:
2001 if (ret == -ENOEXEC) {
2002 kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
2003 ret = 1;
2004 }
94f8e641
CD
2005out_unlock:
2006 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2007 return ret;
342cd0ab
CD
2008}
2009
1d2ebacc
MZ
2010static int handle_hva_to_gpa(struct kvm *kvm,
2011 unsigned long start,
2012 unsigned long end,
2013 int (*handler)(struct kvm *kvm,
056aad67
SP
2014 gpa_t gpa, u64 size,
2015 void *data),
1d2ebacc 2016 void *data)
d5d8184d
CD
2017{
2018 struct kvm_memslots *slots;
2019 struct kvm_memory_slot *memslot;
1d2ebacc 2020 int ret = 0;
d5d8184d
CD
2021
2022 slots = kvm_memslots(kvm);
2023
2024 /* we only care about the pages that the guest sees */
2025 kvm_for_each_memslot(memslot, slots) {
2026 unsigned long hva_start, hva_end;
056aad67 2027 gfn_t gpa;
d5d8184d
CD
2028
2029 hva_start = max(start, memslot->userspace_addr);
2030 hva_end = min(end, memslot->userspace_addr +
2031 (memslot->npages << PAGE_SHIFT));
2032 if (hva_start >= hva_end)
2033 continue;
2034
056aad67
SP
2035 gpa = hva_to_gfn_memslot(hva_start, memslot) << PAGE_SHIFT;
2036 ret |= handler(kvm, gpa, (u64)(hva_end - hva_start), data);
d5d8184d 2037 }
1d2ebacc
MZ
2038
2039 return ret;
d5d8184d
CD
2040}
2041
056aad67 2042static int kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data)
d5d8184d 2043{
056aad67 2044 unmap_stage2_range(kvm, gpa, size);
1d2ebacc 2045 return 0;
d5d8184d
CD
2046}
2047
d5d8184d
CD
2048int kvm_unmap_hva_range(struct kvm *kvm,
2049 unsigned long start, unsigned long end)
2050{
2051 if (!kvm->arch.pgd)
2052 return 0;
2053
2054 trace_kvm_unmap_hva_range(start, end);
2055 handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL);
2056 return 0;
2057}
2058
056aad67 2059static int kvm_set_spte_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data)
d5d8184d
CD
2060{
2061 pte_t *pte = (pte_t *)data;
2062
056aad67 2063 WARN_ON(size != PAGE_SIZE);
15a49a44
MS
2064 /*
2065 * We can always call stage2_set_pte with KVM_S2PTE_FLAG_LOGGING_ACTIVE
2066 * flag clear because MMU notifiers will have unmapped a huge PMD before
2067 * calling ->change_pte() (which in turn calls kvm_set_spte_hva()) and
2068 * therefore stage2_set_pte() never needs to clear out a huge PMD
2069 * through this calling path.
2070 */
2071 stage2_set_pte(kvm, NULL, gpa, pte, 0);
1d2ebacc 2072 return 0;
d5d8184d
CD
2073}
2074
2075
748c0e31 2076int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
d5d8184d
CD
2077{
2078 unsigned long end = hva + PAGE_SIZE;
694556d5 2079 kvm_pfn_t pfn = pte_pfn(pte);
d5d8184d
CD
2080 pte_t stage2_pte;
2081
2082 if (!kvm->arch.pgd)
748c0e31 2083 return 0;
d5d8184d
CD
2084
2085 trace_kvm_set_spte_hva(hva);
694556d5
MZ
2086
2087 /*
2088 * We've moved a page around, probably through CoW, so let's treat it
2089 * just like a translation fault and clean the cache to the PoC.
2090 */
2091 clean_dcache_guest_page(pfn, PAGE_SIZE);
f8df7338 2092 stage2_pte = kvm_pfn_pte(pfn, PAGE_S2);
d5d8184d 2093 handle_hva_to_gpa(kvm, hva, end, &kvm_set_spte_handler, &stage2_pte);
748c0e31
LT
2094
2095 return 0;
d5d8184d
CD
2096}
2097
056aad67 2098static int kvm_age_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data)
35307b9a 2099{
35a63966 2100 pud_t *pud;
35307b9a
MZ
2101 pmd_t *pmd;
2102 pte_t *pte;
2103
35a63966
PA
2104 WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE);
2105 if (!stage2_get_leaf_entry(kvm, gpa, &pud, &pmd, &pte))
35307b9a
MZ
2106 return 0;
2107
35a63966
PA
2108 if (pud)
2109 return stage2_pudp_test_and_clear_young(pud);
2110 else if (pmd)
06485053 2111 return stage2_pmdp_test_and_clear_young(pmd);
35a63966
PA
2112 else
2113 return stage2_ptep_test_and_clear_young(pte);
35307b9a
MZ
2114}
2115
056aad67 2116static int kvm_test_age_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data)
35307b9a 2117{
35a63966 2118 pud_t *pud;
35307b9a
MZ
2119 pmd_t *pmd;
2120 pte_t *pte;
2121
35a63966
PA
2122 WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE);
2123 if (!stage2_get_leaf_entry(kvm, gpa, &pud, &pmd, &pte))
35307b9a
MZ
2124 return 0;
2125
35a63966
PA
2126 if (pud)
2127 return kvm_s2pud_young(*pud);
2128 else if (pmd)
35307b9a 2129 return pmd_young(*pmd);
35a63966 2130 else
35307b9a 2131 return pte_young(*pte);
35307b9a
MZ
2132}
2133
2134int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
2135{
7e5a6722
SP
2136 if (!kvm->arch.pgd)
2137 return 0;
35307b9a
MZ
2138 trace_kvm_age_hva(start, end);
2139 return handle_hva_to_gpa(kvm, start, end, kvm_age_hva_handler, NULL);
2140}
2141
2142int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
2143{
7e5a6722
SP
2144 if (!kvm->arch.pgd)
2145 return 0;
35307b9a
MZ
2146 trace_kvm_test_age_hva(hva);
2147 return handle_hva_to_gpa(kvm, hva, hva, kvm_test_age_hva_handler, NULL);
2148}
2149
d5d8184d
CD
2150void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu)
2151{
2152 mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
2153}
2154
342cd0ab
CD
2155phys_addr_t kvm_mmu_get_httbr(void)
2156{
e4c5a685
AB
2157 if (__kvm_cpu_uses_extended_idmap())
2158 return virt_to_phys(merged_hyp_pgd);
2159 else
2160 return virt_to_phys(hyp_pgd);
342cd0ab
CD
2161}
2162
5a677ce0
MZ
2163phys_addr_t kvm_get_idmap_vector(void)
2164{
2165 return hyp_idmap_vector;
2166}
2167
0535a3e2
MZ
2168static int kvm_map_idmap_text(pgd_t *pgd)
2169{
2170 int err;
2171
2172 /* Create the idmap in the boot page tables */
98732d1b 2173 err = __create_hyp_mappings(pgd, __kvm_idmap_ptrs_per_pgd(),
0535a3e2
MZ
2174 hyp_idmap_start, hyp_idmap_end,
2175 __phys_to_pfn(hyp_idmap_start),
2176 PAGE_HYP_EXEC);
2177 if (err)
2178 kvm_err("Failed to idmap %lx-%lx\n",
2179 hyp_idmap_start, hyp_idmap_end);
2180
2181 return err;
2182}
2183
342cd0ab
CD
2184int kvm_mmu_init(void)
2185{
2fb41059
MZ
2186 int err;
2187
4fda342c 2188 hyp_idmap_start = kvm_virt_to_phys(__hyp_idmap_text_start);
46fef158 2189 hyp_idmap_start = ALIGN_DOWN(hyp_idmap_start, PAGE_SIZE);
4fda342c 2190 hyp_idmap_end = kvm_virt_to_phys(__hyp_idmap_text_end);
46fef158 2191 hyp_idmap_end = ALIGN(hyp_idmap_end, PAGE_SIZE);
4fda342c 2192 hyp_idmap_vector = kvm_virt_to_phys(__kvm_hyp_init);
5a677ce0 2193
06f75a1f
AB
2194 /*
2195 * We rely on the linker script to ensure at build time that the HYP
2196 * init code does not cross a page boundary.
2197 */
2198 BUG_ON((hyp_idmap_start ^ (hyp_idmap_end - 1)) & PAGE_MASK);
5a677ce0 2199
b4ef0499
MZ
2200 kvm_debug("IDMAP page: %lx\n", hyp_idmap_start);
2201 kvm_debug("HYP VA range: %lx:%lx\n",
2202 kern_hyp_va(PAGE_OFFSET),
2203 kern_hyp_va((unsigned long)high_memory - 1));
eac378a9 2204
6c41a413 2205 if (hyp_idmap_start >= kern_hyp_va(PAGE_OFFSET) &&
ed57cac8 2206 hyp_idmap_start < kern_hyp_va((unsigned long)high_memory - 1) &&
d2896d4b 2207 hyp_idmap_start != (unsigned long)__hyp_idmap_text_start) {
eac378a9
MZ
2208 /*
2209 * The idmap page is intersecting with the VA space,
2210 * it is not safe to continue further.
2211 */
2212 kvm_err("IDMAP intersecting with HYP VA, unable to continue\n");
2213 err = -EINVAL;
2214 goto out;
2215 }
2216
38f791a4 2217 hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, hyp_pgd_order);
0535a3e2 2218 if (!hyp_pgd) {
d5d8184d 2219 kvm_err("Hyp mode PGD not allocated\n");
2fb41059
MZ
2220 err = -ENOMEM;
2221 goto out;
2222 }
2223
0535a3e2
MZ
2224 if (__kvm_cpu_uses_extended_idmap()) {
2225 boot_hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2226 hyp_pgd_order);
2227 if (!boot_hyp_pgd) {
2228 kvm_err("Hyp boot PGD not allocated\n");
2229 err = -ENOMEM;
2230 goto out;
2231 }
2fb41059 2232
0535a3e2
MZ
2233 err = kvm_map_idmap_text(boot_hyp_pgd);
2234 if (err)
2235 goto out;
d5d8184d 2236
e4c5a685
AB
2237 merged_hyp_pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
2238 if (!merged_hyp_pgd) {
2239 kvm_err("Failed to allocate extra HYP pgd\n");
2240 goto out;
2241 }
2242 __kvm_extend_hypmap(boot_hyp_pgd, hyp_pgd, merged_hyp_pgd,
2243 hyp_idmap_start);
0535a3e2
MZ
2244 } else {
2245 err = kvm_map_idmap_text(hyp_pgd);
2246 if (err)
2247 goto out;
5a677ce0
MZ
2248 }
2249
e3f019b3 2250 io_map_base = hyp_idmap_start;
d5d8184d 2251 return 0;
2fb41059 2252out:
4f728276 2253 free_hyp_pgds();
2fb41059 2254 return err;
342cd0ab 2255}
df6ce24f
EA
2256
2257void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 2258 const struct kvm_userspace_memory_region *mem,
df6ce24f 2259 const struct kvm_memory_slot *old,
f36f3f28 2260 const struct kvm_memory_slot *new,
df6ce24f
EA
2261 enum kvm_mr_change change)
2262{
c6473555
MS
2263 /*
2264 * At this point memslot has been committed and there is an
2265 * allocated dirty_bitmap[], dirty pages will be be tracked while the
2266 * memory slot is write protected.
2267 */
2268 if (change != KVM_MR_DELETE && mem->flags & KVM_MEM_LOG_DIRTY_PAGES)
2269 kvm_mmu_wp_memory_region(kvm, mem->slot);
df6ce24f
EA
2270}
2271
2272int kvm_arch_prepare_memory_region(struct kvm *kvm,
2273 struct kvm_memory_slot *memslot,
09170a49 2274 const struct kvm_userspace_memory_region *mem,
df6ce24f
EA
2275 enum kvm_mr_change change)
2276{
8eef9123
AB
2277 hva_t hva = mem->userspace_addr;
2278 hva_t reg_end = hva + mem->memory_size;
2279 bool writable = !(mem->flags & KVM_MEM_READONLY);
2280 int ret = 0;
2281
15a49a44
MS
2282 if (change != KVM_MR_CREATE && change != KVM_MR_MOVE &&
2283 change != KVM_MR_FLAGS_ONLY)
8eef9123
AB
2284 return 0;
2285
c3058d5d
CD
2286 /*
2287 * Prevent userspace from creating a memory region outside of the IPA
2288 * space addressable by the KVM guest IPA space.
2289 */
2290 if (memslot->base_gfn + memslot->npages >=
e55cac5b 2291 (kvm_phys_size(kvm) >> PAGE_SHIFT))
c3058d5d
CD
2292 return -EFAULT;
2293
72f31048 2294 down_read(&current->mm->mmap_sem);
8eef9123
AB
2295 /*
2296 * A memory region could potentially cover multiple VMAs, and any holes
2297 * between them, so iterate over all of them to find out if we can map
2298 * any of them right now.
2299 *
2300 * +--------------------------------------------+
2301 * +---------------+----------------+ +----------------+
2302 * | : VMA 1 | VMA 2 | | VMA 3 : |
2303 * +---------------+----------------+ +----------------+
2304 * | memory region |
2305 * +--------------------------------------------+
2306 */
2307 do {
2308 struct vm_area_struct *vma = find_vma(current->mm, hva);
2309 hva_t vm_start, vm_end;
2310
2311 if (!vma || vma->vm_start >= reg_end)
2312 break;
2313
8eef9123
AB
2314 /*
2315 * Take the intersection of this VMA with the memory region
2316 */
2317 vm_start = max(hva, vma->vm_start);
2318 vm_end = min(reg_end, vma->vm_end);
2319
2320 if (vma->vm_flags & VM_PFNMAP) {
2321 gpa_t gpa = mem->guest_phys_addr +
2322 (vm_start - mem->userspace_addr);
ca09f02f
MM
2323 phys_addr_t pa;
2324
2325 pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
2326 pa += vm_start - vma->vm_start;
8eef9123 2327
15a49a44 2328 /* IO region dirty page logging not allowed */
72f31048
MZ
2329 if (memslot->flags & KVM_MEM_LOG_DIRTY_PAGES) {
2330 ret = -EINVAL;
2331 goto out;
2332 }
15a49a44 2333
8eef9123
AB
2334 ret = kvm_phys_addr_ioremap(kvm, gpa, pa,
2335 vm_end - vm_start,
2336 writable);
2337 if (ret)
2338 break;
2339 }
2340 hva = vm_end;
2341 } while (hva < reg_end);
2342
15a49a44 2343 if (change == KVM_MR_FLAGS_ONLY)
72f31048 2344 goto out;
15a49a44 2345
849260c7
AB
2346 spin_lock(&kvm->mmu_lock);
2347 if (ret)
8eef9123 2348 unmap_stage2_range(kvm, mem->guest_phys_addr, mem->memory_size);
849260c7
AB
2349 else
2350 stage2_flush_memslot(kvm, memslot);
2351 spin_unlock(&kvm->mmu_lock);
72f31048
MZ
2352out:
2353 up_read(&current->mm->mmap_sem);
8eef9123 2354 return ret;
df6ce24f
EA
2355}
2356
2357void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
2358 struct kvm_memory_slot *dont)
2359{
2360}
2361
2362int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
2363 unsigned long npages)
2364{
2365 return 0;
2366}
2367
15248258 2368void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
df6ce24f
EA
2369{
2370}
2371
2372void kvm_arch_flush_shadow_all(struct kvm *kvm)
2373{
293f2936 2374 kvm_free_stage2_pgd(kvm);
df6ce24f
EA
2375}
2376
2377void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
2378 struct kvm_memory_slot *slot)
2379{
8eef9123
AB
2380 gpa_t gpa = slot->base_gfn << PAGE_SHIFT;
2381 phys_addr_t size = slot->npages << PAGE_SHIFT;
2382
2383 spin_lock(&kvm->mmu_lock);
2384 unmap_stage2_range(kvm, gpa, size);
2385 spin_unlock(&kvm->mmu_lock);
df6ce24f 2386}
3c1e7165
MZ
2387
2388/*
2389 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
2390 *
2391 * Main problems:
2392 * - S/W ops are local to a CPU (not broadcast)
2393 * - We have line migration behind our back (speculation)
2394 * - System caches don't support S/W at all (damn!)
2395 *
2396 * In the face of the above, the best we can do is to try and convert
2397 * S/W ops to VA ops. Because the guest is not allowed to infer the
2398 * S/W to PA mapping, it can only use S/W to nuke the whole cache,
2399 * which is a rather good thing for us.
2400 *
2401 * Also, it is only used when turning caches on/off ("The expected
2402 * usage of the cache maintenance instructions that operate by set/way
2403 * is associated with the cache maintenance instructions associated
2404 * with the powerdown and powerup of caches, if this is required by
2405 * the implementation.").
2406 *
2407 * We use the following policy:
2408 *
2409 * - If we trap a S/W operation, we enable VM trapping to detect
2410 * caches being turned on/off, and do a full clean.
2411 *
2412 * - We flush the caches on both caches being turned on and off.
2413 *
2414 * - Once the caches are enabled, we stop trapping VM ops.
2415 */
2416void kvm_set_way_flush(struct kvm_vcpu *vcpu)
2417{
3df59d8d 2418 unsigned long hcr = *vcpu_hcr(vcpu);
3c1e7165
MZ
2419
2420 /*
2421 * If this is the first time we do a S/W operation
2422 * (i.e. HCR_TVM not set) flush the whole memory, and set the
2423 * VM trapping.
2424 *
2425 * Otherwise, rely on the VM trapping to wait for the MMU +
2426 * Caches to be turned off. At that point, we'll be able to
2427 * clean the caches again.
2428 */
2429 if (!(hcr & HCR_TVM)) {
2430 trace_kvm_set_way_flush(*vcpu_pc(vcpu),
2431 vcpu_has_cache_enabled(vcpu));
2432 stage2_flush_vm(vcpu->kvm);
3df59d8d 2433 *vcpu_hcr(vcpu) = hcr | HCR_TVM;
3c1e7165
MZ
2434 }
2435}
2436
2437void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled)
2438{
2439 bool now_enabled = vcpu_has_cache_enabled(vcpu);
2440
2441 /*
2442 * If switching the MMU+caches on, need to invalidate the caches.
2443 * If switching it off, need to clean the caches.
2444 * Clean + invalidate does the trick always.
2445 */
2446 if (now_enabled != was_enabled)
2447 stage2_flush_vm(vcpu->kvm);
2448
2449 /* Caches are now on, stop trapping VM ops (until a S/W op) */
2450 if (now_enabled)
3df59d8d 2451 *vcpu_hcr(vcpu) &= ~HCR_TVM;
3c1e7165
MZ
2452
2453 trace_kvm_toggle_cache(*vcpu_pc(vcpu), was_enabled, now_enabled);
2454}