[linux-2.6-block.git] / tools / testing / selftests / kvm / aarch64 / arch_timer.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * The test validates both the virtual and physical timer IRQs using
 * CVAL and TVAL registers.
 *
 * Copyright (c) 2021, Google LLC.
 */
#define _GNU_SOURCE

#include "arch_timer.h"
#include "delay.h"
#include "gic.h"
#include "processor.h"
#include "timer_test.h"
#include "vgic.h"

#define GICD_BASE_GPA			0x8000000ULL
#define GICR_BASE_GPA			0x80A0000ULL

enum guest_stage {
	GUEST_STAGE_VTIMER_CVAL = 1,
	GUEST_STAGE_VTIMER_TVAL,
	GUEST_STAGE_PTIMER_CVAL,
	GUEST_STAGE_PTIMER_TVAL,
	GUEST_STAGE_MAX,
};

static int vtimer_irq, ptimer_irq;

static void
guest_configure_timer_action(struct test_vcpu_shared_data *shared_data)
{
	switch (shared_data->guest_stage) {
	case GUEST_STAGE_VTIMER_CVAL:
		timer_set_next_cval_ms(VIRTUAL, test_args.timer_period_ms);
		shared_data->xcnt = timer_get_cntct(VIRTUAL);
		timer_set_ctl(VIRTUAL, CTL_ENABLE);
		break;
	case GUEST_STAGE_VTIMER_TVAL:
		timer_set_next_tval_ms(VIRTUAL, test_args.timer_period_ms);
		shared_data->xcnt = timer_get_cntct(VIRTUAL);
		timer_set_ctl(VIRTUAL, CTL_ENABLE);
		break;
	case GUEST_STAGE_PTIMER_CVAL:
		timer_set_next_cval_ms(PHYSICAL, test_args.timer_period_ms);
		shared_data->xcnt = timer_get_cntct(PHYSICAL);
		timer_set_ctl(PHYSICAL, CTL_ENABLE);
		break;
	case GUEST_STAGE_PTIMER_TVAL:
		timer_set_next_tval_ms(PHYSICAL, test_args.timer_period_ms);
		shared_data->xcnt = timer_get_cntct(PHYSICAL);
		timer_set_ctl(PHYSICAL, CTL_ENABLE);
		break;
	default:
		GUEST_ASSERT(0);
	}
}

static void guest_validate_irq(unsigned int intid,
				struct test_vcpu_shared_data *shared_data)
{
	enum guest_stage stage = shared_data->guest_stage;
	uint64_t xcnt = 0, xcnt_diff_us, cval = 0;
	unsigned long xctl = 0;
	unsigned int timer_irq = 0;
	unsigned int accessor;

	if (intid == IAR_SPURIOUS)
		return;

	switch (stage) {
	case GUEST_STAGE_VTIMER_CVAL:
	case GUEST_STAGE_VTIMER_TVAL:
		accessor = VIRTUAL;
		timer_irq = vtimer_irq;
		break;
	case GUEST_STAGE_PTIMER_CVAL:
	case GUEST_STAGE_PTIMER_TVAL:
		accessor = PHYSICAL;
		timer_irq = ptimer_irq;
		break;
	default:
		GUEST_ASSERT(0);
		return;
	}

	xctl = timer_get_ctl(accessor);
	if ((xctl & CTL_IMASK) || !(xctl & CTL_ENABLE))
		return;

	timer_set_ctl(accessor, CTL_IMASK);
	xcnt = timer_get_cntct(accessor);
	cval = timer_get_cval(accessor);

	xcnt_diff_us = cycles_to_usec(xcnt - shared_data->xcnt);

	/* Make sure we are dealing with the correct timer IRQ */
	GUEST_ASSERT_EQ(intid, timer_irq);

	/* Basic 'timer condition met' check */
	__GUEST_ASSERT(xcnt >= cval,
		       "xcnt = 0x%lx, cval = 0x%lx, xcnt_diff_us = 0x%lx",
		       xcnt, cval, xcnt_diff_us);
	__GUEST_ASSERT(xctl & CTL_ISTATUS, "xctl = 0x%lx", xctl);

	WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1);
}

static void guest_irq_handler(struct ex_regs *regs)
{
	unsigned int intid = gic_get_and_ack_irq();
	uint32_t cpu = guest_get_vcpuid();
	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];

	guest_validate_irq(intid, shared_data);

	gic_set_eoi(intid);
}

static void guest_run_stage(struct test_vcpu_shared_data *shared_data,
				enum guest_stage stage)
{
	uint32_t irq_iter, config_iter;

	shared_data->guest_stage = stage;
	shared_data->nr_iter = 0;

	for (config_iter = 0; config_iter < test_args.nr_iter; config_iter++) {
		/* Setup the next interrupt */
		guest_configure_timer_action(shared_data);

		/* Setup a timeout for the interrupt to arrive */
		udelay(msecs_to_usecs(test_args.timer_period_ms) +
			test_args.timer_err_margin_us);

		irq_iter = READ_ONCE(shared_data->nr_iter);
		__GUEST_ASSERT(config_iter + 1 == irq_iter,
				"config_iter + 1 = 0x%lx, irq_iter = 0x%lx.\n"
				"  Guest timer interrupt was not trigged within the specified\n"
				"  interval, try to increase the error margin by [-e] option.\n",
				config_iter + 1, irq_iter);
	}
}

static void guest_code(void)
{
	uint32_t cpu = guest_get_vcpuid();
	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];

	local_irq_disable();

	gic_init(GIC_V3, test_args.nr_vcpus,
		(void *)GICD_BASE_GPA, (void *)GICR_BASE_GPA);

	timer_set_ctl(VIRTUAL, CTL_IMASK);
	timer_set_ctl(PHYSICAL, CTL_IMASK);

	gic_irq_enable(vtimer_irq);
	gic_irq_enable(ptimer_irq);
	local_irq_enable();

	guest_run_stage(shared_data, GUEST_STAGE_VTIMER_CVAL);
	guest_run_stage(shared_data, GUEST_STAGE_VTIMER_TVAL);
	guest_run_stage(shared_data, GUEST_STAGE_PTIMER_CVAL);
	guest_run_stage(shared_data, GUEST_STAGE_PTIMER_TVAL);

	GUEST_DONE();
}

static void test_init_timer_irq(struct kvm_vm *vm)
{
	/* Timer initid should be same for all the vCPUs, so query only vCPU-0 */
	vcpu_device_attr_get(vcpus[0], KVM_ARM_VCPU_TIMER_CTRL,
			     KVM_ARM_VCPU_TIMER_IRQ_PTIMER, &ptimer_irq);
	vcpu_device_attr_get(vcpus[0], KVM_ARM_VCPU_TIMER_CTRL,
			     KVM_ARM_VCPU_TIMER_IRQ_VTIMER, &vtimer_irq);

	sync_global_to_guest(vm, ptimer_irq);
	sync_global_to_guest(vm, vtimer_irq);

	pr_debug("ptimer_irq: %d; vtimer_irq: %d\n", ptimer_irq, vtimer_irq);
}

static int gic_fd;

struct kvm_vm *test_vm_create(void)
{
	struct kvm_vm *vm;
	unsigned int i;
	int nr_vcpus = test_args.nr_vcpus;

	vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus);

	vm_init_descriptor_tables(vm);
	vm_install_exception_handler(vm, VECTOR_IRQ_CURRENT, guest_irq_handler);

	if (!test_args.reserved) {
		if (kvm_has_cap(KVM_CAP_COUNTER_OFFSET)) {
			struct kvm_arm_counter_offset offset = {
				.counter_offset = test_args.counter_offset,
				.reserved = 0,
			};
			vm_ioctl(vm, KVM_ARM_SET_COUNTER_OFFSET, &offset);
		} else
			TEST_FAIL("no support for global offset");
	}

	for (i = 0; i < nr_vcpus; i++)
		vcpu_init_descriptor_tables(vcpus[i]);

	test_init_timer_irq(vm);
	gic_fd = vgic_v3_setup(vm, nr_vcpus, 64, GICD_BASE_GPA, GICR_BASE_GPA);
	__TEST_REQUIRE(gic_fd >= 0, "Failed to create vgic-v3");

	/* Make all the test's cmdline args visible to the guest */
	sync_global_to_guest(vm, test_args);

	return vm;
}

void test_vm_cleanup(struct kvm_vm *vm)
{
	close(gic_fd);
	kvm_vm_free(vm);
}
Commit	Line	Data
4959d865 RRA	1	// SPDX-License-Identifier: GPL-2.0-only
4959d865 RRA	2	/*
4959d865	3	* The test validates both the virtual and physical timer IRQs using
c20dd9e0	4	* CVAL and TVAL registers.
4959d865 RRA	5	*
	6	* Copyright (c) 2021, Google LLC.
	7	*/
4959d865 RRA	8	#define _GNU_SOURCE
4959d865 RRA	9
4959d865	10	#include "arch_timer.h"
c20dd9e0	11	#include "delay.h"
4959d865	12	#include "gic.h"
c20dd9e0 HX	13	#include "processor.h"
c20dd9e0 HX	14	#include "timer_test.h"
4959d865 RRA	15	#include "vgic.h"
4959d865 RRA	16
4959d865 RRA	17	#define GICD_BASE_GPA 0x8000000ULL
	18	#define GICR_BASE_GPA 0x80A0000ULL
	19
	20	enum guest_stage {
	21	GUEST_STAGE_VTIMER_CVAL = 1,
	22	GUEST_STAGE_VTIMER_TVAL,
	23	GUEST_STAGE_PTIMER_CVAL,
	24	GUEST_STAGE_PTIMER_TVAL,
	25	GUEST_STAGE_MAX,
	26	};
	27
4959d865 RRA	28	static int vtimer_irq, ptimer_irq;
	29
	30	static void
	31	guest_configure_timer_action(struct test_vcpu_shared_data *shared_data)
	32	{
	33	switch (shared_data->guest_stage) {
	34	case GUEST_STAGE_VTIMER_CVAL:
	35	timer_set_next_cval_ms(VIRTUAL, test_args.timer_period_ms);
	36	shared_data->xcnt = timer_get_cntct(VIRTUAL);
	37	timer_set_ctl(VIRTUAL, CTL_ENABLE);
	38	break;
	39	case GUEST_STAGE_VTIMER_TVAL:
	40	timer_set_next_tval_ms(VIRTUAL, test_args.timer_period_ms);
	41	shared_data->xcnt = timer_get_cntct(VIRTUAL);
	42	timer_set_ctl(VIRTUAL, CTL_ENABLE);
	43	break;
	44	case GUEST_STAGE_PTIMER_CVAL:
	45	timer_set_next_cval_ms(PHYSICAL, test_args.timer_period_ms);
	46	shared_data->xcnt = timer_get_cntct(PHYSICAL);
	47	timer_set_ctl(PHYSICAL, CTL_ENABLE);
	48	break;
	49	case GUEST_STAGE_PTIMER_TVAL:
	50	timer_set_next_tval_ms(PHYSICAL, test_args.timer_period_ms);
	51	shared_data->xcnt = timer_get_cntct(PHYSICAL);
	52	timer_set_ctl(PHYSICAL, CTL_ENABLE);
	53	break;
	54	default:
	55	GUEST_ASSERT(0);
	56	}
	57	}
	58
	59	static void guest_validate_irq(unsigned int intid,
	60	struct test_vcpu_shared_data *shared_data)
	61	{
	62	enum guest_stage stage = shared_data->guest_stage;
	63	uint64_t xcnt = 0, xcnt_diff_us, cval = 0;
	64	unsigned long xctl = 0;
	65	unsigned int timer_irq = 0;
056c1566	66	unsigned int accessor;
4959d865	67
056c1566 MZ	68	if (intid == IAR_SPURIOUS)
	69	return;
	70
	71	switch (stage) {
	72	case GUEST_STAGE_VTIMER_CVAL:
	73	case GUEST_STAGE_VTIMER_TVAL:
	74	accessor = VIRTUAL;
4959d865	75	timer_irq = vtimer_irq;
056c1566 MZ	76	break;
	77	case GUEST_STAGE_PTIMER_CVAL:
	78	case GUEST_STAGE_PTIMER_TVAL:
	79	accessor = PHYSICAL;
4959d865	80	timer_irq = ptimer_irq;
056c1566 MZ	81	break;
056c1566 MZ	82	default:
4959d865	83	GUEST_ASSERT(0);
056c1566	84	return;
4959d865 RRA	85	}
4959d865 RRA	86
056c1566 MZ	87	xctl = timer_get_ctl(accessor);
	88	if ((xctl & CTL_IMASK) \|\| !(xctl & CTL_ENABLE))
	89	return;
	90
	91	timer_set_ctl(accessor, CTL_IMASK);
	92	xcnt = timer_get_cntct(accessor);
	93	cval = timer_get_cval(accessor);
	94
4959d865 RRA	95	xcnt_diff_us = cycles_to_usec(xcnt - shared_data->xcnt);
	96
	97	/* Make sure we are dealing with the correct timer IRQ */
db44e1c8	98	GUEST_ASSERT_EQ(intid, timer_irq);
4959d865 RRA	99
4959d865 RRA	100	/* Basic 'timer condition met' check */
db44e1c8	101	__GUEST_ASSERT(xcnt >= cval,
06fdd894	102	"xcnt = 0x%lx, cval = 0x%lx, xcnt_diff_us = 0x%lx",
db44e1c8	103	xcnt, cval, xcnt_diff_us);
8cdc71fb	104	__GUEST_ASSERT(xctl & CTL_ISTATUS, "xctl = 0x%lx", xctl);
056c1566 MZ	105
056c1566 MZ	106	WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1);
4959d865 RRA	107	}
	108
	109	static void guest_irq_handler(struct ex_regs *regs)
	110	{
	111	unsigned int intid = gic_get_and_ack_irq();
	112	uint32_t cpu = guest_get_vcpuid();
	113	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
	114
	115	guest_validate_irq(intid, shared_data);
	116
4959d865 RRA	117	gic_set_eoi(intid);
	118	}
	119
	120	static void guest_run_stage(struct test_vcpu_shared_data *shared_data,
	121	enum guest_stage stage)
	122	{
	123	uint32_t irq_iter, config_iter;
	124
	125	shared_data->guest_stage = stage;
	126	shared_data->nr_iter = 0;
	127
	128	for (config_iter = 0; config_iter < test_args.nr_iter; config_iter++) {
	129	/* Setup the next interrupt */
	130	guest_configure_timer_action(shared_data);
	131
	132	/* Setup a timeout for the interrupt to arrive */
	133	udelay(msecs_to_usecs(test_args.timer_period_ms) +
d1dafd06	134	test_args.timer_err_margin_us);
4959d865 RRA	135
4959d865 RRA	136	irq_iter = READ_ONCE(shared_data->nr_iter);
d1dafd06 HX	137	__GUEST_ASSERT(config_iter + 1 == irq_iter,
	138	"config_iter + 1 = 0x%lx, irq_iter = 0x%lx.\n"
	139	" Guest timer interrupt was not trigged within the specified\n"
	140	" interval, try to increase the error margin by [-e] option.\n",
	141	config_iter + 1, irq_iter);
4959d865 RRA	142	}
	143	}
	144
	145	static void guest_code(void)
	146	{
	147	uint32_t cpu = guest_get_vcpuid();
	148	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
	149
	150	local_irq_disable();
	151
	152	gic_init(GIC_V3, test_args.nr_vcpus,
	153	(void )GICD_BASE_GPA, (void )GICR_BASE_GPA);
	154
	155	timer_set_ctl(VIRTUAL, CTL_IMASK);
	156	timer_set_ctl(PHYSICAL, CTL_IMASK);
	157
	158	gic_irq_enable(vtimer_irq);
	159	gic_irq_enable(ptimer_irq);
	160	local_irq_enable();
	161
	162	guest_run_stage(shared_data, GUEST_STAGE_VTIMER_CVAL);
	163	guest_run_stage(shared_data, GUEST_STAGE_VTIMER_TVAL);
	164	guest_run_stage(shared_data, GUEST_STAGE_PTIMER_CVAL);
	165	guest_run_stage(shared_data, GUEST_STAGE_PTIMER_TVAL);
	166
	167	GUEST_DONE();
	168	}
	169
4959d865 RRA	170	static void test_init_timer_irq(struct kvm_vm *vm)
	171	{
	172	/* Timer initid should be same for all the vCPUs, so query only vCPU-0 */
768e9a61	173	vcpu_device_attr_get(vcpus[0], KVM_ARM_VCPU_TIMER_CTRL,
40918184	174	KVM_ARM_VCPU_TIMER_IRQ_PTIMER, &ptimer_irq);
768e9a61	175	vcpu_device_attr_get(vcpus[0], KVM_ARM_VCPU_TIMER_CTRL,
40918184	176	KVM_ARM_VCPU_TIMER_IRQ_VTIMER, &vtimer_irq);
4959d865 RRA	177
	178	sync_global_to_guest(vm, ptimer_irq);
	179	sync_global_to_guest(vm, vtimer_irq);
	180
	181	pr_debug("ptimer_irq: %d; vtimer_irq: %d\n", ptimer_irq, vtimer_irq);
	182	}
	183
21db8384 OU	184	static int gic_fd;
21db8384 OU	185
c20dd9e0	186	struct kvm_vm *test_vm_create(void)
4959d865 RRA	187	{
	188	struct kvm_vm *vm;
	189	unsigned int i;
	190	int nr_vcpus = test_args.nr_vcpus;
	191
7a5e4ae3	192	vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus);
4959d865 RRA	193
	194	vm_init_descriptor_tables(vm);
	195	vm_install_exception_handler(vm, VECTOR_IRQ_CURRENT, guest_irq_handler);
	196
d0b94bcb HX	197	if (!test_args.reserved) {
	198	if (kvm_has_cap(KVM_CAP_COUNTER_OFFSET)) {
	199	struct kvm_arm_counter_offset offset = {
	200	.counter_offset = test_args.counter_offset,
	201	.reserved = 0,
	202	};
	203	vm_ioctl(vm, KVM_ARM_SET_COUNTER_OFFSET, &offset);
	204	} else
95be17e4	205	TEST_FAIL("no support for global offset");
2fe9e0fc MZ	206	}
2fe9e0fc MZ	207
7a5e4ae3	208	for (i = 0; i < nr_vcpus; i++)
768e9a61	209	vcpu_init_descriptor_tables(vcpus[i]);
4959d865	210
4959d865	211	test_init_timer_irq(vm);
21db8384	212	gic_fd = vgic_v3_setup(vm, nr_vcpus, 64, GICD_BASE_GPA, GICR_BASE_GPA);
7ed397d1	213	__TEST_REQUIRE(gic_fd >= 0, "Failed to create vgic-v3");
4959d865 RRA	214
	215	/* Make all the test's cmdline args visible to the guest */
	216	sync_global_to_guest(vm, test_args);
	217
	218	return vm;
	219	}
	220
c20dd9e0	221	void test_vm_cleanup(struct kvm_vm *vm)
21db8384 OU	222	{
	223	close(gic_fd);
	224	kvm_vm_free(vm);
	225	}