Commit | Line | Data |
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facb7cb2 WJ |
1 | /* SPDX-License-Identifier: GPL-2.0 |
2 | * Copyright(c) 2020 Intel Corporation. | |
3 | */ | |
4 | ||
5 | #ifndef XDPXCEIVER_H_ | |
6 | #define XDPXCEIVER_H_ | |
7 | ||
8 | #ifndef SOL_XDP | |
9 | #define SOL_XDP 283 | |
10 | #endif | |
11 | ||
12 | #ifndef AF_XDP | |
13 | #define AF_XDP 44 | |
14 | #endif | |
15 | ||
16 | #ifndef PF_XDP | |
17 | #define PF_XDP AF_XDP | |
18 | #endif | |
19 | ||
20 | #define MAX_INTERFACES 2 | |
21 | #define MAX_INTERFACE_NAME_CHARS 7 | |
22 | #define MAX_INTERFACES_NAMESPACE_CHARS 10 | |
ed7b74dc | 23 | #define MAX_SOCKETS 2 |
53cb3cec | 24 | #define MAX_TEST_NAME_SIZE 32 |
6674bf66 | 25 | #define MAX_TEARDOWN_ITER 10 |
facb7cb2 WJ |
26 | #define PKT_HDR_SIZE (sizeof(struct ethhdr) + sizeof(struct iphdr) + \ |
27 | sizeof(struct udphdr)) | |
28 | #define MIN_PKT_SIZE 64 | |
29 | #define ETH_FCS_SIZE 4 | |
30 | #define PKT_SIZE (MIN_PKT_SIZE - ETH_FCS_SIZE) | |
31 | #define IP_PKT_SIZE (PKT_SIZE - sizeof(struct ethhdr)) | |
32 | #define IP_PKT_VER 0x4 | |
33 | #define IP_PKT_TOS 0x9 | |
34 | #define UDP_PKT_SIZE (IP_PKT_SIZE - sizeof(struct iphdr)) | |
35 | #define UDP_PKT_DATA_SIZE (UDP_PKT_SIZE - sizeof(struct udphdr)) | |
1314c353 | 36 | #define USLEEP_MAX 10000 |
facb7cb2 | 37 | #define SOCK_RECONF_CTR 10 |
1bf36496 | 38 | #define BATCH_SIZE 64 |
facb7cb2 | 39 | #define POLL_TMOUT 1000 |
25c0a305 | 40 | #define DEFAULT_PKT_CNT (4 * 1024) |
0d1b7f3a MK |
41 | #define DEFAULT_UMEM_BUFFERS (DEFAULT_PKT_CNT / 4) |
42 | #define UMEM_SIZE (DEFAULT_UMEM_BUFFERS * XSK_UMEM__DEFAULT_FRAME_SIZE) | |
b267e5a4 | 43 | #define RX_FULL_RXQSIZE 32 |
e34087fc | 44 | #define UMEM_HEADROOM_TEST_SIZE 128 |
29f128b3 | 45 | #define XSK_UMEM__INVALID_FRAME_SIZE (XSK_UMEM__DEFAULT_FRAME_SIZE + 1) |
facb7cb2 | 46 | |
ecde6061 MK |
47 | #define print_verbose(x...) do { if (opt_verbose) ksft_print_msg(x); } while (0) |
48 | ||
279bdf6b | 49 | enum test_mode { |
d3e3bf5b CL |
50 | TEST_MODE_SKB, |
51 | TEST_MODE_DRV, | |
52 | TEST_MODE_MAX | |
facb7cb2 WJ |
53 | }; |
54 | ||
279bdf6b | 55 | enum test_type { |
0d1b7f3a | 56 | TEST_TYPE_RUN_TO_COMPLETION, |
909f0e28 | 57 | TEST_TYPE_RUN_TO_COMPLETION_2K_FRAME, |
96a40678 | 58 | TEST_TYPE_RUN_TO_COMPLETION_SINGLE_PKT, |
d3e3bf5b | 59 | TEST_TYPE_POLL, |
a4ba98dd | 60 | TEST_TYPE_UNALIGNED, |
0d1b7f3a | 61 | TEST_TYPE_ALIGNED_INV_DESC, |
909f0e28 | 62 | TEST_TYPE_ALIGNED_INV_DESC_2K_FRAME, |
0d1b7f3a | 63 | TEST_TYPE_UNALIGNED_INV_DESC, |
e34087fc | 64 | TEST_TYPE_HEADROOM, |
d3e3bf5b CL |
65 | TEST_TYPE_TEARDOWN, |
66 | TEST_TYPE_BIDI, | |
b267e5a4 | 67 | TEST_TYPE_STATS, |
27e1ca25 | 68 | TEST_TYPE_BPF_RES, |
d3e3bf5b CL |
69 | TEST_TYPE_MAX |
70 | }; | |
71 | ||
279bdf6b | 72 | enum stat_test_type { |
b267e5a4 CL |
73 | STAT_TEST_RX_DROPPED, |
74 | STAT_TEST_TX_INVALID, | |
75 | STAT_TEST_RX_FULL, | |
76 | STAT_TEST_RX_FILL_EMPTY, | |
77 | STAT_TEST_TYPE_MAX | |
78 | }; | |
79 | ||
33a6bef8 | 80 | static bool opt_pkt_dump; |
d3e3bf5b | 81 | static int test_type; |
facb7cb2 | 82 | |
33a6bef8 | 83 | static bool opt_verbose; |
b267e5a4 | 84 | static int stat_test_type; |
facb7cb2 WJ |
85 | |
86 | struct xsk_umem_info { | |
87 | struct xsk_ring_prod fq; | |
88 | struct xsk_ring_cons cq; | |
89 | struct xsk_umem *umem; | |
83f4ae2f MK |
90 | u32 num_frames; |
91 | u32 frame_headroom; | |
facb7cb2 | 92 | void *buffer; |
c160d7af | 93 | u32 frame_size; |
a4ba98dd | 94 | bool unaligned_mode; |
facb7cb2 WJ |
95 | }; |
96 | ||
97 | struct xsk_socket_info { | |
98 | struct xsk_ring_cons rx; | |
99 | struct xsk_ring_prod tx; | |
100 | struct xsk_umem_info *umem; | |
101 | struct xsk_socket *xsk; | |
facb7cb2 | 102 | u32 outstanding_tx; |
4bf8ee65 | 103 | u32 rxqsize; |
facb7cb2 WJ |
104 | }; |
105 | ||
29f128b3 MK |
106 | struct pkt { |
107 | u64 addr; | |
108 | u32 len; | |
109 | u32 payload; | |
8abf6f72 | 110 | bool valid; |
29f128b3 MK |
111 | }; |
112 | ||
113 | struct pkt_stream { | |
114 | u32 nb_pkts; | |
0d1b7f3a | 115 | u32 rx_pkt_nb; |
29f128b3 | 116 | struct pkt *pkts; |
a4ba98dd | 117 | bool use_addr_for_fill; |
29f128b3 MK |
118 | }; |
119 | ||
744eb5c8 MK |
120 | typedef void *(*thread_func_t)(void *arg); |
121 | ||
facb7cb2 | 122 | struct ifobject { |
facb7cb2 WJ |
123 | char ifname[MAX_INTERFACE_NAME_CHARS]; |
124 | char nsname[MAX_INTERFACES_NAMESPACE_CHARS]; | |
facb7cb2 | 125 | struct xsk_socket_info *xsk; |
ed7b74dc | 126 | struct xsk_socket_info *xsk_arr; |
facb7cb2 | 127 | struct xsk_umem_info *umem; |
ed7b74dc | 128 | struct xsk_umem_info *umem_arr; |
744eb5c8 | 129 | thread_func_t func_ptr; |
29f128b3 | 130 | struct pkt_stream *pkt_stream; |
9445f8c7 | 131 | int ns_fd; |
facb7cb2 WJ |
132 | u32 dst_ip; |
133 | u32 src_ip; | |
af6731d1 MK |
134 | u32 xdp_flags; |
135 | u32 bind_flags; | |
facb7cb2 WJ |
136 | u16 src_port; |
137 | u16 dst_port; | |
1856c24d MK |
138 | bool tx_on; |
139 | bool rx_on; | |
119d4b02 | 140 | bool use_poll; |
1bf36496 | 141 | bool pacing_on; |
9445f8c7 MF |
142 | u8 dst_mac[ETH_ALEN]; |
143 | u8 src_mac[ETH_ALEN]; | |
facb7cb2 WJ |
144 | }; |
145 | ||
ce74acaf MK |
146 | struct test_spec { |
147 | struct ifobject *ifobj_tx; | |
148 | struct ifobject *ifobj_rx; | |
605091c5 | 149 | struct pkt_stream *pkt_stream_default; |
55be575d MK |
150 | u16 total_steps; |
151 | u16 current_step; | |
85c6c957 | 152 | u16 nb_sockets; |
53cb3cec | 153 | char name[MAX_TEST_NAME_SIZE]; |
ce74acaf | 154 | }; |
facb7cb2 | 155 | |
96539f1c | 156 | pthread_barrier_t barr; |
1bf36496 MK |
157 | pthread_mutex_t pacing_mutex = PTHREAD_MUTEX_INITIALIZER; |
158 | pthread_cond_t pacing_cond = PTHREAD_COND_INITIALIZER; | |
159 | ||
160 | u32 pkts_in_flight; | |
facb7cb2 | 161 | |
facb7cb2 | 162 | #endif /* XDPXCEIVER_H */ |