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tools/power turbostat: show GFX%rc6
[linux-block.git] / tools / power / x86 / turbostat / turbostat.c
CommitLineData
103a8fea
LB		 1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
144b44b1 5 * Copyright (c) 2013 Intel Corporation.
103a8fea
LB		 6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
88c3281f 22#define _GNU_SOURCE
b731f311 23#include MSRHEADER
95aebc44 24#include <stdarg.h>
103a8fea 25#include <stdio.h>
b2c95d90 26#include <err.h>
103a8fea
LB		 27#include <unistd.h>
28#include <sys/types.h>
29#include <sys/wait.h>
30#include <sys/stat.h>
31#include <sys/resource.h>
32#include <fcntl.h>
33#include <signal.h>
34#include <sys/time.h>
35#include <stdlib.h>
d8af6f5f 36#include <getopt.h>
103a8fea
LB		 37#include <dirent.h>
38#include <string.h>
39#include <ctype.h>
88c3281f 40#include <sched.h>
2a0609c0 41#include <time.h>
2b92865e 42#include <cpuid.h>
98481e79
LB		 43#include <linux/capability.h>
44#include <errno.h>
103a8fea 45
103a8fea 46char *proc_stat = "/proc/stat";
b7d8c148 47FILE *outf;
36229897 48int *fd_percpu;
2a0609c0 49struct timespec interval_ts = {5, 0};
d8af6f5f
LB		 50unsigned int debug;
51unsigned int rapl_joules;
52unsigned int summary_only;
53unsigned int dump_only;
103a8fea
LB		 54unsigned int skip_c0;
55unsigned int skip_c1;
56unsigned int do_nhm_cstates;
57unsigned int do_snb_cstates;
fb5d4327 58unsigned int do_knl_cstates;
ee7e38e3
LB		 59unsigned int do_pc2;
60unsigned int do_pc3;
61unsigned int do_pc6;
62unsigned int do_pc7;
ca58710f 63unsigned int do_c8_c9_c10;
0b2bb692 64unsigned int do_skl_residency;
144b44b1
LB		 65unsigned int do_slm_cstates;
66unsigned int use_c1_residency_msr;
103a8fea 67unsigned int has_aperf;
889facbe 68unsigned int has_epb;
fc04cc67 69unsigned int units = 1000000; /* MHz etc */
103a8fea
LB		 70unsigned int genuine_intel;
71unsigned int has_invariant_tsc;
d7899447 72unsigned int do_nhm_platform_info;
2f32edf1
LB		 73unsigned int extra_msr_offset32;
74unsigned int extra_msr_offset64;
8e180f3c
LB		 75unsigned int extra_delta_offset32;
76unsigned int extra_delta_offset64;
b2b34dfe 77unsigned int aperf_mperf_multiplier = 1;
562a2d37 78int do_irq = 1;
1ed51011 79int do_smi;
103a8fea 80double bclk;
a2b7b749 81double base_hz;
21ed5574 82unsigned int has_base_hz;
a2b7b749 83double tsc_tweak = 1.0;
103a8fea
LB		 84unsigned int show_pkg;
85unsigned int show_core;
86unsigned int show_cpu;
c98d5d94
LB		 87unsigned int show_pkg_only;
88unsigned int show_core_only;
89char *output_buffer, *outp;
889facbe
LB		 90unsigned int do_rapl;
91unsigned int do_dts;
92unsigned int do_ptm;
fdf676e5
LB		 93unsigned int do_gfx_rc6_ms;
94unsigned long long gfx_cur_rc6_ms;
27d47356
LB		 95unsigned int do_gfx_mhz;
96unsigned int gfx_cur_mhz;
889facbe
LB		 97unsigned int tcc_activation_temp;
98unsigned int tcc_activation_temp_override;
40ee8e3b
AS		 99double rapl_power_units, rapl_time_units;
100double rapl_dram_energy_units, rapl_energy_units;
889facbe 101double rapl_joule_counter_range;
3a9a941d
LB		 102unsigned int do_core_perf_limit_reasons;
103unsigned int do_gfx_perf_limit_reasons;
104unsigned int do_ring_perf_limit_reasons;
8a5bdf41
LB		 105unsigned int crystal_hz;
106unsigned long long tsc_hz;
7ce7d5de 107int base_cpu;
21ed5574 108double discover_bclk(unsigned int family, unsigned int model);
7f5c258e
LB		 109unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
110 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
111unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
112unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
113unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
114unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
889facbe 115
e6f9bb3c
LB		 116#define RAPL_PKG (1 << 0)
117 /* 0x610 MSR_PKG_POWER_LIMIT */
118 /* 0x611 MSR_PKG_ENERGY_STATUS */
119#define RAPL_PKG_PERF_STATUS (1 << 1)
120 /* 0x613 MSR_PKG_PERF_STATUS */
121#define RAPL_PKG_POWER_INFO (1 << 2)
122 /* 0x614 MSR_PKG_POWER_INFO */
123
124#define RAPL_DRAM (1 << 3)
125 /* 0x618 MSR_DRAM_POWER_LIMIT */
126 /* 0x619 MSR_DRAM_ENERGY_STATUS */
e6f9bb3c
LB		 127#define RAPL_DRAM_PERF_STATUS (1 << 4)
128 /* 0x61b MSR_DRAM_PERF_STATUS */
0b2bb692
LB		 129#define RAPL_DRAM_POWER_INFO (1 << 5)
130 /* 0x61c MSR_DRAM_POWER_INFO */
e6f9bb3c 131
0b2bb692 132#define RAPL_CORES (1 << 6)
e6f9bb3c
LB		 133 /* 0x638 MSR_PP0_POWER_LIMIT */
134 /* 0x639 MSR_PP0_ENERGY_STATUS */
0b2bb692 135#define RAPL_CORE_POLICY (1 << 7)
e6f9bb3c
LB		 136 /* 0x63a MSR_PP0_POLICY */
137
0b2bb692 138#define RAPL_GFX (1 << 8)
e6f9bb3c
LB		 139 /* 0x640 MSR_PP1_POWER_LIMIT */
140 /* 0x641 MSR_PP1_ENERGY_STATUS */
141 /* 0x642 MSR_PP1_POLICY */
889facbe
LB		 142#define TJMAX_DEFAULT 100
143
144#define MAX(a, b) ((a) > (b) ? (a) : (b))
103a8fea
LB		 145
146int aperf_mperf_unstable;
147int backwards_count;
148char *progname;
103a8fea 149
c98d5d94
LB		 150cpu_set_t *cpu_present_set, *cpu_affinity_set;
151size_t cpu_present_setsize, cpu_affinity_setsize;
152
153struct thread_data {
154 unsigned long long tsc;
155 unsigned long long aperf;
156 unsigned long long mperf;
144b44b1 157 unsigned long long c1;
2f32edf1 158 unsigned long long extra_msr64;
8e180f3c
LB		 159 unsigned long long extra_delta64;
160 unsigned long long extra_msr32;
161 unsigned long long extra_delta32;
562a2d37 162 unsigned int irq_count;
1ed51011 163 unsigned int smi_count;
c98d5d94
LB		 164 unsigned int cpu_id;
165 unsigned int flags;
166#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
167#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
168} *thread_even, *thread_odd;
169
170struct core_data {
171 unsigned long long c3;
172 unsigned long long c6;
173 unsigned long long c7;
889facbe 174 unsigned int core_temp_c;
c98d5d94
LB		 175 unsigned int core_id;
176} *core_even, *core_odd;
177
178struct pkg_data {
179 unsigned long long pc2;
180 unsigned long long pc3;
181 unsigned long long pc6;
182 unsigned long long pc7;
ca58710f
KCA		 183 unsigned long long pc8;
184 unsigned long long pc9;
185 unsigned long long pc10;
0b2bb692
LB		 186 unsigned long long pkg_wtd_core_c0;
187 unsigned long long pkg_any_core_c0;
188 unsigned long long pkg_any_gfxe_c0;
189 unsigned long long pkg_both_core_gfxe_c0;
fdf676e5 190 unsigned long long gfx_rc6_ms;
27d47356 191 unsigned int gfx_mhz;
c98d5d94 192 unsigned int package_id;
889facbe
LB		 193 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
194 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
195 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
196 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
197 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
198 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
199 unsigned int pkg_temp_c;
200
c98d5d94
LB		 201} *package_even, *package_odd;
202
203#define ODD_COUNTERS thread_odd, core_odd, package_odd
204#define EVEN_COUNTERS thread_even, core_even, package_even
205
206#define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
207 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
208 topo.num_threads_per_core + \
209 (core_no) * topo.num_threads_per_core + (thread_no))
210#define GET_CORE(core_base, core_no, pkg_no) \
211 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
212#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
213
214struct system_summary {
215 struct thread_data threads;
216 struct core_data cores;
217 struct pkg_data packages;
218} sum, average;
219
220
221struct topo_params {
222 int num_packages;
223 int num_cpus;
224 int num_cores;
225 int max_cpu_num;
226 int num_cores_per_pkg;
227 int num_threads_per_core;
228} topo;
229
230struct timeval tv_even, tv_odd, tv_delta;
231
562a2d37
LB		 232int *irq_column_2_cpu; /* /proc/interrupts column numbers */
233int *irqs_per_cpu; /* indexed by cpu_num */
234
c98d5d94
LB		 235void setup_all_buffers(void);
236
237int cpu_is_not_present(int cpu)
d15cf7c1 238{
c98d5d94 239 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
d15cf7c1 240}
88c3281f 241/*
c98d5d94
LB		 242 * run func(thread, core, package) in topology order
243 * skip non-present cpus
88c3281f 244 */
c98d5d94
LB		 245
246int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
247 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
88c3281f 248{
c98d5d94 249 int retval, pkg_no, core_no, thread_no;
d15cf7c1 250
c98d5d94
LB		 251 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
252 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
253 for (thread_no = 0; thread_no <
254 topo.num_threads_per_core; ++thread_no) {
255 struct thread_data *t;
256 struct core_data *c;
257 struct pkg_data *p;
88c3281f 258
c98d5d94
LB		 259 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
260
261 if (cpu_is_not_present(t->cpu_id))
262 continue;
263
264 c = GET_CORE(core_base, core_no, pkg_no);
265 p = GET_PKG(pkg_base, pkg_no);
266
267 retval = func(t, c, p);
268 if (retval)
269 return retval;
270 }
271 }
272 }
273 return 0;
88c3281f
LB		 274}
275
276int cpu_migrate(int cpu)
277{
c98d5d94
LB		 278 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
279 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
280 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
88c3281f
LB		 281 return -1;
282 else
283 return 0;
284}
36229897 285int get_msr_fd(int cpu)
103a8fea 286{
103a8fea
LB		 287 char pathname[32];
288 int fd;
289
36229897
LB		 290 fd = fd_percpu[cpu];
291
292 if (fd)
293 return fd;
294
103a8fea
LB		 295 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
296 fd = open(pathname, O_RDONLY);
15aaa346 297 if (fd < 0)
98481e79 298 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
103a8fea 299
36229897
LB		 300 fd_percpu[cpu] = fd;
301
302 return fd;
303}
304
305int get_msr(int cpu, off_t offset, unsigned long long *msr)
306{
307 ssize_t retval;
308
309 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
15aaa346 310
98481e79 311 if (retval != sizeof *msr)
36229897 312 err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset);
15aaa346
LB		 313
314 return 0;
103a8fea
LB		 315}
316
fc04cc67
LB		 317/*
318 * Example Format w/ field column widths:
319 *
27d47356 320 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz IRQ SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp GFXMHz Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
562a2d37 321 * 12345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678
fc04cc67
LB		 322 */
323
a829eb4d 324void print_header(void)
103a8fea
LB		 325{
326 if (show_pkg)
e7c95ff3 327 outp += sprintf(outp, " Package");
103a8fea 328 if (show_core)
e7c95ff3 329 outp += sprintf(outp, " Core");
103a8fea 330 if (show_cpu)
e7c95ff3 331 outp += sprintf(outp, " CPU");
fc04cc67 332 if (has_aperf)
e7c95ff3 333 outp += sprintf(outp, " Avg_MHz");
d7899447 334 if (has_aperf)
75d2e44e 335 outp += sprintf(outp, " Busy%%");
103a8fea 336 if (has_aperf)
e7c95ff3
LB		 337 outp += sprintf(outp, " Bzy_MHz");
338 outp += sprintf(outp, " TSC_MHz");
1cc21f7b 339
8e180f3c 340 if (extra_delta_offset32)
e7c95ff3 341 outp += sprintf(outp, " count 0x%03X", extra_delta_offset32);
8e180f3c 342 if (extra_delta_offset64)
e7c95ff3 343 outp += sprintf(outp, " COUNT 0x%03X", extra_delta_offset64);
2f32edf1 344 if (extra_msr_offset32)
e7c95ff3 345 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset32);
2f32edf1 346 if (extra_msr_offset64)
e7c95ff3 347 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset64);
1cc21f7b
LB		 348
349 if (!debug)
350 goto done;
351
562a2d37
LB		 352 if (do_irq)
353 outp += sprintf(outp, " IRQ");
1cc21f7b
LB		 354 if (do_smi)
355 outp += sprintf(outp, " SMI");
356
103a8fea 357 if (do_nhm_cstates)
e7c95ff3 358 outp += sprintf(outp, " CPU%%c1");
fb5d4327 359 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
e7c95ff3 360 outp += sprintf(outp, " CPU%%c3");
103a8fea 361 if (do_nhm_cstates)
e7c95ff3 362 outp += sprintf(outp, " CPU%%c6");
103a8fea 363 if (do_snb_cstates)
e7c95ff3 364 outp += sprintf(outp, " CPU%%c7");
889facbe
LB		 365
366 if (do_dts)
e7c95ff3 367 outp += sprintf(outp, " CoreTmp");
889facbe 368 if (do_ptm)
e7c95ff3 369 outp += sprintf(outp, " PkgTmp");
889facbe 370
fdf676e5
LB		 371 if (do_gfx_rc6_ms)
372 outp += sprintf(outp, " GFX%%rc6");
373
27d47356
LB		 374 if (do_gfx_mhz)
375 outp += sprintf(outp, " GFXMHz");
376
0b2bb692
LB		 377 if (do_skl_residency) {
378 outp += sprintf(outp, " Totl%%C0");
379 outp += sprintf(outp, " Any%%C0");
380 outp += sprintf(outp, " GFX%%C0");
381 outp += sprintf(outp, " CPUGFX%%");
382 }
383
ee7e38e3 384 if (do_pc2)
e7c95ff3 385 outp += sprintf(outp, " Pkg%%pc2");
ee7e38e3 386 if (do_pc3)
e7c95ff3 387 outp += sprintf(outp, " Pkg%%pc3");
ee7e38e3 388 if (do_pc6)
e7c95ff3 389 outp += sprintf(outp, " Pkg%%pc6");
ee7e38e3 390 if (do_pc7)
e7c95ff3 391 outp += sprintf(outp, " Pkg%%pc7");
ca58710f 392 if (do_c8_c9_c10) {
e7c95ff3
LB		 393 outp += sprintf(outp, " Pkg%%pc8");
394 outp += sprintf(outp, " Pkg%%pc9");
395 outp += sprintf(outp, " Pk%%pc10");
ca58710f 396 }
103a8fea 397
5c56be9a
DB		 398 if (do_rapl && !rapl_joules) {
399 if (do_rapl & RAPL_PKG)
e7c95ff3 400 outp += sprintf(outp, " PkgWatt");
5c56be9a 401 if (do_rapl & RAPL_CORES)
e7c95ff3 402 outp += sprintf(outp, " CorWatt");
5c56be9a 403 if (do_rapl & RAPL_GFX)
e7c95ff3 404 outp += sprintf(outp, " GFXWatt");
5c56be9a 405 if (do_rapl & RAPL_DRAM)
e7c95ff3 406 outp += sprintf(outp, " RAMWatt");
5c56be9a 407 if (do_rapl & RAPL_PKG_PERF_STATUS)
e7c95ff3 408 outp += sprintf(outp, " PKG_%%");
5c56be9a 409 if (do_rapl & RAPL_DRAM_PERF_STATUS)
e7c95ff3 410 outp += sprintf(outp, " RAM_%%");
d7899447 411 } else if (do_rapl && rapl_joules) {
5c56be9a 412 if (do_rapl & RAPL_PKG)
e7c95ff3 413 outp += sprintf(outp, " Pkg_J");
5c56be9a 414 if (do_rapl & RAPL_CORES)
e7c95ff3 415 outp += sprintf(outp, " Cor_J");
5c56be9a 416 if (do_rapl & RAPL_GFX)
e7c95ff3 417 outp += sprintf(outp, " GFX_J");
5c56be9a 418 if (do_rapl & RAPL_DRAM)
bd6906ed 419 outp += sprintf(outp, " RAM_J");
5c56be9a 420 if (do_rapl & RAPL_PKG_PERF_STATUS)
e7c95ff3 421 outp += sprintf(outp, " PKG_%%");
5c56be9a 422 if (do_rapl & RAPL_DRAM_PERF_STATUS)
e7c95ff3
LB		 423 outp += sprintf(outp, " RAM_%%");
424 outp += sprintf(outp, " time");
889facbe 425
5c56be9a 426 }
1cc21f7b 427 done:
c98d5d94 428 outp += sprintf(outp, "\n");
103a8fea
LB		 429}
430
c98d5d94
LB		 431int dump_counters(struct thread_data *t, struct core_data *c,
432 struct pkg_data *p)
103a8fea 433{
3b4d5c7f 434 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
c98d5d94
LB		 435
436 if (t) {
3b4d5c7f
AS		 437 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
438 t->cpu_id, t->flags);
439 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
440 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
441 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
442 outp += sprintf(outp, "c1: %016llX\n", t->c1);
443 outp += sprintf(outp, "msr0x%x: %08llX\n",
8e180f3c 444 extra_delta_offset32, t->extra_delta32);
3b4d5c7f 445 outp += sprintf(outp, "msr0x%x: %016llX\n",
8e180f3c 446 extra_delta_offset64, t->extra_delta64);
3b4d5c7f 447 outp += sprintf(outp, "msr0x%x: %08llX\n",
2f32edf1 448 extra_msr_offset32, t->extra_msr32);
3b4d5c7f 449 outp += sprintf(outp, "msr0x%x: %016llX\n",
2f32edf1 450 extra_msr_offset64, t->extra_msr64);
562a2d37
LB		 451 if (do_irq)
452 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count);
1ed51011 453 if (do_smi)
3b4d5c7f 454 outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
c98d5d94 455 }
103a8fea 456
c98d5d94 457 if (c) {
3b4d5c7f
AS		 458 outp += sprintf(outp, "core: %d\n", c->core_id);
459 outp += sprintf(outp, "c3: %016llX\n", c->c3);
460 outp += sprintf(outp, "c6: %016llX\n", c->c6);
461 outp += sprintf(outp, "c7: %016llX\n", c->c7);
462 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
c98d5d94 463 }
103a8fea 464
c98d5d94 465 if (p) {
3b4d5c7f 466 outp += sprintf(outp, "package: %d\n", p->package_id);
0b2bb692
LB		 467
468 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
469 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
470 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
471 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
472
3b4d5c7f 473 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
ee7e38e3
LB		 474 if (do_pc3)
475 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
476 if (do_pc6)
477 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
478 if (do_pc7)
479 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
3b4d5c7f
AS		 480 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
481 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
482 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
483 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
484 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
485 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
486 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
487 outp += sprintf(outp, "Throttle PKG: %0X\n",
488 p->rapl_pkg_perf_status);
489 outp += sprintf(outp, "Throttle RAM: %0X\n",
490 p->rapl_dram_perf_status);
491 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
c98d5d94 492 }
3b4d5c7f
AS		 493
494 outp += sprintf(outp, "\n");
495
c98d5d94 496 return 0;
103a8fea
LB		 497}
498
e23da037
LB		 499/*
500 * column formatting convention & formats
e23da037 501 */
c98d5d94
LB		 502int format_counters(struct thread_data *t, struct core_data *c,
503 struct pkg_data *p)
103a8fea
LB		 504{
505 double interval_float;
fc04cc67 506 char *fmt8;
103a8fea 507
c98d5d94
LB		 508 /* if showing only 1st thread in core and this isn't one, bail out */
509 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
510 return 0;
511
512 /* if showing only 1st thread in pkg and this isn't one, bail out */
513 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
514 return 0;
515
103a8fea
LB		 516 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
517
c98d5d94
LB		 518 /* topo columns, print blanks on 1st (average) line */
519 if (t == &average.threads) {
103a8fea 520 if (show_pkg)
fc04cc67 521 outp += sprintf(outp, " -");
103a8fea 522 if (show_core)
fc04cc67 523 outp += sprintf(outp, " -");
103a8fea 524 if (show_cpu)
fc04cc67 525 outp += sprintf(outp, " -");
103a8fea 526 } else {
c98d5d94
LB		 527 if (show_pkg) {
528 if (p)
fc04cc67 529 outp += sprintf(outp, "%8d", p->package_id);
c98d5d94 530 else
fc04cc67 531 outp += sprintf(outp, " -");
c98d5d94 532 }
c98d5d94
LB		 533 if (show_core) {
534 if (c)
fc04cc67 535 outp += sprintf(outp, "%8d", c->core_id);
c98d5d94 536 else
fc04cc67 537 outp += sprintf(outp, " -");
c98d5d94 538 }
103a8fea 539 if (show_cpu)
fc04cc67 540 outp += sprintf(outp, "%8d", t->cpu_id);
103a8fea 541 }
fc04cc67 542
d7899447 543 /* Avg_MHz */
fc04cc67
LB		 544 if (has_aperf)
545 outp += sprintf(outp, "%8.0f",
546 1.0 / units * t->aperf / interval_float);
547
75d2e44e 548 /* Busy% */
d7899447 549 if (has_aperf) {
103a8fea 550 if (!skip_c0)
a2b7b749 551 outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
103a8fea 552 else
fc04cc67 553 outp += sprintf(outp, "********");
103a8fea
LB		 554 }
555
d7899447 556 /* Bzy_MHz */
21ed5574
LB		 557 if (has_aperf) {
558 if (has_base_hz)
559 outp += sprintf(outp, "%8.0f", base_hz / units * t->aperf / t->mperf);
560 else
561 outp += sprintf(outp, "%8.0f",
562 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
563 }
103a8fea 564
d7899447 565 /* TSC_MHz */
fc04cc67 566 outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float);
103a8fea 567
8e180f3c
LB		 568 /* delta */
569 if (extra_delta_offset32)
570 outp += sprintf(outp, " %11llu", t->extra_delta32);
571
572 /* DELTA */
573 if (extra_delta_offset64)
574 outp += sprintf(outp, " %11llu", t->extra_delta64);
2f32edf1
LB		 575 /* msr */
576 if (extra_msr_offset32)
8e180f3c 577 outp += sprintf(outp, " 0x%08llx", t->extra_msr32);
2f32edf1 578
130ff304 579 /* MSR */
2f32edf1
LB		 580 if (extra_msr_offset64)
581 outp += sprintf(outp, " 0x%016llx", t->extra_msr64);
130ff304 582
1cc21f7b
LB		 583 if (!debug)
584 goto done;
585
562a2d37
LB		 586 /* IRQ */
587 if (do_irq)
588 outp += sprintf(outp, "%8d", t->irq_count);
589
1cc21f7b
LB		 590 /* SMI */
591 if (do_smi)
592 outp += sprintf(outp, "%8d", t->smi_count);
593
103a8fea
LB		 594 if (do_nhm_cstates) {
595 if (!skip_c1)
fc04cc67 596 outp += sprintf(outp, "%8.2f", 100.0 * t->c1/t->tsc);
103a8fea 597 else
fc04cc67 598 outp += sprintf(outp, "********");
103a8fea 599 }
c98d5d94
LB		 600
601 /* print per-core data only for 1st thread in core */
602 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
603 goto done;
604
fb5d4327 605 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
fc04cc67 606 outp += sprintf(outp, "%8.2f", 100.0 * c->c3/t->tsc);
103a8fea 607 if (do_nhm_cstates)
fc04cc67 608 outp += sprintf(outp, "%8.2f", 100.0 * c->c6/t->tsc);
103a8fea 609 if (do_snb_cstates)
fc04cc67 610 outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc);
c98d5d94 611
889facbe 612 if (do_dts)
fc04cc67 613 outp += sprintf(outp, "%8d", c->core_temp_c);
889facbe 614
c98d5d94
LB		 615 /* print per-package data only for 1st core in package */
616 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
617 goto done;
618
0b2bb692 619 /* PkgTmp */
889facbe 620 if (do_ptm)
fc04cc67 621 outp += sprintf(outp, "%8d", p->pkg_temp_c);
889facbe 622
fdf676e5
LB		 623 /* GFXrc6 */
624 if (do_gfx_rc6_ms)
625 outp += sprintf(outp, "%8.2f", 100.0 * p->gfx_rc6_ms / 1000.0 / interval_float);
626
27d47356
LB		 627 /* GFXMHz */
628 if (do_gfx_mhz)
629 outp += sprintf(outp, "%8d", p->gfx_mhz);
630
0b2bb692
LB		 631 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
632 if (do_skl_residency) {
633 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc);
634 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_core_c0/t->tsc);
635 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc);
636 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc);
637 }
638
ee7e38e3 639 if (do_pc2)
fc04cc67 640 outp += sprintf(outp, "%8.2f", 100.0 * p->pc2/t->tsc);
ee7e38e3 641 if (do_pc3)
fc04cc67 642 outp += sprintf(outp, "%8.2f", 100.0 * p->pc3/t->tsc);
ee7e38e3 643 if (do_pc6)
fc04cc67 644 outp += sprintf(outp, "%8.2f", 100.0 * p->pc6/t->tsc);
ee7e38e3 645 if (do_pc7)
fc04cc67 646 outp += sprintf(outp, "%8.2f", 100.0 * p->pc7/t->tsc);
ca58710f 647 if (do_c8_c9_c10) {
fc04cc67
LB		 648 outp += sprintf(outp, "%8.2f", 100.0 * p->pc8/t->tsc);
649 outp += sprintf(outp, "%8.2f", 100.0 * p->pc9/t->tsc);
650 outp += sprintf(outp, "%8.2f", 100.0 * p->pc10/t->tsc);
ca58710f 651 }
889facbe
LB		 652
653 /*
654 * If measurement interval exceeds minimum RAPL Joule Counter range,
655 * indicate that results are suspect by printing "**" in fraction place.
656 */
fc04cc67
LB		 657 if (interval_float < rapl_joule_counter_range)
658 fmt8 = "%8.2f";
659 else
660 fmt8 = " %6.0f**";
889facbe 661
5c56be9a
DB		 662 if (do_rapl && !rapl_joules) {
663 if (do_rapl & RAPL_PKG)
fc04cc67 664 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
5c56be9a 665 if (do_rapl & RAPL_CORES)
fc04cc67 666 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
5c56be9a 667 if (do_rapl & RAPL_GFX)
fc04cc67 668 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
5c56be9a 669 if (do_rapl & RAPL_DRAM)
40ee8e3b 670 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
5c56be9a 671 if (do_rapl & RAPL_PKG_PERF_STATUS)
fc04cc67 672 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
5c56be9a 673 if (do_rapl & RAPL_DRAM_PERF_STATUS)
fc04cc67 674 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
d7899447 675 } else if (do_rapl && rapl_joules) {
5c56be9a 676 if (do_rapl & RAPL_PKG)
fc04cc67 677 outp += sprintf(outp, fmt8,
5c56be9a
DB		 678 p->energy_pkg * rapl_energy_units);
679 if (do_rapl & RAPL_CORES)
fc04cc67 680 outp += sprintf(outp, fmt8,
5c56be9a
DB		 681 p->energy_cores * rapl_energy_units);
682 if (do_rapl & RAPL_GFX)
fc04cc67 683 outp += sprintf(outp, fmt8,
5c56be9a
DB		 684 p->energy_gfx * rapl_energy_units);
685 if (do_rapl & RAPL_DRAM)
fc04cc67 686 outp += sprintf(outp, fmt8,
40ee8e3b 687 p->energy_dram * rapl_dram_energy_units);
5c56be9a 688 if (do_rapl & RAPL_PKG_PERF_STATUS)
fc04cc67 689 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
5c56be9a 690 if (do_rapl & RAPL_DRAM_PERF_STATUS)
fc04cc67 691 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
889facbe 692
d7899447 693 outp += sprintf(outp, fmt8, interval_float);
5c56be9a 694 }
c98d5d94 695done:
c98d5d94
LB		 696 outp += sprintf(outp, "\n");
697
698 return 0;
103a8fea
LB		 699}
700
b7d8c148 701void flush_output_stdout(void)
c98d5d94 702{
b7d8c148
LB		 703 FILE *filep;
704
705 if (outf == stderr)
706 filep = stdout;
707 else
708 filep = outf;
709
710 fputs(output_buffer, filep);
711 fflush(filep);
712
c98d5d94
LB		 713 outp = output_buffer;
714}
b7d8c148 715void flush_output_stderr(void)
c98d5d94 716{
b7d8c148
LB		 717 fputs(output_buffer, outf);
718 fflush(outf);
c98d5d94
LB		 719 outp = output_buffer;
720}
721void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 722{
e23da037 723 static int printed;
103a8fea 724
e23da037
LB		 725 if (!printed || !summary_only)
726 print_header();
103a8fea 727
c98d5d94
LB		 728 if (topo.num_cpus > 1)
729 format_counters(&average.threads, &average.cores,
730 &average.packages);
103a8fea 731
e23da037
LB		 732 printed = 1;
733
734 if (summary_only)
735 return;
736
c98d5d94 737 for_all_cpus(format_counters, t, c, p);
103a8fea
LB		 738}
739
889facbe
LB		 740#define DELTA_WRAP32(new, old) \
741 if (new > old) { \
742 old = new - old; \
743 } else { \
744 old = 0x100000000 + new - old; \
745 }
746
c98d5d94
LB		 747void
748delta_package(struct pkg_data *new, struct pkg_data *old)
749{
0b2bb692
LB		 750
751 if (do_skl_residency) {
752 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
753 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
754 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
755 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
756 }
c98d5d94 757 old->pc2 = new->pc2 - old->pc2;
ee7e38e3
LB		 758 if (do_pc3)
759 old->pc3 = new->pc3 - old->pc3;
760 if (do_pc6)
761 old->pc6 = new->pc6 - old->pc6;
762 if (do_pc7)
763 old->pc7 = new->pc7 - old->pc7;
ca58710f
KCA		 764 old->pc8 = new->pc8 - old->pc8;
765 old->pc9 = new->pc9 - old->pc9;
766 old->pc10 = new->pc10 - old->pc10;
889facbe
LB		 767 old->pkg_temp_c = new->pkg_temp_c;
768
fdf676e5 769 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
27d47356
LB		 770 old->gfx_mhz = new->gfx_mhz;
771
889facbe
LB		 772 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
773 DELTA_WRAP32(new->energy_cores, old->energy_cores);
774 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
775 DELTA_WRAP32(new->energy_dram, old->energy_dram);
776 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
777 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
c98d5d94 778}
103a8fea 779
c98d5d94
LB		 780void
781delta_core(struct core_data *new, struct core_data *old)
103a8fea 782{
c98d5d94
LB		 783 old->c3 = new->c3 - old->c3;
784 old->c6 = new->c6 - old->c6;
785 old->c7 = new->c7 - old->c7;
889facbe 786 old->core_temp_c = new->core_temp_c;
c98d5d94 787}
103a8fea 788
c3ae331d
LB		 789/*
790 * old = new - old
791 */
c98d5d94
LB		 792void
793delta_thread(struct thread_data *new, struct thread_data *old,
794 struct core_data *core_delta)
795{
796 old->tsc = new->tsc - old->tsc;
797
798 /* check for TSC < 1 Mcycles over interval */
b2c95d90
JT		 799 if (old->tsc < (1000 * 1000))
800 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
801 "You can disable all c-states by booting with \"idle=poll\"\n"
802 "or just the deep ones with \"processor.max_cstate=1\"");
103a8fea 803
c98d5d94 804 old->c1 = new->c1 - old->c1;
103a8fea 805
a729617c
LB		 806 if (has_aperf) {
807 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
808 old->aperf = new->aperf - old->aperf;
809 old->mperf = new->mperf - old->mperf;
810 } else {
103a8fea 811
a729617c 812 if (!aperf_mperf_unstable) {
b7d8c148
LB		 813 fprintf(outf, "%s: APERF or MPERF went backwards *\n", progname);
814 fprintf(outf, "* Frequency results do not cover entire interval *\n");
815 fprintf(outf, "* fix this by running Linux-2.6.30 or later *\n");
103a8fea 816
a729617c
LB		 817 aperf_mperf_unstable = 1;
818 }
819 /*
820 * mperf delta is likely a huge "positive" number
821 * can not use it for calculating c0 time
822 */
823 skip_c0 = 1;
824 skip_c1 = 1;
103a8fea 825 }
c98d5d94 826 }
103a8fea 827
103a8fea 828
144b44b1
LB		 829 if (use_c1_residency_msr) {
830 /*
831 * Some models have a dedicated C1 residency MSR,
832 * which should be more accurate than the derivation below.
833 */
834 } else {
835 /*
836 * As counter collection is not atomic,
837 * it is possible for mperf's non-halted cycles + idle states
838 * to exceed TSC's all cycles: show c1 = 0% in that case.
839 */
840 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc)
841 old->c1 = 0;
842 else {
843 /* normal case, derive c1 */
844 old->c1 = old->tsc - old->mperf - core_delta->c3
c98d5d94 845 - core_delta->c6 - core_delta->c7;
144b44b1 846 }
c98d5d94 847 }
c3ae331d 848
c98d5d94 849 if (old->mperf == 0) {
b7d8c148
LB		 850 if (debug > 1)
851 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
c98d5d94 852 old->mperf = 1; /* divide by 0 protection */
103a8fea 853 }
c98d5d94 854
8e180f3c
LB		 855 old->extra_delta32 = new->extra_delta32 - old->extra_delta32;
856 old->extra_delta32 &= 0xFFFFFFFF;
857
858 old->extra_delta64 = new->extra_delta64 - old->extra_delta64;
859
c98d5d94 860 /*
8e180f3c 861 * Extra MSR is just a snapshot, simply copy latest w/o subtracting
c98d5d94 862 */
2f32edf1
LB		 863 old->extra_msr32 = new->extra_msr32;
864 old->extra_msr64 = new->extra_msr64;
1ed51011 865
562a2d37
LB		 866 if (do_irq)
867 old->irq_count = new->irq_count - old->irq_count;
868
1ed51011
LB		 869 if (do_smi)
870 old->smi_count = new->smi_count - old->smi_count;
c98d5d94
LB		 871}
872
873int delta_cpu(struct thread_data *t, struct core_data *c,
874 struct pkg_data *p, struct thread_data *t2,
875 struct core_data *c2, struct pkg_data *p2)
876{
877 /* calculate core delta only for 1st thread in core */
878 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
879 delta_core(c, c2);
880
881 /* always calculate thread delta */
882 delta_thread(t, t2, c2); /* c2 is core delta */
883
884 /* calculate package delta only for 1st core in package */
885 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
886 delta_package(p, p2);
887
103a8fea
LB		 888 return 0;
889}
890
c98d5d94
LB		 891void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
892{
893 t->tsc = 0;
894 t->aperf = 0;
895 t->mperf = 0;
896 t->c1 = 0;
897
8e180f3c
LB		 898 t->extra_delta32 = 0;
899 t->extra_delta64 = 0;
900
562a2d37
LB		 901 t->irq_count = 0;
902 t->smi_count = 0;
903
c98d5d94
LB		 904 /* tells format_counters to dump all fields from this set */
905 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
906
907 c->c3 = 0;
908 c->c6 = 0;
909 c->c7 = 0;
889facbe 910 c->core_temp_c = 0;
c98d5d94 911
0b2bb692
LB		 912 p->pkg_wtd_core_c0 = 0;
913 p->pkg_any_core_c0 = 0;
914 p->pkg_any_gfxe_c0 = 0;
915 p->pkg_both_core_gfxe_c0 = 0;
916
c98d5d94 917 p->pc2 = 0;
ee7e38e3
LB		 918 if (do_pc3)
919 p->pc3 = 0;
920 if (do_pc6)
921 p->pc6 = 0;
922 if (do_pc7)
923 p->pc7 = 0;
ca58710f
KCA		 924 p->pc8 = 0;
925 p->pc9 = 0;
926 p->pc10 = 0;
889facbe
LB		 927
928 p->energy_pkg = 0;
929 p->energy_dram = 0;
930 p->energy_cores = 0;
931 p->energy_gfx = 0;
932 p->rapl_pkg_perf_status = 0;
933 p->rapl_dram_perf_status = 0;
934 p->pkg_temp_c = 0;
27d47356 935
fdf676e5 936 p->gfx_rc6_ms = 0;
27d47356 937 p->gfx_mhz = 0;
c98d5d94
LB		 938}
939int sum_counters(struct thread_data *t, struct core_data *c,
940 struct pkg_data *p)
103a8fea 941{
c98d5d94
LB		 942 average.threads.tsc += t->tsc;
943 average.threads.aperf += t->aperf;
944 average.threads.mperf += t->mperf;
945 average.threads.c1 += t->c1;
103a8fea 946
8e180f3c
LB		 947 average.threads.extra_delta32 += t->extra_delta32;
948 average.threads.extra_delta64 += t->extra_delta64;
949
562a2d37
LB		 950 average.threads.irq_count += t->irq_count;
951 average.threads.smi_count += t->smi_count;
952
c98d5d94
LB		 953 /* sum per-core values only for 1st thread in core */
954 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
955 return 0;
103a8fea 956
c98d5d94
LB		 957 average.cores.c3 += c->c3;
958 average.cores.c6 += c->c6;
959 average.cores.c7 += c->c7;
960
889facbe
LB		 961 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
962
c98d5d94
LB		 963 /* sum per-pkg values only for 1st core in pkg */
964 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
965 return 0;
966
0b2bb692
LB		 967 if (do_skl_residency) {
968 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
969 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
970 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
971 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
972 }
973
c98d5d94 974 average.packages.pc2 += p->pc2;
ee7e38e3
LB		 975 if (do_pc3)
976 average.packages.pc3 += p->pc3;
977 if (do_pc6)
978 average.packages.pc6 += p->pc6;
979 if (do_pc7)
980 average.packages.pc7 += p->pc7;
ca58710f
KCA		 981 average.packages.pc8 += p->pc8;
982 average.packages.pc9 += p->pc9;
983 average.packages.pc10 += p->pc10;
c98d5d94 984
889facbe
LB		 985 average.packages.energy_pkg += p->energy_pkg;
986 average.packages.energy_dram += p->energy_dram;
987 average.packages.energy_cores += p->energy_cores;
988 average.packages.energy_gfx += p->energy_gfx;
989
fdf676e5 990 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
27d47356
LB		 991 average.packages.gfx_mhz = p->gfx_mhz;
992
889facbe
LB		 993 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
994
995 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
996 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
c98d5d94
LB		 997 return 0;
998}
999/*
1000 * sum the counters for all cpus in the system
1001 * compute the weighted average
1002 */
1003void compute_average(struct thread_data *t, struct core_data *c,
1004 struct pkg_data *p)
1005{
1006 clear_counters(&average.threads, &average.cores, &average.packages);
1007
1008 for_all_cpus(sum_counters, t, c, p);
1009
1010 average.threads.tsc /= topo.num_cpus;
1011 average.threads.aperf /= topo.num_cpus;
1012 average.threads.mperf /= topo.num_cpus;
1013 average.threads.c1 /= topo.num_cpus;
1014
8e180f3c
LB		 1015 average.threads.extra_delta32 /= topo.num_cpus;
1016 average.threads.extra_delta32 &= 0xFFFFFFFF;
1017
1018 average.threads.extra_delta64 /= topo.num_cpus;
1019
c98d5d94
LB		 1020 average.cores.c3 /= topo.num_cores;
1021 average.cores.c6 /= topo.num_cores;
1022 average.cores.c7 /= topo.num_cores;
1023
0b2bb692
LB		 1024 if (do_skl_residency) {
1025 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1026 average.packages.pkg_any_core_c0 /= topo.num_packages;
1027 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1028 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1029 }
1030
c98d5d94 1031 average.packages.pc2 /= topo.num_packages;
ee7e38e3
LB		 1032 if (do_pc3)
1033 average.packages.pc3 /= topo.num_packages;
1034 if (do_pc6)
1035 average.packages.pc6 /= topo.num_packages;
1036 if (do_pc7)
1037 average.packages.pc7 /= topo.num_packages;
ca58710f
KCA		 1038
1039 average.packages.pc8 /= topo.num_packages;
1040 average.packages.pc9 /= topo.num_packages;
1041 average.packages.pc10 /= topo.num_packages;
103a8fea
LB		 1042}
1043
c98d5d94 1044static unsigned long long rdtsc(void)
103a8fea 1045{
c98d5d94 1046 unsigned int low, high;
15aaa346 1047
c98d5d94 1048 asm volatile("rdtsc" : "=a" (low), "=d" (high));
15aaa346 1049
c98d5d94
LB		 1050 return low | ((unsigned long long)high) << 32;
1051}
15aaa346 1052
c98d5d94
LB		 1053/*
1054 * get_counters(...)
1055 * migrate to cpu
1056 * acquire and record local counters for that cpu
1057 */
1058int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1059{
1060 int cpu = t->cpu_id;
889facbe 1061 unsigned long long msr;
88c3281f 1062
e52966c0 1063 if (cpu_migrate(cpu)) {
b7d8c148 1064 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
c98d5d94 1065 return -1;
e52966c0 1066 }
15aaa346 1067
c98d5d94
LB		 1068 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1069
1070 if (has_aperf) {
9c63a650 1071 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
c98d5d94 1072 return -3;
9c63a650 1073 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
c98d5d94 1074 return -4;
b2b34dfe
HC		 1075 t->aperf = t->aperf * aperf_mperf_multiplier;
1076 t->mperf = t->mperf * aperf_mperf_multiplier;
c98d5d94
LB		 1077 }
1078
562a2d37
LB		 1079 if (do_irq)
1080 t->irq_count = irqs_per_cpu[cpu];
1ed51011
LB		 1081 if (do_smi) {
1082 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1083 return -5;
1084 t->smi_count = msr & 0xFFFFFFFF;
1085 }
8e180f3c 1086 if (extra_delta_offset32) {
889facbe 1087 if (get_msr(cpu, extra_delta_offset32, &msr))
8e180f3c 1088 return -5;
889facbe 1089 t->extra_delta32 = msr & 0xFFFFFFFF;
8e180f3c
LB		 1090 }
1091
1092 if (extra_delta_offset64)
1093 if (get_msr(cpu, extra_delta_offset64, &t->extra_delta64))
2f32edf1
LB		 1094 return -5;
1095
8e180f3c 1096 if (extra_msr_offset32) {
889facbe 1097 if (get_msr(cpu, extra_msr_offset32, &msr))
8e180f3c 1098 return -5;
889facbe 1099 t->extra_msr32 = msr & 0xFFFFFFFF;
8e180f3c
LB		 1100 }
1101
2f32edf1
LB		 1102 if (extra_msr_offset64)
1103 if (get_msr(cpu, extra_msr_offset64, &t->extra_msr64))
c98d5d94
LB		 1104 return -5;
1105
144b44b1
LB		 1106 if (use_c1_residency_msr) {
1107 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1108 return -6;
1109 }
1110
c98d5d94
LB		 1111 /* collect core counters only for 1st thread in core */
1112 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1113 return 0;
1114
fb5d4327 1115 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) {
c98d5d94
LB		 1116 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1117 return -6;
144b44b1
LB		 1118 }
1119
fb5d4327 1120 if (do_nhm_cstates && !do_knl_cstates) {
c98d5d94
LB		 1121 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1122 return -7;
fb5d4327
DC		 1123 } else if (do_knl_cstates) {
1124 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1125 return -7;
c98d5d94
LB		 1126 }
1127
1128 if (do_snb_cstates)
1129 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1130 return -8;
1131
889facbe
LB		 1132 if (do_dts) {
1133 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1134 return -9;
1135 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1136 }
1137
1138
c98d5d94
LB		 1139 /* collect package counters only for 1st core in package */
1140 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1141 return 0;
1142
0b2bb692
LB		 1143 if (do_skl_residency) {
1144 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1145 return -10;
1146 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1147 return -11;
1148 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1149 return -12;
1150 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1151 return -13;
1152 }
ee7e38e3 1153 if (do_pc3)
c98d5d94
LB		 1154 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1155 return -9;
ee7e38e3 1156 if (do_pc6)
c98d5d94
LB		 1157 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1158 return -10;
ee7e38e3 1159 if (do_pc2)
c98d5d94
LB		 1160 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1161 return -11;
ee7e38e3 1162 if (do_pc7)
c98d5d94
LB		 1163 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1164 return -12;
ca58710f
KCA		 1165 if (do_c8_c9_c10) {
1166 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1167 return -13;
1168 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1169 return -13;
1170 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1171 return -13;
1172 }
889facbe
LB		 1173 if (do_rapl & RAPL_PKG) {
1174 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1175 return -13;
1176 p->energy_pkg = msr & 0xFFFFFFFF;
1177 }
1178 if (do_rapl & RAPL_CORES) {
1179 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1180 return -14;
1181 p->energy_cores = msr & 0xFFFFFFFF;
1182 }
1183 if (do_rapl & RAPL_DRAM) {
1184 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1185 return -15;
1186 p->energy_dram = msr & 0xFFFFFFFF;
1187 }
1188 if (do_rapl & RAPL_GFX) {
1189 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1190 return -16;
1191 p->energy_gfx = msr & 0xFFFFFFFF;
1192 }
1193 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1194 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1195 return -16;
1196 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1197 }
1198 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1199 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1200 return -16;
1201 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1202 }
1203 if (do_ptm) {
1204 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1205 return -17;
1206 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1207 }
fdf676e5
LB		 1208
1209 if (do_gfx_rc6_ms)
1210 p->gfx_rc6_ms = gfx_cur_rc6_ms;
1211
27d47356
LB		 1212 if (do_gfx_mhz)
1213 p->gfx_mhz = gfx_cur_mhz;
1214
15aaa346 1215 return 0;
103a8fea
LB		 1216}
1217
ee7e38e3
LB		 1218/*
1219 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1220 * If you change the values, note they are used both in comparisons
1221 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1222 */
1223
1224#define PCLUKN 0 /* Unknown */
1225#define PCLRSV 1 /* Reserved */
1226#define PCL__0 2 /* PC0 */
1227#define PCL__1 3 /* PC1 */
1228#define PCL__2 4 /* PC2 */
1229#define PCL__3 5 /* PC3 */
1230#define PCL__4 6 /* PC4 */
1231#define PCL__6 7 /* PC6 */
1232#define PCL_6N 8 /* PC6 No Retention */
1233#define PCL_6R 9 /* PC6 Retention */
1234#define PCL__7 10 /* PC7 */
1235#define PCL_7S 11 /* PC7 Shrink */
0b2bb692
LB		 1236#define PCL__8 12 /* PC8 */
1237#define PCL__9 13 /* PC9 */
1238#define PCLUNL 14 /* Unlimited */
ee7e38e3
LB		 1239
1240int pkg_cstate_limit = PCLUKN;
1241char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
0b2bb692 1242 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
ee7e38e3 1243
e9257f5f
LB		 1244int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1245int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1246int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1247int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1248int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1249int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
ee7e38e3 1250
a2b7b749
LB		 1251
1252static void
1253calculate_tsc_tweak()
1254{
a2b7b749
LB		 1255 tsc_tweak = base_hz / tsc_hz;
1256}
1257
fcd17211
LB		 1258static void
1259dump_nhm_platform_info(void)
103a8fea
LB		 1260{
1261 unsigned long long msr;
1262 unsigned int ratio;
1263
ec0adc53 1264 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
103a8fea 1265
b7d8c148 1266 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
6574a5d5 1267
103a8fea 1268 ratio = (msr >> 40) & 0xFF;
b7d8c148 1269 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n",
103a8fea
LB		 1270 ratio, bclk, ratio * bclk);
1271
1272 ratio = (msr >> 8) & 0xFF;
b7d8c148 1273 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n",
103a8fea
LB		 1274 ratio, bclk, ratio * bclk);
1275
7ce7d5de 1276 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
b7d8c148 1277 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
bfae2052 1278 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
67920418 1279
fcd17211
LB		 1280 return;
1281}
1282
1283static void
1284dump_hsw_turbo_ratio_limits(void)
1285{
1286 unsigned long long msr;
1287 unsigned int ratio;
1288
7ce7d5de 1289 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
fcd17211 1290
b7d8c148 1291 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
fcd17211
LB		 1292
1293 ratio = (msr >> 8) & 0xFF;
1294 if (ratio)
b7d8c148 1295 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n",
fcd17211
LB		 1296 ratio, bclk, ratio * bclk);
1297
1298 ratio = (msr >> 0) & 0xFF;
1299 if (ratio)
b7d8c148 1300 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n",
fcd17211
LB		 1301 ratio, bclk, ratio * bclk);
1302 return;
1303}
1304
1305static void
1306dump_ivt_turbo_ratio_limits(void)
1307{
1308 unsigned long long msr;
1309 unsigned int ratio;
6574a5d5 1310
7ce7d5de 1311 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
6574a5d5 1312
b7d8c148 1313 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 1314
1315 ratio = (msr >> 56) & 0xFF;
1316 if (ratio)
b7d8c148 1317 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n",
6574a5d5
LB		 1318 ratio, bclk, ratio * bclk);
1319
1320 ratio = (msr >> 48) & 0xFF;
1321 if (ratio)
b7d8c148 1322 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n",
6574a5d5
LB		 1323 ratio, bclk, ratio * bclk);
1324
1325 ratio = (msr >> 40) & 0xFF;
1326 if (ratio)
b7d8c148 1327 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n",
6574a5d5
LB		 1328 ratio, bclk, ratio * bclk);
1329
1330 ratio = (msr >> 32) & 0xFF;
1331 if (ratio)
b7d8c148 1332 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n",
6574a5d5
LB		 1333 ratio, bclk, ratio * bclk);
1334
1335 ratio = (msr >> 24) & 0xFF;
1336 if (ratio)
b7d8c148 1337 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n",
6574a5d5
LB		 1338 ratio, bclk, ratio * bclk);
1339
1340 ratio = (msr >> 16) & 0xFF;
1341 if (ratio)
b7d8c148 1342 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n",
6574a5d5
LB		 1343 ratio, bclk, ratio * bclk);
1344
1345 ratio = (msr >> 8) & 0xFF;
1346 if (ratio)
b7d8c148 1347 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n",
6574a5d5
LB		 1348 ratio, bclk, ratio * bclk);
1349
1350 ratio = (msr >> 0) & 0xFF;
1351 if (ratio)
b7d8c148 1352 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n",
6574a5d5 1353 ratio, bclk, ratio * bclk);
fcd17211
LB		 1354 return;
1355}
6574a5d5 1356
fcd17211
LB		 1357static void
1358dump_nhm_turbo_ratio_limits(void)
1359{
1360 unsigned long long msr;
1361 unsigned int ratio;
103a8fea 1362
7ce7d5de 1363 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
103a8fea 1364
b7d8c148 1365 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 1366
1367 ratio = (msr >> 56) & 0xFF;
1368 if (ratio)
b7d8c148 1369 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n",
6574a5d5
LB		 1370 ratio, bclk, ratio * bclk);
1371
1372 ratio = (msr >> 48) & 0xFF;
1373 if (ratio)
b7d8c148 1374 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n",
6574a5d5
LB		 1375 ratio, bclk, ratio * bclk);
1376
1377 ratio = (msr >> 40) & 0xFF;
1378 if (ratio)
b7d8c148 1379 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n",
6574a5d5
LB		 1380 ratio, bclk, ratio * bclk);
1381
1382 ratio = (msr >> 32) & 0xFF;
1383 if (ratio)
b7d8c148 1384 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n",
6574a5d5
LB		 1385 ratio, bclk, ratio * bclk);
1386
103a8fea
LB		 1387 ratio = (msr >> 24) & 0xFF;
1388 if (ratio)
b7d8c148 1389 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n",
103a8fea
LB		 1390 ratio, bclk, ratio * bclk);
1391
1392 ratio = (msr >> 16) & 0xFF;
1393 if (ratio)
b7d8c148 1394 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n",
103a8fea
LB		 1395 ratio, bclk, ratio * bclk);
1396
1397 ratio = (msr >> 8) & 0xFF;
1398 if (ratio)
b7d8c148 1399 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n",
103a8fea
LB		 1400 ratio, bclk, ratio * bclk);
1401
1402 ratio = (msr >> 0) & 0xFF;
1403 if (ratio)
b7d8c148 1404 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n",
103a8fea 1405 ratio, bclk, ratio * bclk);
fcd17211
LB		 1406 return;
1407}
3a9a941d 1408
fb5d4327
DC		 1409static void
1410dump_knl_turbo_ratio_limits(void)
1411{
cbf97aba
HC		 1412 const unsigned int buckets_no = 7;
1413
fb5d4327 1414 unsigned long long msr;
cbf97aba
HC		 1415 int delta_cores, delta_ratio;
1416 int i, b_nr;
1417 unsigned int cores[buckets_no];
1418 unsigned int ratio[buckets_no];
fb5d4327 1419
7ce7d5de 1420 get_msr(base_cpu, MSR_NHM_TURBO_RATIO_LIMIT, &msr);
fb5d4327 1421
b7d8c148 1422 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
bfae2052 1423 base_cpu, msr);
fb5d4327
DC		 1424
1425 /**
1426 * Turbo encoding in KNL is as follows:
cbf97aba
HC		 1427 * [0] -- Reserved
1428 * [7:1] -- Base value of number of active cores of bucket 1.
fb5d4327
DC		 1429 * [15:8] -- Base value of freq ratio of bucket 1.
1430 * [20:16] -- +ve delta of number of active cores of bucket 2.
1431 * i.e. active cores of bucket 2 =
1432 * active cores of bucket 1 + delta
1433 * [23:21] -- Negative delta of freq ratio of bucket 2.
1434 * i.e. freq ratio of bucket 2 =
1435 * freq ratio of bucket 1 - delta
1436 * [28:24]-- +ve delta of number of active cores of bucket 3.
1437 * [31:29]-- -ve delta of freq ratio of bucket 3.
1438 * [36:32]-- +ve delta of number of active cores of bucket 4.
1439 * [39:37]-- -ve delta of freq ratio of bucket 4.
1440 * [44:40]-- +ve delta of number of active cores of bucket 5.
1441 * [47:45]-- -ve delta of freq ratio of bucket 5.
1442 * [52:48]-- +ve delta of number of active cores of bucket 6.
1443 * [55:53]-- -ve delta of freq ratio of bucket 6.
1444 * [60:56]-- +ve delta of number of active cores of bucket 7.
1445 * [63:61]-- -ve delta of freq ratio of bucket 7.
1446 */
cbf97aba
HC		 1447
1448 b_nr = 0;
1449 cores[b_nr] = (msr & 0xFF) >> 1;
1450 ratio[b_nr] = (msr >> 8) & 0xFF;
1451
1452 for (i = 16; i < 64; i += 8) {
fb5d4327 1453 delta_cores = (msr >> i) & 0x1F;
cbf97aba
HC		 1454 delta_ratio = (msr >> (i + 5)) & 0x7;
1455
1456 cores[b_nr + 1] = cores[b_nr] + delta_cores;
1457 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
1458 b_nr++;
1459 }
1460
1461 for (i = buckets_no - 1; i >= 0; i--)
1462 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
b7d8c148 1463 fprintf(outf,
fb5d4327 1464 "%d * %.0f = %.0f MHz max turbo %d active cores\n",
cbf97aba 1465 ratio[i], bclk, ratio[i] * bclk, cores[i]);
fb5d4327
DC		 1466}
1467
fcd17211
LB		 1468static void
1469dump_nhm_cst_cfg(void)
1470{
1471 unsigned long long msr;
1472
7ce7d5de 1473 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
fcd17211
LB		 1474
1475#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
1476#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
1477
b7d8c148 1478 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr);
fcd17211 1479
b7d8c148 1480 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
fcd17211
LB		 1481 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
1482 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
1483 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
1484 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1485 (msr & (1 << 15)) ? "" : "UN",
1486 (unsigned int)msr & 7,
1487 pkg_cstate_limit_strings[pkg_cstate_limit]);
1488 return;
103a8fea
LB		 1489}
1490
6fb3143b
LB		 1491static void
1492dump_config_tdp(void)
1493{
1494 unsigned long long msr;
1495
1496 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
b7d8c148
LB		 1497 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
1498 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xEF);
6fb3143b
LB		 1499
1500 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
b7d8c148 1501 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
6fb3143b 1502 if (msr) {
b7d8c148
LB		 1503 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0xEFFF);
1504 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0xEFFF);
1505 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xEF);
1506 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0xEFFF);
6fb3143b 1507 }
b7d8c148 1508 fprintf(outf, ")\n");
6fb3143b
LB		 1509
1510 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
b7d8c148 1511 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
6fb3143b 1512 if (msr) {
b7d8c148
LB		 1513 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0xEFFF);
1514 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0xEFFF);
1515 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xEF);
1516 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0xEFFF);
6fb3143b 1517 }
b7d8c148 1518 fprintf(outf, ")\n");
6fb3143b
LB		 1519
1520 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
b7d8c148 1521 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
6fb3143b 1522 if ((msr) & 0x3)
b7d8c148
LB		 1523 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
1524 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1525 fprintf(outf, ")\n");
36229897 1526
6fb3143b 1527 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
b7d8c148
LB		 1528 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
1529 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0x7F);
1530 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1531 fprintf(outf, ")\n");
6fb3143b 1532}
36229897
LB		 1533void free_fd_percpu(void)
1534{
1535 int i;
1536
1537 for (i = 0; i < topo.max_cpu_num; ++i) {
1538 if (fd_percpu[i] != 0)
1539 close(fd_percpu[i]);
1540 }
1541
1542 free(fd_percpu);
1543}
6fb3143b 1544
c98d5d94 1545void free_all_buffers(void)
103a8fea 1546{
c98d5d94
LB		 1547 CPU_FREE(cpu_present_set);
1548 cpu_present_set = NULL;
36229897 1549 cpu_present_setsize = 0;
103a8fea 1550
c98d5d94
LB		 1551 CPU_FREE(cpu_affinity_set);
1552 cpu_affinity_set = NULL;
1553 cpu_affinity_setsize = 0;
103a8fea 1554
c98d5d94
LB		 1555 free(thread_even);
1556 free(core_even);
1557 free(package_even);
103a8fea 1558
c98d5d94
LB		 1559 thread_even = NULL;
1560 core_even = NULL;
1561 package_even = NULL;
103a8fea 1562
c98d5d94
LB		 1563 free(thread_odd);
1564 free(core_odd);
1565 free(package_odd);
103a8fea 1566
c98d5d94
LB		 1567 thread_odd = NULL;
1568 core_odd = NULL;
1569 package_odd = NULL;
103a8fea 1570
c98d5d94
LB		 1571 free(output_buffer);
1572 output_buffer = NULL;
1573 outp = NULL;
36229897
LB		 1574
1575 free_fd_percpu();
562a2d37
LB		 1576
1577 free(irq_column_2_cpu);
1578 free(irqs_per_cpu);
103a8fea
LB		 1579}
1580
57a42a34
JT		 1581/*
1582 * Open a file, and exit on failure
1583 */
1584FILE *fopen_or_die(const char *path, const char *mode)
1585{
b7d8c148 1586 FILE *filep = fopen(path, mode);
b2c95d90
JT		 1587 if (!filep)
1588 err(1, "%s: open failed", path);
57a42a34
JT		 1589 return filep;
1590}
1591
c98d5d94 1592/*
95aebc44 1593 * Parse a file containing a single int.
c98d5d94 1594 */
95aebc44 1595int parse_int_file(const char *fmt, ...)
103a8fea 1596{
95aebc44
JT		 1597 va_list args;
1598 char path[PATH_MAX];
c98d5d94 1599 FILE *filep;
95aebc44 1600 int value;
103a8fea 1601
95aebc44
JT		 1602 va_start(args, fmt);
1603 vsnprintf(path, sizeof(path), fmt, args);
1604 va_end(args);
57a42a34 1605 filep = fopen_or_die(path, "r");
b2c95d90
JT		 1606 if (fscanf(filep, "%d", &value) != 1)
1607 err(1, "%s: failed to parse number from file", path);
c98d5d94 1608 fclose(filep);
95aebc44
JT		 1609 return value;
1610}
1611
1612/*
e275b388
DC		 1613 * get_cpu_position_in_core(cpu)
1614 * return the position of the CPU among its HT siblings in the core
1615 * return -1 if the sibling is not in list
95aebc44 1616 */
e275b388 1617int get_cpu_position_in_core(int cpu)
95aebc44 1618{
e275b388
DC		 1619 char path[64];
1620 FILE *filep;
1621 int this_cpu;
1622 char character;
1623 int i;
1624
1625 sprintf(path,
1626 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
1627 cpu);
1628 filep = fopen(path, "r");
1629 if (filep == NULL) {
1630 perror(path);
1631 exit(1);
1632 }
1633
1634 for (i = 0; i < topo.num_threads_per_core; i++) {
1635 fscanf(filep, "%d", &this_cpu);
1636 if (this_cpu == cpu) {
1637 fclose(filep);
1638 return i;
1639 }
1640
1641 /* Account for no separator after last thread*/
1642 if (i != (topo.num_threads_per_core - 1))
1643 fscanf(filep, "%c", &character);
1644 }
1645
1646 fclose(filep);
1647 return -1;
103a8fea
LB		 1648}
1649
c98d5d94
LB		 1650/*
1651 * cpu_is_first_core_in_package(cpu)
1652 * return 1 if given CPU is 1st core in package
1653 */
1654int cpu_is_first_core_in_package(int cpu)
103a8fea 1655{
95aebc44 1656 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
103a8fea
LB		 1657}
1658
1659int get_physical_package_id(int cpu)
1660{
95aebc44 1661 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
103a8fea
LB		 1662}
1663
1664int get_core_id(int cpu)
1665{
95aebc44 1666 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
103a8fea
LB		 1667}
1668
c98d5d94
LB		 1669int get_num_ht_siblings(int cpu)
1670{
1671 char path[80];
1672 FILE *filep;
e275b388
DC		 1673 int sib1;
1674 int matches = 0;
c98d5d94 1675 char character;
e275b388
DC		 1676 char str[100];
1677 char *ch;
c98d5d94
LB		 1678
1679 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
57a42a34 1680 filep = fopen_or_die(path, "r");
e275b388 1681
c98d5d94
LB		 1682 /*
1683 * file format:
e275b388
DC		 1684 * A ',' separated or '-' separated set of numbers
1685 * (eg 1-2 or 1,3,4,5)
c98d5d94 1686 */
e275b388
DC		 1687 fscanf(filep, "%d%c\n", &sib1, &character);
1688 fseek(filep, 0, SEEK_SET);
1689 fgets(str, 100, filep);
1690 ch = strchr(str, character);
1691 while (ch != NULL) {
1692 matches++;
1693 ch = strchr(ch+1, character);
1694 }
c98d5d94
LB		 1695
1696 fclose(filep);
e275b388 1697 return matches+1;
c98d5d94
LB		 1698}
1699
103a8fea 1700/*
c98d5d94
LB		 1701 * run func(thread, core, package) in topology order
1702 * skip non-present cpus
103a8fea
LB		 1703 */
1704
c98d5d94
LB		 1705int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
1706 struct pkg_data *, struct thread_data *, struct core_data *,
1707 struct pkg_data *), struct thread_data *thread_base,
1708 struct core_data *core_base, struct pkg_data *pkg_base,
1709 struct thread_data *thread_base2, struct core_data *core_base2,
1710 struct pkg_data *pkg_base2)
1711{
1712 int retval, pkg_no, core_no, thread_no;
1713
1714 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
1715 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
1716 for (thread_no = 0; thread_no <
1717 topo.num_threads_per_core; ++thread_no) {
1718 struct thread_data *t, *t2;
1719 struct core_data *c, *c2;
1720 struct pkg_data *p, *p2;
1721
1722 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
1723
1724 if (cpu_is_not_present(t->cpu_id))
1725 continue;
1726
1727 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
1728
1729 c = GET_CORE(core_base, core_no, pkg_no);
1730 c2 = GET_CORE(core_base2, core_no, pkg_no);
1731
1732 p = GET_PKG(pkg_base, pkg_no);
1733 p2 = GET_PKG(pkg_base2, pkg_no);
1734
1735 retval = func(t, c, p, t2, c2, p2);
1736 if (retval)
1737 return retval;
1738 }
1739 }
1740 }
1741 return 0;
1742}
1743
1744/*
1745 * run func(cpu) on every cpu in /proc/stat
1746 * return max_cpu number
1747 */
1748int for_all_proc_cpus(int (func)(int))
103a8fea
LB		 1749{
1750 FILE *fp;
c98d5d94 1751 int cpu_num;
103a8fea
LB		 1752 int retval;
1753
57a42a34 1754 fp = fopen_or_die(proc_stat, "r");
103a8fea
LB		 1755
1756 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
b2c95d90
JT		 1757 if (retval != 0)
1758 err(1, "%s: failed to parse format", proc_stat);
103a8fea 1759
c98d5d94
LB		 1760 while (1) {
1761 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
103a8fea
LB		 1762 if (retval != 1)
1763 break;
1764
c98d5d94
LB		 1765 retval = func(cpu_num);
1766 if (retval) {
1767 fclose(fp);
1768 return(retval);
1769 }
103a8fea
LB		 1770 }
1771 fclose(fp);
c98d5d94 1772 return 0;
103a8fea
LB		 1773}
1774
1775void re_initialize(void)
1776{
c98d5d94
LB		 1777 free_all_buffers();
1778 setup_all_buffers();
1779 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
103a8fea
LB		 1780}
1781
c98d5d94 1782
103a8fea 1783/*
c98d5d94
LB		 1784 * count_cpus()
1785 * remember the last one seen, it will be the max
103a8fea 1786 */
c98d5d94 1787int count_cpus(int cpu)
103a8fea 1788{
c98d5d94
LB		 1789 if (topo.max_cpu_num < cpu)
1790 topo.max_cpu_num = cpu;
103a8fea 1791
c98d5d94
LB		 1792 topo.num_cpus += 1;
1793 return 0;
1794}
1795int mark_cpu_present(int cpu)
1796{
1797 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
15aaa346 1798 return 0;
103a8fea
LB		 1799}
1800
562a2d37
LB		 1801/*
1802 * snapshot_proc_interrupts()
1803 *
1804 * read and record summary of /proc/interrupts
1805 *
1806 * return 1 if config change requires a restart, else return 0
1807 */
1808int snapshot_proc_interrupts(void)
1809{
1810 static FILE *fp;
1811 int column, retval;
1812
1813 if (fp == NULL)
1814 fp = fopen_or_die("/proc/interrupts", "r");
1815 else
1816 rewind(fp);
1817
1818 /* read 1st line of /proc/interrupts to get cpu* name for each column */
1819 for (column = 0; column < topo.num_cpus; ++column) {
1820 int cpu_number;
1821
1822 retval = fscanf(fp, " CPU%d", &cpu_number);
1823 if (retval != 1)
1824 break;
1825
1826 if (cpu_number > topo.max_cpu_num) {
1827 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
1828 return 1;
1829 }
1830
1831 irq_column_2_cpu[column] = cpu_number;
1832 irqs_per_cpu[cpu_number] = 0;
1833 }
1834
1835 /* read /proc/interrupt count lines and sum up irqs per cpu */
1836 while (1) {
1837 int column;
1838 char buf[64];
1839
1840 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
1841 if (retval != 1)
1842 break;
1843
1844 /* read the count per cpu */
1845 for (column = 0; column < topo.num_cpus; ++column) {
1846
1847 int cpu_number, irq_count;
1848
1849 retval = fscanf(fp, " %d", &irq_count);
1850 if (retval != 1)
1851 break;
1852
1853 cpu_number = irq_column_2_cpu[column];
1854 irqs_per_cpu[cpu_number] += irq_count;
1855
1856 }
1857
1858 while (getc(fp) != '\n')
1859 ; /* flush interrupt description */
1860
1861 }
1862 return 0;
1863}
fdf676e5
LB		 1864/*
1865 * snapshot_gfx_rc6_ms()
1866 *
1867 * record snapshot of
1868 * /sys/class/drm/card0/power/rc6_residency_ms
1869 *
1870 * return 1 if config change requires a restart, else return 0
1871 */
1872int snapshot_gfx_rc6_ms(void)
1873{
1874 FILE *fp;
1875 int retval;
1876
1877 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
1878
1879 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
1880 if (retval != 1)
1881 err(1, "GFX rc6");
1882
1883 fclose(fp);
1884
1885 return 0;
1886}
27d47356
LB		 1887/*
1888 * snapshot_gfx_mhz()
1889 *
1890 * record snapshot of
1891 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
1892 *
1893 * return 1 if config change requires a restart, else return 0
1894 */
1895int snapshot_gfx_mhz(void)
1896{
1897 static FILE *fp;
1898 int retval;
1899
1900 if (fp == NULL)
1901 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
1902 else
1903 rewind(fp);
1904
1905 retval = fscanf(fp, "%d", &gfx_cur_mhz);
1906 if (retval != 1)
1907 err(1, "GFX MHz");
1908
1909 return 0;
1910}
562a2d37
LB		 1911
1912/*
1913 * snapshot /proc and /sys files
1914 *
1915 * return 1 if configuration restart needed, else return 0
1916 */
1917int snapshot_proc_sysfs_files(void)
1918{
1919 if (snapshot_proc_interrupts())
1920 return 1;
1921
fdf676e5
LB		 1922 if (do_gfx_rc6_ms)
1923 snapshot_gfx_rc6_ms();
1924
27d47356
LB		 1925 if (do_gfx_mhz)
1926 snapshot_gfx_mhz();
1927
562a2d37
LB		 1928 return 0;
1929}
1930
103a8fea
LB		 1931void turbostat_loop()
1932{
c98d5d94 1933 int retval;
e52966c0 1934 int restarted = 0;
c98d5d94 1935
103a8fea 1936restart:
e52966c0
LB		 1937 restarted++;
1938
562a2d37 1939 snapshot_proc_sysfs_files();
c98d5d94 1940 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 1941 if (retval < -1) {
1942 exit(retval);
1943 } else if (retval == -1) {
e52966c0
LB		 1944 if (restarted > 1) {
1945 exit(retval);
1946 }
c98d5d94
LB		 1947 re_initialize();
1948 goto restart;
1949 }
e52966c0 1950 restarted = 0;
103a8fea
LB		 1951 gettimeofday(&tv_even, (struct timezone *)NULL);
1952
1953 while (1) {
c98d5d94 1954 if (for_all_proc_cpus(cpu_is_not_present)) {
103a8fea
LB		 1955 re_initialize();
1956 goto restart;
1957 }
2a0609c0 1958 nanosleep(&interval_ts, NULL);
562a2d37
LB		 1959 if (snapshot_proc_sysfs_files())
1960 goto restart;
c98d5d94 1961 retval = for_all_cpus(get_counters, ODD_COUNTERS);
d91bb17c
LB		 1962 if (retval < -1) {
1963 exit(retval);
1964 } else if (retval == -1) {
15aaa346
LB		 1965 re_initialize();
1966 goto restart;
1967 }
103a8fea 1968 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 1969 timersub(&tv_odd, &tv_even, &tv_delta);
c98d5d94
LB		 1970 for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS);
1971 compute_average(EVEN_COUNTERS);
1972 format_all_counters(EVEN_COUNTERS);
b7d8c148 1973 flush_output_stdout();
2a0609c0 1974 nanosleep(&interval_ts, NULL);
562a2d37
LB		 1975 if (snapshot_proc_sysfs_files())
1976 goto restart;
c98d5d94 1977 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 1978 if (retval < -1) {
1979 exit(retval);
1980 } else if (retval == -1) {
103a8fea
LB		 1981 re_initialize();
1982 goto restart;
1983 }
103a8fea 1984 gettimeofday(&tv_even, (struct timezone *)NULL);
103a8fea 1985 timersub(&tv_even, &tv_odd, &tv_delta);
c98d5d94
LB		 1986 for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS);
1987 compute_average(ODD_COUNTERS);
1988 format_all_counters(ODD_COUNTERS);
b7d8c148 1989 flush_output_stdout();
103a8fea
LB		 1990 }
1991}
1992
1993void check_dev_msr()
1994{
1995 struct stat sb;
7ce7d5de 1996 char pathname[32];
103a8fea 1997
7ce7d5de
PB		 1998 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
1999 if (stat(pathname, &sb))
a21d38c8
LB		 2000 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2001 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
103a8fea
LB		 2002}
2003
98481e79 2004void check_permissions()
103a8fea 2005{
98481e79
LB		 2006 struct __user_cap_header_struct cap_header_data;
2007 cap_user_header_t cap_header = &cap_header_data;
2008 struct __user_cap_data_struct cap_data_data;
2009 cap_user_data_t cap_data = &cap_data_data;
2010 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
2011 int do_exit = 0;
7ce7d5de 2012 char pathname[32];
98481e79
LB		 2013
2014 /* check for CAP_SYS_RAWIO */
2015 cap_header->pid = getpid();
2016 cap_header->version = _LINUX_CAPABILITY_VERSION;
2017 if (capget(cap_header, cap_data) < 0)
2018 err(-6, "capget(2) failed");
2019
2020 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
2021 do_exit++;
2022 warnx("capget(CAP_SYS_RAWIO) failed,"
2023 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
2024 }
2025
2026 /* test file permissions */
7ce7d5de
PB		 2027 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2028 if (euidaccess(pathname, R_OK)) {
98481e79
LB		 2029 do_exit++;
2030 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2031 }
2032
2033 /* if all else fails, thell them to be root */
2034 if (do_exit)
2035 if (getuid() != 0)
d7899447 2036 warnx("... or simply run as root");
98481e79
LB		 2037
2038 if (do_exit)
2039 exit(-6);
103a8fea
LB		 2040}
2041
d7899447
LB		 2042/*
2043 * NHM adds support for additional MSRs:
2044 *
2045 * MSR_SMI_COUNT 0x00000034
2046 *
ec0adc53 2047 * MSR_PLATFORM_INFO 0x000000ce
d7899447
LB		 2048 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
2049 *
2050 * MSR_PKG_C3_RESIDENCY 0x000003f8
2051 * MSR_PKG_C6_RESIDENCY 0x000003f9
2052 * MSR_CORE_C3_RESIDENCY 0x000003fc
2053 * MSR_CORE_C6_RESIDENCY 0x000003fd
2054 *
ee7e38e3
LB		 2055 * Side effect:
2056 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL
d7899447 2057 */
ee7e38e3 2058int probe_nhm_msrs(unsigned int family, unsigned int model)
103a8fea 2059{
ee7e38e3 2060 unsigned long long msr;
21ed5574 2061 unsigned int base_ratio;
ee7e38e3
LB		 2062 int *pkg_cstate_limits;
2063
103a8fea
LB		 2064 if (!genuine_intel)
2065 return 0;
2066
2067 if (family != 6)
2068 return 0;
2069
21ed5574
LB		 2070 bclk = discover_bclk(family, model);
2071
103a8fea
LB		 2072 switch (model) {
2073 case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2074 case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
2075 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
2076 case 0x25: /* Westmere Client - Clarkdale, Arrandale */
2077 case 0x2C: /* Westmere EP - Gulftown */
ee7e38e3
LB		 2078 case 0x2E: /* Nehalem-EX Xeon - Beckton */
2079 case 0x2F: /* Westmere-EX Xeon - Eagleton */
2080 pkg_cstate_limits = nhm_pkg_cstate_limits;
2081 break;
103a8fea
LB		 2082 case 0x2A: /* SNB */
2083 case 0x2D: /* SNB Xeon */
553575f1 2084 case 0x3A: /* IVB */
1300651b 2085 case 0x3E: /* IVB Xeon */
ee7e38e3
LB		 2086 pkg_cstate_limits = snb_pkg_cstate_limits;
2087 break;
70b43400 2088 case 0x3C: /* HSW */
e6f9bb3c 2089 case 0x3F: /* HSX */
70b43400 2090 case 0x45: /* HSW */
149c2319 2091 case 0x46: /* HSW */
4e8e863f 2092 case 0x3D: /* BDW */
48a0631c 2093 case 0x47: /* BDW */
4e8e863f
LB		 2094 case 0x4F: /* BDX */
2095 case 0x56: /* BDX-DE */
0b2bb692
LB		 2096 case 0x4E: /* SKL */
2097 case 0x5E: /* SKL */
ee7e38e3
LB		 2098 pkg_cstate_limits = hsw_pkg_cstate_limits;
2099 break;
2100 case 0x37: /* BYT */
2101 case 0x4D: /* AVN */
2102 pkg_cstate_limits = slv_pkg_cstate_limits;
2103 break;
2104 case 0x4C: /* AMT */
2105 pkg_cstate_limits = amt_pkg_cstate_limits;
2106 break;
2107 case 0x57: /* PHI */
2108 pkg_cstate_limits = phi_pkg_cstate_limits;
2109 break;
103a8fea
LB		 2110 default:
2111 return 0;
2112 }
7ce7d5de 2113 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
e9257f5f 2114 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
ee7e38e3 2115
ec0adc53 2116 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
21ed5574
LB		 2117 base_ratio = (msr >> 8) & 0xFF;
2118
2119 base_hz = base_ratio * bclk * 1000000;
2120 has_base_hz = 1;
ee7e38e3 2121 return 1;
103a8fea 2122}
d7899447
LB		 2123int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
2124{
d7899447
LB		 2125 switch (model) {
2126 /* Nehalem compatible, but do not include turbo-ratio limit support */
2127 case 0x2E: /* Nehalem-EX Xeon - Beckton */
2128 case 0x2F: /* Westmere-EX Xeon - Eagleton */
cbf97aba 2129 case 0x57: /* PHI - Knights Landing (different MSR definition) */
d7899447
LB		 2130 return 0;
2131 default:
2132 return 1;
2133 }
2134}
6574a5d5
LB		 2135int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2136{
2137 if (!genuine_intel)
2138 return 0;
2139
2140 if (family != 6)
2141 return 0;
2142
2143 switch (model) {
2144 case 0x3E: /* IVB Xeon */
fcd17211
LB		 2145 case 0x3F: /* HSW Xeon */
2146 return 1;
2147 default:
2148 return 0;
2149 }
2150}
2151int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
2152{
2153 if (!genuine_intel)
2154 return 0;
2155
2156 if (family != 6)
2157 return 0;
2158
2159 switch (model) {
2160 case 0x3F: /* HSW Xeon */
6574a5d5
LB		 2161 return 1;
2162 default:
2163 return 0;
2164 }
2165}
2166
fb5d4327
DC		 2167int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
2168{
2169 if (!genuine_intel)
2170 return 0;
2171
2172 if (family != 6)
2173 return 0;
2174
2175 switch (model) {
2176 case 0x57: /* Knights Landing */
2177 return 1;
2178 default:
2179 return 0;
2180 }
2181}
6fb3143b
LB		 2182int has_config_tdp(unsigned int family, unsigned int model)
2183{
2184 if (!genuine_intel)
2185 return 0;
2186
2187 if (family != 6)
2188 return 0;
2189
2190 switch (model) {
2191 case 0x3A: /* IVB */
6fb3143b
LB		 2192 case 0x3C: /* HSW */
2193 case 0x3F: /* HSX */
2194 case 0x45: /* HSW */
2195 case 0x46: /* HSW */
2196 case 0x3D: /* BDW */
2197 case 0x47: /* BDW */
2198 case 0x4F: /* BDX */
2199 case 0x56: /* BDX-DE */
2200 case 0x4E: /* SKL */
2201 case 0x5E: /* SKL */
2202
2203 case 0x57: /* Knights Landing */
2204 return 1;
2205 default:
2206 return 0;
2207 }
2208}
2209
fcd17211 2210static void
58cc30a4 2211dump_cstate_pstate_config_info(int family, int model)
fcd17211
LB		 2212{
2213 if (!do_nhm_platform_info)
2214 return;
2215
2216 dump_nhm_platform_info();
2217
2218 if (has_hsw_turbo_ratio_limit(family, model))
2219 dump_hsw_turbo_ratio_limits();
2220
2221 if (has_ivt_turbo_ratio_limit(family, model))
2222 dump_ivt_turbo_ratio_limits();
2223
2224 if (has_nhm_turbo_ratio_limit(family, model))
2225 dump_nhm_turbo_ratio_limits();
2226
fb5d4327
DC		 2227 if (has_knl_turbo_ratio_limit(family, model))
2228 dump_knl_turbo_ratio_limits();
2229
6fb3143b
LB		 2230 if (has_config_tdp(family, model))
2231 dump_config_tdp();
2232
fcd17211
LB		 2233 dump_nhm_cst_cfg();
2234}
2235
2236
889facbe
LB		 2237/*
2238 * print_epb()
2239 * Decode the ENERGY_PERF_BIAS MSR
2240 */
2241int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2242{
2243 unsigned long long msr;
2244 char *epb_string;
2245 int cpu;
2246
2247 if (!has_epb)
2248 return 0;
2249
2250 cpu = t->cpu_id;
2251
2252 /* EPB is per-package */
2253 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2254 return 0;
2255
2256 if (cpu_migrate(cpu)) {
b7d8c148 2257 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2258 return -1;
2259 }
2260
2261 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
2262 return 0;
2263
e9be7dd6 2264 switch (msr & 0xF) {
889facbe
LB		 2265 case ENERGY_PERF_BIAS_PERFORMANCE:
2266 epb_string = "performance";
2267 break;
2268 case ENERGY_PERF_BIAS_NORMAL:
2269 epb_string = "balanced";
2270 break;
2271 case ENERGY_PERF_BIAS_POWERSAVE:
2272 epb_string = "powersave";
2273 break;
2274 default:
2275 epb_string = "custom";
2276 break;
2277 }
b7d8c148 2278 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
889facbe
LB		 2279
2280 return 0;
2281}
7f5c258e
LB		 2282/*
2283 * print_hwp()
2284 * Decode the MSR_HWP_CAPABILITIES
2285 */
2286int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2287{
2288 unsigned long long msr;
2289 int cpu;
2290
2291 if (!has_hwp)
2292 return 0;
2293
2294 cpu = t->cpu_id;
2295
2296 /* MSR_HWP_CAPABILITIES is per-package */
2297 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2298 return 0;
2299
2300 if (cpu_migrate(cpu)) {
b7d8c148 2301 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
7f5c258e
LB		 2302 return -1;
2303 }
2304
2305 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
2306 return 0;
2307
b7d8c148 2308 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
7f5c258e
LB		 2309 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
2310
2311 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
2312 if ((msr & (1 << 0)) == 0)
2313 return 0;
2314
2315 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
2316 return 0;
2317
b7d8c148 2318 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
7f5c258e
LB		 2319 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n",
2320 cpu, msr,
2321 (unsigned int)HWP_HIGHEST_PERF(msr),
2322 (unsigned int)HWP_GUARANTEED_PERF(msr),
2323 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
2324 (unsigned int)HWP_LOWEST_PERF(msr));
2325
2326 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
2327 return 0;
2328
b7d8c148 2329 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
7f5c258e
LB		 2330 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n",
2331 cpu, msr,
2332 (unsigned int)(((msr) >> 0) & 0xff),
2333 (unsigned int)(((msr) >> 8) & 0xff),
2334 (unsigned int)(((msr) >> 16) & 0xff),
2335 (unsigned int)(((msr) >> 24) & 0xff),
2336 (unsigned int)(((msr) >> 32) & 0xff3),
2337 (unsigned int)(((msr) >> 42) & 0x1));
2338
2339 if (has_hwp_pkg) {
2340 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
2341 return 0;
2342
b7d8c148 2343 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
7f5c258e
LB		 2344 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n",
2345 cpu, msr,
2346 (unsigned int)(((msr) >> 0) & 0xff),
2347 (unsigned int)(((msr) >> 8) & 0xff),
2348 (unsigned int)(((msr) >> 16) & 0xff),
2349 (unsigned int)(((msr) >> 24) & 0xff),
2350 (unsigned int)(((msr) >> 32) & 0xff3));
2351 }
2352 if (has_hwp_notify) {
2353 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
2354 return 0;
2355
b7d8c148 2356 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
7f5c258e
LB		 2357 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
2358 cpu, msr,
2359 ((msr) & 0x1) ? "EN" : "Dis",
2360 ((msr) & 0x2) ? "EN" : "Dis");
2361 }
2362 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
2363 return 0;
2364
b7d8c148 2365 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
7f5c258e
LB		 2366 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
2367 cpu, msr,
2368 ((msr) & 0x1) ? "" : "No-",
2369 ((msr) & 0x2) ? "" : "No-");
2370
2371 return 0;
2372}
889facbe 2373
3a9a941d
LB		 2374/*
2375 * print_perf_limit()
2376 */
2377int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2378{
2379 unsigned long long msr;
2380 int cpu;
2381
2382 cpu = t->cpu_id;
2383
2384 /* per-package */
2385 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2386 return 0;
2387
2388 if (cpu_migrate(cpu)) {
b7d8c148 2389 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3a9a941d
LB		 2390 return -1;
2391 }
2392
2393 if (do_core_perf_limit_reasons) {
2394 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2395 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2396 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
e33cbe85 2397 (msr & 1 << 15) ? "bit15, " : "",
3a9a941d 2398 (msr & 1 << 14) ? "bit14, " : "",
e33cbe85
LB		 2399 (msr & 1 << 13) ? "Transitions, " : "",
2400 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
2401 (msr & 1 << 11) ? "PkgPwrL2, " : "",
2402 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2403 (msr & 1 << 9) ? "CorePwr, " : "",
2404 (msr & 1 << 8) ? "Amps, " : "",
2405 (msr & 1 << 6) ? "VR-Therm, " : "",
2406 (msr & 1 << 5) ? "Auto-HWP, " : "",
2407 (msr & 1 << 4) ? "Graphics, " : "",
2408 (msr & 1 << 2) ? "bit2, " : "",
2409 (msr & 1 << 1) ? "ThermStatus, " : "",
2410 (msr & 1 << 0) ? "PROCHOT, " : "");
b7d8c148 2411 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
e33cbe85 2412 (msr & 1 << 31) ? "bit31, " : "",
3a9a941d 2413 (msr & 1 << 30) ? "bit30, " : "",
e33cbe85
LB		 2414 (msr & 1 << 29) ? "Transitions, " : "",
2415 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
2416 (msr & 1 << 27) ? "PkgPwrL2, " : "",
2417 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2418 (msr & 1 << 25) ? "CorePwr, " : "",
2419 (msr & 1 << 24) ? "Amps, " : "",
2420 (msr & 1 << 22) ? "VR-Therm, " : "",
2421 (msr & 1 << 21) ? "Auto-HWP, " : "",
2422 (msr & 1 << 20) ? "Graphics, " : "",
2423 (msr & 1 << 18) ? "bit18, " : "",
2424 (msr & 1 << 17) ? "ThermStatus, " : "",
2425 (msr & 1 << 16) ? "PROCHOT, " : "");
3a9a941d
LB		 2426
2427 }
2428 if (do_gfx_perf_limit_reasons) {
2429 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2430 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2431 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3a9a941d
LB		 2432 (msr & 1 << 0) ? "PROCHOT, " : "",
2433 (msr & 1 << 1) ? "ThermStatus, " : "",
2434 (msr & 1 << 4) ? "Graphics, " : "",
2435 (msr & 1 << 6) ? "VR-Therm, " : "",
2436 (msr & 1 << 8) ? "Amps, " : "",
2437 (msr & 1 << 9) ? "GFXPwr, " : "",
2438 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2439 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 2440 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3a9a941d
LB		 2441 (msr & 1 << 16) ? "PROCHOT, " : "",
2442 (msr & 1 << 17) ? "ThermStatus, " : "",
2443 (msr & 1 << 20) ? "Graphics, " : "",
2444 (msr & 1 << 22) ? "VR-Therm, " : "",
2445 (msr & 1 << 24) ? "Amps, " : "",
2446 (msr & 1 << 25) ? "GFXPwr, " : "",
2447 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2448 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2449 }
2450 if (do_ring_perf_limit_reasons) {
2451 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2452 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2453 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3a9a941d
LB		 2454 (msr & 1 << 0) ? "PROCHOT, " : "",
2455 (msr & 1 << 1) ? "ThermStatus, " : "",
2456 (msr & 1 << 6) ? "VR-Therm, " : "",
2457 (msr & 1 << 8) ? "Amps, " : "",
2458 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2459 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 2460 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3a9a941d
LB		 2461 (msr & 1 << 16) ? "PROCHOT, " : "",
2462 (msr & 1 << 17) ? "ThermStatus, " : "",
2463 (msr & 1 << 22) ? "VR-Therm, " : "",
2464 (msr & 1 << 24) ? "Amps, " : "",
2465 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2466 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2467 }
2468 return 0;
2469}
2470
889facbe
LB		 2471#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
2472#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
2473
58cc30a4 2474double get_tdp(int model)
144b44b1
LB		 2475{
2476 unsigned long long msr;
2477
2478 if (do_rapl & RAPL_PKG_POWER_INFO)
7ce7d5de 2479 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
144b44b1
LB		 2480 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
2481
2482 switch (model) {
2483 case 0x37:
2484 case 0x4D:
2485 return 30.0;
2486 default:
2487 return 135.0;
2488 }
2489}
2490
40ee8e3b
AS		 2491/*
2492 * rapl_dram_energy_units_probe()
2493 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
2494 */
2495static double
2496rapl_dram_energy_units_probe(int model, double rapl_energy_units)
2497{
2498 /* only called for genuine_intel, family 6 */
2499
2500 switch (model) {
2501 case 0x3F: /* HSX */
2502 case 0x4F: /* BDX */
2503 case 0x56: /* BDX-DE */
fb5d4327 2504 case 0x57: /* KNL */
40ee8e3b
AS		 2505 return (rapl_dram_energy_units = 15.3 / 1000000);
2506 default:
2507 return (rapl_energy_units);
2508 }
2509}
2510
144b44b1 2511
889facbe
LB		 2512/*
2513 * rapl_probe()
2514 *
144b44b1 2515 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
889facbe
LB		 2516 */
2517void rapl_probe(unsigned int family, unsigned int model)
2518{
2519 unsigned long long msr;
144b44b1 2520 unsigned int time_unit;
889facbe
LB		 2521 double tdp;
2522
2523 if (!genuine_intel)
2524 return;
2525
2526 if (family != 6)
2527 return;
2528
2529 switch (model) {
2530 case 0x2A:
2531 case 0x3A:
70b43400 2532 case 0x3C: /* HSW */
70b43400 2533 case 0x45: /* HSW */
149c2319 2534 case 0x46: /* HSW */
4e8e863f 2535 case 0x3D: /* BDW */
48a0631c 2536 case 0x47: /* BDW */
144b44b1 2537 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
889facbe 2538 break;
0b2bb692
LB		 2539 case 0x4E: /* SKL */
2540 case 0x5E: /* SKL */
2541 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2542 break;
e6f9bb3c 2543 case 0x3F: /* HSX */
4e8e863f
LB		 2544 case 0x4F: /* BDX */
2545 case 0x56: /* BDX-DE */
fb5d4327 2546 case 0x57: /* KNL */
0b2bb692 2547 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
e6f9bb3c 2548 break;
889facbe
LB		 2549 case 0x2D:
2550 case 0x3E:
0b2bb692 2551 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
144b44b1
LB		 2552 break;
2553 case 0x37: /* BYT */
2554 case 0x4D: /* AVN */
2555 do_rapl = RAPL_PKG | RAPL_CORES ;
889facbe
LB		 2556 break;
2557 default:
2558 return;
2559 }
2560
2561 /* units on package 0, verify later other packages match */
7ce7d5de 2562 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
889facbe
LB		 2563 return;
2564
2565 rapl_power_units = 1.0 / (1 << (msr & 0xF));
144b44b1
LB		 2566 if (model == 0x37)
2567 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
2568 else
2569 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
889facbe 2570
40ee8e3b
AS		 2571 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
2572
144b44b1
LB		 2573 time_unit = msr >> 16 & 0xF;
2574 if (time_unit == 0)
2575 time_unit = 0xA;
889facbe 2576
144b44b1 2577 rapl_time_units = 1.0 / (1 << (time_unit));
889facbe 2578
144b44b1 2579 tdp = get_tdp(model);
889facbe 2580
144b44b1 2581 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
d8af6f5f 2582 if (debug)
b7d8c148 2583 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
889facbe
LB		 2584
2585 return;
2586}
2587
58cc30a4 2588void perf_limit_reasons_probe(int family, int model)
3a9a941d
LB		 2589{
2590 if (!genuine_intel)
2591 return;
2592
2593 if (family != 6)
2594 return;
2595
2596 switch (model) {
2597 case 0x3C: /* HSW */
2598 case 0x45: /* HSW */
2599 case 0x46: /* HSW */
2600 do_gfx_perf_limit_reasons = 1;
2601 case 0x3F: /* HSX */
2602 do_core_perf_limit_reasons = 1;
2603 do_ring_perf_limit_reasons = 1;
2604 default:
2605 return;
2606 }
2607}
2608
889facbe
LB		 2609int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2610{
2611 unsigned long long msr;
2612 unsigned int dts;
2613 int cpu;
2614
2615 if (!(do_dts || do_ptm))
2616 return 0;
2617
2618 cpu = t->cpu_id;
2619
2620 /* DTS is per-core, no need to print for each thread */
2621 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2622 return 0;
2623
2624 if (cpu_migrate(cpu)) {
b7d8c148 2625 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2626 return -1;
2627 }
2628
2629 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
2630 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2631 return 0;
2632
2633 dts = (msr >> 16) & 0x7F;
b7d8c148 2634 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
889facbe
LB		 2635 cpu, msr, tcc_activation_temp - dts);
2636
2637#ifdef THERM_DEBUG
2638 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
2639 return 0;
2640
2641 dts = (msr >> 16) & 0x7F;
2642 dts2 = (msr >> 8) & 0x7F;
b7d8c148 2643 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 2644 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
2645#endif
2646 }
2647
2648
2649 if (do_dts) {
2650 unsigned int resolution;
2651
2652 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2653 return 0;
2654
2655 dts = (msr >> 16) & 0x7F;
2656 resolution = (msr >> 27) & 0xF;
b7d8c148 2657 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
889facbe
LB		 2658 cpu, msr, tcc_activation_temp - dts, resolution);
2659
2660#ifdef THERM_DEBUG
2661 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
2662 return 0;
2663
2664 dts = (msr >> 16) & 0x7F;
2665 dts2 = (msr >> 8) & 0x7F;
b7d8c148 2666 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 2667 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
2668#endif
2669 }
2670
2671 return 0;
2672}
36229897 2673
889facbe
LB		 2674void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
2675{
b7d8c148 2676 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
889facbe
LB		 2677 cpu, label,
2678 ((msr >> 15) & 1) ? "EN" : "DIS",
2679 ((msr >> 0) & 0x7FFF) * rapl_power_units,
2680 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
2681 (((msr >> 16) & 1) ? "EN" : "DIS"));
2682
2683 return;
2684}
2685
2686int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2687{
2688 unsigned long long msr;
2689 int cpu;
889facbe
LB		 2690
2691 if (!do_rapl)
2692 return 0;
2693
2694 /* RAPL counters are per package, so print only for 1st thread/package */
2695 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2696 return 0;
2697
2698 cpu = t->cpu_id;
2699 if (cpu_migrate(cpu)) {
b7d8c148 2700 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2701 return -1;
2702 }
2703
2704 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
2705 return -1;
2706
d8af6f5f 2707 if (debug) {
b7d8c148 2708 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx "
889facbe 2709 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr,
144b44b1 2710 rapl_power_units, rapl_energy_units, rapl_time_units);
889facbe 2711 }
144b44b1
LB		 2712 if (do_rapl & RAPL_PKG_POWER_INFO) {
2713
889facbe
LB		 2714 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
2715 return -5;
2716
2717
b7d8c148 2718 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 2719 cpu, msr,
2720 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2721 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2722 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2723 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
2724
144b44b1
LB		 2725 }
2726 if (do_rapl & RAPL_PKG) {
2727
889facbe
LB		 2728 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
2729 return -9;
2730
b7d8c148 2731 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2732 cpu, msr, (msr >> 63) & 1 ? "": "UN");
2733
2734 print_power_limit_msr(cpu, msr, "PKG Limit #1");
b7d8c148 2735 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
889facbe
LB		 2736 cpu,
2737 ((msr >> 47) & 1) ? "EN" : "DIS",
2738 ((msr >> 32) & 0x7FFF) * rapl_power_units,
2739 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
2740 ((msr >> 48) & 1) ? "EN" : "DIS");
2741 }
2742
0b2bb692 2743 if (do_rapl & RAPL_DRAM_POWER_INFO) {
889facbe
LB		 2744 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
2745 return -6;
2746
b7d8c148 2747 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 2748 cpu, msr,
2749 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2750 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2751 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2752 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
0b2bb692
LB		 2753 }
2754 if (do_rapl & RAPL_DRAM) {
889facbe
LB		 2755 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
2756 return -9;
b7d8c148 2757 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2758 cpu, msr, (msr >> 31) & 1 ? "": "UN");
2759
2760 print_power_limit_msr(cpu, msr, "DRAM Limit");
2761 }
144b44b1 2762 if (do_rapl & RAPL_CORE_POLICY) {
d8af6f5f 2763 if (debug) {
889facbe
LB		 2764 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
2765 return -7;
2766
b7d8c148 2767 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
144b44b1
LB		 2768 }
2769 }
2770 if (do_rapl & RAPL_CORES) {
d8af6f5f 2771 if (debug) {
889facbe
LB		 2772
2773 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
2774 return -9;
b7d8c148 2775 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2776 cpu, msr, (msr >> 31) & 1 ? "": "UN");
2777 print_power_limit_msr(cpu, msr, "Cores Limit");
2778 }
2779 }
2780 if (do_rapl & RAPL_GFX) {
d8af6f5f 2781 if (debug) {
889facbe
LB		 2782 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
2783 return -8;
2784
b7d8c148 2785 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
889facbe
LB		 2786
2787 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
2788 return -9;
b7d8c148 2789 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2790 cpu, msr, (msr >> 31) & 1 ? "": "UN");
2791 print_power_limit_msr(cpu, msr, "GFX Limit");
2792 }
2793 }
2794 return 0;
2795}
2796
d7899447
LB		 2797/*
2798 * SNB adds support for additional MSRs:
2799 *
2800 * MSR_PKG_C7_RESIDENCY 0x000003fa
2801 * MSR_CORE_C7_RESIDENCY 0x000003fe
2802 * MSR_PKG_C2_RESIDENCY 0x0000060d
2803 */
103a8fea 2804
d7899447 2805int has_snb_msrs(unsigned int family, unsigned int model)
103a8fea
LB		 2806{
2807 if (!genuine_intel)
2808 return 0;
2809
2810 switch (model) {
2811 case 0x2A:
2812 case 0x2D:
650a37f3 2813 case 0x3A: /* IVB */
1300651b 2814 case 0x3E: /* IVB Xeon */
70b43400
LB		 2815 case 0x3C: /* HSW */
2816 case 0x3F: /* HSW */
2817 case 0x45: /* HSW */
149c2319 2818 case 0x46: /* HSW */
4e8e863f 2819 case 0x3D: /* BDW */
48a0631c 2820 case 0x47: /* BDW */
4e8e863f
LB		 2821 case 0x4F: /* BDX */
2822 case 0x56: /* BDX-DE */
0b2bb692
LB		 2823 case 0x4E: /* SKL */
2824 case 0x5E: /* SKL */
103a8fea
LB		 2825 return 1;
2826 }
2827 return 0;
2828}
2829
d7899447
LB		 2830/*
2831 * HSW adds support for additional MSRs:
2832 *
2833 * MSR_PKG_C8_RESIDENCY 0x00000630
2834 * MSR_PKG_C9_RESIDENCY 0x00000631
2835 * MSR_PKG_C10_RESIDENCY 0x00000632
2836 */
2837int has_hsw_msrs(unsigned int family, unsigned int model)
ca58710f
KCA		 2838{
2839 if (!genuine_intel)
2840 return 0;
2841
2842 switch (model) {
4e8e863f
LB		 2843 case 0x45: /* HSW */
2844 case 0x3D: /* BDW */
0b2bb692
LB		 2845 case 0x4E: /* SKL */
2846 case 0x5E: /* SKL */
2847 return 1;
2848 }
2849 return 0;
2850}
2851
2852/*
2853 * SKL adds support for additional MSRS:
2854 *
2855 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
2856 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
2857 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
2858 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
2859 */
2860int has_skl_msrs(unsigned int family, unsigned int model)
2861{
2862 if (!genuine_intel)
2863 return 0;
2864
2865 switch (model) {
2866 case 0x4E: /* SKL */
2867 case 0x5E: /* SKL */
ca58710f
KCA		 2868 return 1;
2869 }
2870 return 0;
2871}
2872
2873
0b2bb692 2874
144b44b1
LB		 2875int is_slm(unsigned int family, unsigned int model)
2876{
2877 if (!genuine_intel)
2878 return 0;
2879 switch (model) {
2880 case 0x37: /* BYT */
2881 case 0x4D: /* AVN */
2882 return 1;
2883 }
2884 return 0;
2885}
2886
fb5d4327
DC		 2887int is_knl(unsigned int family, unsigned int model)
2888{
2889 if (!genuine_intel)
2890 return 0;
2891 switch (model) {
2892 case 0x57: /* KNL */
2893 return 1;
2894 }
2895 return 0;
2896}
2897
b2b34dfe
HC		 2898unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
2899{
2900 if (is_knl(family, model))
2901 return 1024;
2902 return 1;
2903}
2904
144b44b1
LB		 2905#define SLM_BCLK_FREQS 5
2906double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
2907
2908double slm_bclk(void)
2909{
2910 unsigned long long msr = 3;
2911 unsigned int i;
2912 double freq;
2913
7ce7d5de 2914 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
b7d8c148 2915 fprintf(outf, "SLM BCLK: unknown\n");
144b44b1
LB		 2916
2917 i = msr & 0xf;
2918 if (i >= SLM_BCLK_FREQS) {
b7d8c148 2919 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
144b44b1
LB		 2920 msr = 3;
2921 }
2922 freq = slm_freq_table[i];
2923
b7d8c148 2924 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
144b44b1
LB		 2925
2926 return freq;
2927}
2928
103a8fea
LB		 2929double discover_bclk(unsigned int family, unsigned int model)
2930{
121b48bb 2931 if (has_snb_msrs(family, model) || is_knl(family, model))
103a8fea 2932 return 100.00;
144b44b1
LB		 2933 else if (is_slm(family, model))
2934 return slm_bclk();
103a8fea
LB		 2935 else
2936 return 133.33;
2937}
2938
889facbe
LB		 2939/*
2940 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
2941 * the Thermal Control Circuit (TCC) activates.
2942 * This is usually equal to tjMax.
2943 *
2944 * Older processors do not have this MSR, so there we guess,
2945 * but also allow cmdline over-ride with -T.
2946 *
2947 * Several MSR temperature values are in units of degrees-C
2948 * below this value, including the Digital Thermal Sensor (DTS),
2949 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
2950 */
2951int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2952{
2953 unsigned long long msr;
2954 unsigned int target_c_local;
2955 int cpu;
2956
2957 /* tcc_activation_temp is used only for dts or ptm */
2958 if (!(do_dts || do_ptm))
2959 return 0;
2960
2961 /* this is a per-package concept */
2962 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2963 return 0;
2964
2965 cpu = t->cpu_id;
2966 if (cpu_migrate(cpu)) {
b7d8c148 2967 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2968 return -1;
2969 }
2970
2971 if (tcc_activation_temp_override != 0) {
2972 tcc_activation_temp = tcc_activation_temp_override;
b7d8c148 2973 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
889facbe
LB		 2974 cpu, tcc_activation_temp);
2975 return 0;
2976 }
2977
2978 /* Temperature Target MSR is Nehalem and newer only */
d7899447 2979 if (!do_nhm_platform_info)
889facbe
LB		 2980 goto guess;
2981
7ce7d5de 2982 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
889facbe
LB		 2983 goto guess;
2984
3482124a 2985 target_c_local = (msr >> 16) & 0xFF;
889facbe 2986
d8af6f5f 2987 if (debug)
b7d8c148 2988 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
889facbe
LB		 2989 cpu, msr, target_c_local);
2990
3482124a 2991 if (!target_c_local)
889facbe
LB		 2992 goto guess;
2993
2994 tcc_activation_temp = target_c_local;
2995
2996 return 0;
2997
2998guess:
2999 tcc_activation_temp = TJMAX_DEFAULT;
b7d8c148 3000 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
889facbe
LB		 3001 cpu, tcc_activation_temp);
3002
3003 return 0;
3004}
69807a63
LB		 3005
3006void decode_misc_enable_msr(void)
3007{
3008 unsigned long long msr;
3009
3010 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
b7d8c148 3011 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n",
69807a63
LB		 3012 base_cpu, msr,
3013 msr & (1 << 3) ? "TCC" : "",
3014 msr & (1 << 16) ? "EIST" : "",
3015 msr & (1 << 18) ? "MONITOR" : "");
3016}
3017
f0057310
LB		 3018/*
3019 * Decode MSR_MISC_PWR_MGMT
3020 *
3021 * Decode the bits according to the Nehalem documentation
3022 * bit[0] seems to continue to have same meaning going forward
3023 * bit[1] less so...
3024 */
3025void decode_misc_pwr_mgmt_msr(void)
3026{
3027 unsigned long long msr;
3028
3029 if (!do_nhm_platform_info)
3030 return;
3031
3032 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
b7d8c148 3033 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB)\n",
f0057310
LB		 3034 base_cpu, msr,
3035 msr & (1 << 0) ? "DIS" : "EN",
3036 msr & (1 << 1) ? "EN" : "DIS");
3037}
7f5c258e 3038
fcd17211 3039void process_cpuid()
103a8fea 3040{
61a87ba7 3041 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
103a8fea
LB		 3042 unsigned int fms, family, model, stepping;
3043
3044 eax = ebx = ecx = edx = 0;
3045
2b92865e 3046 __get_cpuid(0, &max_level, &ebx, &ecx, &edx);
103a8fea
LB		 3047
3048 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
3049 genuine_intel = 1;
3050
d8af6f5f 3051 if (debug)
b7d8c148 3052 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
103a8fea
LB		 3053 (char *)&ebx, (char *)&edx, (char *)&ecx);
3054
2b92865e 3055 __get_cpuid(1, &fms, &ebx, &ecx, &edx);
103a8fea
LB		 3056 family = (fms >> 8) & 0xf;
3057 model = (fms >> 4) & 0xf;
3058 stepping = fms & 0xf;
3059 if (family == 6 || family == 0xf)
3060 model += ((fms >> 16) & 0xf) << 4;
3061
69807a63 3062 if (debug) {
b7d8c148 3063 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
103a8fea 3064 max_level, family, model, stepping, family, model, stepping);
b7d8c148 3065 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s\n",
69807a63
LB		 3066 ecx & (1 << 0) ? "SSE3" : "-",
3067 ecx & (1 << 3) ? "MONITOR" : "-",
3068 ecx & (1 << 7) ? "EIST" : "-",
3069 ecx & (1 << 8) ? "TM2" : "-",
3070 edx & (1 << 4) ? "TSC" : "-",
3071 edx & (1 << 5) ? "MSR" : "-",
3072 edx & (1 << 22) ? "ACPI-TM" : "-",
3073 edx & (1 << 29) ? "TM" : "-");
3074 }
103a8fea 3075
b2c95d90
JT		 3076 if (!(edx & (1 << 5)))
3077 errx(1, "CPUID: no MSR");
103a8fea
LB		 3078
3079 /*
3080 * check max extended function levels of CPUID.
3081 * This is needed to check for invariant TSC.
3082 * This check is valid for both Intel and AMD.
3083 */
3084 ebx = ecx = edx = 0;
61a87ba7 3085 __get_cpuid(0x80000000, &max_extended_level, &ebx, &ecx, &edx);
103a8fea 3086
61a87ba7 3087 if (max_extended_level >= 0x80000007) {
103a8fea 3088
d7899447
LB		 3089 /*
3090 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
3091 * this check is valid for both Intel and AMD
3092 */
3093 __get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
3094 has_invariant_tsc = edx & (1 << 8);
3095 }
103a8fea
LB		 3096
3097 /*
3098 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
3099 * this check is valid for both Intel and AMD
3100 */
3101
2b92865e 3102 __get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
8209e054 3103 has_aperf = ecx & (1 << 0);
889facbe
LB		 3104 do_dts = eax & (1 << 0);
3105 do_ptm = eax & (1 << 6);
7f5c258e
LB		 3106 has_hwp = eax & (1 << 7);
3107 has_hwp_notify = eax & (1 << 8);
3108 has_hwp_activity_window = eax & (1 << 9);
3109 has_hwp_epp = eax & (1 << 10);
3110 has_hwp_pkg = eax & (1 << 11);
889facbe
LB		 3111 has_epb = ecx & (1 << 3);
3112
d8af6f5f 3113 if (debug)
b7d8c148 3114 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, "
7f5c258e
LB		 3115 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
3116 has_aperf ? "" : "No-",
3117 do_dts ? "" : "No-",
3118 do_ptm ? "" : "No-",
3119 has_hwp ? "" : "No-",
3120 has_hwp_notify ? "" : "No-",
3121 has_hwp_activity_window ? "" : "No-",
3122 has_hwp_epp ? "" : "No-",
3123 has_hwp_pkg ? "" : "No-",
3124 has_epb ? "" : "No-");
103a8fea 3125
69807a63
LB		 3126 if (debug)
3127 decode_misc_enable_msr();
3128
61a87ba7 3129 if (max_level >= 0x15) {
8a5bdf41
LB		 3130 unsigned int eax_crystal;
3131 unsigned int ebx_tsc;
3132
3133 /*
3134 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
3135 */
3136 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
3137 __get_cpuid(0x15, &eax_crystal, &ebx_tsc, &crystal_hz, &edx);
3138
3139 if (ebx_tsc != 0) {
3140
3141 if (debug && (ebx != 0))
b7d8c148 3142 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
8a5bdf41
LB		 3143 eax_crystal, ebx_tsc, crystal_hz);
3144
3145 if (crystal_hz == 0)
3146 switch(model) {
3147 case 0x4E: /* SKL */
3148 case 0x5E: /* SKL */
3149 crystal_hz = 24000000; /* 24 MHz */
3150 break;
3151 default:
3152 crystal_hz = 0;
3153 }
3154
3155 if (crystal_hz) {
3156 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
3157 if (debug)
b7d8c148 3158 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
8a5bdf41
LB		 3159 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
3160 }
3161 }
3162 }
61a87ba7
LB		 3163 if (max_level >= 0x16) {
3164 unsigned int base_mhz, max_mhz, bus_mhz, edx;
3165
3166 /*
3167 * CPUID 16H Base MHz, Max MHz, Bus MHz
3168 */
3169 base_mhz = max_mhz = bus_mhz = edx = 0;
3170
3171 __get_cpuid(0x16, &base_mhz, &max_mhz, &bus_mhz, &edx);
3172 if (debug)
b7d8c148 3173 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
61a87ba7
LB		 3174 base_mhz, max_mhz, bus_mhz);
3175 }
8a5bdf41 3176
b2b34dfe
HC		 3177 if (has_aperf)
3178 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
3179
ee7e38e3 3180 do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model);
d7899447 3181 do_snb_cstates = has_snb_msrs(family, model);
ee7e38e3
LB		 3182 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
3183 do_pc3 = (pkg_cstate_limit >= PCL__3);
3184 do_pc6 = (pkg_cstate_limit >= PCL__6);
3185 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
d7899447 3186 do_c8_c9_c10 = has_hsw_msrs(family, model);
0b2bb692 3187 do_skl_residency = has_skl_msrs(family, model);
144b44b1 3188 do_slm_cstates = is_slm(family, model);
fb5d4327 3189 do_knl_cstates = is_knl(family, model);
103a8fea 3190
f0057310
LB		 3191 if (debug)
3192 decode_misc_pwr_mgmt_msr();
3193
889facbe 3194 rapl_probe(family, model);
3a9a941d 3195 perf_limit_reasons_probe(family, model);
889facbe 3196
fcd17211 3197 if (debug)
58cc30a4 3198 dump_cstate_pstate_config_info(family, model);
fcd17211 3199
a2b7b749
LB		 3200 if (has_skl_msrs(family, model))
3201 calculate_tsc_tweak();
3202
fdf676e5
LB		 3203 do_gfx_rc6_ms = !access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK);
3204
27d47356
LB		 3205 do_gfx_mhz = !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK);
3206
889facbe 3207 return;
103a8fea
LB		 3208}
3209
d8af6f5f 3210void help()
103a8fea 3211{
b7d8c148 3212 fprintf(outf,
d8af6f5f
LB		 3213 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
3214 "\n"
3215 "Turbostat forks the specified COMMAND and prints statistics\n"
3216 "when COMMAND completes.\n"
3217 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
3218 "to print statistics, until interrupted.\n"
3219 "--debug run in \"debug\" mode\n"
3220 "--interval sec Override default 5-second measurement interval\n"
3221 "--help print this help message\n"
3222 "--counter msr print 32-bit counter at address \"msr\"\n"
3223 "--Counter msr print 64-bit Counter at address \"msr\"\n"
b7d8c148 3224 "--out file create or truncate \"file\" for all output\n"
d8af6f5f
LB		 3225 "--msr msr print 32-bit value at address \"msr\"\n"
3226 "--MSR msr print 64-bit Value at address \"msr\"\n"
3227 "--version print version information\n"
3228 "\n"
3229 "For more help, run \"man turbostat\"\n");
103a8fea
LB		 3230}
3231
3232
3233/*
3234 * in /dev/cpu/ return success for names that are numbers
3235 * ie. filter out ".", "..", "microcode".
3236 */
3237int dir_filter(const struct dirent *dirp)
3238{
3239 if (isdigit(dirp->d_name[0]))
3240 return 1;
3241 else
3242 return 0;
3243}
3244
3245int open_dev_cpu_msr(int dummy1)
3246{
3247 return 0;
3248}
3249
c98d5d94
LB		 3250void topology_probe()
3251{
3252 int i;
3253 int max_core_id = 0;
3254 int max_package_id = 0;
3255 int max_siblings = 0;
3256 struct cpu_topology {
3257 int core_id;
3258 int physical_package_id;
3259 } *cpus;
3260
3261 /* Initialize num_cpus, max_cpu_num */
3262 topo.num_cpus = 0;
3263 topo.max_cpu_num = 0;
3264 for_all_proc_cpus(count_cpus);
3265 if (!summary_only && topo.num_cpus > 1)
3266 show_cpu = 1;
3267
d8af6f5f 3268 if (debug > 1)
b7d8c148 3269 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
c98d5d94
LB		 3270
3271 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
b2c95d90
JT		 3272 if (cpus == NULL)
3273 err(1, "calloc cpus");
c98d5d94
LB		 3274
3275 /*
3276 * Allocate and initialize cpu_present_set
3277 */
3278 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 3279 if (cpu_present_set == NULL)
3280 err(3, "CPU_ALLOC");
c98d5d94
LB		 3281 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3282 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
3283 for_all_proc_cpus(mark_cpu_present);
3284
3285 /*
3286 * Allocate and initialize cpu_affinity_set
3287 */
3288 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 3289 if (cpu_affinity_set == NULL)
3290 err(3, "CPU_ALLOC");
c98d5d94
LB		 3291 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3292 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
3293
3294
3295 /*
3296 * For online cpus
3297 * find max_core_id, max_package_id
3298 */
3299 for (i = 0; i <= topo.max_cpu_num; ++i) {
3300 int siblings;
3301
3302 if (cpu_is_not_present(i)) {
d8af6f5f 3303 if (debug > 1)
b7d8c148 3304 fprintf(outf, "cpu%d NOT PRESENT\n", i);
c98d5d94
LB		 3305 continue;
3306 }
3307 cpus[i].core_id = get_core_id(i);
3308 if (cpus[i].core_id > max_core_id)
3309 max_core_id = cpus[i].core_id;
3310
3311 cpus[i].physical_package_id = get_physical_package_id(i);
3312 if (cpus[i].physical_package_id > max_package_id)
3313 max_package_id = cpus[i].physical_package_id;
3314
3315 siblings = get_num_ht_siblings(i);
3316 if (siblings > max_siblings)
3317 max_siblings = siblings;
d8af6f5f 3318 if (debug > 1)
b7d8c148 3319 fprintf(outf, "cpu %d pkg %d core %d\n",
c98d5d94
LB		 3320 i, cpus[i].physical_package_id, cpus[i].core_id);
3321 }
3322 topo.num_cores_per_pkg = max_core_id + 1;
d8af6f5f 3323 if (debug > 1)
b7d8c148 3324 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
c98d5d94 3325 max_core_id, topo.num_cores_per_pkg);
1cc21f7b 3326 if (debug && !summary_only && topo.num_cores_per_pkg > 1)
c98d5d94
LB		 3327 show_core = 1;
3328
3329 topo.num_packages = max_package_id + 1;
d8af6f5f 3330 if (debug > 1)
b7d8c148 3331 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
c98d5d94 3332 max_package_id, topo.num_packages);
1cc21f7b 3333 if (debug && !summary_only && topo.num_packages > 1)
c98d5d94
LB		 3334 show_pkg = 1;
3335
3336 topo.num_threads_per_core = max_siblings;
d8af6f5f 3337 if (debug > 1)
b7d8c148 3338 fprintf(outf, "max_siblings %d\n", max_siblings);
c98d5d94
LB		 3339
3340 free(cpus);
3341}
3342
3343void
3344allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
3345{
3346 int i;
3347
3348 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
3349 topo.num_packages, sizeof(struct thread_data));
3350 if (*t == NULL)
3351 goto error;
3352
3353 for (i = 0; i < topo.num_threads_per_core *
3354 topo.num_cores_per_pkg * topo.num_packages; i++)
3355 (*t)[i].cpu_id = -1;
3356
3357 *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
3358 sizeof(struct core_data));
3359 if (*c == NULL)
3360 goto error;
3361
3362 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
3363 (*c)[i].core_id = -1;
3364
3365 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
3366 if (*p == NULL)
3367 goto error;
3368
3369 for (i = 0; i < topo.num_packages; i++)
3370 (*p)[i].package_id = i;
3371
3372 return;
3373error:
b2c95d90 3374 err(1, "calloc counters");
c98d5d94
LB		 3375}
3376/*
3377 * init_counter()
3378 *
3379 * set cpu_id, core_num, pkg_num
3380 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
3381 *
3382 * increment topo.num_cores when 1st core in pkg seen
3383 */
3384void init_counter(struct thread_data *thread_base, struct core_data *core_base,
3385 struct pkg_data *pkg_base, int thread_num, int core_num,
3386 int pkg_num, int cpu_id)
3387{
3388 struct thread_data *t;
3389 struct core_data *c;
3390 struct pkg_data *p;
3391
3392 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
3393 c = GET_CORE(core_base, core_num, pkg_num);
3394 p = GET_PKG(pkg_base, pkg_num);
3395
3396 t->cpu_id = cpu_id;
3397 if (thread_num == 0) {
3398 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
3399 if (cpu_is_first_core_in_package(cpu_id))
3400 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
3401 }
3402
3403 c->core_id = core_num;
3404 p->package_id = pkg_num;
3405}
3406
3407
3408int initialize_counters(int cpu_id)
3409{
3410 int my_thread_id, my_core_id, my_package_id;
3411
3412 my_package_id = get_physical_package_id(cpu_id);
3413 my_core_id = get_core_id(cpu_id);
e275b388
DC		 3414 my_thread_id = get_cpu_position_in_core(cpu_id);
3415 if (!my_thread_id)
c98d5d94 3416 topo.num_cores++;
c98d5d94
LB		 3417
3418 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3419 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3420 return 0;
3421}
3422
3423void allocate_output_buffer()
3424{
3b4d5c7f 3425 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024);
c98d5d94 3426 outp = output_buffer;
b2c95d90
JT		 3427 if (outp == NULL)
3428 err(-1, "calloc output buffer");
c98d5d94 3429}
36229897
LB		 3430void allocate_fd_percpu(void)
3431{
3432 fd_percpu = calloc(topo.max_cpu_num, sizeof(int));
3433 if (fd_percpu == NULL)
3434 err(-1, "calloc fd_percpu");
3435}
562a2d37
LB		 3436void allocate_irq_buffers(void)
3437{
3438 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
3439 if (irq_column_2_cpu == NULL)
3440 err(-1, "calloc %d", topo.num_cpus);
3441
3442 irqs_per_cpu = calloc(topo.max_cpu_num, sizeof(int));
3443 if (irqs_per_cpu == NULL)
3444 err(-1, "calloc %d", topo.max_cpu_num);
3445}
c98d5d94
LB		 3446void setup_all_buffers(void)
3447{
3448 topology_probe();
562a2d37 3449 allocate_irq_buffers();
36229897 3450 allocate_fd_percpu();
c98d5d94
LB		 3451 allocate_counters(&thread_even, &core_even, &package_even);
3452 allocate_counters(&thread_odd, &core_odd, &package_odd);
3453 allocate_output_buffer();
3454 for_all_proc_cpus(initialize_counters);
3455}
3b4d5c7f 3456
7ce7d5de
PB		 3457void set_base_cpu(void)
3458{
3459 base_cpu = sched_getcpu();
3460 if (base_cpu < 0)
3461 err(-ENODEV, "No valid cpus found");
3462
3463 if (debug > 1)
b7d8c148 3464 fprintf(outf, "base_cpu = %d\n", base_cpu);
7ce7d5de
PB		 3465}
3466
103a8fea
LB		 3467void turbostat_init()
3468{
7ce7d5de
PB		 3469 setup_all_buffers();
3470 set_base_cpu();
103a8fea 3471 check_dev_msr();
98481e79 3472 check_permissions();
fcd17211 3473 process_cpuid();
103a8fea 3474
103a8fea 3475
7f5c258e
LB		 3476 if (debug)
3477 for_all_cpus(print_hwp, ODD_COUNTERS);
3478
d8af6f5f 3479 if (debug)
889facbe
LB		 3480 for_all_cpus(print_epb, ODD_COUNTERS);
3481
d8af6f5f 3482 if (debug)
3a9a941d
LB		 3483 for_all_cpus(print_perf_limit, ODD_COUNTERS);
3484
d8af6f5f 3485 if (debug)
889facbe
LB		 3486 for_all_cpus(print_rapl, ODD_COUNTERS);
3487
3488 for_all_cpus(set_temperature_target, ODD_COUNTERS);
3489
d8af6f5f 3490 if (debug)
889facbe 3491 for_all_cpus(print_thermal, ODD_COUNTERS);
103a8fea
LB		 3492}
3493
3494int fork_it(char **argv)
3495{
103a8fea 3496 pid_t child_pid;
d91bb17c 3497 int status;
d15cf7c1 3498
d91bb17c
LB		 3499 status = for_all_cpus(get_counters, EVEN_COUNTERS);
3500 if (status)
3501 exit(status);
c98d5d94
LB		 3502 /* clear affinity side-effect of get_counters() */
3503 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
103a8fea
LB		 3504 gettimeofday(&tv_even, (struct timezone *)NULL);
3505
3506 child_pid = fork();
3507 if (!child_pid) {
3508 /* child */
3509 execvp(argv[0], argv);
3510 } else {
103a8fea
LB		 3511
3512 /* parent */
b2c95d90
JT		 3513 if (child_pid == -1)
3514 err(1, "fork");
103a8fea
LB		 3515
3516 signal(SIGINT, SIG_IGN);
3517 signal(SIGQUIT, SIG_IGN);
b2c95d90
JT		 3518 if (waitpid(child_pid, &status, 0) == -1)
3519 err(status, "waitpid");
103a8fea 3520 }
c98d5d94
LB		 3521 /*
3522 * n.b. fork_it() does not check for errors from for_all_cpus()
3523 * because re-starting is problematic when forking
3524 */
3525 for_all_cpus(get_counters, ODD_COUNTERS);
103a8fea 3526 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 3527 timersub(&tv_odd, &tv_even, &tv_delta);
c98d5d94
LB		 3528 for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS);
3529 compute_average(EVEN_COUNTERS);
3530 format_all_counters(EVEN_COUNTERS);
103a8fea 3531
b7d8c148
LB		 3532 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
3533
3534 flush_output_stderr();
103a8fea 3535
d91bb17c 3536 return status;
103a8fea
LB		 3537}
3538
3b4d5c7f
AS		 3539int get_and_dump_counters(void)
3540{
3541 int status;
3542
3543 status = for_all_cpus(get_counters, ODD_COUNTERS);
3544 if (status)
3545 return status;
3546
3547 status = for_all_cpus(dump_counters, ODD_COUNTERS);
3548 if (status)
3549 return status;
3550
b7d8c148 3551 flush_output_stdout();
3b4d5c7f
AS		 3552
3553 return status;
3554}
3555
d8af6f5f 3556void print_version() {
b7d8c148 3557 fprintf(outf, "turbostat version 4.10 10 Dec, 2015"
d8af6f5f
LB		 3558 " - Len Brown <lenb@kernel.org>\n");
3559}
3560
103a8fea
LB		 3561void cmdline(int argc, char **argv)
3562{
3563 int opt;
d8af6f5f
LB		 3564 int option_index = 0;
3565 static struct option long_options[] = {
3566 {"Counter", required_argument, 0, 'C'},
3567 {"counter", required_argument, 0, 'c'},
3568 {"Dump", no_argument, 0, 'D'},
3569 {"debug", no_argument, 0, 'd'},
3570 {"interval", required_argument, 0, 'i'},
3571 {"help", no_argument, 0, 'h'},
3572 {"Joules", no_argument, 0, 'J'},
3573 {"MSR", required_argument, 0, 'M'},
3574 {"msr", required_argument, 0, 'm'},
b7d8c148 3575 {"out", required_argument, 0, 'o'},
d8af6f5f
LB		 3576 {"Package", no_argument, 0, 'p'},
3577 {"processor", no_argument, 0, 'p'},
3578 {"Summary", no_argument, 0, 'S'},
3579 {"TCC", required_argument, 0, 'T'},
3580 {"version", no_argument, 0, 'v' },
3581 {0, 0, 0, 0 }
3582 };
103a8fea
LB		 3583
3584 progname = argv[0];
3585
b7d8c148 3586 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v",
d8af6f5f 3587 long_options, &option_index)) != -1) {
103a8fea 3588 switch (opt) {
d8af6f5f
LB		 3589 case 'C':
3590 sscanf(optarg, "%x", &extra_delta_offset64);
c98d5d94 3591 break;
d8af6f5f
LB		 3592 case 'c':
3593 sscanf(optarg, "%x", &extra_delta_offset32);
c98d5d94 3594 break;
d8af6f5f 3595 case 'D':
3b4d5c7f
AS		 3596 dump_only++;
3597 break;
d8af6f5f
LB		 3598 case 'd':
3599 debug++;
103a8fea 3600 break;
d8af6f5f
LB		 3601 case 'h':
3602 default:
3603 help();
3604 exit(1);
103a8fea 3605 case 'i':
2a0609c0
LB		 3606 {
3607 double interval = strtod(optarg, NULL);
3608
3609 if (interval < 0.001) {
b7d8c148 3610 fprintf(outf, "interval %f seconds is too small\n",
2a0609c0
LB		 3611 interval);
3612 exit(2);
3613 }
3614
3615 interval_ts.tv_sec = interval;
3616 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
3617 }
103a8fea 3618 break;
d8af6f5f
LB		 3619 case 'J':
3620 rapl_joules++;
8e180f3c 3621 break;
d8af6f5f
LB		 3622 case 'M':
3623 sscanf(optarg, "%x", &extra_msr_offset64);
8e180f3c 3624 break;
2f32edf1
LB		 3625 case 'm':
3626 sscanf(optarg, "%x", &extra_msr_offset32);
2f32edf1 3627 break;
b7d8c148
LB		 3628 case 'o':
3629 outf = fopen_or_die(optarg, "w");
3630 break;
d8af6f5f
LB		 3631 case 'P':
3632 show_pkg_only++;
3633 break;
3634 case 'p':
3635 show_core_only++;
103a8fea 3636 break;
d8af6f5f
LB		 3637 case 'S':
3638 summary_only++;
889facbe
LB		 3639 break;
3640 case 'T':
3641 tcc_activation_temp_override = atoi(optarg);
3642 break;
d8af6f5f
LB		 3643 case 'v':
3644 print_version();
3645 exit(0);
5c56be9a 3646 break;
103a8fea
LB		 3647 }
3648 }
3649}
3650
3651int main(int argc, char **argv)
3652{
b7d8c148
LB		 3653 outf = stderr;
3654
103a8fea
LB		 3655 cmdline(argc, argv);
3656
d8af6f5f
LB		 3657 if (debug)
3658 print_version();
103a8fea
LB		 3659
3660 turbostat_init();
3661
3b4d5c7f
AS		 3662 /* dump counters and exit */
3663 if (dump_only)
3664 return get_and_dump_counters();
3665
103a8fea
LB		 3666 /*
3667 * if any params left, it must be a command to fork
3668 */
3669 if (argc - optind)
3670 return fork_it(argv + optind);
3671 else
3672 turbostat_loop();
3673
3674 return 0;
3675}
Linux 6.x block layer and io_uring tree(s)