Commit | Line | Data |
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103a8fea LB |
1 | /* |
2 | * turbostat -- show CPU frequency and C-state residency | |
3 | * on modern Intel turbo-capable processors. | |
4 | * | |
144b44b1 | 5 | * Copyright (c) 2013 Intel Corporation. |
103a8fea LB |
6 | * Len Brown <len.brown@intel.com> |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
20 | */ | |
21 | ||
88c3281f | 22 | #define _GNU_SOURCE |
b731f311 | 23 | #include MSRHEADER |
95aebc44 | 24 | #include <stdarg.h> |
103a8fea | 25 | #include <stdio.h> |
b2c95d90 | 26 | #include <err.h> |
103a8fea LB |
27 | #include <unistd.h> |
28 | #include <sys/types.h> | |
29 | #include <sys/wait.h> | |
30 | #include <sys/stat.h> | |
31 | #include <sys/resource.h> | |
32 | #include <fcntl.h> | |
33 | #include <signal.h> | |
34 | #include <sys/time.h> | |
35 | #include <stdlib.h> | |
d8af6f5f | 36 | #include <getopt.h> |
103a8fea LB |
37 | #include <dirent.h> |
38 | #include <string.h> | |
39 | #include <ctype.h> | |
88c3281f | 40 | #include <sched.h> |
2b92865e | 41 | #include <cpuid.h> |
98481e79 LB |
42 | #include <linux/capability.h> |
43 | #include <errno.h> | |
103a8fea | 44 | |
103a8fea | 45 | char *proc_stat = "/proc/stat"; |
d8af6f5f LB |
46 | unsigned int interval_sec = 5; |
47 | unsigned int debug; | |
48 | unsigned int rapl_joules; | |
49 | unsigned int summary_only; | |
50 | unsigned int dump_only; | |
103a8fea LB |
51 | unsigned int skip_c0; |
52 | unsigned int skip_c1; | |
53 | unsigned int do_nhm_cstates; | |
54 | unsigned int do_snb_cstates; | |
ee7e38e3 LB |
55 | unsigned int do_pc2; |
56 | unsigned int do_pc3; | |
57 | unsigned int do_pc6; | |
58 | unsigned int do_pc7; | |
ca58710f | 59 | unsigned int do_c8_c9_c10; |
144b44b1 LB |
60 | unsigned int do_slm_cstates; |
61 | unsigned int use_c1_residency_msr; | |
103a8fea | 62 | unsigned int has_aperf; |
889facbe | 63 | unsigned int has_epb; |
fc04cc67 | 64 | unsigned int units = 1000000; /* MHz etc */ |
103a8fea LB |
65 | unsigned int genuine_intel; |
66 | unsigned int has_invariant_tsc; | |
d7899447 | 67 | unsigned int do_nhm_platform_info; |
2f32edf1 LB |
68 | unsigned int extra_msr_offset32; |
69 | unsigned int extra_msr_offset64; | |
8e180f3c LB |
70 | unsigned int extra_delta_offset32; |
71 | unsigned int extra_delta_offset64; | |
1ed51011 | 72 | int do_smi; |
103a8fea LB |
73 | double bclk; |
74 | unsigned int show_pkg; | |
75 | unsigned int show_core; | |
76 | unsigned int show_cpu; | |
c98d5d94 LB |
77 | unsigned int show_pkg_only; |
78 | unsigned int show_core_only; | |
79 | char *output_buffer, *outp; | |
889facbe LB |
80 | unsigned int do_rapl; |
81 | unsigned int do_dts; | |
82 | unsigned int do_ptm; | |
83 | unsigned int tcc_activation_temp; | |
84 | unsigned int tcc_activation_temp_override; | |
85 | double rapl_power_units, rapl_energy_units, rapl_time_units; | |
86 | double rapl_joule_counter_range; | |
3a9a941d LB |
87 | unsigned int do_core_perf_limit_reasons; |
88 | unsigned int do_gfx_perf_limit_reasons; | |
89 | unsigned int do_ring_perf_limit_reasons; | |
889facbe | 90 | |
e6f9bb3c LB |
91 | #define RAPL_PKG (1 << 0) |
92 | /* 0x610 MSR_PKG_POWER_LIMIT */ | |
93 | /* 0x611 MSR_PKG_ENERGY_STATUS */ | |
94 | #define RAPL_PKG_PERF_STATUS (1 << 1) | |
95 | /* 0x613 MSR_PKG_PERF_STATUS */ | |
96 | #define RAPL_PKG_POWER_INFO (1 << 2) | |
97 | /* 0x614 MSR_PKG_POWER_INFO */ | |
98 | ||
99 | #define RAPL_DRAM (1 << 3) | |
100 | /* 0x618 MSR_DRAM_POWER_LIMIT */ | |
101 | /* 0x619 MSR_DRAM_ENERGY_STATUS */ | |
102 | /* 0x61c MSR_DRAM_POWER_INFO */ | |
103 | #define RAPL_DRAM_PERF_STATUS (1 << 4) | |
104 | /* 0x61b MSR_DRAM_PERF_STATUS */ | |
105 | ||
106 | #define RAPL_CORES (1 << 5) | |
107 | /* 0x638 MSR_PP0_POWER_LIMIT */ | |
108 | /* 0x639 MSR_PP0_ENERGY_STATUS */ | |
109 | #define RAPL_CORE_POLICY (1 << 6) | |
110 | /* 0x63a MSR_PP0_POLICY */ | |
111 | ||
112 | ||
113 | #define RAPL_GFX (1 << 7) | |
114 | /* 0x640 MSR_PP1_POWER_LIMIT */ | |
115 | /* 0x641 MSR_PP1_ENERGY_STATUS */ | |
116 | /* 0x642 MSR_PP1_POLICY */ | |
889facbe LB |
117 | #define TJMAX_DEFAULT 100 |
118 | ||
119 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) | |
103a8fea LB |
120 | |
121 | int aperf_mperf_unstable; | |
122 | int backwards_count; | |
123 | char *progname; | |
103a8fea | 124 | |
c98d5d94 LB |
125 | cpu_set_t *cpu_present_set, *cpu_affinity_set; |
126 | size_t cpu_present_setsize, cpu_affinity_setsize; | |
127 | ||
128 | struct thread_data { | |
129 | unsigned long long tsc; | |
130 | unsigned long long aperf; | |
131 | unsigned long long mperf; | |
144b44b1 | 132 | unsigned long long c1; |
2f32edf1 | 133 | unsigned long long extra_msr64; |
8e180f3c LB |
134 | unsigned long long extra_delta64; |
135 | unsigned long long extra_msr32; | |
136 | unsigned long long extra_delta32; | |
1ed51011 | 137 | unsigned int smi_count; |
c98d5d94 LB |
138 | unsigned int cpu_id; |
139 | unsigned int flags; | |
140 | #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 | |
141 | #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 | |
142 | } *thread_even, *thread_odd; | |
143 | ||
144 | struct core_data { | |
145 | unsigned long long c3; | |
146 | unsigned long long c6; | |
147 | unsigned long long c7; | |
889facbe | 148 | unsigned int core_temp_c; |
c98d5d94 LB |
149 | unsigned int core_id; |
150 | } *core_even, *core_odd; | |
151 | ||
152 | struct pkg_data { | |
153 | unsigned long long pc2; | |
154 | unsigned long long pc3; | |
155 | unsigned long long pc6; | |
156 | unsigned long long pc7; | |
ca58710f KCA |
157 | unsigned long long pc8; |
158 | unsigned long long pc9; | |
159 | unsigned long long pc10; | |
c98d5d94 | 160 | unsigned int package_id; |
889facbe LB |
161 | unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ |
162 | unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ | |
163 | unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ | |
164 | unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ | |
165 | unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ | |
166 | unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ | |
167 | unsigned int pkg_temp_c; | |
168 | ||
c98d5d94 LB |
169 | } *package_even, *package_odd; |
170 | ||
171 | #define ODD_COUNTERS thread_odd, core_odd, package_odd | |
172 | #define EVEN_COUNTERS thread_even, core_even, package_even | |
173 | ||
174 | #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ | |
175 | (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ | |
176 | topo.num_threads_per_core + \ | |
177 | (core_no) * topo.num_threads_per_core + (thread_no)) | |
178 | #define GET_CORE(core_base, core_no, pkg_no) \ | |
179 | (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) | |
180 | #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) | |
181 | ||
182 | struct system_summary { | |
183 | struct thread_data threads; | |
184 | struct core_data cores; | |
185 | struct pkg_data packages; | |
186 | } sum, average; | |
187 | ||
188 | ||
189 | struct topo_params { | |
190 | int num_packages; | |
191 | int num_cpus; | |
192 | int num_cores; | |
193 | int max_cpu_num; | |
194 | int num_cores_per_pkg; | |
195 | int num_threads_per_core; | |
196 | } topo; | |
197 | ||
198 | struct timeval tv_even, tv_odd, tv_delta; | |
199 | ||
200 | void setup_all_buffers(void); | |
201 | ||
202 | int cpu_is_not_present(int cpu) | |
d15cf7c1 | 203 | { |
c98d5d94 | 204 | return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); |
d15cf7c1 | 205 | } |
88c3281f | 206 | /* |
c98d5d94 LB |
207 | * run func(thread, core, package) in topology order |
208 | * skip non-present cpus | |
88c3281f | 209 | */ |
c98d5d94 LB |
210 | |
211 | int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), | |
212 | struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) | |
88c3281f | 213 | { |
c98d5d94 | 214 | int retval, pkg_no, core_no, thread_no; |
d15cf7c1 | 215 | |
c98d5d94 LB |
216 | for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { |
217 | for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { | |
218 | for (thread_no = 0; thread_no < | |
219 | topo.num_threads_per_core; ++thread_no) { | |
220 | struct thread_data *t; | |
221 | struct core_data *c; | |
222 | struct pkg_data *p; | |
88c3281f | 223 | |
c98d5d94 LB |
224 | t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); |
225 | ||
226 | if (cpu_is_not_present(t->cpu_id)) | |
227 | continue; | |
228 | ||
229 | c = GET_CORE(core_base, core_no, pkg_no); | |
230 | p = GET_PKG(pkg_base, pkg_no); | |
231 | ||
232 | retval = func(t, c, p); | |
233 | if (retval) | |
234 | return retval; | |
235 | } | |
236 | } | |
237 | } | |
238 | return 0; | |
88c3281f LB |
239 | } |
240 | ||
241 | int cpu_migrate(int cpu) | |
242 | { | |
c98d5d94 LB |
243 | CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); |
244 | CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); | |
245 | if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) | |
88c3281f LB |
246 | return -1; |
247 | else | |
248 | return 0; | |
249 | } | |
250 | ||
15aaa346 | 251 | int get_msr(int cpu, off_t offset, unsigned long long *msr) |
103a8fea LB |
252 | { |
253 | ssize_t retval; | |
103a8fea LB |
254 | char pathname[32]; |
255 | int fd; | |
256 | ||
257 | sprintf(pathname, "/dev/cpu/%d/msr", cpu); | |
258 | fd = open(pathname, O_RDONLY); | |
15aaa346 | 259 | if (fd < 0) |
98481e79 | 260 | err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); |
103a8fea | 261 | |
15aaa346 | 262 | retval = pread(fd, msr, sizeof *msr, offset); |
103a8fea | 263 | close(fd); |
15aaa346 | 264 | |
98481e79 LB |
265 | if (retval != sizeof *msr) |
266 | err(-1, "%s offset 0x%llx read failed", pathname, (unsigned long long)offset); | |
15aaa346 LB |
267 | |
268 | return 0; | |
103a8fea LB |
269 | } |
270 | ||
fc04cc67 LB |
271 | /* |
272 | * Example Format w/ field column widths: | |
273 | * | |
e7c95ff3 LB |
274 | * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz SMI %Busy CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt |
275 | * 123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678 | |
fc04cc67 LB |
276 | */ |
277 | ||
a829eb4d | 278 | void print_header(void) |
103a8fea LB |
279 | { |
280 | if (show_pkg) | |
e7c95ff3 | 281 | outp += sprintf(outp, " Package"); |
103a8fea | 282 | if (show_core) |
e7c95ff3 | 283 | outp += sprintf(outp, " Core"); |
103a8fea | 284 | if (show_cpu) |
e7c95ff3 | 285 | outp += sprintf(outp, " CPU"); |
fc04cc67 | 286 | if (has_aperf) |
e7c95ff3 | 287 | outp += sprintf(outp, " Avg_MHz"); |
d7899447 | 288 | if (has_aperf) |
e7c95ff3 | 289 | outp += sprintf(outp, " %%Busy"); |
103a8fea | 290 | if (has_aperf) |
e7c95ff3 LB |
291 | outp += sprintf(outp, " Bzy_MHz"); |
292 | outp += sprintf(outp, " TSC_MHz"); | |
1cc21f7b | 293 | |
8e180f3c | 294 | if (extra_delta_offset32) |
e7c95ff3 | 295 | outp += sprintf(outp, " count 0x%03X", extra_delta_offset32); |
8e180f3c | 296 | if (extra_delta_offset64) |
e7c95ff3 | 297 | outp += sprintf(outp, " COUNT 0x%03X", extra_delta_offset64); |
2f32edf1 | 298 | if (extra_msr_offset32) |
e7c95ff3 | 299 | outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset32); |
2f32edf1 | 300 | if (extra_msr_offset64) |
e7c95ff3 | 301 | outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset64); |
1cc21f7b LB |
302 | |
303 | if (!debug) | |
304 | goto done; | |
305 | ||
306 | if (do_smi) | |
307 | outp += sprintf(outp, " SMI"); | |
308 | ||
103a8fea | 309 | if (do_nhm_cstates) |
e7c95ff3 | 310 | outp += sprintf(outp, " CPU%%c1"); |
144b44b1 | 311 | if (do_nhm_cstates && !do_slm_cstates) |
e7c95ff3 | 312 | outp += sprintf(outp, " CPU%%c3"); |
103a8fea | 313 | if (do_nhm_cstates) |
e7c95ff3 | 314 | outp += sprintf(outp, " CPU%%c6"); |
103a8fea | 315 | if (do_snb_cstates) |
e7c95ff3 | 316 | outp += sprintf(outp, " CPU%%c7"); |
889facbe LB |
317 | |
318 | if (do_dts) | |
e7c95ff3 | 319 | outp += sprintf(outp, " CoreTmp"); |
889facbe | 320 | if (do_ptm) |
e7c95ff3 | 321 | outp += sprintf(outp, " PkgTmp"); |
889facbe | 322 | |
ee7e38e3 | 323 | if (do_pc2) |
e7c95ff3 | 324 | outp += sprintf(outp, " Pkg%%pc2"); |
ee7e38e3 | 325 | if (do_pc3) |
e7c95ff3 | 326 | outp += sprintf(outp, " Pkg%%pc3"); |
ee7e38e3 | 327 | if (do_pc6) |
e7c95ff3 | 328 | outp += sprintf(outp, " Pkg%%pc6"); |
ee7e38e3 | 329 | if (do_pc7) |
e7c95ff3 | 330 | outp += sprintf(outp, " Pkg%%pc7"); |
ca58710f | 331 | if (do_c8_c9_c10) { |
e7c95ff3 LB |
332 | outp += sprintf(outp, " Pkg%%pc8"); |
333 | outp += sprintf(outp, " Pkg%%pc9"); | |
334 | outp += sprintf(outp, " Pk%%pc10"); | |
ca58710f | 335 | } |
103a8fea | 336 | |
5c56be9a DB |
337 | if (do_rapl && !rapl_joules) { |
338 | if (do_rapl & RAPL_PKG) | |
e7c95ff3 | 339 | outp += sprintf(outp, " PkgWatt"); |
5c56be9a | 340 | if (do_rapl & RAPL_CORES) |
e7c95ff3 | 341 | outp += sprintf(outp, " CorWatt"); |
5c56be9a | 342 | if (do_rapl & RAPL_GFX) |
e7c95ff3 | 343 | outp += sprintf(outp, " GFXWatt"); |
5c56be9a | 344 | if (do_rapl & RAPL_DRAM) |
e7c95ff3 | 345 | outp += sprintf(outp, " RAMWatt"); |
5c56be9a | 346 | if (do_rapl & RAPL_PKG_PERF_STATUS) |
e7c95ff3 | 347 | outp += sprintf(outp, " PKG_%%"); |
5c56be9a | 348 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
e7c95ff3 | 349 | outp += sprintf(outp, " RAM_%%"); |
d7899447 | 350 | } else if (do_rapl && rapl_joules) { |
5c56be9a | 351 | if (do_rapl & RAPL_PKG) |
e7c95ff3 | 352 | outp += sprintf(outp, " Pkg_J"); |
5c56be9a | 353 | if (do_rapl & RAPL_CORES) |
e7c95ff3 | 354 | outp += sprintf(outp, " Cor_J"); |
5c56be9a | 355 | if (do_rapl & RAPL_GFX) |
e7c95ff3 | 356 | outp += sprintf(outp, " GFX_J"); |
5c56be9a | 357 | if (do_rapl & RAPL_DRAM) |
e7c95ff3 | 358 | outp += sprintf(outp, " RAM_W"); |
5c56be9a | 359 | if (do_rapl & RAPL_PKG_PERF_STATUS) |
e7c95ff3 | 360 | outp += sprintf(outp, " PKG_%%"); |
5c56be9a | 361 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
e7c95ff3 LB |
362 | outp += sprintf(outp, " RAM_%%"); |
363 | outp += sprintf(outp, " time"); | |
889facbe | 364 | |
5c56be9a | 365 | } |
1cc21f7b | 366 | done: |
c98d5d94 | 367 | outp += sprintf(outp, "\n"); |
103a8fea LB |
368 | } |
369 | ||
c98d5d94 LB |
370 | int dump_counters(struct thread_data *t, struct core_data *c, |
371 | struct pkg_data *p) | |
103a8fea | 372 | { |
3b4d5c7f | 373 | outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); |
c98d5d94 LB |
374 | |
375 | if (t) { | |
3b4d5c7f AS |
376 | outp += sprintf(outp, "CPU: %d flags 0x%x\n", |
377 | t->cpu_id, t->flags); | |
378 | outp += sprintf(outp, "TSC: %016llX\n", t->tsc); | |
379 | outp += sprintf(outp, "aperf: %016llX\n", t->aperf); | |
380 | outp += sprintf(outp, "mperf: %016llX\n", t->mperf); | |
381 | outp += sprintf(outp, "c1: %016llX\n", t->c1); | |
382 | outp += sprintf(outp, "msr0x%x: %08llX\n", | |
8e180f3c | 383 | extra_delta_offset32, t->extra_delta32); |
3b4d5c7f | 384 | outp += sprintf(outp, "msr0x%x: %016llX\n", |
8e180f3c | 385 | extra_delta_offset64, t->extra_delta64); |
3b4d5c7f | 386 | outp += sprintf(outp, "msr0x%x: %08llX\n", |
2f32edf1 | 387 | extra_msr_offset32, t->extra_msr32); |
3b4d5c7f | 388 | outp += sprintf(outp, "msr0x%x: %016llX\n", |
2f32edf1 | 389 | extra_msr_offset64, t->extra_msr64); |
1ed51011 | 390 | if (do_smi) |
3b4d5c7f | 391 | outp += sprintf(outp, "SMI: %08X\n", t->smi_count); |
c98d5d94 | 392 | } |
103a8fea | 393 | |
c98d5d94 | 394 | if (c) { |
3b4d5c7f AS |
395 | outp += sprintf(outp, "core: %d\n", c->core_id); |
396 | outp += sprintf(outp, "c3: %016llX\n", c->c3); | |
397 | outp += sprintf(outp, "c6: %016llX\n", c->c6); | |
398 | outp += sprintf(outp, "c7: %016llX\n", c->c7); | |
399 | outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); | |
c98d5d94 | 400 | } |
103a8fea | 401 | |
c98d5d94 | 402 | if (p) { |
3b4d5c7f AS |
403 | outp += sprintf(outp, "package: %d\n", p->package_id); |
404 | outp += sprintf(outp, "pc2: %016llX\n", p->pc2); | |
ee7e38e3 LB |
405 | if (do_pc3) |
406 | outp += sprintf(outp, "pc3: %016llX\n", p->pc3); | |
407 | if (do_pc6) | |
408 | outp += sprintf(outp, "pc6: %016llX\n", p->pc6); | |
409 | if (do_pc7) | |
410 | outp += sprintf(outp, "pc7: %016llX\n", p->pc7); | |
3b4d5c7f AS |
411 | outp += sprintf(outp, "pc8: %016llX\n", p->pc8); |
412 | outp += sprintf(outp, "pc9: %016llX\n", p->pc9); | |
413 | outp += sprintf(outp, "pc10: %016llX\n", p->pc10); | |
414 | outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); | |
415 | outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); | |
416 | outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); | |
417 | outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); | |
418 | outp += sprintf(outp, "Throttle PKG: %0X\n", | |
419 | p->rapl_pkg_perf_status); | |
420 | outp += sprintf(outp, "Throttle RAM: %0X\n", | |
421 | p->rapl_dram_perf_status); | |
422 | outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); | |
c98d5d94 | 423 | } |
3b4d5c7f AS |
424 | |
425 | outp += sprintf(outp, "\n"); | |
426 | ||
c98d5d94 | 427 | return 0; |
103a8fea LB |
428 | } |
429 | ||
e23da037 LB |
430 | /* |
431 | * column formatting convention & formats | |
e23da037 | 432 | */ |
c98d5d94 LB |
433 | int format_counters(struct thread_data *t, struct core_data *c, |
434 | struct pkg_data *p) | |
103a8fea LB |
435 | { |
436 | double interval_float; | |
fc04cc67 | 437 | char *fmt8; |
103a8fea | 438 | |
c98d5d94 LB |
439 | /* if showing only 1st thread in core and this isn't one, bail out */ |
440 | if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
441 | return 0; | |
442 | ||
443 | /* if showing only 1st thread in pkg and this isn't one, bail out */ | |
444 | if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
445 | return 0; | |
446 | ||
103a8fea LB |
447 | interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; |
448 | ||
c98d5d94 LB |
449 | /* topo columns, print blanks on 1st (average) line */ |
450 | if (t == &average.threads) { | |
103a8fea | 451 | if (show_pkg) |
fc04cc67 | 452 | outp += sprintf(outp, " -"); |
103a8fea | 453 | if (show_core) |
fc04cc67 | 454 | outp += sprintf(outp, " -"); |
103a8fea | 455 | if (show_cpu) |
fc04cc67 | 456 | outp += sprintf(outp, " -"); |
103a8fea | 457 | } else { |
c98d5d94 LB |
458 | if (show_pkg) { |
459 | if (p) | |
fc04cc67 | 460 | outp += sprintf(outp, "%8d", p->package_id); |
c98d5d94 | 461 | else |
fc04cc67 | 462 | outp += sprintf(outp, " -"); |
c98d5d94 | 463 | } |
c98d5d94 LB |
464 | if (show_core) { |
465 | if (c) | |
fc04cc67 | 466 | outp += sprintf(outp, "%8d", c->core_id); |
c98d5d94 | 467 | else |
fc04cc67 | 468 | outp += sprintf(outp, " -"); |
c98d5d94 | 469 | } |
103a8fea | 470 | if (show_cpu) |
fc04cc67 | 471 | outp += sprintf(outp, "%8d", t->cpu_id); |
103a8fea | 472 | } |
fc04cc67 | 473 | |
d7899447 | 474 | /* Avg_MHz */ |
fc04cc67 LB |
475 | if (has_aperf) |
476 | outp += sprintf(outp, "%8.0f", | |
477 | 1.0 / units * t->aperf / interval_float); | |
478 | ||
d7899447 LB |
479 | /* %Busy */ |
480 | if (has_aperf) { | |
103a8fea | 481 | if (!skip_c0) |
fc04cc67 | 482 | outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc); |
103a8fea | 483 | else |
fc04cc67 | 484 | outp += sprintf(outp, "********"); |
103a8fea LB |
485 | } |
486 | ||
d7899447 | 487 | /* Bzy_MHz */ |
fc04cc67 LB |
488 | if (has_aperf) |
489 | outp += sprintf(outp, "%8.0f", | |
490 | 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float); | |
103a8fea | 491 | |
d7899447 | 492 | /* TSC_MHz */ |
fc04cc67 | 493 | outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float); |
103a8fea | 494 | |
8e180f3c LB |
495 | /* delta */ |
496 | if (extra_delta_offset32) | |
497 | outp += sprintf(outp, " %11llu", t->extra_delta32); | |
498 | ||
499 | /* DELTA */ | |
500 | if (extra_delta_offset64) | |
501 | outp += sprintf(outp, " %11llu", t->extra_delta64); | |
2f32edf1 LB |
502 | /* msr */ |
503 | if (extra_msr_offset32) | |
8e180f3c | 504 | outp += sprintf(outp, " 0x%08llx", t->extra_msr32); |
2f32edf1 | 505 | |
130ff304 | 506 | /* MSR */ |
2f32edf1 LB |
507 | if (extra_msr_offset64) |
508 | outp += sprintf(outp, " 0x%016llx", t->extra_msr64); | |
130ff304 | 509 | |
1cc21f7b LB |
510 | if (!debug) |
511 | goto done; | |
512 | ||
513 | /* SMI */ | |
514 | if (do_smi) | |
515 | outp += sprintf(outp, "%8d", t->smi_count); | |
516 | ||
103a8fea LB |
517 | if (do_nhm_cstates) { |
518 | if (!skip_c1) | |
fc04cc67 | 519 | outp += sprintf(outp, "%8.2f", 100.0 * t->c1/t->tsc); |
103a8fea | 520 | else |
fc04cc67 | 521 | outp += sprintf(outp, "********"); |
103a8fea | 522 | } |
c98d5d94 LB |
523 | |
524 | /* print per-core data only for 1st thread in core */ | |
525 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
526 | goto done; | |
527 | ||
144b44b1 | 528 | if (do_nhm_cstates && !do_slm_cstates) |
fc04cc67 | 529 | outp += sprintf(outp, "%8.2f", 100.0 * c->c3/t->tsc); |
103a8fea | 530 | if (do_nhm_cstates) |
fc04cc67 | 531 | outp += sprintf(outp, "%8.2f", 100.0 * c->c6/t->tsc); |
103a8fea | 532 | if (do_snb_cstates) |
fc04cc67 | 533 | outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc); |
c98d5d94 | 534 | |
889facbe | 535 | if (do_dts) |
fc04cc67 | 536 | outp += sprintf(outp, "%8d", c->core_temp_c); |
889facbe | 537 | |
c98d5d94 LB |
538 | /* print per-package data only for 1st core in package */ |
539 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
540 | goto done; | |
541 | ||
889facbe | 542 | if (do_ptm) |
fc04cc67 | 543 | outp += sprintf(outp, "%8d", p->pkg_temp_c); |
889facbe | 544 | |
ee7e38e3 | 545 | if (do_pc2) |
fc04cc67 | 546 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc2/t->tsc); |
ee7e38e3 | 547 | if (do_pc3) |
fc04cc67 | 548 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc3/t->tsc); |
ee7e38e3 | 549 | if (do_pc6) |
fc04cc67 | 550 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc6/t->tsc); |
ee7e38e3 | 551 | if (do_pc7) |
fc04cc67 | 552 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc7/t->tsc); |
ca58710f | 553 | if (do_c8_c9_c10) { |
fc04cc67 LB |
554 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc8/t->tsc); |
555 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc9/t->tsc); | |
556 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc10/t->tsc); | |
ca58710f | 557 | } |
889facbe LB |
558 | |
559 | /* | |
560 | * If measurement interval exceeds minimum RAPL Joule Counter range, | |
561 | * indicate that results are suspect by printing "**" in fraction place. | |
562 | */ | |
fc04cc67 LB |
563 | if (interval_float < rapl_joule_counter_range) |
564 | fmt8 = "%8.2f"; | |
565 | else | |
566 | fmt8 = " %6.0f**"; | |
889facbe | 567 | |
5c56be9a DB |
568 | if (do_rapl && !rapl_joules) { |
569 | if (do_rapl & RAPL_PKG) | |
fc04cc67 | 570 | outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); |
5c56be9a | 571 | if (do_rapl & RAPL_CORES) |
fc04cc67 | 572 | outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); |
5c56be9a | 573 | if (do_rapl & RAPL_GFX) |
fc04cc67 | 574 | outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); |
5c56be9a | 575 | if (do_rapl & RAPL_DRAM) |
fc04cc67 | 576 | outp += sprintf(outp, fmt8, p->energy_dram * rapl_energy_units / interval_float); |
5c56be9a | 577 | if (do_rapl & RAPL_PKG_PERF_STATUS) |
fc04cc67 | 578 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); |
5c56be9a | 579 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
fc04cc67 | 580 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); |
d7899447 | 581 | } else if (do_rapl && rapl_joules) { |
5c56be9a | 582 | if (do_rapl & RAPL_PKG) |
fc04cc67 | 583 | outp += sprintf(outp, fmt8, |
5c56be9a DB |
584 | p->energy_pkg * rapl_energy_units); |
585 | if (do_rapl & RAPL_CORES) | |
fc04cc67 | 586 | outp += sprintf(outp, fmt8, |
5c56be9a DB |
587 | p->energy_cores * rapl_energy_units); |
588 | if (do_rapl & RAPL_GFX) | |
fc04cc67 | 589 | outp += sprintf(outp, fmt8, |
5c56be9a DB |
590 | p->energy_gfx * rapl_energy_units); |
591 | if (do_rapl & RAPL_DRAM) | |
fc04cc67 | 592 | outp += sprintf(outp, fmt8, |
5c56be9a DB |
593 | p->energy_dram * rapl_energy_units); |
594 | if (do_rapl & RAPL_PKG_PERF_STATUS) | |
fc04cc67 | 595 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); |
5c56be9a | 596 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
fc04cc67 | 597 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); |
889facbe | 598 | |
d7899447 | 599 | outp += sprintf(outp, fmt8, interval_float); |
5c56be9a | 600 | } |
c98d5d94 | 601 | done: |
c98d5d94 LB |
602 | outp += sprintf(outp, "\n"); |
603 | ||
604 | return 0; | |
103a8fea LB |
605 | } |
606 | ||
c98d5d94 LB |
607 | void flush_stdout() |
608 | { | |
609 | fputs(output_buffer, stdout); | |
ddac0d68 | 610 | fflush(stdout); |
c98d5d94 LB |
611 | outp = output_buffer; |
612 | } | |
613 | void flush_stderr() | |
614 | { | |
615 | fputs(output_buffer, stderr); | |
616 | outp = output_buffer; | |
617 | } | |
618 | void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
103a8fea | 619 | { |
e23da037 | 620 | static int printed; |
103a8fea | 621 | |
e23da037 LB |
622 | if (!printed || !summary_only) |
623 | print_header(); | |
103a8fea | 624 | |
c98d5d94 LB |
625 | if (topo.num_cpus > 1) |
626 | format_counters(&average.threads, &average.cores, | |
627 | &average.packages); | |
103a8fea | 628 | |
e23da037 LB |
629 | printed = 1; |
630 | ||
631 | if (summary_only) | |
632 | return; | |
633 | ||
c98d5d94 | 634 | for_all_cpus(format_counters, t, c, p); |
103a8fea LB |
635 | } |
636 | ||
889facbe LB |
637 | #define DELTA_WRAP32(new, old) \ |
638 | if (new > old) { \ | |
639 | old = new - old; \ | |
640 | } else { \ | |
641 | old = 0x100000000 + new - old; \ | |
642 | } | |
643 | ||
c98d5d94 LB |
644 | void |
645 | delta_package(struct pkg_data *new, struct pkg_data *old) | |
646 | { | |
647 | old->pc2 = new->pc2 - old->pc2; | |
ee7e38e3 LB |
648 | if (do_pc3) |
649 | old->pc3 = new->pc3 - old->pc3; | |
650 | if (do_pc6) | |
651 | old->pc6 = new->pc6 - old->pc6; | |
652 | if (do_pc7) | |
653 | old->pc7 = new->pc7 - old->pc7; | |
ca58710f KCA |
654 | old->pc8 = new->pc8 - old->pc8; |
655 | old->pc9 = new->pc9 - old->pc9; | |
656 | old->pc10 = new->pc10 - old->pc10; | |
889facbe LB |
657 | old->pkg_temp_c = new->pkg_temp_c; |
658 | ||
659 | DELTA_WRAP32(new->energy_pkg, old->energy_pkg); | |
660 | DELTA_WRAP32(new->energy_cores, old->energy_cores); | |
661 | DELTA_WRAP32(new->energy_gfx, old->energy_gfx); | |
662 | DELTA_WRAP32(new->energy_dram, old->energy_dram); | |
663 | DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); | |
664 | DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); | |
c98d5d94 | 665 | } |
103a8fea | 666 | |
c98d5d94 LB |
667 | void |
668 | delta_core(struct core_data *new, struct core_data *old) | |
103a8fea | 669 | { |
c98d5d94 LB |
670 | old->c3 = new->c3 - old->c3; |
671 | old->c6 = new->c6 - old->c6; | |
672 | old->c7 = new->c7 - old->c7; | |
889facbe | 673 | old->core_temp_c = new->core_temp_c; |
c98d5d94 | 674 | } |
103a8fea | 675 | |
c3ae331d LB |
676 | /* |
677 | * old = new - old | |
678 | */ | |
c98d5d94 LB |
679 | void |
680 | delta_thread(struct thread_data *new, struct thread_data *old, | |
681 | struct core_data *core_delta) | |
682 | { | |
683 | old->tsc = new->tsc - old->tsc; | |
684 | ||
685 | /* check for TSC < 1 Mcycles over interval */ | |
b2c95d90 JT |
686 | if (old->tsc < (1000 * 1000)) |
687 | errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" | |
688 | "You can disable all c-states by booting with \"idle=poll\"\n" | |
689 | "or just the deep ones with \"processor.max_cstate=1\""); | |
103a8fea | 690 | |
c98d5d94 | 691 | old->c1 = new->c1 - old->c1; |
103a8fea | 692 | |
a729617c LB |
693 | if (has_aperf) { |
694 | if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { | |
695 | old->aperf = new->aperf - old->aperf; | |
696 | old->mperf = new->mperf - old->mperf; | |
697 | } else { | |
103a8fea | 698 | |
a729617c LB |
699 | if (!aperf_mperf_unstable) { |
700 | fprintf(stderr, "%s: APERF or MPERF went backwards *\n", progname); | |
701 | fprintf(stderr, "* Frequency results do not cover entire interval *\n"); | |
702 | fprintf(stderr, "* fix this by running Linux-2.6.30 or later *\n"); | |
103a8fea | 703 | |
a729617c LB |
704 | aperf_mperf_unstable = 1; |
705 | } | |
706 | /* | |
707 | * mperf delta is likely a huge "positive" number | |
708 | * can not use it for calculating c0 time | |
709 | */ | |
710 | skip_c0 = 1; | |
711 | skip_c1 = 1; | |
103a8fea | 712 | } |
c98d5d94 | 713 | } |
103a8fea | 714 | |
103a8fea | 715 | |
144b44b1 LB |
716 | if (use_c1_residency_msr) { |
717 | /* | |
718 | * Some models have a dedicated C1 residency MSR, | |
719 | * which should be more accurate than the derivation below. | |
720 | */ | |
721 | } else { | |
722 | /* | |
723 | * As counter collection is not atomic, | |
724 | * it is possible for mperf's non-halted cycles + idle states | |
725 | * to exceed TSC's all cycles: show c1 = 0% in that case. | |
726 | */ | |
727 | if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) | |
728 | old->c1 = 0; | |
729 | else { | |
730 | /* normal case, derive c1 */ | |
731 | old->c1 = old->tsc - old->mperf - core_delta->c3 | |
c98d5d94 | 732 | - core_delta->c6 - core_delta->c7; |
144b44b1 | 733 | } |
c98d5d94 | 734 | } |
c3ae331d | 735 | |
c98d5d94 | 736 | if (old->mperf == 0) { |
d8af6f5f | 737 | if (debug > 1) fprintf(stderr, "cpu%d MPERF 0!\n", old->cpu_id); |
c98d5d94 | 738 | old->mperf = 1; /* divide by 0 protection */ |
103a8fea | 739 | } |
c98d5d94 | 740 | |
8e180f3c LB |
741 | old->extra_delta32 = new->extra_delta32 - old->extra_delta32; |
742 | old->extra_delta32 &= 0xFFFFFFFF; | |
743 | ||
744 | old->extra_delta64 = new->extra_delta64 - old->extra_delta64; | |
745 | ||
c98d5d94 | 746 | /* |
8e180f3c | 747 | * Extra MSR is just a snapshot, simply copy latest w/o subtracting |
c98d5d94 | 748 | */ |
2f32edf1 LB |
749 | old->extra_msr32 = new->extra_msr32; |
750 | old->extra_msr64 = new->extra_msr64; | |
1ed51011 LB |
751 | |
752 | if (do_smi) | |
753 | old->smi_count = new->smi_count - old->smi_count; | |
c98d5d94 LB |
754 | } |
755 | ||
756 | int delta_cpu(struct thread_data *t, struct core_data *c, | |
757 | struct pkg_data *p, struct thread_data *t2, | |
758 | struct core_data *c2, struct pkg_data *p2) | |
759 | { | |
760 | /* calculate core delta only for 1st thread in core */ | |
761 | if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) | |
762 | delta_core(c, c2); | |
763 | ||
764 | /* always calculate thread delta */ | |
765 | delta_thread(t, t2, c2); /* c2 is core delta */ | |
766 | ||
767 | /* calculate package delta only for 1st core in package */ | |
768 | if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) | |
769 | delta_package(p, p2); | |
770 | ||
103a8fea LB |
771 | return 0; |
772 | } | |
773 | ||
c98d5d94 LB |
774 | void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) |
775 | { | |
776 | t->tsc = 0; | |
777 | t->aperf = 0; | |
778 | t->mperf = 0; | |
779 | t->c1 = 0; | |
780 | ||
1ed51011 | 781 | t->smi_count = 0; |
8e180f3c LB |
782 | t->extra_delta32 = 0; |
783 | t->extra_delta64 = 0; | |
784 | ||
c98d5d94 LB |
785 | /* tells format_counters to dump all fields from this set */ |
786 | t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; | |
787 | ||
788 | c->c3 = 0; | |
789 | c->c6 = 0; | |
790 | c->c7 = 0; | |
889facbe | 791 | c->core_temp_c = 0; |
c98d5d94 LB |
792 | |
793 | p->pc2 = 0; | |
ee7e38e3 LB |
794 | if (do_pc3) |
795 | p->pc3 = 0; | |
796 | if (do_pc6) | |
797 | p->pc6 = 0; | |
798 | if (do_pc7) | |
799 | p->pc7 = 0; | |
ca58710f KCA |
800 | p->pc8 = 0; |
801 | p->pc9 = 0; | |
802 | p->pc10 = 0; | |
889facbe LB |
803 | |
804 | p->energy_pkg = 0; | |
805 | p->energy_dram = 0; | |
806 | p->energy_cores = 0; | |
807 | p->energy_gfx = 0; | |
808 | p->rapl_pkg_perf_status = 0; | |
809 | p->rapl_dram_perf_status = 0; | |
810 | p->pkg_temp_c = 0; | |
c98d5d94 LB |
811 | } |
812 | int sum_counters(struct thread_data *t, struct core_data *c, | |
813 | struct pkg_data *p) | |
103a8fea | 814 | { |
c98d5d94 LB |
815 | average.threads.tsc += t->tsc; |
816 | average.threads.aperf += t->aperf; | |
817 | average.threads.mperf += t->mperf; | |
818 | average.threads.c1 += t->c1; | |
103a8fea | 819 | |
8e180f3c LB |
820 | average.threads.extra_delta32 += t->extra_delta32; |
821 | average.threads.extra_delta64 += t->extra_delta64; | |
822 | ||
c98d5d94 LB |
823 | /* sum per-core values only for 1st thread in core */ |
824 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
825 | return 0; | |
103a8fea | 826 | |
c98d5d94 LB |
827 | average.cores.c3 += c->c3; |
828 | average.cores.c6 += c->c6; | |
829 | average.cores.c7 += c->c7; | |
830 | ||
889facbe LB |
831 | average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); |
832 | ||
c98d5d94 LB |
833 | /* sum per-pkg values only for 1st core in pkg */ |
834 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
835 | return 0; | |
836 | ||
837 | average.packages.pc2 += p->pc2; | |
ee7e38e3 LB |
838 | if (do_pc3) |
839 | average.packages.pc3 += p->pc3; | |
840 | if (do_pc6) | |
841 | average.packages.pc6 += p->pc6; | |
842 | if (do_pc7) | |
843 | average.packages.pc7 += p->pc7; | |
ca58710f KCA |
844 | average.packages.pc8 += p->pc8; |
845 | average.packages.pc9 += p->pc9; | |
846 | average.packages.pc10 += p->pc10; | |
c98d5d94 | 847 | |
889facbe LB |
848 | average.packages.energy_pkg += p->energy_pkg; |
849 | average.packages.energy_dram += p->energy_dram; | |
850 | average.packages.energy_cores += p->energy_cores; | |
851 | average.packages.energy_gfx += p->energy_gfx; | |
852 | ||
853 | average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); | |
854 | ||
855 | average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; | |
856 | average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; | |
c98d5d94 LB |
857 | return 0; |
858 | } | |
859 | /* | |
860 | * sum the counters for all cpus in the system | |
861 | * compute the weighted average | |
862 | */ | |
863 | void compute_average(struct thread_data *t, struct core_data *c, | |
864 | struct pkg_data *p) | |
865 | { | |
866 | clear_counters(&average.threads, &average.cores, &average.packages); | |
867 | ||
868 | for_all_cpus(sum_counters, t, c, p); | |
869 | ||
870 | average.threads.tsc /= topo.num_cpus; | |
871 | average.threads.aperf /= topo.num_cpus; | |
872 | average.threads.mperf /= topo.num_cpus; | |
873 | average.threads.c1 /= topo.num_cpus; | |
874 | ||
8e180f3c LB |
875 | average.threads.extra_delta32 /= topo.num_cpus; |
876 | average.threads.extra_delta32 &= 0xFFFFFFFF; | |
877 | ||
878 | average.threads.extra_delta64 /= topo.num_cpus; | |
879 | ||
c98d5d94 LB |
880 | average.cores.c3 /= topo.num_cores; |
881 | average.cores.c6 /= topo.num_cores; | |
882 | average.cores.c7 /= topo.num_cores; | |
883 | ||
884 | average.packages.pc2 /= topo.num_packages; | |
ee7e38e3 LB |
885 | if (do_pc3) |
886 | average.packages.pc3 /= topo.num_packages; | |
887 | if (do_pc6) | |
888 | average.packages.pc6 /= topo.num_packages; | |
889 | if (do_pc7) | |
890 | average.packages.pc7 /= topo.num_packages; | |
ca58710f KCA |
891 | |
892 | average.packages.pc8 /= topo.num_packages; | |
893 | average.packages.pc9 /= topo.num_packages; | |
894 | average.packages.pc10 /= topo.num_packages; | |
103a8fea LB |
895 | } |
896 | ||
c98d5d94 | 897 | static unsigned long long rdtsc(void) |
103a8fea | 898 | { |
c98d5d94 | 899 | unsigned int low, high; |
15aaa346 | 900 | |
c98d5d94 | 901 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
15aaa346 | 902 | |
c98d5d94 LB |
903 | return low | ((unsigned long long)high) << 32; |
904 | } | |
15aaa346 | 905 | |
15aaa346 | 906 | |
c98d5d94 LB |
907 | /* |
908 | * get_counters(...) | |
909 | * migrate to cpu | |
910 | * acquire and record local counters for that cpu | |
911 | */ | |
912 | int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
913 | { | |
914 | int cpu = t->cpu_id; | |
889facbe | 915 | unsigned long long msr; |
88c3281f | 916 | |
e52966c0 LB |
917 | if (cpu_migrate(cpu)) { |
918 | fprintf(stderr, "Could not migrate to CPU %d\n", cpu); | |
c98d5d94 | 919 | return -1; |
e52966c0 | 920 | } |
15aaa346 | 921 | |
c98d5d94 LB |
922 | t->tsc = rdtsc(); /* we are running on local CPU of interest */ |
923 | ||
924 | if (has_aperf) { | |
9c63a650 | 925 | if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) |
c98d5d94 | 926 | return -3; |
9c63a650 | 927 | if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) |
c98d5d94 LB |
928 | return -4; |
929 | } | |
930 | ||
1ed51011 LB |
931 | if (do_smi) { |
932 | if (get_msr(cpu, MSR_SMI_COUNT, &msr)) | |
933 | return -5; | |
934 | t->smi_count = msr & 0xFFFFFFFF; | |
935 | } | |
8e180f3c | 936 | if (extra_delta_offset32) { |
889facbe | 937 | if (get_msr(cpu, extra_delta_offset32, &msr)) |
8e180f3c | 938 | return -5; |
889facbe | 939 | t->extra_delta32 = msr & 0xFFFFFFFF; |
8e180f3c LB |
940 | } |
941 | ||
942 | if (extra_delta_offset64) | |
943 | if (get_msr(cpu, extra_delta_offset64, &t->extra_delta64)) | |
2f32edf1 LB |
944 | return -5; |
945 | ||
8e180f3c | 946 | if (extra_msr_offset32) { |
889facbe | 947 | if (get_msr(cpu, extra_msr_offset32, &msr)) |
8e180f3c | 948 | return -5; |
889facbe | 949 | t->extra_msr32 = msr & 0xFFFFFFFF; |
8e180f3c LB |
950 | } |
951 | ||
2f32edf1 LB |
952 | if (extra_msr_offset64) |
953 | if (get_msr(cpu, extra_msr_offset64, &t->extra_msr64)) | |
c98d5d94 LB |
954 | return -5; |
955 | ||
144b44b1 LB |
956 | if (use_c1_residency_msr) { |
957 | if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) | |
958 | return -6; | |
959 | } | |
960 | ||
c98d5d94 LB |
961 | /* collect core counters only for 1st thread in core */ |
962 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
963 | return 0; | |
964 | ||
144b44b1 | 965 | if (do_nhm_cstates && !do_slm_cstates) { |
c98d5d94 LB |
966 | if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) |
967 | return -6; | |
144b44b1 LB |
968 | } |
969 | ||
970 | if (do_nhm_cstates) { | |
c98d5d94 LB |
971 | if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) |
972 | return -7; | |
973 | } | |
974 | ||
975 | if (do_snb_cstates) | |
976 | if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) | |
977 | return -8; | |
978 | ||
889facbe LB |
979 | if (do_dts) { |
980 | if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) | |
981 | return -9; | |
982 | c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); | |
983 | } | |
984 | ||
985 | ||
c98d5d94 LB |
986 | /* collect package counters only for 1st core in package */ |
987 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
988 | return 0; | |
989 | ||
ee7e38e3 | 990 | if (do_pc3) |
c98d5d94 LB |
991 | if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) |
992 | return -9; | |
ee7e38e3 | 993 | if (do_pc6) |
c98d5d94 LB |
994 | if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) |
995 | return -10; | |
ee7e38e3 | 996 | if (do_pc2) |
c98d5d94 LB |
997 | if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) |
998 | return -11; | |
ee7e38e3 | 999 | if (do_pc7) |
c98d5d94 LB |
1000 | if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) |
1001 | return -12; | |
ca58710f KCA |
1002 | if (do_c8_c9_c10) { |
1003 | if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) | |
1004 | return -13; | |
1005 | if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) | |
1006 | return -13; | |
1007 | if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) | |
1008 | return -13; | |
1009 | } | |
889facbe LB |
1010 | if (do_rapl & RAPL_PKG) { |
1011 | if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) | |
1012 | return -13; | |
1013 | p->energy_pkg = msr & 0xFFFFFFFF; | |
1014 | } | |
1015 | if (do_rapl & RAPL_CORES) { | |
1016 | if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) | |
1017 | return -14; | |
1018 | p->energy_cores = msr & 0xFFFFFFFF; | |
1019 | } | |
1020 | if (do_rapl & RAPL_DRAM) { | |
1021 | if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) | |
1022 | return -15; | |
1023 | p->energy_dram = msr & 0xFFFFFFFF; | |
1024 | } | |
1025 | if (do_rapl & RAPL_GFX) { | |
1026 | if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) | |
1027 | return -16; | |
1028 | p->energy_gfx = msr & 0xFFFFFFFF; | |
1029 | } | |
1030 | if (do_rapl & RAPL_PKG_PERF_STATUS) { | |
1031 | if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) | |
1032 | return -16; | |
1033 | p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; | |
1034 | } | |
1035 | if (do_rapl & RAPL_DRAM_PERF_STATUS) { | |
1036 | if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) | |
1037 | return -16; | |
1038 | p->rapl_dram_perf_status = msr & 0xFFFFFFFF; | |
1039 | } | |
1040 | if (do_ptm) { | |
1041 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) | |
1042 | return -17; | |
1043 | p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); | |
1044 | } | |
15aaa346 | 1045 | return 0; |
103a8fea LB |
1046 | } |
1047 | ||
ee7e38e3 LB |
1048 | /* |
1049 | * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: | |
1050 | * If you change the values, note they are used both in comparisons | |
1051 | * (>= PCL__7) and to index pkg_cstate_limit_strings[]. | |
1052 | */ | |
1053 | ||
1054 | #define PCLUKN 0 /* Unknown */ | |
1055 | #define PCLRSV 1 /* Reserved */ | |
1056 | #define PCL__0 2 /* PC0 */ | |
1057 | #define PCL__1 3 /* PC1 */ | |
1058 | #define PCL__2 4 /* PC2 */ | |
1059 | #define PCL__3 5 /* PC3 */ | |
1060 | #define PCL__4 6 /* PC4 */ | |
1061 | #define PCL__6 7 /* PC6 */ | |
1062 | #define PCL_6N 8 /* PC6 No Retention */ | |
1063 | #define PCL_6R 9 /* PC6 Retention */ | |
1064 | #define PCL__7 10 /* PC7 */ | |
1065 | #define PCL_7S 11 /* PC7 Shrink */ | |
1066 | #define PCLUNL 12 /* Unlimited */ | |
1067 | ||
1068 | int pkg_cstate_limit = PCLUKN; | |
1069 | char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", | |
1070 | "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "unlimited"}; | |
1071 | ||
1072 | int nhm_pkg_cstate_limits[8] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL}; | |
1073 | int snb_pkg_cstate_limits[8] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL}; | |
1074 | int hsw_pkg_cstate_limits[8] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCLRSV, PCLUNL}; | |
1075 | int slv_pkg_cstate_limits[8] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7}; | |
1076 | int amt_pkg_cstate_limits[8] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; | |
1077 | int phi_pkg_cstate_limits[8] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL}; | |
1078 | ||
fcd17211 LB |
1079 | static void |
1080 | dump_nhm_platform_info(void) | |
103a8fea LB |
1081 | { |
1082 | unsigned long long msr; | |
1083 | unsigned int ratio; | |
1084 | ||
9c63a650 | 1085 | get_msr(0, MSR_NHM_PLATFORM_INFO, &msr); |
103a8fea | 1086 | |
67920418 | 1087 | fprintf(stderr, "cpu0: MSR_NHM_PLATFORM_INFO: 0x%08llx\n", msr); |
6574a5d5 | 1088 | |
103a8fea | 1089 | ratio = (msr >> 40) & 0xFF; |
8f61f359 | 1090 | fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency frequency\n", |
103a8fea LB |
1091 | ratio, bclk, ratio * bclk); |
1092 | ||
1093 | ratio = (msr >> 8) & 0xFF; | |
8f61f359 | 1094 | fprintf(stderr, "%d * %.0f = %.0f MHz base frequency\n", |
103a8fea LB |
1095 | ratio, bclk, ratio * bclk); |
1096 | ||
67920418 | 1097 | get_msr(0, MSR_IA32_POWER_CTL, &msr); |
144b44b1 | 1098 | fprintf(stderr, "cpu0: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", |
67920418 LB |
1099 | msr, msr & 0x2 ? "EN" : "DIS"); |
1100 | ||
fcd17211 LB |
1101 | return; |
1102 | } | |
1103 | ||
1104 | static void | |
1105 | dump_hsw_turbo_ratio_limits(void) | |
1106 | { | |
1107 | unsigned long long msr; | |
1108 | unsigned int ratio; | |
1109 | ||
1110 | get_msr(0, MSR_TURBO_RATIO_LIMIT2, &msr); | |
1111 | ||
1112 | fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", msr); | |
1113 | ||
1114 | ratio = (msr >> 8) & 0xFF; | |
1115 | if (ratio) | |
1116 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 18 active cores\n", | |
1117 | ratio, bclk, ratio * bclk); | |
1118 | ||
1119 | ratio = (msr >> 0) & 0xFF; | |
1120 | if (ratio) | |
1121 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 17 active cores\n", | |
1122 | ratio, bclk, ratio * bclk); | |
1123 | return; | |
1124 | } | |
1125 | ||
1126 | static void | |
1127 | dump_ivt_turbo_ratio_limits(void) | |
1128 | { | |
1129 | unsigned long long msr; | |
1130 | unsigned int ratio; | |
6574a5d5 | 1131 | |
12bb43c6 | 1132 | get_msr(0, MSR_TURBO_RATIO_LIMIT1, &msr); |
6574a5d5 | 1133 | |
12bb43c6 | 1134 | fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", msr); |
6574a5d5 LB |
1135 | |
1136 | ratio = (msr >> 56) & 0xFF; | |
1137 | if (ratio) | |
1138 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 16 active cores\n", | |
1139 | ratio, bclk, ratio * bclk); | |
1140 | ||
1141 | ratio = (msr >> 48) & 0xFF; | |
1142 | if (ratio) | |
1143 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 15 active cores\n", | |
1144 | ratio, bclk, ratio * bclk); | |
1145 | ||
1146 | ratio = (msr >> 40) & 0xFF; | |
1147 | if (ratio) | |
1148 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 14 active cores\n", | |
1149 | ratio, bclk, ratio * bclk); | |
1150 | ||
1151 | ratio = (msr >> 32) & 0xFF; | |
1152 | if (ratio) | |
1153 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 13 active cores\n", | |
1154 | ratio, bclk, ratio * bclk); | |
1155 | ||
1156 | ratio = (msr >> 24) & 0xFF; | |
1157 | if (ratio) | |
1158 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 12 active cores\n", | |
1159 | ratio, bclk, ratio * bclk); | |
1160 | ||
1161 | ratio = (msr >> 16) & 0xFF; | |
1162 | if (ratio) | |
1163 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 11 active cores\n", | |
1164 | ratio, bclk, ratio * bclk); | |
1165 | ||
1166 | ratio = (msr >> 8) & 0xFF; | |
1167 | if (ratio) | |
1168 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 10 active cores\n", | |
1169 | ratio, bclk, ratio * bclk); | |
1170 | ||
1171 | ratio = (msr >> 0) & 0xFF; | |
1172 | if (ratio) | |
1173 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 9 active cores\n", | |
1174 | ratio, bclk, ratio * bclk); | |
fcd17211 LB |
1175 | return; |
1176 | } | |
6574a5d5 | 1177 | |
fcd17211 LB |
1178 | static void |
1179 | dump_nhm_turbo_ratio_limits(void) | |
1180 | { | |
1181 | unsigned long long msr; | |
1182 | unsigned int ratio; | |
103a8fea | 1183 | |
12bb43c6 | 1184 | get_msr(0, MSR_TURBO_RATIO_LIMIT, &msr); |
103a8fea | 1185 | |
12bb43c6 | 1186 | fprintf(stderr, "cpu0: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", msr); |
6574a5d5 LB |
1187 | |
1188 | ratio = (msr >> 56) & 0xFF; | |
1189 | if (ratio) | |
1190 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 8 active cores\n", | |
1191 | ratio, bclk, ratio * bclk); | |
1192 | ||
1193 | ratio = (msr >> 48) & 0xFF; | |
1194 | if (ratio) | |
1195 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 7 active cores\n", | |
1196 | ratio, bclk, ratio * bclk); | |
1197 | ||
1198 | ratio = (msr >> 40) & 0xFF; | |
1199 | if (ratio) | |
1200 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 6 active cores\n", | |
1201 | ratio, bclk, ratio * bclk); | |
1202 | ||
1203 | ratio = (msr >> 32) & 0xFF; | |
1204 | if (ratio) | |
1205 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 5 active cores\n", | |
1206 | ratio, bclk, ratio * bclk); | |
1207 | ||
103a8fea LB |
1208 | ratio = (msr >> 24) & 0xFF; |
1209 | if (ratio) | |
1210 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 4 active cores\n", | |
1211 | ratio, bclk, ratio * bclk); | |
1212 | ||
1213 | ratio = (msr >> 16) & 0xFF; | |
1214 | if (ratio) | |
1215 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 3 active cores\n", | |
1216 | ratio, bclk, ratio * bclk); | |
1217 | ||
1218 | ratio = (msr >> 8) & 0xFF; | |
1219 | if (ratio) | |
1220 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 2 active cores\n", | |
1221 | ratio, bclk, ratio * bclk); | |
1222 | ||
1223 | ratio = (msr >> 0) & 0xFF; | |
1224 | if (ratio) | |
1225 | fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 1 active cores\n", | |
1226 | ratio, bclk, ratio * bclk); | |
fcd17211 LB |
1227 | return; |
1228 | } | |
3a9a941d | 1229 | |
fcd17211 LB |
1230 | static void |
1231 | dump_nhm_cst_cfg(void) | |
1232 | { | |
1233 | unsigned long long msr; | |
1234 | ||
1235 | get_msr(0, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); | |
1236 | ||
1237 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) | |
1238 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) | |
1239 | ||
1240 | fprintf(stderr, "cpu0: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", msr); | |
1241 | ||
1242 | fprintf(stderr, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", | |
1243 | (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", | |
1244 | (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", | |
1245 | (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", | |
1246 | (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", | |
1247 | (msr & (1 << 15)) ? "" : "UN", | |
1248 | (unsigned int)msr & 7, | |
1249 | pkg_cstate_limit_strings[pkg_cstate_limit]); | |
1250 | return; | |
103a8fea LB |
1251 | } |
1252 | ||
c98d5d94 | 1253 | void free_all_buffers(void) |
103a8fea | 1254 | { |
c98d5d94 LB |
1255 | CPU_FREE(cpu_present_set); |
1256 | cpu_present_set = NULL; | |
1257 | cpu_present_set = 0; | |
103a8fea | 1258 | |
c98d5d94 LB |
1259 | CPU_FREE(cpu_affinity_set); |
1260 | cpu_affinity_set = NULL; | |
1261 | cpu_affinity_setsize = 0; | |
103a8fea | 1262 | |
c98d5d94 LB |
1263 | free(thread_even); |
1264 | free(core_even); | |
1265 | free(package_even); | |
103a8fea | 1266 | |
c98d5d94 LB |
1267 | thread_even = NULL; |
1268 | core_even = NULL; | |
1269 | package_even = NULL; | |
103a8fea | 1270 | |
c98d5d94 LB |
1271 | free(thread_odd); |
1272 | free(core_odd); | |
1273 | free(package_odd); | |
103a8fea | 1274 | |
c98d5d94 LB |
1275 | thread_odd = NULL; |
1276 | core_odd = NULL; | |
1277 | package_odd = NULL; | |
103a8fea | 1278 | |
c98d5d94 LB |
1279 | free(output_buffer); |
1280 | output_buffer = NULL; | |
1281 | outp = NULL; | |
103a8fea LB |
1282 | } |
1283 | ||
57a42a34 JT |
1284 | /* |
1285 | * Open a file, and exit on failure | |
1286 | */ | |
1287 | FILE *fopen_or_die(const char *path, const char *mode) | |
1288 | { | |
1289 | FILE *filep = fopen(path, "r"); | |
b2c95d90 JT |
1290 | if (!filep) |
1291 | err(1, "%s: open failed", path); | |
57a42a34 JT |
1292 | return filep; |
1293 | } | |
1294 | ||
c98d5d94 | 1295 | /* |
95aebc44 | 1296 | * Parse a file containing a single int. |
c98d5d94 | 1297 | */ |
95aebc44 | 1298 | int parse_int_file(const char *fmt, ...) |
103a8fea | 1299 | { |
95aebc44 JT |
1300 | va_list args; |
1301 | char path[PATH_MAX]; | |
c98d5d94 | 1302 | FILE *filep; |
95aebc44 | 1303 | int value; |
103a8fea | 1304 | |
95aebc44 JT |
1305 | va_start(args, fmt); |
1306 | vsnprintf(path, sizeof(path), fmt, args); | |
1307 | va_end(args); | |
57a42a34 | 1308 | filep = fopen_or_die(path, "r"); |
b2c95d90 JT |
1309 | if (fscanf(filep, "%d", &value) != 1) |
1310 | err(1, "%s: failed to parse number from file", path); | |
c98d5d94 | 1311 | fclose(filep); |
95aebc44 JT |
1312 | return value; |
1313 | } | |
1314 | ||
1315 | /* | |
1316 | * cpu_is_first_sibling_in_core(cpu) | |
1317 | * return 1 if given CPU is 1st HT sibling in the core | |
1318 | */ | |
1319 | int cpu_is_first_sibling_in_core(int cpu) | |
1320 | { | |
1321 | return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); | |
103a8fea LB |
1322 | } |
1323 | ||
c98d5d94 LB |
1324 | /* |
1325 | * cpu_is_first_core_in_package(cpu) | |
1326 | * return 1 if given CPU is 1st core in package | |
1327 | */ | |
1328 | int cpu_is_first_core_in_package(int cpu) | |
103a8fea | 1329 | { |
95aebc44 | 1330 | return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); |
103a8fea LB |
1331 | } |
1332 | ||
1333 | int get_physical_package_id(int cpu) | |
1334 | { | |
95aebc44 | 1335 | return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); |
103a8fea LB |
1336 | } |
1337 | ||
1338 | int get_core_id(int cpu) | |
1339 | { | |
95aebc44 | 1340 | return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); |
103a8fea LB |
1341 | } |
1342 | ||
c98d5d94 LB |
1343 | int get_num_ht_siblings(int cpu) |
1344 | { | |
1345 | char path[80]; | |
1346 | FILE *filep; | |
1347 | int sib1, sib2; | |
1348 | int matches; | |
1349 | char character; | |
1350 | ||
1351 | sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); | |
57a42a34 | 1352 | filep = fopen_or_die(path, "r"); |
c98d5d94 LB |
1353 | /* |
1354 | * file format: | |
1355 | * if a pair of number with a character between: 2 siblings (eg. 1-2, or 1,4) | |
1356 | * otherwinse 1 sibling (self). | |
1357 | */ | |
1358 | matches = fscanf(filep, "%d%c%d\n", &sib1, &character, &sib2); | |
1359 | ||
1360 | fclose(filep); | |
1361 | ||
1362 | if (matches == 3) | |
1363 | return 2; | |
1364 | else | |
1365 | return 1; | |
1366 | } | |
1367 | ||
103a8fea | 1368 | /* |
c98d5d94 LB |
1369 | * run func(thread, core, package) in topology order |
1370 | * skip non-present cpus | |
103a8fea LB |
1371 | */ |
1372 | ||
c98d5d94 LB |
1373 | int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, |
1374 | struct pkg_data *, struct thread_data *, struct core_data *, | |
1375 | struct pkg_data *), struct thread_data *thread_base, | |
1376 | struct core_data *core_base, struct pkg_data *pkg_base, | |
1377 | struct thread_data *thread_base2, struct core_data *core_base2, | |
1378 | struct pkg_data *pkg_base2) | |
1379 | { | |
1380 | int retval, pkg_no, core_no, thread_no; | |
1381 | ||
1382 | for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { | |
1383 | for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { | |
1384 | for (thread_no = 0; thread_no < | |
1385 | topo.num_threads_per_core; ++thread_no) { | |
1386 | struct thread_data *t, *t2; | |
1387 | struct core_data *c, *c2; | |
1388 | struct pkg_data *p, *p2; | |
1389 | ||
1390 | t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); | |
1391 | ||
1392 | if (cpu_is_not_present(t->cpu_id)) | |
1393 | continue; | |
1394 | ||
1395 | t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); | |
1396 | ||
1397 | c = GET_CORE(core_base, core_no, pkg_no); | |
1398 | c2 = GET_CORE(core_base2, core_no, pkg_no); | |
1399 | ||
1400 | p = GET_PKG(pkg_base, pkg_no); | |
1401 | p2 = GET_PKG(pkg_base2, pkg_no); | |
1402 | ||
1403 | retval = func(t, c, p, t2, c2, p2); | |
1404 | if (retval) | |
1405 | return retval; | |
1406 | } | |
1407 | } | |
1408 | } | |
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | /* | |
1413 | * run func(cpu) on every cpu in /proc/stat | |
1414 | * return max_cpu number | |
1415 | */ | |
1416 | int for_all_proc_cpus(int (func)(int)) | |
103a8fea LB |
1417 | { |
1418 | FILE *fp; | |
c98d5d94 | 1419 | int cpu_num; |
103a8fea LB |
1420 | int retval; |
1421 | ||
57a42a34 | 1422 | fp = fopen_or_die(proc_stat, "r"); |
103a8fea LB |
1423 | |
1424 | retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); | |
b2c95d90 JT |
1425 | if (retval != 0) |
1426 | err(1, "%s: failed to parse format", proc_stat); | |
103a8fea | 1427 | |
c98d5d94 LB |
1428 | while (1) { |
1429 | retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); | |
103a8fea LB |
1430 | if (retval != 1) |
1431 | break; | |
1432 | ||
c98d5d94 LB |
1433 | retval = func(cpu_num); |
1434 | if (retval) { | |
1435 | fclose(fp); | |
1436 | return(retval); | |
1437 | } | |
103a8fea LB |
1438 | } |
1439 | fclose(fp); | |
c98d5d94 | 1440 | return 0; |
103a8fea LB |
1441 | } |
1442 | ||
1443 | void re_initialize(void) | |
1444 | { | |
c98d5d94 LB |
1445 | free_all_buffers(); |
1446 | setup_all_buffers(); | |
1447 | printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); | |
103a8fea LB |
1448 | } |
1449 | ||
c98d5d94 | 1450 | |
103a8fea | 1451 | /* |
c98d5d94 LB |
1452 | * count_cpus() |
1453 | * remember the last one seen, it will be the max | |
103a8fea | 1454 | */ |
c98d5d94 | 1455 | int count_cpus(int cpu) |
103a8fea | 1456 | { |
c98d5d94 LB |
1457 | if (topo.max_cpu_num < cpu) |
1458 | topo.max_cpu_num = cpu; | |
103a8fea | 1459 | |
c98d5d94 LB |
1460 | topo.num_cpus += 1; |
1461 | return 0; | |
1462 | } | |
1463 | int mark_cpu_present(int cpu) | |
1464 | { | |
1465 | CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); | |
15aaa346 | 1466 | return 0; |
103a8fea LB |
1467 | } |
1468 | ||
1469 | void turbostat_loop() | |
1470 | { | |
c98d5d94 | 1471 | int retval; |
e52966c0 | 1472 | int restarted = 0; |
c98d5d94 | 1473 | |
103a8fea | 1474 | restart: |
e52966c0 LB |
1475 | restarted++; |
1476 | ||
c98d5d94 | 1477 | retval = for_all_cpus(get_counters, EVEN_COUNTERS); |
d91bb17c LB |
1478 | if (retval < -1) { |
1479 | exit(retval); | |
1480 | } else if (retval == -1) { | |
e52966c0 LB |
1481 | if (restarted > 1) { |
1482 | exit(retval); | |
1483 | } | |
c98d5d94 LB |
1484 | re_initialize(); |
1485 | goto restart; | |
1486 | } | |
e52966c0 | 1487 | restarted = 0; |
103a8fea LB |
1488 | gettimeofday(&tv_even, (struct timezone *)NULL); |
1489 | ||
1490 | while (1) { | |
c98d5d94 | 1491 | if (for_all_proc_cpus(cpu_is_not_present)) { |
103a8fea LB |
1492 | re_initialize(); |
1493 | goto restart; | |
1494 | } | |
1495 | sleep(interval_sec); | |
c98d5d94 | 1496 | retval = for_all_cpus(get_counters, ODD_COUNTERS); |
d91bb17c LB |
1497 | if (retval < -1) { |
1498 | exit(retval); | |
1499 | } else if (retval == -1) { | |
15aaa346 LB |
1500 | re_initialize(); |
1501 | goto restart; | |
1502 | } | |
103a8fea | 1503 | gettimeofday(&tv_odd, (struct timezone *)NULL); |
103a8fea | 1504 | timersub(&tv_odd, &tv_even, &tv_delta); |
c98d5d94 LB |
1505 | for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS); |
1506 | compute_average(EVEN_COUNTERS); | |
1507 | format_all_counters(EVEN_COUNTERS); | |
1508 | flush_stdout(); | |
15aaa346 | 1509 | sleep(interval_sec); |
c98d5d94 | 1510 | retval = for_all_cpus(get_counters, EVEN_COUNTERS); |
d91bb17c LB |
1511 | if (retval < -1) { |
1512 | exit(retval); | |
1513 | } else if (retval == -1) { | |
103a8fea LB |
1514 | re_initialize(); |
1515 | goto restart; | |
1516 | } | |
103a8fea | 1517 | gettimeofday(&tv_even, (struct timezone *)NULL); |
103a8fea | 1518 | timersub(&tv_even, &tv_odd, &tv_delta); |
c98d5d94 LB |
1519 | for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS); |
1520 | compute_average(ODD_COUNTERS); | |
1521 | format_all_counters(ODD_COUNTERS); | |
1522 | flush_stdout(); | |
103a8fea LB |
1523 | } |
1524 | } | |
1525 | ||
1526 | void check_dev_msr() | |
1527 | { | |
1528 | struct stat sb; | |
1529 | ||
b2c95d90 | 1530 | if (stat("/dev/cpu/0/msr", &sb)) |
a21d38c8 LB |
1531 | if (system("/sbin/modprobe msr > /dev/null 2>&1")) |
1532 | err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); | |
103a8fea LB |
1533 | } |
1534 | ||
98481e79 | 1535 | void check_permissions() |
103a8fea | 1536 | { |
98481e79 LB |
1537 | struct __user_cap_header_struct cap_header_data; |
1538 | cap_user_header_t cap_header = &cap_header_data; | |
1539 | struct __user_cap_data_struct cap_data_data; | |
1540 | cap_user_data_t cap_data = &cap_data_data; | |
1541 | extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); | |
1542 | int do_exit = 0; | |
1543 | ||
1544 | /* check for CAP_SYS_RAWIO */ | |
1545 | cap_header->pid = getpid(); | |
1546 | cap_header->version = _LINUX_CAPABILITY_VERSION; | |
1547 | if (capget(cap_header, cap_data) < 0) | |
1548 | err(-6, "capget(2) failed"); | |
1549 | ||
1550 | if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { | |
1551 | do_exit++; | |
1552 | warnx("capget(CAP_SYS_RAWIO) failed," | |
1553 | " try \"# setcap cap_sys_rawio=ep %s\"", progname); | |
1554 | } | |
1555 | ||
1556 | /* test file permissions */ | |
1557 | if (euidaccess("/dev/cpu/0/msr", R_OK)) { | |
1558 | do_exit++; | |
1559 | warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); | |
1560 | } | |
1561 | ||
1562 | /* if all else fails, thell them to be root */ | |
1563 | if (do_exit) | |
1564 | if (getuid() != 0) | |
d7899447 | 1565 | warnx("... or simply run as root"); |
98481e79 LB |
1566 | |
1567 | if (do_exit) | |
1568 | exit(-6); | |
103a8fea LB |
1569 | } |
1570 | ||
d7899447 LB |
1571 | /* |
1572 | * NHM adds support for additional MSRs: | |
1573 | * | |
1574 | * MSR_SMI_COUNT 0x00000034 | |
1575 | * | |
1576 | * MSR_NHM_PLATFORM_INFO 0x000000ce | |
1577 | * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 | |
1578 | * | |
1579 | * MSR_PKG_C3_RESIDENCY 0x000003f8 | |
1580 | * MSR_PKG_C6_RESIDENCY 0x000003f9 | |
1581 | * MSR_CORE_C3_RESIDENCY 0x000003fc | |
1582 | * MSR_CORE_C6_RESIDENCY 0x000003fd | |
1583 | * | |
ee7e38e3 LB |
1584 | * Side effect: |
1585 | * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL | |
d7899447 | 1586 | */ |
ee7e38e3 | 1587 | int probe_nhm_msrs(unsigned int family, unsigned int model) |
103a8fea | 1588 | { |
ee7e38e3 LB |
1589 | unsigned long long msr; |
1590 | int *pkg_cstate_limits; | |
1591 | ||
103a8fea LB |
1592 | if (!genuine_intel) |
1593 | return 0; | |
1594 | ||
1595 | if (family != 6) | |
1596 | return 0; | |
1597 | ||
1598 | switch (model) { | |
1599 | case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ | |
1600 | case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ | |
1601 | case 0x1F: /* Core i7 and i5 Processor - Nehalem */ | |
1602 | case 0x25: /* Westmere Client - Clarkdale, Arrandale */ | |
1603 | case 0x2C: /* Westmere EP - Gulftown */ | |
ee7e38e3 LB |
1604 | case 0x2E: /* Nehalem-EX Xeon - Beckton */ |
1605 | case 0x2F: /* Westmere-EX Xeon - Eagleton */ | |
1606 | pkg_cstate_limits = nhm_pkg_cstate_limits; | |
1607 | break; | |
103a8fea LB |
1608 | case 0x2A: /* SNB */ |
1609 | case 0x2D: /* SNB Xeon */ | |
553575f1 | 1610 | case 0x3A: /* IVB */ |
1300651b | 1611 | case 0x3E: /* IVB Xeon */ |
ee7e38e3 LB |
1612 | pkg_cstate_limits = snb_pkg_cstate_limits; |
1613 | break; | |
70b43400 | 1614 | case 0x3C: /* HSW */ |
e6f9bb3c | 1615 | case 0x3F: /* HSX */ |
70b43400 | 1616 | case 0x45: /* HSW */ |
149c2319 | 1617 | case 0x46: /* HSW */ |
4e8e863f | 1618 | case 0x3D: /* BDW */ |
48a0631c | 1619 | case 0x47: /* BDW */ |
4e8e863f LB |
1620 | case 0x4F: /* BDX */ |
1621 | case 0x56: /* BDX-DE */ | |
ee7e38e3 LB |
1622 | pkg_cstate_limits = hsw_pkg_cstate_limits; |
1623 | break; | |
1624 | case 0x37: /* BYT */ | |
1625 | case 0x4D: /* AVN */ | |
1626 | pkg_cstate_limits = slv_pkg_cstate_limits; | |
1627 | break; | |
1628 | case 0x4C: /* AMT */ | |
1629 | pkg_cstate_limits = amt_pkg_cstate_limits; | |
1630 | break; | |
1631 | case 0x57: /* PHI */ | |
1632 | pkg_cstate_limits = phi_pkg_cstate_limits; | |
1633 | break; | |
103a8fea LB |
1634 | default: |
1635 | return 0; | |
1636 | } | |
ee7e38e3 LB |
1637 | get_msr(0, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); |
1638 | ||
1639 | pkg_cstate_limit = pkg_cstate_limits[msr & 0x7]; | |
1640 | ||
1641 | return 1; | |
103a8fea | 1642 | } |
d7899447 LB |
1643 | int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) |
1644 | { | |
d7899447 LB |
1645 | switch (model) { |
1646 | /* Nehalem compatible, but do not include turbo-ratio limit support */ | |
1647 | case 0x2E: /* Nehalem-EX Xeon - Beckton */ | |
1648 | case 0x2F: /* Westmere-EX Xeon - Eagleton */ | |
1649 | return 0; | |
1650 | default: | |
1651 | return 1; | |
1652 | } | |
1653 | } | |
6574a5d5 LB |
1654 | int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) |
1655 | { | |
1656 | if (!genuine_intel) | |
1657 | return 0; | |
1658 | ||
1659 | if (family != 6) | |
1660 | return 0; | |
1661 | ||
1662 | switch (model) { | |
1663 | case 0x3E: /* IVB Xeon */ | |
fcd17211 LB |
1664 | case 0x3F: /* HSW Xeon */ |
1665 | return 1; | |
1666 | default: | |
1667 | return 0; | |
1668 | } | |
1669 | } | |
1670 | int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) | |
1671 | { | |
1672 | if (!genuine_intel) | |
1673 | return 0; | |
1674 | ||
1675 | if (family != 6) | |
1676 | return 0; | |
1677 | ||
1678 | switch (model) { | |
1679 | case 0x3F: /* HSW Xeon */ | |
6574a5d5 LB |
1680 | return 1; |
1681 | default: | |
1682 | return 0; | |
1683 | } | |
1684 | } | |
1685 | ||
fcd17211 LB |
1686 | static void |
1687 | dump_cstate_pstate_config_info(family, model) | |
1688 | { | |
1689 | if (!do_nhm_platform_info) | |
1690 | return; | |
1691 | ||
1692 | dump_nhm_platform_info(); | |
1693 | ||
1694 | if (has_hsw_turbo_ratio_limit(family, model)) | |
1695 | dump_hsw_turbo_ratio_limits(); | |
1696 | ||
1697 | if (has_ivt_turbo_ratio_limit(family, model)) | |
1698 | dump_ivt_turbo_ratio_limits(); | |
1699 | ||
1700 | if (has_nhm_turbo_ratio_limit(family, model)) | |
1701 | dump_nhm_turbo_ratio_limits(); | |
1702 | ||
1703 | dump_nhm_cst_cfg(); | |
1704 | } | |
1705 | ||
1706 | ||
889facbe LB |
1707 | /* |
1708 | * print_epb() | |
1709 | * Decode the ENERGY_PERF_BIAS MSR | |
1710 | */ | |
1711 | int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
1712 | { | |
1713 | unsigned long long msr; | |
1714 | char *epb_string; | |
1715 | int cpu; | |
1716 | ||
1717 | if (!has_epb) | |
1718 | return 0; | |
1719 | ||
1720 | cpu = t->cpu_id; | |
1721 | ||
1722 | /* EPB is per-package */ | |
1723 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
1724 | return 0; | |
1725 | ||
1726 | if (cpu_migrate(cpu)) { | |
1727 | fprintf(stderr, "Could not migrate to CPU %d\n", cpu); | |
1728 | return -1; | |
1729 | } | |
1730 | ||
1731 | if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) | |
1732 | return 0; | |
1733 | ||
1734 | switch (msr & 0x7) { | |
1735 | case ENERGY_PERF_BIAS_PERFORMANCE: | |
1736 | epb_string = "performance"; | |
1737 | break; | |
1738 | case ENERGY_PERF_BIAS_NORMAL: | |
1739 | epb_string = "balanced"; | |
1740 | break; | |
1741 | case ENERGY_PERF_BIAS_POWERSAVE: | |
1742 | epb_string = "powersave"; | |
1743 | break; | |
1744 | default: | |
1745 | epb_string = "custom"; | |
1746 | break; | |
1747 | } | |
1748 | fprintf(stderr, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); | |
1749 | ||
1750 | return 0; | |
1751 | } | |
1752 | ||
3a9a941d LB |
1753 | /* |
1754 | * print_perf_limit() | |
1755 | */ | |
1756 | int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
1757 | { | |
1758 | unsigned long long msr; | |
1759 | int cpu; | |
1760 | ||
1761 | cpu = t->cpu_id; | |
1762 | ||
1763 | /* per-package */ | |
1764 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
1765 | return 0; | |
1766 | ||
1767 | if (cpu_migrate(cpu)) { | |
1768 | fprintf(stderr, "Could not migrate to CPU %d\n", cpu); | |
1769 | return -1; | |
1770 | } | |
1771 | ||
1772 | if (do_core_perf_limit_reasons) { | |
1773 | get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); | |
1774 | fprintf(stderr, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); | |
1775 | fprintf(stderr, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", | |
e33cbe85 | 1776 | (msr & 1 << 15) ? "bit15, " : "", |
3a9a941d | 1777 | (msr & 1 << 14) ? "bit14, " : "", |
e33cbe85 LB |
1778 | (msr & 1 << 13) ? "Transitions, " : "", |
1779 | (msr & 1 << 12) ? "MultiCoreTurbo, " : "", | |
1780 | (msr & 1 << 11) ? "PkgPwrL2, " : "", | |
1781 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
1782 | (msr & 1 << 9) ? "CorePwr, " : "", | |
1783 | (msr & 1 << 8) ? "Amps, " : "", | |
1784 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
1785 | (msr & 1 << 5) ? "Auto-HWP, " : "", | |
1786 | (msr & 1 << 4) ? "Graphics, " : "", | |
1787 | (msr & 1 << 2) ? "bit2, " : "", | |
1788 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
1789 | (msr & 1 << 0) ? "PROCHOT, " : ""); | |
3a9a941d | 1790 | fprintf(stderr, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", |
e33cbe85 | 1791 | (msr & 1 << 31) ? "bit31, " : "", |
3a9a941d | 1792 | (msr & 1 << 30) ? "bit30, " : "", |
e33cbe85 LB |
1793 | (msr & 1 << 29) ? "Transitions, " : "", |
1794 | (msr & 1 << 28) ? "MultiCoreTurbo, " : "", | |
1795 | (msr & 1 << 27) ? "PkgPwrL2, " : "", | |
1796 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
1797 | (msr & 1 << 25) ? "CorePwr, " : "", | |
1798 | (msr & 1 << 24) ? "Amps, " : "", | |
1799 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
1800 | (msr & 1 << 21) ? "Auto-HWP, " : "", | |
1801 | (msr & 1 << 20) ? "Graphics, " : "", | |
1802 | (msr & 1 << 18) ? "bit18, " : "", | |
1803 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
1804 | (msr & 1 << 16) ? "PROCHOT, " : ""); | |
3a9a941d LB |
1805 | |
1806 | } | |
1807 | if (do_gfx_perf_limit_reasons) { | |
1808 | get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); | |
1809 | fprintf(stderr, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); | |
1810 | fprintf(stderr, " (Active: %s%s%s%s%s%s%s%s)", | |
1811 | (msr & 1 << 0) ? "PROCHOT, " : "", | |
1812 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
1813 | (msr & 1 << 4) ? "Graphics, " : "", | |
1814 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
1815 | (msr & 1 << 8) ? "Amps, " : "", | |
1816 | (msr & 1 << 9) ? "GFXPwr, " : "", | |
1817 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
1818 | (msr & 1 << 11) ? "PkgPwrL2, " : ""); | |
1819 | fprintf(stderr, " (Logged: %s%s%s%s%s%s%s%s)\n", | |
1820 | (msr & 1 << 16) ? "PROCHOT, " : "", | |
1821 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
1822 | (msr & 1 << 20) ? "Graphics, " : "", | |
1823 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
1824 | (msr & 1 << 24) ? "Amps, " : "", | |
1825 | (msr & 1 << 25) ? "GFXPwr, " : "", | |
1826 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
1827 | (msr & 1 << 27) ? "PkgPwrL2, " : ""); | |
1828 | } | |
1829 | if (do_ring_perf_limit_reasons) { | |
1830 | get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); | |
1831 | fprintf(stderr, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); | |
1832 | fprintf(stderr, " (Active: %s%s%s%s%s%s)", | |
1833 | (msr & 1 << 0) ? "PROCHOT, " : "", | |
1834 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
1835 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
1836 | (msr & 1 << 8) ? "Amps, " : "", | |
1837 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
1838 | (msr & 1 << 11) ? "PkgPwrL2, " : ""); | |
1839 | fprintf(stderr, " (Logged: %s%s%s%s%s%s)\n", | |
1840 | (msr & 1 << 16) ? "PROCHOT, " : "", | |
1841 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
1842 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
1843 | (msr & 1 << 24) ? "Amps, " : "", | |
1844 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
1845 | (msr & 1 << 27) ? "PkgPwrL2, " : ""); | |
1846 | } | |
1847 | return 0; | |
1848 | } | |
1849 | ||
889facbe LB |
1850 | #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ |
1851 | #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ | |
1852 | ||
144b44b1 LB |
1853 | double get_tdp(model) |
1854 | { | |
1855 | unsigned long long msr; | |
1856 | ||
1857 | if (do_rapl & RAPL_PKG_POWER_INFO) | |
1858 | if (!get_msr(0, MSR_PKG_POWER_INFO, &msr)) | |
1859 | return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; | |
1860 | ||
1861 | switch (model) { | |
1862 | case 0x37: | |
1863 | case 0x4D: | |
1864 | return 30.0; | |
1865 | default: | |
1866 | return 135.0; | |
1867 | } | |
1868 | } | |
1869 | ||
1870 | ||
889facbe LB |
1871 | /* |
1872 | * rapl_probe() | |
1873 | * | |
144b44b1 | 1874 | * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units |
889facbe LB |
1875 | */ |
1876 | void rapl_probe(unsigned int family, unsigned int model) | |
1877 | { | |
1878 | unsigned long long msr; | |
144b44b1 | 1879 | unsigned int time_unit; |
889facbe LB |
1880 | double tdp; |
1881 | ||
1882 | if (!genuine_intel) | |
1883 | return; | |
1884 | ||
1885 | if (family != 6) | |
1886 | return; | |
1887 | ||
1888 | switch (model) { | |
1889 | case 0x2A: | |
1890 | case 0x3A: | |
70b43400 | 1891 | case 0x3C: /* HSW */ |
70b43400 | 1892 | case 0x45: /* HSW */ |
149c2319 | 1893 | case 0x46: /* HSW */ |
4e8e863f | 1894 | case 0x3D: /* BDW */ |
48a0631c | 1895 | case 0x47: /* BDW */ |
144b44b1 | 1896 | do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; |
889facbe | 1897 | break; |
e6f9bb3c | 1898 | case 0x3F: /* HSX */ |
4e8e863f LB |
1899 | case 0x4F: /* BDX */ |
1900 | case 0x56: /* BDX-DE */ | |
e6f9bb3c LB |
1901 | do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; |
1902 | break; | |
889facbe LB |
1903 | case 0x2D: |
1904 | case 0x3E: | |
144b44b1 LB |
1905 | do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; |
1906 | break; | |
1907 | case 0x37: /* BYT */ | |
1908 | case 0x4D: /* AVN */ | |
1909 | do_rapl = RAPL_PKG | RAPL_CORES ; | |
889facbe LB |
1910 | break; |
1911 | default: | |
1912 | return; | |
1913 | } | |
1914 | ||
1915 | /* units on package 0, verify later other packages match */ | |
1916 | if (get_msr(0, MSR_RAPL_POWER_UNIT, &msr)) | |
1917 | return; | |
1918 | ||
1919 | rapl_power_units = 1.0 / (1 << (msr & 0xF)); | |
144b44b1 LB |
1920 | if (model == 0x37) |
1921 | rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; | |
1922 | else | |
1923 | rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); | |
889facbe | 1924 | |
144b44b1 LB |
1925 | time_unit = msr >> 16 & 0xF; |
1926 | if (time_unit == 0) | |
1927 | time_unit = 0xA; | |
889facbe | 1928 | |
144b44b1 | 1929 | rapl_time_units = 1.0 / (1 << (time_unit)); |
889facbe | 1930 | |
144b44b1 | 1931 | tdp = get_tdp(model); |
889facbe | 1932 | |
144b44b1 | 1933 | rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; |
d8af6f5f | 1934 | if (debug) |
144b44b1 | 1935 | fprintf(stderr, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); |
889facbe LB |
1936 | |
1937 | return; | |
1938 | } | |
1939 | ||
3a9a941d LB |
1940 | void perf_limit_reasons_probe(family, model) |
1941 | { | |
1942 | if (!genuine_intel) | |
1943 | return; | |
1944 | ||
1945 | if (family != 6) | |
1946 | return; | |
1947 | ||
1948 | switch (model) { | |
1949 | case 0x3C: /* HSW */ | |
1950 | case 0x45: /* HSW */ | |
1951 | case 0x46: /* HSW */ | |
1952 | do_gfx_perf_limit_reasons = 1; | |
1953 | case 0x3F: /* HSX */ | |
1954 | do_core_perf_limit_reasons = 1; | |
1955 | do_ring_perf_limit_reasons = 1; | |
1956 | default: | |
1957 | return; | |
1958 | } | |
1959 | } | |
1960 | ||
889facbe LB |
1961 | int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) |
1962 | { | |
1963 | unsigned long long msr; | |
1964 | unsigned int dts; | |
1965 | int cpu; | |
1966 | ||
1967 | if (!(do_dts || do_ptm)) | |
1968 | return 0; | |
1969 | ||
1970 | cpu = t->cpu_id; | |
1971 | ||
1972 | /* DTS is per-core, no need to print for each thread */ | |
1973 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
1974 | return 0; | |
1975 | ||
1976 | if (cpu_migrate(cpu)) { | |
1977 | fprintf(stderr, "Could not migrate to CPU %d\n", cpu); | |
1978 | return -1; | |
1979 | } | |
1980 | ||
1981 | if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { | |
1982 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) | |
1983 | return 0; | |
1984 | ||
1985 | dts = (msr >> 16) & 0x7F; | |
1986 | fprintf(stderr, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", | |
1987 | cpu, msr, tcc_activation_temp - dts); | |
1988 | ||
1989 | #ifdef THERM_DEBUG | |
1990 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) | |
1991 | return 0; | |
1992 | ||
1993 | dts = (msr >> 16) & 0x7F; | |
1994 | dts2 = (msr >> 8) & 0x7F; | |
1995 | fprintf(stderr, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", | |
1996 | cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); | |
1997 | #endif | |
1998 | } | |
1999 | ||
2000 | ||
2001 | if (do_dts) { | |
2002 | unsigned int resolution; | |
2003 | ||
2004 | if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) | |
2005 | return 0; | |
2006 | ||
2007 | dts = (msr >> 16) & 0x7F; | |
2008 | resolution = (msr >> 27) & 0xF; | |
2009 | fprintf(stderr, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", | |
2010 | cpu, msr, tcc_activation_temp - dts, resolution); | |
2011 | ||
2012 | #ifdef THERM_DEBUG | |
2013 | if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) | |
2014 | return 0; | |
2015 | ||
2016 | dts = (msr >> 16) & 0x7F; | |
2017 | dts2 = (msr >> 8) & 0x7F; | |
2018 | fprintf(stderr, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", | |
2019 | cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); | |
2020 | #endif | |
2021 | } | |
2022 | ||
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | void print_power_limit_msr(int cpu, unsigned long long msr, char *label) | |
2027 | { | |
2028 | fprintf(stderr, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", | |
2029 | cpu, label, | |
2030 | ((msr >> 15) & 1) ? "EN" : "DIS", | |
2031 | ((msr >> 0) & 0x7FFF) * rapl_power_units, | |
2032 | (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, | |
2033 | (((msr >> 16) & 1) ? "EN" : "DIS")); | |
2034 | ||
2035 | return; | |
2036 | } | |
2037 | ||
2038 | int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2039 | { | |
2040 | unsigned long long msr; | |
2041 | int cpu; | |
889facbe LB |
2042 | |
2043 | if (!do_rapl) | |
2044 | return 0; | |
2045 | ||
2046 | /* RAPL counters are per package, so print only for 1st thread/package */ | |
2047 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2048 | return 0; | |
2049 | ||
2050 | cpu = t->cpu_id; | |
2051 | if (cpu_migrate(cpu)) { | |
2052 | fprintf(stderr, "Could not migrate to CPU %d\n", cpu); | |
2053 | return -1; | |
2054 | } | |
2055 | ||
2056 | if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) | |
2057 | return -1; | |
2058 | ||
d8af6f5f | 2059 | if (debug) { |
889facbe LB |
2060 | fprintf(stderr, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " |
2061 | "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, | |
144b44b1 | 2062 | rapl_power_units, rapl_energy_units, rapl_time_units); |
889facbe | 2063 | } |
144b44b1 LB |
2064 | if (do_rapl & RAPL_PKG_POWER_INFO) { |
2065 | ||
889facbe LB |
2066 | if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) |
2067 | return -5; | |
2068 | ||
2069 | ||
2070 | fprintf(stderr, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", | |
2071 | cpu, msr, | |
2072 | ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2073 | ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2074 | ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2075 | ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); | |
2076 | ||
144b44b1 LB |
2077 | } |
2078 | if (do_rapl & RAPL_PKG) { | |
2079 | ||
889facbe LB |
2080 | if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) |
2081 | return -9; | |
2082 | ||
2083 | fprintf(stderr, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", | |
2084 | cpu, msr, (msr >> 63) & 1 ? "": "UN"); | |
2085 | ||
2086 | print_power_limit_msr(cpu, msr, "PKG Limit #1"); | |
2087 | fprintf(stderr, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", | |
2088 | cpu, | |
2089 | ((msr >> 47) & 1) ? "EN" : "DIS", | |
2090 | ((msr >> 32) & 0x7FFF) * rapl_power_units, | |
2091 | (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, | |
2092 | ((msr >> 48) & 1) ? "EN" : "DIS"); | |
2093 | } | |
2094 | ||
2095 | if (do_rapl & RAPL_DRAM) { | |
2096 | if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) | |
2097 | return -6; | |
2098 | ||
2099 | ||
2100 | fprintf(stderr, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", | |
2101 | cpu, msr, | |
2102 | ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2103 | ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2104 | ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2105 | ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); | |
2106 | ||
2107 | ||
2108 | if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) | |
2109 | return -9; | |
2110 | fprintf(stderr, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", | |
2111 | cpu, msr, (msr >> 31) & 1 ? "": "UN"); | |
2112 | ||
2113 | print_power_limit_msr(cpu, msr, "DRAM Limit"); | |
2114 | } | |
144b44b1 | 2115 | if (do_rapl & RAPL_CORE_POLICY) { |
d8af6f5f | 2116 | if (debug) { |
889facbe LB |
2117 | if (get_msr(cpu, MSR_PP0_POLICY, &msr)) |
2118 | return -7; | |
2119 | ||
2120 | fprintf(stderr, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); | |
144b44b1 LB |
2121 | } |
2122 | } | |
2123 | if (do_rapl & RAPL_CORES) { | |
d8af6f5f | 2124 | if (debug) { |
889facbe LB |
2125 | |
2126 | if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) | |
2127 | return -9; | |
2128 | fprintf(stderr, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", | |
2129 | cpu, msr, (msr >> 31) & 1 ? "": "UN"); | |
2130 | print_power_limit_msr(cpu, msr, "Cores Limit"); | |
2131 | } | |
2132 | } | |
2133 | if (do_rapl & RAPL_GFX) { | |
d8af6f5f | 2134 | if (debug) { |
889facbe LB |
2135 | if (get_msr(cpu, MSR_PP1_POLICY, &msr)) |
2136 | return -8; | |
2137 | ||
2138 | fprintf(stderr, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); | |
2139 | ||
2140 | if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) | |
2141 | return -9; | |
2142 | fprintf(stderr, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", | |
2143 | cpu, msr, (msr >> 31) & 1 ? "": "UN"); | |
2144 | print_power_limit_msr(cpu, msr, "GFX Limit"); | |
2145 | } | |
2146 | } | |
2147 | return 0; | |
2148 | } | |
2149 | ||
d7899447 LB |
2150 | /* |
2151 | * SNB adds support for additional MSRs: | |
2152 | * | |
2153 | * MSR_PKG_C7_RESIDENCY 0x000003fa | |
2154 | * MSR_CORE_C7_RESIDENCY 0x000003fe | |
2155 | * MSR_PKG_C2_RESIDENCY 0x0000060d | |
2156 | */ | |
103a8fea | 2157 | |
d7899447 | 2158 | int has_snb_msrs(unsigned int family, unsigned int model) |
103a8fea LB |
2159 | { |
2160 | if (!genuine_intel) | |
2161 | return 0; | |
2162 | ||
2163 | switch (model) { | |
2164 | case 0x2A: | |
2165 | case 0x2D: | |
650a37f3 | 2166 | case 0x3A: /* IVB */ |
1300651b | 2167 | case 0x3E: /* IVB Xeon */ |
70b43400 LB |
2168 | case 0x3C: /* HSW */ |
2169 | case 0x3F: /* HSW */ | |
2170 | case 0x45: /* HSW */ | |
149c2319 | 2171 | case 0x46: /* HSW */ |
4e8e863f | 2172 | case 0x3D: /* BDW */ |
48a0631c | 2173 | case 0x47: /* BDW */ |
4e8e863f LB |
2174 | case 0x4F: /* BDX */ |
2175 | case 0x56: /* BDX-DE */ | |
103a8fea LB |
2176 | return 1; |
2177 | } | |
2178 | return 0; | |
2179 | } | |
2180 | ||
d7899447 LB |
2181 | /* |
2182 | * HSW adds support for additional MSRs: | |
2183 | * | |
2184 | * MSR_PKG_C8_RESIDENCY 0x00000630 | |
2185 | * MSR_PKG_C9_RESIDENCY 0x00000631 | |
2186 | * MSR_PKG_C10_RESIDENCY 0x00000632 | |
2187 | */ | |
2188 | int has_hsw_msrs(unsigned int family, unsigned int model) | |
ca58710f KCA |
2189 | { |
2190 | if (!genuine_intel) | |
2191 | return 0; | |
2192 | ||
2193 | switch (model) { | |
4e8e863f LB |
2194 | case 0x45: /* HSW */ |
2195 | case 0x3D: /* BDW */ | |
ca58710f KCA |
2196 | return 1; |
2197 | } | |
2198 | return 0; | |
2199 | } | |
2200 | ||
2201 | ||
144b44b1 LB |
2202 | int is_slm(unsigned int family, unsigned int model) |
2203 | { | |
2204 | if (!genuine_intel) | |
2205 | return 0; | |
2206 | switch (model) { | |
2207 | case 0x37: /* BYT */ | |
2208 | case 0x4D: /* AVN */ | |
2209 | return 1; | |
2210 | } | |
2211 | return 0; | |
2212 | } | |
2213 | ||
2214 | #define SLM_BCLK_FREQS 5 | |
2215 | double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; | |
2216 | ||
2217 | double slm_bclk(void) | |
2218 | { | |
2219 | unsigned long long msr = 3; | |
2220 | unsigned int i; | |
2221 | double freq; | |
2222 | ||
2223 | if (get_msr(0, MSR_FSB_FREQ, &msr)) | |
2224 | fprintf(stderr, "SLM BCLK: unknown\n"); | |
2225 | ||
2226 | i = msr & 0xf; | |
2227 | if (i >= SLM_BCLK_FREQS) { | |
2228 | fprintf(stderr, "SLM BCLK[%d] invalid\n", i); | |
2229 | msr = 3; | |
2230 | } | |
2231 | freq = slm_freq_table[i]; | |
2232 | ||
2233 | fprintf(stderr, "SLM BCLK: %.1f Mhz\n", freq); | |
2234 | ||
2235 | return freq; | |
2236 | } | |
2237 | ||
103a8fea LB |
2238 | double discover_bclk(unsigned int family, unsigned int model) |
2239 | { | |
d7899447 | 2240 | if (has_snb_msrs(family, model)) |
103a8fea | 2241 | return 100.00; |
144b44b1 LB |
2242 | else if (is_slm(family, model)) |
2243 | return slm_bclk(); | |
103a8fea LB |
2244 | else |
2245 | return 133.33; | |
2246 | } | |
2247 | ||
889facbe LB |
2248 | /* |
2249 | * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where | |
2250 | * the Thermal Control Circuit (TCC) activates. | |
2251 | * This is usually equal to tjMax. | |
2252 | * | |
2253 | * Older processors do not have this MSR, so there we guess, | |
2254 | * but also allow cmdline over-ride with -T. | |
2255 | * | |
2256 | * Several MSR temperature values are in units of degrees-C | |
2257 | * below this value, including the Digital Thermal Sensor (DTS), | |
2258 | * Package Thermal Management Sensor (PTM), and thermal event thresholds. | |
2259 | */ | |
2260 | int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2261 | { | |
2262 | unsigned long long msr; | |
2263 | unsigned int target_c_local; | |
2264 | int cpu; | |
2265 | ||
2266 | /* tcc_activation_temp is used only for dts or ptm */ | |
2267 | if (!(do_dts || do_ptm)) | |
2268 | return 0; | |
2269 | ||
2270 | /* this is a per-package concept */ | |
2271 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2272 | return 0; | |
2273 | ||
2274 | cpu = t->cpu_id; | |
2275 | if (cpu_migrate(cpu)) { | |
2276 | fprintf(stderr, "Could not migrate to CPU %d\n", cpu); | |
2277 | return -1; | |
2278 | } | |
2279 | ||
2280 | if (tcc_activation_temp_override != 0) { | |
2281 | tcc_activation_temp = tcc_activation_temp_override; | |
2282 | fprintf(stderr, "cpu%d: Using cmdline TCC Target (%d C)\n", | |
2283 | cpu, tcc_activation_temp); | |
2284 | return 0; | |
2285 | } | |
2286 | ||
2287 | /* Temperature Target MSR is Nehalem and newer only */ | |
d7899447 | 2288 | if (!do_nhm_platform_info) |
889facbe LB |
2289 | goto guess; |
2290 | ||
2291 | if (get_msr(0, MSR_IA32_TEMPERATURE_TARGET, &msr)) | |
2292 | goto guess; | |
2293 | ||
3482124a | 2294 | target_c_local = (msr >> 16) & 0xFF; |
889facbe | 2295 | |
d8af6f5f | 2296 | if (debug) |
889facbe LB |
2297 | fprintf(stderr, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", |
2298 | cpu, msr, target_c_local); | |
2299 | ||
3482124a | 2300 | if (!target_c_local) |
889facbe LB |
2301 | goto guess; |
2302 | ||
2303 | tcc_activation_temp = target_c_local; | |
2304 | ||
2305 | return 0; | |
2306 | ||
2307 | guess: | |
2308 | tcc_activation_temp = TJMAX_DEFAULT; | |
2309 | fprintf(stderr, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", | |
2310 | cpu, tcc_activation_temp); | |
2311 | ||
2312 | return 0; | |
2313 | } | |
fcd17211 | 2314 | void process_cpuid() |
103a8fea LB |
2315 | { |
2316 | unsigned int eax, ebx, ecx, edx, max_level; | |
2317 | unsigned int fms, family, model, stepping; | |
2318 | ||
2319 | eax = ebx = ecx = edx = 0; | |
2320 | ||
2b92865e | 2321 | __get_cpuid(0, &max_level, &ebx, &ecx, &edx); |
103a8fea LB |
2322 | |
2323 | if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) | |
2324 | genuine_intel = 1; | |
2325 | ||
d8af6f5f | 2326 | if (debug) |
889facbe | 2327 | fprintf(stderr, "CPUID(0): %.4s%.4s%.4s ", |
103a8fea LB |
2328 | (char *)&ebx, (char *)&edx, (char *)&ecx); |
2329 | ||
2b92865e | 2330 | __get_cpuid(1, &fms, &ebx, &ecx, &edx); |
103a8fea LB |
2331 | family = (fms >> 8) & 0xf; |
2332 | model = (fms >> 4) & 0xf; | |
2333 | stepping = fms & 0xf; | |
2334 | if (family == 6 || family == 0xf) | |
2335 | model += ((fms >> 16) & 0xf) << 4; | |
2336 | ||
d8af6f5f | 2337 | if (debug) |
103a8fea LB |
2338 | fprintf(stderr, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", |
2339 | max_level, family, model, stepping, family, model, stepping); | |
2340 | ||
b2c95d90 JT |
2341 | if (!(edx & (1 << 5))) |
2342 | errx(1, "CPUID: no MSR"); | |
103a8fea LB |
2343 | |
2344 | /* | |
2345 | * check max extended function levels of CPUID. | |
2346 | * This is needed to check for invariant TSC. | |
2347 | * This check is valid for both Intel and AMD. | |
2348 | */ | |
2349 | ebx = ecx = edx = 0; | |
2b92865e | 2350 | __get_cpuid(0x80000000, &max_level, &ebx, &ecx, &edx); |
103a8fea | 2351 | |
d7899447 | 2352 | if (max_level >= 0x80000007) { |
103a8fea | 2353 | |
d7899447 LB |
2354 | /* |
2355 | * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 | |
2356 | * this check is valid for both Intel and AMD | |
2357 | */ | |
2358 | __get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
2359 | has_invariant_tsc = edx & (1 << 8); | |
2360 | } | |
103a8fea LB |
2361 | |
2362 | /* | |
2363 | * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 | |
2364 | * this check is valid for both Intel and AMD | |
2365 | */ | |
2366 | ||
2b92865e | 2367 | __get_cpuid(0x6, &eax, &ebx, &ecx, &edx); |
8209e054 | 2368 | has_aperf = ecx & (1 << 0); |
889facbe LB |
2369 | do_dts = eax & (1 << 0); |
2370 | do_ptm = eax & (1 << 6); | |
2371 | has_epb = ecx & (1 << 3); | |
2372 | ||
d8af6f5f | 2373 | if (debug) |
a729617c LB |
2374 | fprintf(stderr, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sEPB\n", |
2375 | has_aperf ? "" : "No ", | |
2376 | do_dts ? "" : "No ", | |
2377 | do_ptm ? "" : "No ", | |
2378 | has_epb ? "" : "No "); | |
103a8fea | 2379 | |
ee7e38e3 | 2380 | do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model); |
d7899447 | 2381 | do_snb_cstates = has_snb_msrs(family, model); |
ee7e38e3 LB |
2382 | do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2); |
2383 | do_pc3 = (pkg_cstate_limit >= PCL__3); | |
2384 | do_pc6 = (pkg_cstate_limit >= PCL__6); | |
2385 | do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7); | |
d7899447 | 2386 | do_c8_c9_c10 = has_hsw_msrs(family, model); |
144b44b1 | 2387 | do_slm_cstates = is_slm(family, model); |
103a8fea LB |
2388 | bclk = discover_bclk(family, model); |
2389 | ||
889facbe | 2390 | rapl_probe(family, model); |
3a9a941d | 2391 | perf_limit_reasons_probe(family, model); |
889facbe | 2392 | |
fcd17211 LB |
2393 | if (debug) |
2394 | dump_cstate_pstate_config_info(); | |
2395 | ||
889facbe | 2396 | return; |
103a8fea LB |
2397 | } |
2398 | ||
d8af6f5f | 2399 | void help() |
103a8fea | 2400 | { |
d8af6f5f LB |
2401 | fprintf(stderr, |
2402 | "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" | |
2403 | "\n" | |
2404 | "Turbostat forks the specified COMMAND and prints statistics\n" | |
2405 | "when COMMAND completes.\n" | |
2406 | "If no COMMAND is specified, turbostat wakes every 5-seconds\n" | |
2407 | "to print statistics, until interrupted.\n" | |
2408 | "--debug run in \"debug\" mode\n" | |
2409 | "--interval sec Override default 5-second measurement interval\n" | |
2410 | "--help print this help message\n" | |
2411 | "--counter msr print 32-bit counter at address \"msr\"\n" | |
2412 | "--Counter msr print 64-bit Counter at address \"msr\"\n" | |
2413 | "--msr msr print 32-bit value at address \"msr\"\n" | |
2414 | "--MSR msr print 64-bit Value at address \"msr\"\n" | |
2415 | "--version print version information\n" | |
2416 | "\n" | |
2417 | "For more help, run \"man turbostat\"\n"); | |
103a8fea LB |
2418 | } |
2419 | ||
2420 | ||
2421 | /* | |
2422 | * in /dev/cpu/ return success for names that are numbers | |
2423 | * ie. filter out ".", "..", "microcode". | |
2424 | */ | |
2425 | int dir_filter(const struct dirent *dirp) | |
2426 | { | |
2427 | if (isdigit(dirp->d_name[0])) | |
2428 | return 1; | |
2429 | else | |
2430 | return 0; | |
2431 | } | |
2432 | ||
2433 | int open_dev_cpu_msr(int dummy1) | |
2434 | { | |
2435 | return 0; | |
2436 | } | |
2437 | ||
c98d5d94 LB |
2438 | void topology_probe() |
2439 | { | |
2440 | int i; | |
2441 | int max_core_id = 0; | |
2442 | int max_package_id = 0; | |
2443 | int max_siblings = 0; | |
2444 | struct cpu_topology { | |
2445 | int core_id; | |
2446 | int physical_package_id; | |
2447 | } *cpus; | |
2448 | ||
2449 | /* Initialize num_cpus, max_cpu_num */ | |
2450 | topo.num_cpus = 0; | |
2451 | topo.max_cpu_num = 0; | |
2452 | for_all_proc_cpus(count_cpus); | |
2453 | if (!summary_only && topo.num_cpus > 1) | |
2454 | show_cpu = 1; | |
2455 | ||
d8af6f5f | 2456 | if (debug > 1) |
c98d5d94 LB |
2457 | fprintf(stderr, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); |
2458 | ||
2459 | cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); | |
b2c95d90 JT |
2460 | if (cpus == NULL) |
2461 | err(1, "calloc cpus"); | |
c98d5d94 LB |
2462 | |
2463 | /* | |
2464 | * Allocate and initialize cpu_present_set | |
2465 | */ | |
2466 | cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); | |
b2c95d90 JT |
2467 | if (cpu_present_set == NULL) |
2468 | err(3, "CPU_ALLOC"); | |
c98d5d94 LB |
2469 | cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); |
2470 | CPU_ZERO_S(cpu_present_setsize, cpu_present_set); | |
2471 | for_all_proc_cpus(mark_cpu_present); | |
2472 | ||
2473 | /* | |
2474 | * Allocate and initialize cpu_affinity_set | |
2475 | */ | |
2476 | cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); | |
b2c95d90 JT |
2477 | if (cpu_affinity_set == NULL) |
2478 | err(3, "CPU_ALLOC"); | |
c98d5d94 LB |
2479 | cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); |
2480 | CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); | |
2481 | ||
2482 | ||
2483 | /* | |
2484 | * For online cpus | |
2485 | * find max_core_id, max_package_id | |
2486 | */ | |
2487 | for (i = 0; i <= topo.max_cpu_num; ++i) { | |
2488 | int siblings; | |
2489 | ||
2490 | if (cpu_is_not_present(i)) { | |
d8af6f5f | 2491 | if (debug > 1) |
c98d5d94 LB |
2492 | fprintf(stderr, "cpu%d NOT PRESENT\n", i); |
2493 | continue; | |
2494 | } | |
2495 | cpus[i].core_id = get_core_id(i); | |
2496 | if (cpus[i].core_id > max_core_id) | |
2497 | max_core_id = cpus[i].core_id; | |
2498 | ||
2499 | cpus[i].physical_package_id = get_physical_package_id(i); | |
2500 | if (cpus[i].physical_package_id > max_package_id) | |
2501 | max_package_id = cpus[i].physical_package_id; | |
2502 | ||
2503 | siblings = get_num_ht_siblings(i); | |
2504 | if (siblings > max_siblings) | |
2505 | max_siblings = siblings; | |
d8af6f5f | 2506 | if (debug > 1) |
c98d5d94 LB |
2507 | fprintf(stderr, "cpu %d pkg %d core %d\n", |
2508 | i, cpus[i].physical_package_id, cpus[i].core_id); | |
2509 | } | |
2510 | topo.num_cores_per_pkg = max_core_id + 1; | |
d8af6f5f | 2511 | if (debug > 1) |
c98d5d94 LB |
2512 | fprintf(stderr, "max_core_id %d, sizing for %d cores per package\n", |
2513 | max_core_id, topo.num_cores_per_pkg); | |
1cc21f7b | 2514 | if (debug && !summary_only && topo.num_cores_per_pkg > 1) |
c98d5d94 LB |
2515 | show_core = 1; |
2516 | ||
2517 | topo.num_packages = max_package_id + 1; | |
d8af6f5f | 2518 | if (debug > 1) |
c98d5d94 LB |
2519 | fprintf(stderr, "max_package_id %d, sizing for %d packages\n", |
2520 | max_package_id, topo.num_packages); | |
1cc21f7b | 2521 | if (debug && !summary_only && topo.num_packages > 1) |
c98d5d94 LB |
2522 | show_pkg = 1; |
2523 | ||
2524 | topo.num_threads_per_core = max_siblings; | |
d8af6f5f | 2525 | if (debug > 1) |
c98d5d94 LB |
2526 | fprintf(stderr, "max_siblings %d\n", max_siblings); |
2527 | ||
2528 | free(cpus); | |
2529 | } | |
2530 | ||
2531 | void | |
2532 | allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) | |
2533 | { | |
2534 | int i; | |
2535 | ||
2536 | *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * | |
2537 | topo.num_packages, sizeof(struct thread_data)); | |
2538 | if (*t == NULL) | |
2539 | goto error; | |
2540 | ||
2541 | for (i = 0; i < topo.num_threads_per_core * | |
2542 | topo.num_cores_per_pkg * topo.num_packages; i++) | |
2543 | (*t)[i].cpu_id = -1; | |
2544 | ||
2545 | *c = calloc(topo.num_cores_per_pkg * topo.num_packages, | |
2546 | sizeof(struct core_data)); | |
2547 | if (*c == NULL) | |
2548 | goto error; | |
2549 | ||
2550 | for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) | |
2551 | (*c)[i].core_id = -1; | |
2552 | ||
2553 | *p = calloc(topo.num_packages, sizeof(struct pkg_data)); | |
2554 | if (*p == NULL) | |
2555 | goto error; | |
2556 | ||
2557 | for (i = 0; i < topo.num_packages; i++) | |
2558 | (*p)[i].package_id = i; | |
2559 | ||
2560 | return; | |
2561 | error: | |
b2c95d90 | 2562 | err(1, "calloc counters"); |
c98d5d94 LB |
2563 | } |
2564 | /* | |
2565 | * init_counter() | |
2566 | * | |
2567 | * set cpu_id, core_num, pkg_num | |
2568 | * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE | |
2569 | * | |
2570 | * increment topo.num_cores when 1st core in pkg seen | |
2571 | */ | |
2572 | void init_counter(struct thread_data *thread_base, struct core_data *core_base, | |
2573 | struct pkg_data *pkg_base, int thread_num, int core_num, | |
2574 | int pkg_num, int cpu_id) | |
2575 | { | |
2576 | struct thread_data *t; | |
2577 | struct core_data *c; | |
2578 | struct pkg_data *p; | |
2579 | ||
2580 | t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); | |
2581 | c = GET_CORE(core_base, core_num, pkg_num); | |
2582 | p = GET_PKG(pkg_base, pkg_num); | |
2583 | ||
2584 | t->cpu_id = cpu_id; | |
2585 | if (thread_num == 0) { | |
2586 | t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; | |
2587 | if (cpu_is_first_core_in_package(cpu_id)) | |
2588 | t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; | |
2589 | } | |
2590 | ||
2591 | c->core_id = core_num; | |
2592 | p->package_id = pkg_num; | |
2593 | } | |
2594 | ||
2595 | ||
2596 | int initialize_counters(int cpu_id) | |
2597 | { | |
2598 | int my_thread_id, my_core_id, my_package_id; | |
2599 | ||
2600 | my_package_id = get_physical_package_id(cpu_id); | |
2601 | my_core_id = get_core_id(cpu_id); | |
2602 | ||
2603 | if (cpu_is_first_sibling_in_core(cpu_id)) { | |
2604 | my_thread_id = 0; | |
2605 | topo.num_cores++; | |
2606 | } else { | |
2607 | my_thread_id = 1; | |
2608 | } | |
2609 | ||
2610 | init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); | |
2611 | init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); | |
2612 | return 0; | |
2613 | } | |
2614 | ||
2615 | void allocate_output_buffer() | |
2616 | { | |
3b4d5c7f | 2617 | output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); |
c98d5d94 | 2618 | outp = output_buffer; |
b2c95d90 JT |
2619 | if (outp == NULL) |
2620 | err(-1, "calloc output buffer"); | |
c98d5d94 LB |
2621 | } |
2622 | ||
2623 | void setup_all_buffers(void) | |
2624 | { | |
2625 | topology_probe(); | |
2626 | allocate_counters(&thread_even, &core_even, &package_even); | |
2627 | allocate_counters(&thread_odd, &core_odd, &package_odd); | |
2628 | allocate_output_buffer(); | |
2629 | for_all_proc_cpus(initialize_counters); | |
2630 | } | |
3b4d5c7f | 2631 | |
103a8fea LB |
2632 | void turbostat_init() |
2633 | { | |
103a8fea | 2634 | check_dev_msr(); |
98481e79 | 2635 | check_permissions(); |
fcd17211 | 2636 | process_cpuid(); |
103a8fea | 2637 | |
c98d5d94 | 2638 | setup_all_buffers(); |
103a8fea | 2639 | |
d8af6f5f | 2640 | if (debug) |
889facbe LB |
2641 | for_all_cpus(print_epb, ODD_COUNTERS); |
2642 | ||
d8af6f5f | 2643 | if (debug) |
3a9a941d LB |
2644 | for_all_cpus(print_perf_limit, ODD_COUNTERS); |
2645 | ||
d8af6f5f | 2646 | if (debug) |
889facbe LB |
2647 | for_all_cpus(print_rapl, ODD_COUNTERS); |
2648 | ||
2649 | for_all_cpus(set_temperature_target, ODD_COUNTERS); | |
2650 | ||
d8af6f5f | 2651 | if (debug) |
889facbe | 2652 | for_all_cpus(print_thermal, ODD_COUNTERS); |
103a8fea LB |
2653 | } |
2654 | ||
2655 | int fork_it(char **argv) | |
2656 | { | |
103a8fea | 2657 | pid_t child_pid; |
d91bb17c | 2658 | int status; |
d15cf7c1 | 2659 | |
d91bb17c LB |
2660 | status = for_all_cpus(get_counters, EVEN_COUNTERS); |
2661 | if (status) | |
2662 | exit(status); | |
c98d5d94 LB |
2663 | /* clear affinity side-effect of get_counters() */ |
2664 | sched_setaffinity(0, cpu_present_setsize, cpu_present_set); | |
103a8fea LB |
2665 | gettimeofday(&tv_even, (struct timezone *)NULL); |
2666 | ||
2667 | child_pid = fork(); | |
2668 | if (!child_pid) { | |
2669 | /* child */ | |
2670 | execvp(argv[0], argv); | |
2671 | } else { | |
103a8fea LB |
2672 | |
2673 | /* parent */ | |
b2c95d90 JT |
2674 | if (child_pid == -1) |
2675 | err(1, "fork"); | |
103a8fea LB |
2676 | |
2677 | signal(SIGINT, SIG_IGN); | |
2678 | signal(SIGQUIT, SIG_IGN); | |
b2c95d90 JT |
2679 | if (waitpid(child_pid, &status, 0) == -1) |
2680 | err(status, "waitpid"); | |
103a8fea | 2681 | } |
c98d5d94 LB |
2682 | /* |
2683 | * n.b. fork_it() does not check for errors from for_all_cpus() | |
2684 | * because re-starting is problematic when forking | |
2685 | */ | |
2686 | for_all_cpus(get_counters, ODD_COUNTERS); | |
103a8fea | 2687 | gettimeofday(&tv_odd, (struct timezone *)NULL); |
103a8fea | 2688 | timersub(&tv_odd, &tv_even, &tv_delta); |
c98d5d94 LB |
2689 | for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS); |
2690 | compute_average(EVEN_COUNTERS); | |
2691 | format_all_counters(EVEN_COUNTERS); | |
2692 | flush_stderr(); | |
103a8fea | 2693 | |
6eab04a8 | 2694 | fprintf(stderr, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); |
103a8fea | 2695 | |
d91bb17c | 2696 | return status; |
103a8fea LB |
2697 | } |
2698 | ||
3b4d5c7f AS |
2699 | int get_and_dump_counters(void) |
2700 | { | |
2701 | int status; | |
2702 | ||
2703 | status = for_all_cpus(get_counters, ODD_COUNTERS); | |
2704 | if (status) | |
2705 | return status; | |
2706 | ||
2707 | status = for_all_cpus(dump_counters, ODD_COUNTERS); | |
2708 | if (status) | |
2709 | return status; | |
2710 | ||
2711 | flush_stdout(); | |
2712 | ||
2713 | return status; | |
2714 | } | |
2715 | ||
d8af6f5f | 2716 | void print_version() { |
a21d38c8 | 2717 | fprintf(stderr, "turbostat version 4.3 24 Mar, 2015" |
d8af6f5f LB |
2718 | " - Len Brown <lenb@kernel.org>\n"); |
2719 | } | |
2720 | ||
103a8fea LB |
2721 | void cmdline(int argc, char **argv) |
2722 | { | |
2723 | int opt; | |
d8af6f5f LB |
2724 | int option_index = 0; |
2725 | static struct option long_options[] = { | |
2726 | {"Counter", required_argument, 0, 'C'}, | |
2727 | {"counter", required_argument, 0, 'c'}, | |
2728 | {"Dump", no_argument, 0, 'D'}, | |
2729 | {"debug", no_argument, 0, 'd'}, | |
2730 | {"interval", required_argument, 0, 'i'}, | |
2731 | {"help", no_argument, 0, 'h'}, | |
2732 | {"Joules", no_argument, 0, 'J'}, | |
2733 | {"MSR", required_argument, 0, 'M'}, | |
2734 | {"msr", required_argument, 0, 'm'}, | |
2735 | {"Package", no_argument, 0, 'p'}, | |
2736 | {"processor", no_argument, 0, 'p'}, | |
2737 | {"Summary", no_argument, 0, 'S'}, | |
2738 | {"TCC", required_argument, 0, 'T'}, | |
2739 | {"version", no_argument, 0, 'v' }, | |
2740 | {0, 0, 0, 0 } | |
2741 | }; | |
103a8fea LB |
2742 | |
2743 | progname = argv[0]; | |
2744 | ||
d8af6f5f LB |
2745 | while ((opt = getopt_long_only(argc, argv, "C:c:Ddhi:JM:m:PpST:v", |
2746 | long_options, &option_index)) != -1) { | |
103a8fea | 2747 | switch (opt) { |
d8af6f5f LB |
2748 | case 'C': |
2749 | sscanf(optarg, "%x", &extra_delta_offset64); | |
c98d5d94 | 2750 | break; |
d8af6f5f LB |
2751 | case 'c': |
2752 | sscanf(optarg, "%x", &extra_delta_offset32); | |
c98d5d94 | 2753 | break; |
d8af6f5f | 2754 | case 'D': |
3b4d5c7f AS |
2755 | dump_only++; |
2756 | break; | |
d8af6f5f LB |
2757 | case 'd': |
2758 | debug++; | |
103a8fea | 2759 | break; |
d8af6f5f LB |
2760 | case 'h': |
2761 | default: | |
2762 | help(); | |
2763 | exit(1); | |
103a8fea LB |
2764 | case 'i': |
2765 | interval_sec = atoi(optarg); | |
2766 | break; | |
d8af6f5f LB |
2767 | case 'J': |
2768 | rapl_joules++; | |
8e180f3c | 2769 | break; |
d8af6f5f LB |
2770 | case 'M': |
2771 | sscanf(optarg, "%x", &extra_msr_offset64); | |
8e180f3c | 2772 | break; |
2f32edf1 LB |
2773 | case 'm': |
2774 | sscanf(optarg, "%x", &extra_msr_offset32); | |
2f32edf1 | 2775 | break; |
d8af6f5f LB |
2776 | case 'P': |
2777 | show_pkg_only++; | |
2778 | break; | |
2779 | case 'p': | |
2780 | show_core_only++; | |
103a8fea | 2781 | break; |
d8af6f5f LB |
2782 | case 'S': |
2783 | summary_only++; | |
889facbe LB |
2784 | break; |
2785 | case 'T': | |
2786 | tcc_activation_temp_override = atoi(optarg); | |
2787 | break; | |
d8af6f5f LB |
2788 | case 'v': |
2789 | print_version(); | |
2790 | exit(0); | |
5c56be9a | 2791 | break; |
103a8fea LB |
2792 | } |
2793 | } | |
2794 | } | |
2795 | ||
2796 | int main(int argc, char **argv) | |
2797 | { | |
2798 | cmdline(argc, argv); | |
2799 | ||
d8af6f5f LB |
2800 | if (debug) |
2801 | print_version(); | |
103a8fea LB |
2802 | |
2803 | turbostat_init(); | |
2804 | ||
3b4d5c7f AS |
2805 | /* dump counters and exit */ |
2806 | if (dump_only) | |
2807 | return get_and_dump_counters(); | |
2808 | ||
103a8fea LB |
2809 | /* |
2810 | * if any params left, it must be a command to fork | |
2811 | */ | |
2812 | if (argc - optind) | |
2813 | return fork_it(argv + optind); | |
2814 | else | |
2815 | turbostat_loop(); | |
2816 | ||
2817 | return 0; | |
2818 | } |