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tools/power/turbostat: Remove a redundant check
[linux-block.git] / tools / power / x86 / turbostat / turbostat.c
CommitLineData
a61127c2 1// SPDX-License-Identifier: GPL-2.0-only
103a8fea
LB		 2/*
3 * turbostat -- show CPU frequency and C-state residency
34041551 4 * on modern Intel and AMD processors.
103a8fea 5 *
de7839ee 6 * Copyright (c) 2023 Intel Corporation.
103a8fea 7 * Len Brown <len.brown@intel.com>
103a8fea
LB		 8 */
9
88c3281f 10#define _GNU_SOURCE
b731f311 11#include MSRHEADER
869ce69e 12#include INTEL_FAMILY_HEADER
95aebc44 13#include <stdarg.h>
103a8fea 14#include <stdio.h>
b2c95d90 15#include <err.h>
103a8fea
LB		 16#include <unistd.h>
17#include <sys/types.h>
18#include <sys/wait.h>
19#include <sys/stat.h>
b9ad8ee0 20#include <sys/select.h>
103a8fea
LB		 21#include <sys/resource.h>
22#include <fcntl.h>
23#include <signal.h>
24#include <sys/time.h>
25#include <stdlib.h>
d8af6f5f 26#include <getopt.h>
103a8fea
LB		 27#include <dirent.h>
28#include <string.h>
29#include <ctype.h>
88c3281f 30#include <sched.h>
2a0609c0 31#include <time.h>
2b92865e 32#include <cpuid.h>
fcaa681c 33#include <sys/capability.h>
98481e79 34#include <errno.h>
9392bd98 35#include <math.h>
2af4f9b8
LB		 36#include <linux/perf_event.h>
37#include <asm/unistd.h>
7ab5ff49 38#include <stdbool.h>
103a8fea 39
9878bf7a
LB		 40#define UNUSED(x) (void)(x)
41
164d7a96
LB		 42/*
43 * This list matches the column headers, except
44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
45 * 2. Core and CPU are moved to the end, we can't have strings that contain them
46 * matching on them for --show and --hide.
47 */
48
49/*
50 * buffer size used by sscanf() for added column names
51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
52 */
53#define NAME_BYTES 20
54#define PATH_BYTES 128
55
56enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE };
57enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC };
58enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT };
59
60struct msr_counter {
61 unsigned int msr_num;
62 char name[NAME_BYTES];
63 char path[PATH_BYTES];
64 unsigned int width;
65 enum counter_type type;
66 enum counter_format format;
67 struct msr_counter *next;
68 unsigned int flags;
69#define FLAGS_HIDE (1 << 0)
70#define FLAGS_SHOW (1 << 1)
71#define SYSFS_PERCPU (1 << 1)
72};
73
74struct msr_counter bic[] = {
9878bf7a
LB		 75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 },
76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 },
77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 },
78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 },
79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 },
80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 },
81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 },
82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 },
83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 },
84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 },
85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 },
86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 },
87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 },
88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 },
89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 },
90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 },
91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 },
92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 },
93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 },
94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 },
95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 },
96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 },
97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 },
98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 },
99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 },
100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 },
101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 },
102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 },
103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 },
104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 },
105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 },
106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 },
107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 },
108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 },
109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 },
110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 },
111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 },
112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 },
113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 },
114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 },
115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 },
116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 },
117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 },
118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 },
119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 },
120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 },
121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 },
122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 },
123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 },
124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 },
125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 },
126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 },
127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 },
128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 },
a5c6d65d 129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 },
164d7a96
LB		 130};
131
132#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
133#define BIC_USEC (1ULL << 0)
134#define BIC_TOD (1ULL << 1)
135#define BIC_Package (1ULL << 2)
136#define BIC_Node (1ULL << 3)
137#define BIC_Avg_MHz (1ULL << 4)
138#define BIC_Busy (1ULL << 5)
139#define BIC_Bzy_MHz (1ULL << 6)
140#define BIC_TSC_MHz (1ULL << 7)
141#define BIC_IRQ (1ULL << 8)
142#define BIC_SMI (1ULL << 9)
143#define BIC_sysfs (1ULL << 10)
144#define BIC_CPU_c1 (1ULL << 11)
145#define BIC_CPU_c3 (1ULL << 12)
146#define BIC_CPU_c6 (1ULL << 13)
147#define BIC_CPU_c7 (1ULL << 14)
148#define BIC_ThreadC (1ULL << 15)
149#define BIC_CoreTmp (1ULL << 16)
150#define BIC_CoreCnt (1ULL << 17)
151#define BIC_PkgTmp (1ULL << 18)
152#define BIC_GFX_rc6 (1ULL << 19)
153#define BIC_GFXMHz (1ULL << 20)
154#define BIC_Pkgpc2 (1ULL << 21)
155#define BIC_Pkgpc3 (1ULL << 22)
156#define BIC_Pkgpc6 (1ULL << 23)
157#define BIC_Pkgpc7 (1ULL << 24)
158#define BIC_Pkgpc8 (1ULL << 25)
159#define BIC_Pkgpc9 (1ULL << 26)
160#define BIC_Pkgpc10 (1ULL << 27)
161#define BIC_CPU_LPI (1ULL << 28)
162#define BIC_SYS_LPI (1ULL << 29)
163#define BIC_PkgWatt (1ULL << 30)
164#define BIC_CorWatt (1ULL << 31)
165#define BIC_GFXWatt (1ULL << 32)
166#define BIC_PkgCnt (1ULL << 33)
167#define BIC_RAMWatt (1ULL << 34)
168#define BIC_PKG__ (1ULL << 35)
169#define BIC_RAM__ (1ULL << 36)
170#define BIC_Pkg_J (1ULL << 37)
171#define BIC_Cor_J (1ULL << 38)
172#define BIC_GFX_J (1ULL << 39)
173#define BIC_RAM_J (1ULL << 40)
174#define BIC_Mod_c6 (1ULL << 41)
175#define BIC_Totl_c0 (1ULL << 42)
176#define BIC_Any_c0 (1ULL << 43)
177#define BIC_GFX_c0 (1ULL << 44)
178#define BIC_CPUGFX (1ULL << 45)
179#define BIC_Core (1ULL << 46)
180#define BIC_CPU (1ULL << 47)
181#define BIC_APIC (1ULL << 48)
182#define BIC_X2APIC (1ULL << 49)
183#define BIC_Die (1ULL << 50)
184#define BIC_GFXACTMHz (1ULL << 51)
185#define BIC_IPC (1ULL << 52)
186#define BIC_CORE_THROT_CNT (1ULL << 53)
a5c6d65d 187#define BIC_UNCORE_MHZ (1ULL << 54)
164d7a96
LB		 188
189#define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die )
190#define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__)
a5c6d65d 191#define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ)
164d7a96
LB		 192#define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX)
193#define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC)
194
195#define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
196
197unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
198unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
199
200#define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
201#define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
202#define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
203#define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
204#define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
205#define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT)
206
103a8fea 207char *proc_stat = "/proc/stat";
b7d8c148 208FILE *outf;
36229897 209int *fd_percpu;
2af4f9b8 210int *fd_instr_count_percpu;
1b439f01
LB		 211struct timeval interval_tv = { 5, 0 };
212struct timespec interval_ts = { 5, 0 };
e9d3092f 213
023fe0ac 214unsigned int num_iterations;
c7e399f8 215unsigned int header_iterations;
d8af6f5f 216unsigned int debug;
96e47158 217unsigned int quiet;
3f44a5c6 218unsigned int shown;
0de6c0df 219unsigned int sums_need_wide_columns;
d8af6f5f
LB		 220unsigned int rapl_joules;
221unsigned int summary_only;
c8ade361 222unsigned int list_header_only;
d8af6f5f 223unsigned int dump_only;
103a8fea 224unsigned int do_snb_cstates;
fb5d4327 225unsigned int do_knl_cstates;
144b44b1
LB		 226unsigned int do_slm_cstates;
227unsigned int use_c1_residency_msr;
103a8fea 228unsigned int has_aperf;
889facbe 229unsigned int has_epb;
3ea8e52e 230unsigned int has_turbo;
774627c5 231unsigned int is_hybrid;
5a63426e
LB		 232unsigned int do_irtl_snb;
233unsigned int do_irtl_hsw;
fc04cc67 234unsigned int units = 1000000; /* MHz etc */
103a8fea 235unsigned int genuine_intel;
34041551 236unsigned int authentic_amd;
c1c10cc7 237unsigned int hygon_genuine;
34041551 238unsigned int max_level, max_extended_level;
103a8fea 239unsigned int has_invariant_tsc;
b2b34dfe 240unsigned int aperf_mperf_multiplier = 1;
103a8fea 241double bclk;
a2b7b749 242double base_hz;
21ed5574 243unsigned int has_base_hz;
a2b7b749 244double tsc_tweak = 1.0;
c98d5d94
LB		 245unsigned int show_pkg_only;
246unsigned int show_core_only;
247char *output_buffer, *outp;
889facbe
LB		 248unsigned int do_rapl;
249unsigned int do_dts;
250unsigned int do_ptm;
2af4f9b8 251unsigned int do_ipc;
1b439f01 252unsigned long long gfx_cur_rc6_ms;
be0e54c4
LB		 253unsigned long long cpuidle_cur_cpu_lpi_us;
254unsigned long long cpuidle_cur_sys_lpi_us;
27d47356 255unsigned int gfx_cur_mhz;
b4b91569 256unsigned int gfx_act_mhz;
55279aef
ZR		 257unsigned int tj_max;
258unsigned int tj_max_override;
0b9a0b9b 259int tcc_offset_bits;
40ee8e3b
AS		 260double rapl_power_units, rapl_time_units;
261double rapl_dram_energy_units, rapl_energy_units;
889facbe 262double rapl_joule_counter_range;
3a9a941d 263unsigned int do_core_perf_limit_reasons;
ac980e13 264unsigned int has_automatic_cstate_conversion;
aeb01e6d 265unsigned int dis_cstate_prewake;
3a9a941d
LB		 266unsigned int do_gfx_perf_limit_reasons;
267unsigned int do_ring_perf_limit_reasons;
8a5bdf41
LB		 268unsigned int crystal_hz;
269unsigned long long tsc_hz;
7ce7d5de 270int base_cpu;
1b439f01 271unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
7f5c258e 272 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
1b439f01 273unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
7f5c258e 274unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
1b439f01
LB		 275unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
276unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
4c2122d4 277unsigned int first_counter_read = 1;
c026c236 278int ignore_stdin;
889facbe 279
71e84129
ZR		 280int get_msr(int cpu, off_t offset, unsigned long long *msr);
281
45232ab1
ZR		 282/* Model specific support Start */
283
284/* List of features that may diverge among different platforms */
285struct platform_features {
778fc34a 286 bool has_msr_misc_feature_control; /* MSR_MISC_FEATURE_CONTROL */
3dd0e754 287 bool has_msr_misc_pwr_mgmt; /* MSR_MISC_PWR_MGMT */
fcfa1ce0 288 bool has_nhm_msrs; /* MSR_PLATFORM_INFO, MSR_IA32_TEMPERATURE_TARGET, MSR_SMI_COUNT, MSR_PKG_CST_CONFIG_CONTROL, TRL MSRs */
71e84129 289 int bclk_freq; /* CPU base clock */
3989fc89 290 int cst_limit; /* MSR_PKG_CST_CONFIG_CONTROL */
45232ab1
ZR		 291};
292
293struct platform_data {
294 unsigned int model;
295 const struct platform_features *features;
296};
297
71e84129
ZR		 298/* For BCLK */
299enum bclk_freq {
300 BCLK_100MHZ = 1,
301 BCLK_133MHZ,
302 BCLK_SLV,
303};
304
305#define SLM_BCLK_FREQS 5
306double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 };
307
308double slm_bclk(void)
309{
310 unsigned long long msr = 3;
311 unsigned int i;
312 double freq;
313
314 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
315 fprintf(outf, "SLM BCLK: unknown\n");
316
317 i = msr & 0xf;
318 if (i >= SLM_BCLK_FREQS) {
319 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
320 i = 3;
321 }
322 freq = slm_freq_table[i];
323
324 if (!quiet)
325 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
326
327 return freq;
328}
329
3989fc89
ZR		 330/* For Package cstate limit */
331enum package_cstate_limit {
332 CST_LIMIT_NHM = 1,
333 CST_LIMIT_SNB,
334 CST_LIMIT_HSW,
335 CST_LIMIT_SKX,
336 CST_LIMIT_ICX,
337 CST_LIMIT_SLV,
338 CST_LIMIT_AMT,
339 CST_LIMIT_KNL,
340 CST_LIMIT_GMT,
341};
342
45232ab1 343static const struct platform_features nhm_features = {
3dd0e754 344 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 345 .has_nhm_msrs = 1,
71e84129 346 .bclk_freq = BCLK_133MHZ,
3989fc89 347 .cst_limit = CST_LIMIT_NHM,
45232ab1
ZR		 348};
349
350static const struct platform_features nhx_features = {
3dd0e754 351 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 352 .has_nhm_msrs = 1,
71e84129 353 .bclk_freq = BCLK_133MHZ,
3989fc89 354 .cst_limit = CST_LIMIT_NHM,
45232ab1
ZR		 355};
356
357static const struct platform_features snb_features = {
778fc34a 358 .has_msr_misc_feature_control = 1,
3dd0e754 359 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 360 .has_nhm_msrs = 1,
71e84129 361 .bclk_freq = BCLK_100MHZ,
3989fc89 362 .cst_limit = CST_LIMIT_SNB,
45232ab1
ZR		 363};
364
365static const struct platform_features snx_features = {
778fc34a 366 .has_msr_misc_feature_control = 1,
3dd0e754 367 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 368 .has_nhm_msrs = 1,
71e84129 369 .bclk_freq = BCLK_100MHZ,
3989fc89 370 .cst_limit = CST_LIMIT_SNB,
45232ab1
ZR		 371};
372
373static const struct platform_features ivb_features = {
778fc34a 374 .has_msr_misc_feature_control = 1,
3dd0e754 375 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 376 .has_nhm_msrs = 1,
71e84129 377 .bclk_freq = BCLK_100MHZ,
3989fc89 378 .cst_limit = CST_LIMIT_SNB,
45232ab1
ZR		 379};
380
381static const struct platform_features ivx_features = {
778fc34a 382 .has_msr_misc_feature_control = 1,
3dd0e754 383 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 384 .has_nhm_msrs = 1,
71e84129 385 .bclk_freq = BCLK_100MHZ,
3989fc89 386 .cst_limit = CST_LIMIT_SNB,
45232ab1
ZR		 387};
388
389static const struct platform_features hsw_features = {
778fc34a 390 .has_msr_misc_feature_control = 1,
3dd0e754 391 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 392 .has_nhm_msrs = 1,
71e84129 393 .bclk_freq = BCLK_100MHZ,
3989fc89 394 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 395};
396
397static const struct platform_features hsx_features = {
778fc34a 398 .has_msr_misc_feature_control = 1,
3dd0e754 399 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 400 .has_nhm_msrs = 1,
71e84129 401 .bclk_freq = BCLK_100MHZ,
3989fc89 402 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 403};
404
405static const struct platform_features hswl_features = {
778fc34a 406 .has_msr_misc_feature_control = 1,
3dd0e754 407 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 408 .has_nhm_msrs = 1,
71e84129 409 .bclk_freq = BCLK_100MHZ,
3989fc89 410 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 411};
412
413static const struct platform_features hswg_features = {
778fc34a 414 .has_msr_misc_feature_control = 1,
3dd0e754 415 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 416 .has_nhm_msrs = 1,
71e84129 417 .bclk_freq = BCLK_100MHZ,
3989fc89 418 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 419};
420
421static const struct platform_features bdw_features = {
778fc34a 422 .has_msr_misc_feature_control = 1,
3dd0e754 423 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 424 .has_nhm_msrs = 1,
71e84129 425 .bclk_freq = BCLK_100MHZ,
3989fc89 426 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 427};
428
429static const struct platform_features bdwg_features = {
778fc34a 430 .has_msr_misc_feature_control = 1,
3dd0e754 431 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 432 .has_nhm_msrs = 1,
71e84129 433 .bclk_freq = BCLK_100MHZ,
3989fc89 434 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 435};
436
437static const struct platform_features bdx_features = {
778fc34a 438 .has_msr_misc_feature_control = 1,
3dd0e754 439 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 440 .has_nhm_msrs = 1,
71e84129 441 .bclk_freq = BCLK_100MHZ,
3989fc89 442 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 443};
444
445static const struct platform_features skl_features = {
778fc34a 446 .has_msr_misc_feature_control = 1,
3dd0e754 447 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 448 .has_nhm_msrs = 1,
71e84129 449 .bclk_freq = BCLK_100MHZ,
3989fc89 450 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 451};
452
453static const struct platform_features cnl_features = {
778fc34a 454 .has_msr_misc_feature_control = 1,
3dd0e754 455 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 456 .has_nhm_msrs = 1,
71e84129 457 .bclk_freq = BCLK_100MHZ,
3989fc89 458 .cst_limit = CST_LIMIT_HSW,
45232ab1
ZR		 459};
460
461static const struct platform_features skx_features = {
778fc34a 462 .has_msr_misc_feature_control = 1,
3dd0e754 463 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 464 .has_nhm_msrs = 1,
71e84129 465 .bclk_freq = BCLK_100MHZ,
3989fc89 466 .cst_limit = CST_LIMIT_SKX,
45232ab1
ZR		 467};
468
469static const struct platform_features icx_features = {
778fc34a 470 .has_msr_misc_feature_control = 1,
3dd0e754 471 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 472 .has_nhm_msrs = 1,
71e84129 473 .bclk_freq = BCLK_100MHZ,
3989fc89 474 .cst_limit = CST_LIMIT_ICX,
45232ab1
ZR		 475};
476
477static const struct platform_features spr_features = {
778fc34a 478 .has_msr_misc_feature_control = 1,
3dd0e754 479 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 480 .has_nhm_msrs = 1,
71e84129 481 .bclk_freq = BCLK_100MHZ,
3989fc89 482 .cst_limit = CST_LIMIT_SKX,
45232ab1
ZR		 483};
484
485static const struct platform_features slv_features = {
fcfa1ce0 486 .has_nhm_msrs = 1,
71e84129 487 .bclk_freq = BCLK_SLV,
3989fc89 488 .cst_limit = CST_LIMIT_SLV,
45232ab1
ZR		 489};
490
491static const struct platform_features slvd_features = {
3dd0e754 492 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 493 .has_nhm_msrs = 1,
71e84129 494 .bclk_freq = BCLK_SLV,
3989fc89 495 .cst_limit = CST_LIMIT_SLV,
45232ab1
ZR		 496};
497
498static const struct platform_features amt_features = {
fcfa1ce0 499 .has_nhm_msrs = 1,
71e84129 500 .bclk_freq = BCLK_133MHZ,
3989fc89 501 .cst_limit = CST_LIMIT_AMT,
45232ab1
ZR		 502};
503
504static const struct platform_features gmt_features = {
3dd0e754 505 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 506 .has_nhm_msrs = 1,
71e84129 507 .bclk_freq = BCLK_100MHZ,
3989fc89 508 .cst_limit = CST_LIMIT_GMT,
45232ab1
ZR		 509};
510
511static const struct platform_features gmtd_features = {
3dd0e754 512 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 513 .has_nhm_msrs = 1,
71e84129 514 .bclk_freq = BCLK_100MHZ,
3989fc89 515 .cst_limit = CST_LIMIT_GMT,
45232ab1
ZR		 516};
517
518static const struct platform_features gmtp_features = {
3dd0e754 519 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 520 .has_nhm_msrs = 1,
71e84129 521 .bclk_freq = BCLK_100MHZ,
3989fc89 522 .cst_limit = CST_LIMIT_GMT,
45232ab1
ZR		 523};
524
525static const struct platform_features tmt_features = {
3dd0e754 526 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 527 .has_nhm_msrs = 1,
71e84129 528 .bclk_freq = BCLK_100MHZ,
3989fc89 529 .cst_limit = CST_LIMIT_GMT,
45232ab1
ZR		 530};
531
532static const struct platform_features tmtd_features = {
3dd0e754 533 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 534 .has_nhm_msrs = 1,
71e84129 535 .bclk_freq = BCLK_100MHZ,
3989fc89 536 .cst_limit = CST_LIMIT_GMT,
45232ab1
ZR		 537};
538
539static const struct platform_features knl_features = {
3dd0e754 540 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 541 .has_nhm_msrs = 1,
71e84129 542 .bclk_freq = BCLK_100MHZ,
3989fc89 543 .cst_limit = CST_LIMIT_KNL,
45232ab1
ZR		 544};
545
546static const struct platform_features default_features = {
547};
548
549static const struct platform_features amd_features = {
550};
551
552static const struct platform_data turbostat_pdata[] = {
553 { INTEL_FAM6_NEHALEM, &nhm_features },
554 { INTEL_FAM6_NEHALEM_G, &nhm_features },
555 { INTEL_FAM6_NEHALEM_EP, &nhm_features },
556 { INTEL_FAM6_NEHALEM_EX, &nhx_features },
557 { INTEL_FAM6_WESTMERE, &nhm_features },
558 { INTEL_FAM6_WESTMERE_EP, &nhm_features },
559 { INTEL_FAM6_WESTMERE_EX, &nhx_features },
560 { INTEL_FAM6_SANDYBRIDGE, &snb_features },
561 { INTEL_FAM6_SANDYBRIDGE_X, &snx_features },
562 { INTEL_FAM6_IVYBRIDGE, &ivb_features },
563 { INTEL_FAM6_IVYBRIDGE_X, &ivx_features },
564 { INTEL_FAM6_HASWELL, &hsw_features },
565 { INTEL_FAM6_HASWELL_X, &hsx_features },
566 { INTEL_FAM6_HASWELL_L, &hswl_features },
567 { INTEL_FAM6_HASWELL_G, &hswg_features },
568 { INTEL_FAM6_BROADWELL, &bdw_features },
569 { INTEL_FAM6_BROADWELL_G, &bdwg_features },
570 { INTEL_FAM6_BROADWELL_X, &bdx_features },
571 { INTEL_FAM6_BROADWELL_D, &bdx_features },
572 { INTEL_FAM6_SKYLAKE_L, &skl_features },
573 { INTEL_FAM6_SKYLAKE, &skl_features },
574 { INTEL_FAM6_SKYLAKE_X, &skx_features },
575 { INTEL_FAM6_KABYLAKE_L, &skl_features },
576 { INTEL_FAM6_KABYLAKE, &skl_features },
577 { INTEL_FAM6_COMETLAKE, &skl_features },
578 { INTEL_FAM6_COMETLAKE_L, &skl_features },
579 { INTEL_FAM6_CANNONLAKE_L, &cnl_features },
580 { INTEL_FAM6_ICELAKE_X, &icx_features },
581 { INTEL_FAM6_ICELAKE_D, &icx_features },
582 { INTEL_FAM6_ICELAKE_L, &cnl_features },
583 { INTEL_FAM6_ICELAKE_NNPI, &cnl_features },
584 { INTEL_FAM6_ROCKETLAKE, &cnl_features },
585 { INTEL_FAM6_TIGERLAKE_L, &cnl_features },
586 { INTEL_FAM6_TIGERLAKE, &cnl_features },
587 { INTEL_FAM6_SAPPHIRERAPIDS_X, &spr_features },
588 { INTEL_FAM6_EMERALDRAPIDS_X, &spr_features },
589 { INTEL_FAM6_LAKEFIELD, &cnl_features },
590 { INTEL_FAM6_ALDERLAKE, &cnl_features },
591 { INTEL_FAM6_ALDERLAKE_L, &cnl_features },
592 { INTEL_FAM6_RAPTORLAKE, &cnl_features },
593 { INTEL_FAM6_RAPTORLAKE_P, &cnl_features },
594 { INTEL_FAM6_RAPTORLAKE_S, &cnl_features },
595 { INTEL_FAM6_METEORLAKE, &cnl_features },
596 { INTEL_FAM6_METEORLAKE_L, &cnl_features },
597 { INTEL_FAM6_ATOM_SILVERMONT, &slv_features },
598 { INTEL_FAM6_ATOM_SILVERMONT_D, &slvd_features },
599 { INTEL_FAM6_ATOM_AIRMONT, &amt_features },
600 { INTEL_FAM6_ATOM_GOLDMONT, &gmt_features },
601 { INTEL_FAM6_ATOM_GOLDMONT_D, &gmtd_features },
602 { INTEL_FAM6_ATOM_GOLDMONT_PLUS, &gmtp_features },
603 { INTEL_FAM6_ATOM_TREMONT_D, &tmtd_features },
604 { INTEL_FAM6_ATOM_TREMONT, &tmt_features },
605 { INTEL_FAM6_ATOM_TREMONT_L, &tmt_features },
606 { INTEL_FAM6_ATOM_GRACEMONT, &cnl_features },
607 { INTEL_FAM6_XEON_PHI_KNL, &knl_features },
608 { INTEL_FAM6_XEON_PHI_KNM, &knl_features },
609 /*
610 * Missing support for
611 * INTEL_FAM6_ICELAKE
612 * INTEL_FAM6_ATOM_SILVERMONT_MID
613 * INTEL_FAM6_ATOM_AIRMONT_MID
614 * INTEL_FAM6_ATOM_AIRMONT_NP
615 */
616 { 0, NULL },
617};
618
619static const struct platform_features *platform;
620
621void probe_platform_features(unsigned int family, unsigned int model)
622{
623 int i;
624
625 if (authentic_amd || hygon_genuine) {
626 platform = &amd_features;
627 return;
628 }
629
630 platform = &default_features;
631
632 if (!genuine_intel || family != 6)
633 return;
634
635 for (i = 0; turbostat_pdata[i].features; i++) {
636 if (turbostat_pdata[i].model == model) {
637 platform = turbostat_pdata[i].features;
638 return;
639 }
640 }
641}
642
643/* Model specific support End */
644
e6f9bb3c
LB		 645#define RAPL_PKG (1 << 0)
646 /* 0x610 MSR_PKG_POWER_LIMIT */
647 /* 0x611 MSR_PKG_ENERGY_STATUS */
648#define RAPL_PKG_PERF_STATUS (1 << 1)
649 /* 0x613 MSR_PKG_PERF_STATUS */
650#define RAPL_PKG_POWER_INFO (1 << 2)
651 /* 0x614 MSR_PKG_POWER_INFO */
652
653#define RAPL_DRAM (1 << 3)
654 /* 0x618 MSR_DRAM_POWER_LIMIT */
655 /* 0x619 MSR_DRAM_ENERGY_STATUS */
e6f9bb3c
LB		 656#define RAPL_DRAM_PERF_STATUS (1 << 4)
657 /* 0x61b MSR_DRAM_PERF_STATUS */
0b2bb692
LB		 658#define RAPL_DRAM_POWER_INFO (1 << 5)
659 /* 0x61c MSR_DRAM_POWER_INFO */
e6f9bb3c 660
9148494c 661#define RAPL_CORES_POWER_LIMIT (1 << 6)
e6f9bb3c 662 /* 0x638 MSR_PP0_POWER_LIMIT */
0b2bb692 663#define RAPL_CORE_POLICY (1 << 7)
e6f9bb3c
LB		 664 /* 0x63a MSR_PP0_POLICY */
665
0b2bb692 666#define RAPL_GFX (1 << 8)
e6f9bb3c
LB		 667 /* 0x640 MSR_PP1_POWER_LIMIT */
668 /* 0x641 MSR_PP1_ENERGY_STATUS */
669 /* 0x642 MSR_PP1_POLICY */
9148494c
JP		 670
671#define RAPL_CORES_ENERGY_STATUS (1 << 9)
672 /* 0x639 MSR_PP0_ENERGY_STATUS */
9392bd98
CW		 673#define RAPL_PER_CORE_ENERGY (1 << 10)
674 /* Indicates cores energy collection is per-core,
675 * not per-package. */
676#define RAPL_AMD_F17H (1 << 11)
677 /* 0xc0010299 MSR_RAPL_PWR_UNIT */
678 /* 0xc001029a MSR_CORE_ENERGY_STAT */
679 /* 0xc001029b MSR_PKG_ENERGY_STAT */
9148494c 680#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
889facbe
LB		 681#define TJMAX_DEFAULT 100
682
9392bd98
CW		 683/* MSRs that are not yet in the kernel-provided header. */
684#define MSR_RAPL_PWR_UNIT 0xc0010299
685#define MSR_CORE_ENERGY_STAT 0xc001029a
686#define MSR_PKG_ENERGY_STAT 0xc001029b
687
889facbe 688#define MAX(a, b) ((a) > (b) ? (a) : (b))
103a8fea 689
103a8fea
LB		 690int backwards_count;
691char *progname;
103a8fea 692
1ef7d21a
LB		 693#define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
694cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
695size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
0748eaf0
LB		 696#define MAX_ADDED_COUNTERS 8
697#define MAX_ADDED_THREAD_COUNTERS 24
0e2d8f05 698#define BITMASK_SIZE 32
c98d5d94
LB		 699
700struct thread_data {
f4fdf2b4
LB		 701 struct timeval tv_begin;
702 struct timeval tv_end;
d4794f25 703 struct timeval tv_delta;
c98d5d94
LB		 704 unsigned long long tsc;
705 unsigned long long aperf;
706 unsigned long long mperf;
144b44b1 707 unsigned long long c1;
2af4f9b8 708 unsigned long long instr_count;
1b439f01 709 unsigned long long irq_count;
1ed51011 710 unsigned int smi_count;
c98d5d94 711 unsigned int cpu_id;
4c2122d4
LB		 712 unsigned int apic_id;
713 unsigned int x2apic_id;
c98d5d94 714 unsigned int flags;
7ab5ff49 715 bool is_atom;
c98d5d94
LB		 716#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
717#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
0748eaf0 718 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
c98d5d94
LB		 719} *thread_even, *thread_odd;
720
721struct core_data {
722 unsigned long long c3;
723 unsigned long long c6;
724 unsigned long long c7;
0539ba11 725 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
889facbe 726 unsigned int core_temp_c;
9392bd98 727 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
c98d5d94 728 unsigned int core_id;
eae97e05 729 unsigned long long core_throt_cnt;
678a3bd1 730 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 731} *core_even, *core_odd;
732
733struct pkg_data {
734 unsigned long long pc2;
735 unsigned long long pc3;
736 unsigned long long pc6;
737 unsigned long long pc7;
ca58710f
KCA		 738 unsigned long long pc8;
739 unsigned long long pc9;
740 unsigned long long pc10;
be0e54c4
LB		 741 unsigned long long cpu_lpi;
742 unsigned long long sys_lpi;
0b2bb692
LB		 743 unsigned long long pkg_wtd_core_c0;
744 unsigned long long pkg_any_core_c0;
745 unsigned long long pkg_any_gfxe_c0;
746 unsigned long long pkg_both_core_gfxe_c0;
9185e988 747 long long gfx_rc6_ms;
27d47356 748 unsigned int gfx_mhz;
b4b91569 749 unsigned int gfx_act_mhz;
c98d5d94 750 unsigned int package_id;
7c2ccc50
CY		 751 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */
752 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */
753 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */
754 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */
755 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
756 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
889facbe 757 unsigned int pkg_temp_c;
a5c6d65d 758 unsigned int uncore_mhz;
678a3bd1 759 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 760} *package_even, *package_odd;
761
762#define ODD_COUNTERS thread_odd, core_odd, package_odd
763#define EVEN_COUNTERS thread_even, core_even, package_even
764
40f5cfe7
PB		 765#define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
766 ((thread_base) + \
767 ((pkg_no) * \
768 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
769 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
770 ((core_no) * topo.threads_per_core) + \
771 (thread_no))
772
773#define GET_CORE(core_base, core_no, node_no, pkg_no) \
774 ((core_base) + \
775 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
776 ((node_no) * topo.cores_per_node) + \
777 (core_no))
778
c98d5d94
LB		 779#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
780
87e15da9
CY		 781/*
782 * The accumulated sum of MSR is defined as a monotonic
783 * increasing MSR, it will be accumulated periodically,
784 * despite its register's bit width.
785 */
786enum {
787 IDX_PKG_ENERGY,
788 IDX_DRAM_ENERGY,
789 IDX_PP0_ENERGY,
790 IDX_PP1_ENERGY,
791 IDX_PKG_PERF,
792 IDX_DRAM_PERF,
793 IDX_COUNT,
794};
795
796int get_msr_sum(int cpu, off_t offset, unsigned long long *msr);
797
798struct msr_sum_array {
799 /* get_msr_sum() = sum + (get_msr() - last) */
800 struct {
1b439f01 801 /*The accumulated MSR value is updated by the timer */
87e15da9 802 unsigned long long sum;
1b439f01 803 /*The MSR footprint recorded in last timer */
87e15da9
CY		 804 unsigned long long last;
805 } entries[IDX_COUNT];
806};
807
808/* The percpu MSR sum array.*/
809struct msr_sum_array *per_cpu_msr_sum;
810
13a779de 811off_t idx_to_offset(int idx)
87e15da9 812{
13a779de 813 off_t offset;
87e15da9
CY		 814
815 switch (idx) {
816 case IDX_PKG_ENERGY:
301b1d3a
BN		 817 if (do_rapl & RAPL_AMD_F17H)
818 offset = MSR_PKG_ENERGY_STAT;
819 else
820 offset = MSR_PKG_ENERGY_STATUS;
87e15da9
CY		 821 break;
822 case IDX_DRAM_ENERGY:
823 offset = MSR_DRAM_ENERGY_STATUS;
824 break;
825 case IDX_PP0_ENERGY:
826 offset = MSR_PP0_ENERGY_STATUS;
827 break;
828 case IDX_PP1_ENERGY:
829 offset = MSR_PP1_ENERGY_STATUS;
830 break;
831 case IDX_PKG_PERF:
832 offset = MSR_PKG_PERF_STATUS;
833 break;
834 case IDX_DRAM_PERF:
835 offset = MSR_DRAM_PERF_STATUS;
836 break;
837 default:
838 offset = -1;
839 }
840 return offset;
841}
842
13a779de 843int offset_to_idx(off_t offset)
87e15da9
CY		 844{
845 int idx;
846
847 switch (offset) {
848 case MSR_PKG_ENERGY_STATUS:
301b1d3a 849 case MSR_PKG_ENERGY_STAT:
87e15da9
CY		 850 idx = IDX_PKG_ENERGY;
851 break;
852 case MSR_DRAM_ENERGY_STATUS:
853 idx = IDX_DRAM_ENERGY;
854 break;
855 case MSR_PP0_ENERGY_STATUS:
856 idx = IDX_PP0_ENERGY;
857 break;
858 case MSR_PP1_ENERGY_STATUS:
859 idx = IDX_PP1_ENERGY;
860 break;
861 case MSR_PKG_PERF_STATUS:
862 idx = IDX_PKG_PERF;
863 break;
864 case MSR_DRAM_PERF_STATUS:
865 idx = IDX_DRAM_PERF;
866 break;
867 default:
868 idx = -1;
869 }
870 return idx;
871}
872
873int idx_valid(int idx)
874{
875 switch (idx) {
876 case IDX_PKG_ENERGY:
301b1d3a 877 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H);
87e15da9
CY		 878 case IDX_DRAM_ENERGY:
879 return do_rapl & RAPL_DRAM;
880 case IDX_PP0_ENERGY:
881 return do_rapl & RAPL_CORES_ENERGY_STATUS;
882 case IDX_PP1_ENERGY:
883 return do_rapl & RAPL_GFX;
884 case IDX_PKG_PERF:
885 return do_rapl & RAPL_PKG_PERF_STATUS;
886 case IDX_DRAM_PERF:
887 return do_rapl & RAPL_DRAM_PERF_STATUS;
888 default:
889 return 0;
890 }
891}
1b439f01 892
388e9c81 893struct sys_counters {
678a3bd1
LB		 894 unsigned int added_thread_counters;
895 unsigned int added_core_counters;
896 unsigned int added_package_counters;
388e9c81
LB		 897 struct msr_counter *tp;
898 struct msr_counter *cp;
899 struct msr_counter *pp;
900} sys;
901
c98d5d94
LB		 902struct system_summary {
903 struct thread_data threads;
904 struct core_data cores;
905 struct pkg_data packages;
388e9c81 906} average;
c98d5d94 907
0e2d8f05
LB		 908struct cpu_topology {
909 int physical_package_id;
6de68fe1 910 int die_id;
0e2d8f05 911 int logical_cpu_id;
ef605741
PB		 912 int physical_node_id;
913 int logical_node_id; /* 0-based count within the package */
0e2d8f05 914 int physical_core_id;
8cb48b32 915 int thread_id;
1b439f01 916 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
0e2d8f05 917} *cpus;
c98d5d94
LB		 918
919struct topo_params {
920 int num_packages;
6de68fe1 921 int num_die;
c98d5d94
LB		 922 int num_cpus;
923 int num_cores;
924 int max_cpu_num;
ef605741 925 int max_node_num;
70a9c6e8
PB		 926 int nodes_per_pkg;
927 int cores_per_node;
928 int threads_per_core;
c98d5d94
LB		 929} topo;
930
931struct timeval tv_even, tv_odd, tv_delta;
932
1b439f01 933int *irq_column_2_cpu; /* /proc/interrupts column numbers */
562a2d37
LB		 934int *irqs_per_cpu; /* indexed by cpu_num */
935
c98d5d94
LB		 936void setup_all_buffers(void);
937
1f81c5ef
LB		 938char *sys_lpi_file;
939char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
940char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
941
c98d5d94 942int cpu_is_not_present(int cpu)
d15cf7c1 943{
c98d5d94 944 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
d15cf7c1 945}
1b439f01 946
88c3281f 947/*
c98d5d94
LB		 948 * run func(thread, core, package) in topology order
949 * skip non-present cpus
88c3281f 950 */
c98d5d94 951
1b439f01
LB		 952int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *),
953 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
88c3281f 954{
40f5cfe7 955 int retval, pkg_no, core_no, thread_no, node_no;
d15cf7c1 956
c98d5d94 957 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
df2f677d
LB		 958 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
959 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
1b439f01 960 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
40f5cfe7
PB		 961 struct thread_data *t;
962 struct core_data *c;
963 struct pkg_data *p;
964
1b439f01 965 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
40f5cfe7
PB		 966
967 if (cpu_is_not_present(t->cpu_id))
968 continue;
969
1b439f01 970 c = GET_CORE(core_base, core_no, node_no, pkg_no);
40f5cfe7
PB		 971 p = GET_PKG(pkg_base, pkg_no);
972
973 retval = func(t, c, p);
974 if (retval)
975 return retval;
976 }
c98d5d94
LB		 977 }
978 }
979 }
980 return 0;
88c3281f
LB		 981}
982
983int cpu_migrate(int cpu)
984{
c98d5d94
LB		 985 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
986 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
987 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
88c3281f
LB		 988 return -1;
989 else
990 return 0;
991}
1b439f01 992
36229897 993int get_msr_fd(int cpu)
103a8fea 994{
103a8fea
LB		 995 char pathname[32];
996 int fd;
997
36229897
LB		 998 fd = fd_percpu[cpu];
999
1000 if (fd)
1001 return fd;
1002
103a8fea
LB		 1003 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
1004 fd = open(pathname, O_RDONLY);
15aaa346 1005 if (fd < 0)
98481e79 1006 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
103a8fea 1007
36229897
LB		 1008 fd_percpu[cpu] = fd;
1009
1010 return fd;
1011}
1012
2af4f9b8
LB		 1013static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
1014{
1015 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags);
1016}
1017
1018static int perf_instr_count_open(int cpu_num)
1019{
1020 struct perf_event_attr pea;
1021 int fd;
1022
1023 memset(&pea, 0, sizeof(struct perf_event_attr));
1024 pea.type = PERF_TYPE_HARDWARE;
1025 pea.size = sizeof(struct perf_event_attr);
1026 pea.config = PERF_COUNT_HW_INSTRUCTIONS;
1027
1028 /* counter for cpu_num, including user + kernel and all processes */
1029 fd = perf_event_open(&pea, -1, cpu_num, -1, 0);
164d7a96 1030 if (fd == -1) {
de7839ee 1031 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
164d7a96
LB		 1032 BIC_NOT_PRESENT(BIC_IPC);
1033 }
2af4f9b8
LB		 1034
1035 return fd;
1036}
1037
1038int get_instr_count_fd(int cpu)
1039{
1040 if (fd_instr_count_percpu[cpu])
1041 return fd_instr_count_percpu[cpu];
1042
1043 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu);
1044
1045 return fd_instr_count_percpu[cpu];
1046}
1047
36229897
LB		 1048int get_msr(int cpu, off_t offset, unsigned long long *msr)
1049{
1050 ssize_t retval;
1051
1052 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
15aaa346 1053
98481e79 1054 if (retval != sizeof *msr)
cf4cbe53 1055 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
15aaa346
LB		 1056
1057 return 0;
103a8fea
LB		 1058}
1059
dd778a5e 1060#define MAX_DEFERRED 16
0fc521bc 1061char *deferred_add_names[MAX_DEFERRED];
dd778a5e 1062char *deferred_skip_names[MAX_DEFERRED];
0fc521bc 1063int deferred_add_index;
dd778a5e
LB		 1064int deferred_skip_index;
1065
1066/*
1067 * HIDE_LIST - hide this list of counters, show the rest [default]
1068 * SHOW_LIST - show this list of counters, hide the rest
1069 */
1070enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
1071
1072void help(void)
1073{
1074 fprintf(outf,
1b439f01
LB		 1075 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
1076 "\n"
1077 "Turbostat forks the specified COMMAND and prints statistics\n"
1078 "when COMMAND completes.\n"
1079 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
1080 "to print statistics, until interrupted.\n"
1081 " -a, --add add a counter\n"
1082 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
1083 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
1084 " {core | package | j,k,l..m,n-p }\n"
1085 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
1086 " -D, --Dump displays the raw counter values\n"
1087 " -e, --enable [all | column]\n"
1088 " shows all or the specified disabled column\n"
1089 " -H, --hide [column|column,column,...]\n"
1090 " hide the specified column(s)\n"
1091 " -i, --interval sec.subsec\n"
1092 " Override default 5-second measurement interval\n"
1093 " -J, --Joules displays energy in Joules instead of Watts\n"
1094 " -l, --list list column headers only\n"
1095 " -n, --num_iterations num\n"
1096 " number of the measurement iterations\n"
c7e399f8
ZLCH		 1097 " -N, --header_iterations num\n"
1098 " print header every num iterations\n"
1b439f01
LB		 1099 " -o, --out file\n"
1100 " create or truncate \"file\" for all output\n"
1101 " -q, --quiet skip decoding system configuration header\n"
1102 " -s, --show [column|column,column,...]\n"
1103 " show only the specified column(s)\n"
1104 " -S, --Summary\n"
1105 " limits output to 1-line system summary per interval\n"
1106 " -T, --TCC temperature\n"
1107 " sets the Thermal Control Circuit temperature in\n"
1108 " degrees Celsius\n"
1109 " -h, --help print this help message\n"
1110 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n");
dd778a5e
LB		 1111}
1112
812db3f7
LB		 1113/*
1114 * bic_lookup
1115 * for all the strings in comma separate name_list,
1116 * set the approprate bit in return value.
1117 */
dd778a5e 1118unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
812db3f7 1119{
9878bf7a 1120 unsigned int i;
812db3f7
LB		 1121 unsigned long long retval = 0;
1122
1123 while (name_list) {
1124 char *comma;
1125
1126 comma = strchr(name_list, ',');
1127
1128 if (comma)
1129 *comma = '\0';
1130
1131 for (i = 0; i < MAX_BIC; ++i) {
1132 if (!strcmp(name_list, bic[i].name)) {
1133 retval |= (1ULL << i);
1134 break;
1135 }
5dc241f2
LB		 1136 if (!strcmp(name_list, "all")) {
1137 retval |= ~0;
1138 break;
1139 } else if (!strcmp(name_list, "topology")) {
1140 retval |= BIC_TOPOLOGY;
1141 break;
1142 } else if (!strcmp(name_list, "power")) {
1143 retval |= BIC_THERMAL_PWR;
1144 break;
1145 } else if (!strcmp(name_list, "idle")) {
1146 retval |= BIC_IDLE;
1147 break;
1148 } else if (!strcmp(name_list, "frequency")) {
1149 retval |= BIC_FREQUENCY;
1150 break;
1151 } else if (!strcmp(name_list, "other")) {
1152 retval |= BIC_OTHER;
1153 break;
1154 }
1155
812db3f7
LB		 1156 }
1157 if (i == MAX_BIC) {
dd778a5e 1158 if (mode == SHOW_LIST) {
0fc521bc
ZLCH		 1159 deferred_add_names[deferred_add_index++] = name_list;
1160 if (deferred_add_index >= MAX_DEFERRED) {
1161 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n",
164d7a96 1162 MAX_DEFERRED, name_list);
0fc521bc
ZLCH		 1163 help();
1164 exit(1);
1165 }
1166 } else {
1167 deferred_skip_names[deferred_skip_index++] = name_list;
1168 if (debug)
1169 fprintf(stderr, "deferred \"%s\"\n", name_list);
1170 if (deferred_skip_index >= MAX_DEFERRED) {
1171 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
164d7a96 1172 MAX_DEFERRED, name_list);
0fc521bc
ZLCH		 1173 help();
1174 exit(1);
1175 }
dd778a5e 1176 }
812db3f7
LB		 1177 }
1178
1179 name_list = comma;
1180 if (name_list)
1181 name_list++;
1182
1183 }
1184 return retval;
1185}
fc04cc67 1186
c8ade361 1187void print_header(char *delim)
103a8fea 1188{
388e9c81 1189 struct msr_counter *mp;
6168c2e0 1190 int printed = 0;
388e9c81 1191
3f44a5c6
LB		 1192 if (DO_BIC(BIC_USEC))
1193 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
1194 if (DO_BIC(BIC_TOD))
1195 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
812db3f7 1196 if (DO_BIC(BIC_Package))
6168c2e0 1197 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
6de68fe1
LB		 1198 if (DO_BIC(BIC_Die))
1199 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
01235041
PB		 1200 if (DO_BIC(BIC_Node))
1201 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
812db3f7 1202 if (DO_BIC(BIC_Core))
6168c2e0 1203 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
812db3f7 1204 if (DO_BIC(BIC_CPU))
6168c2e0 1205 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
4c2122d4
LB		 1206 if (DO_BIC(BIC_APIC))
1207 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
1208 if (DO_BIC(BIC_X2APIC))
1209 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
812db3f7 1210 if (DO_BIC(BIC_Avg_MHz))
6168c2e0 1211 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
812db3f7 1212 if (DO_BIC(BIC_Busy))
6168c2e0 1213 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
812db3f7 1214 if (DO_BIC(BIC_Bzy_MHz))
6168c2e0 1215 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
812db3f7 1216 if (DO_BIC(BIC_TSC_MHz))
6168c2e0 1217 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
1cc21f7b 1218
2af4f9b8
LB		 1219 if (DO_BIC(BIC_IPC))
1220 outp += sprintf(outp, "%sIPC", (printed++ ? delim : ""));
1221
0de6c0df
LB		 1222 if (DO_BIC(BIC_IRQ)) {
1223 if (sums_need_wide_columns)
6168c2e0 1224 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
0de6c0df 1225 else
6168c2e0 1226 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
0de6c0df
LB		 1227 }
1228
812db3f7 1229 if (DO_BIC(BIC_SMI))
6168c2e0 1230 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
1cc21f7b 1231
388e9c81 1232 for (mp = sys.tp; mp; mp = mp->next) {
dd778a5e 1233
388e9c81
LB		 1234 if (mp->format == FORMAT_RAW) {
1235 if (mp->width == 64)
dd778a5e 1236 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
388e9c81 1237 else
dd778a5e 1238 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
388e9c81 1239 } else {
0de6c0df 1240 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
dd778a5e 1241 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
0de6c0df 1242 else
dd778a5e 1243 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
388e9c81
LB		 1244 }
1245 }
1246
41618e63 1247 if (DO_BIC(BIC_CPU_c1))
6168c2e0 1248 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
562855ee 1249 if (DO_BIC(BIC_CPU_c3))
6168c2e0 1250 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
812db3f7 1251 if (DO_BIC(BIC_CPU_c6))
6168c2e0 1252 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
812db3f7 1253 if (DO_BIC(BIC_CPU_c7))
6168c2e0 1254 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
678a3bd1 1255
0539ba11 1256 if (DO_BIC(BIC_Mod_c6))
6168c2e0 1257 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
678a3bd1 1258
812db3f7 1259 if (DO_BIC(BIC_CoreTmp))
6168c2e0 1260 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
388e9c81 1261
eae97e05
CY		 1262 if (DO_BIC(BIC_CORE_THROT_CNT))
1263 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : ""));
1264
9392bd98
CW		 1265 if (do_rapl && !rapl_joules) {
1266 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1267 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
1268 } else if (do_rapl && rapl_joules) {
1269 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1270 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
1271 }
1272
388e9c81
LB		 1273 for (mp = sys.cp; mp; mp = mp->next) {
1274 if (mp->format == FORMAT_RAW) {
1275 if (mp->width == 64)
c8ade361 1276 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
388e9c81 1277 else
c8ade361 1278 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
388e9c81 1279 } else {
0de6c0df
LB		 1280 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1281 outp += sprintf(outp, "%s%8s", delim, mp->name);
1282 else
1283 outp += sprintf(outp, "%s%s", delim, mp->name);
388e9c81
LB		 1284 }
1285 }
1286
812db3f7 1287 if (DO_BIC(BIC_PkgTmp))
6168c2e0 1288 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
889facbe 1289
812db3f7 1290 if (DO_BIC(BIC_GFX_rc6))
6168c2e0 1291 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
fdf676e5 1292
812db3f7 1293 if (DO_BIC(BIC_GFXMHz))
6168c2e0 1294 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
27d47356 1295
b4b91569
RA		 1296 if (DO_BIC(BIC_GFXACTMHz))
1297 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : ""));
1298
a99d8730 1299 if (DO_BIC(BIC_Totl_c0))
6168c2e0 1300 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
a99d8730 1301 if (DO_BIC(BIC_Any_c0))
6168c2e0 1302 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
a99d8730 1303 if (DO_BIC(BIC_GFX_c0))
6168c2e0 1304 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
a99d8730 1305 if (DO_BIC(BIC_CPUGFX))
6168c2e0 1306 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
0b2bb692 1307
0f47c08d 1308 if (DO_BIC(BIC_Pkgpc2))
6168c2e0 1309 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
0f47c08d 1310 if (DO_BIC(BIC_Pkgpc3))
6168c2e0 1311 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
0f47c08d 1312 if (DO_BIC(BIC_Pkgpc6))
6168c2e0 1313 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
0f47c08d 1314 if (DO_BIC(BIC_Pkgpc7))
6168c2e0 1315 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
0f47c08d 1316 if (DO_BIC(BIC_Pkgpc8))
6168c2e0 1317 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
0f47c08d 1318 if (DO_BIC(BIC_Pkgpc9))
6168c2e0 1319 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
0f47c08d 1320 if (DO_BIC(BIC_Pkgpc10))
6168c2e0 1321 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
be0e54c4
LB		 1322 if (DO_BIC(BIC_CPU_LPI))
1323 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
1324 if (DO_BIC(BIC_SYS_LPI))
1325 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
103a8fea 1326
5c56be9a 1327 if (do_rapl && !rapl_joules) {
812db3f7 1328 if (DO_BIC(BIC_PkgWatt))
6168c2e0 1329 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
9392bd98 1330 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 1331 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
812db3f7 1332 if (DO_BIC(BIC_GFXWatt))
6168c2e0 1333 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
812db3f7 1334 if (DO_BIC(BIC_RAMWatt))
6168c2e0 1335 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
812db3f7 1336 if (DO_BIC(BIC_PKG__))
6168c2e0 1337 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
812db3f7 1338 if (DO_BIC(BIC_RAM__))
6168c2e0 1339 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
d7899447 1340 } else if (do_rapl && rapl_joules) {
812db3f7 1341 if (DO_BIC(BIC_Pkg_J))
6168c2e0 1342 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
9392bd98 1343 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 1344 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
812db3f7 1345 if (DO_BIC(BIC_GFX_J))
6168c2e0 1346 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
812db3f7 1347 if (DO_BIC(BIC_RAM_J))
6168c2e0 1348 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
812db3f7 1349 if (DO_BIC(BIC_PKG__))
6168c2e0 1350 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
812db3f7 1351 if (DO_BIC(BIC_RAM__))
6168c2e0 1352 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
5c56be9a 1353 }
a5c6d65d
LB		 1354 if (DO_BIC(BIC_UNCORE_MHZ))
1355 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : ""));
1356
388e9c81
LB		 1357 for (mp = sys.pp; mp; mp = mp->next) {
1358 if (mp->format == FORMAT_RAW) {
1359 if (mp->width == 64)
c8ade361 1360 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
388e9c81 1361 else
c8ade361 1362 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
388e9c81 1363 } else {
0de6c0df
LB		 1364 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1365 outp += sprintf(outp, "%s%8s", delim, mp->name);
1366 else
1367 outp += sprintf(outp, "%s%s", delim, mp->name);
388e9c81
LB		 1368 }
1369 }
1370
c98d5d94 1371 outp += sprintf(outp, "\n");
103a8fea
LB		 1372}
1373
1b439f01 1374int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1375{
388e9c81
LB		 1376 int i;
1377 struct msr_counter *mp;
1378
3b4d5c7f 1379 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
c98d5d94
LB		 1380
1381 if (t) {
1b439f01 1382 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags);
3b4d5c7f
AS		 1383 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
1384 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
1385 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
1386 outp += sprintf(outp, "c1: %016llX\n", t->c1);
6886fee4 1387
2af4f9b8
LB		 1388 if (DO_BIC(BIC_IPC))
1389 outp += sprintf(outp, "IPC: %lld\n", t->instr_count);
1390
812db3f7 1391 if (DO_BIC(BIC_IRQ))
0de6c0df 1392 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
812db3f7 1393 if (DO_BIC(BIC_SMI))
218f0e8d 1394 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
388e9c81
LB		 1395
1396 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1b439f01 1397 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]);
388e9c81 1398 }
c98d5d94 1399 }
103a8fea 1400
c98d5d94 1401 if (c) {
3b4d5c7f
AS		 1402 outp += sprintf(outp, "core: %d\n", c->core_id);
1403 outp += sprintf(outp, "c3: %016llX\n", c->c3);
1404 outp += sprintf(outp, "c6: %016llX\n", c->c6);
1405 outp += sprintf(outp, "c7: %016llX\n", c->c7);
1406 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
eae97e05 1407 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt);
9392bd98 1408 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
388e9c81
LB		 1409
1410 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1b439f01 1411 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]);
388e9c81 1412 }
0539ba11 1413 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
c98d5d94 1414 }
103a8fea 1415
c98d5d94 1416 if (p) {
3b4d5c7f 1417 outp += sprintf(outp, "package: %d\n", p->package_id);
0b2bb692
LB		 1418
1419 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
1420 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
1421 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
1422 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
1423
3b4d5c7f 1424 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
0f47c08d 1425 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1426 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
0f47c08d 1427 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1428 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
0f47c08d 1429 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1430 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
3b4d5c7f
AS		 1431 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
1432 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
1433 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
be0e54c4
LB		 1434 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
1435 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
7c2ccc50
CY		 1436 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg);
1437 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores);
1438 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx);
1439 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram);
1b439f01
LB		 1440 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status);
1441 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status);
3b4d5c7f 1442 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
388e9c81
LB		 1443
1444 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1b439f01 1445 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]);
388e9c81 1446 }
c98d5d94 1447 }
3b4d5c7f
AS		 1448
1449 outp += sprintf(outp, "\n");
1450
c98d5d94 1451 return 0;
103a8fea
LB		 1452}
1453
e23da037
LB		 1454/*
1455 * column formatting convention & formats
e23da037 1456 */
1b439f01 1457int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1458{
008d396e 1459 double interval_float, tsc;
fc04cc67 1460 char *fmt8;
388e9c81
LB		 1461 int i;
1462 struct msr_counter *mp;
6168c2e0
LB		 1463 char *delim = "\t";
1464 int printed = 0;
103a8fea 1465
1b439f01 1466 /* if showing only 1st thread in core and this isn't one, bail out */
c98d5d94
LB		 1467 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1468 return 0;
1469
1b439f01 1470 /* if showing only 1st thread in pkg and this isn't one, bail out */
c98d5d94
LB		 1471 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1472 return 0;
1473
1ef7d21a 1474 /*if not summary line and --cpu is used */
1b439f01 1475 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
1ef7d21a
LB		 1476 return 0;
1477
3f44a5c6 1478 if (DO_BIC(BIC_USEC)) {
f4fdf2b4
LB		 1479 /* on each row, print how many usec each timestamp took to gather */
1480 struct timeval tv;
1481
1482 timersub(&t->tv_end, &t->tv_begin, &tv);
1483 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
1484 }
1485
3f44a5c6
LB		 1486 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
1487 if (DO_BIC(BIC_TOD))
1488 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
1489
1b439f01 1490 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0;
103a8fea 1491
008d396e
LB		 1492 tsc = t->tsc * tsc_tweak;
1493
c98d5d94
LB		 1494 /* topo columns, print blanks on 1st (average) line */
1495 if (t == &average.threads) {
812db3f7 1496 if (DO_BIC(BIC_Package))
6168c2e0 1497 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
6de68fe1
LB		 1498 if (DO_BIC(BIC_Die))
1499 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
01235041
PB		 1500 if (DO_BIC(BIC_Node))
1501 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
812db3f7 1502 if (DO_BIC(BIC_Core))
6168c2e0 1503 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
812db3f7 1504 if (DO_BIC(BIC_CPU))
6168c2e0 1505 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
4c2122d4
LB		 1506 if (DO_BIC(BIC_APIC))
1507 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1508 if (DO_BIC(BIC_X2APIC))
1509 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
103a8fea 1510 } else {
812db3f7 1511 if (DO_BIC(BIC_Package)) {
c98d5d94 1512 if (p)
6168c2e0 1513 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
c98d5d94 1514 else
6168c2e0 1515 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
c98d5d94 1516 }
6de68fe1
LB		 1517 if (DO_BIC(BIC_Die)) {
1518 if (c)
1519 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
1520 else
1521 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1522 }
01235041
PB		 1523 if (DO_BIC(BIC_Node)) {
1524 if (t)
1525 outp += sprintf(outp, "%s%d",
1b439f01 1526 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id);
01235041 1527 else
1b439f01 1528 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
01235041 1529 }
812db3f7 1530 if (DO_BIC(BIC_Core)) {
c98d5d94 1531 if (c)
6168c2e0 1532 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
c98d5d94 1533 else
6168c2e0 1534 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
c98d5d94 1535 }
812db3f7 1536 if (DO_BIC(BIC_CPU))
6168c2e0 1537 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
4c2122d4
LB		 1538 if (DO_BIC(BIC_APIC))
1539 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
1540 if (DO_BIC(BIC_X2APIC))
1541 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
103a8fea 1542 }
fc04cc67 1543
812db3f7 1544 if (DO_BIC(BIC_Avg_MHz))
1b439f01 1545 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float);
fc04cc67 1546
812db3f7 1547 if (DO_BIC(BIC_Busy))
1b439f01 1548 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc);
103a8fea 1549
812db3f7 1550 if (DO_BIC(BIC_Bzy_MHz)) {
21ed5574 1551 if (has_base_hz)
1b439f01
LB		 1552 outp +=
1553 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
21ed5574 1554 else
6168c2e0 1555 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
1b439f01 1556 tsc / units * t->aperf / t->mperf / interval_float);
21ed5574 1557 }
103a8fea 1558
812db3f7 1559 if (DO_BIC(BIC_TSC_MHz))
1b439f01 1560 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float);
103a8fea 1561
2af4f9b8
LB		 1562 if (DO_BIC(BIC_IPC))
1563 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf);
1564
562a2d37 1565 /* IRQ */
0de6c0df
LB		 1566 if (DO_BIC(BIC_IRQ)) {
1567 if (sums_need_wide_columns)
6168c2e0 1568 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
0de6c0df 1569 else
6168c2e0 1570 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
0de6c0df 1571 }
562a2d37 1572
1cc21f7b 1573 /* SMI */
812db3f7 1574 if (DO_BIC(BIC_SMI))
6168c2e0 1575 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1cc21f7b 1576
678a3bd1 1577 /* Added counters */
388e9c81
LB		 1578 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1579 if (mp->format == FORMAT_RAW) {
1580 if (mp->width == 32)
1b439f01
LB		 1581 outp +=
1582 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]);
388e9c81 1583 else
6168c2e0 1584 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
388e9c81 1585 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1586 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1587 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
0de6c0df 1588 else
6168c2e0 1589 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
388e9c81 1590 } else if (mp->format == FORMAT_PERCENT) {
41618e63 1591 if (mp->type == COUNTER_USEC)
1b439f01
LB		 1592 outp +=
1593 sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1594 t->counter[i] / interval_float / 10000);
41618e63 1595 else
1b439f01 1596 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc);
388e9c81
LB		 1597 }
1598 }
1599
41618e63
LB		 1600 /* C1 */
1601 if (DO_BIC(BIC_CPU_c1))
1b439f01 1602 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc);
41618e63 1603
678a3bd1
LB		 1604 /* print per-core data only for 1st thread in core */
1605 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1606 goto done;
1607
562855ee 1608 if (DO_BIC(BIC_CPU_c3))
1b439f01 1609 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc);
812db3f7 1610 if (DO_BIC(BIC_CPU_c6))
1b439f01 1611 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc);
812db3f7 1612 if (DO_BIC(BIC_CPU_c7))
1b439f01 1613 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc);
678a3bd1 1614
0539ba11
LB		 1615 /* Mod%c6 */
1616 if (DO_BIC(BIC_Mod_c6))
6168c2e0 1617 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
0539ba11 1618
812db3f7 1619 if (DO_BIC(BIC_CoreTmp))
6168c2e0 1620 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
889facbe 1621
eae97e05
CY		 1622 /* Core throttle count */
1623 if (DO_BIC(BIC_CORE_THROT_CNT))
1624 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt);
1625
388e9c81
LB		 1626 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1627 if (mp->format == FORMAT_RAW) {
1628 if (mp->width == 32)
1b439f01
LB		 1629 outp +=
1630 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]);
388e9c81 1631 else
6168c2e0 1632 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
388e9c81 1633 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1634 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1635 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
0de6c0df 1636 else
6168c2e0 1637 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
388e9c81 1638 } else if (mp->format == FORMAT_PERCENT) {
1b439f01 1639 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc);
388e9c81
LB		 1640 }
1641 }
1642
9972d5d8 1643 fmt8 = "%s%.2f";
9392bd98
CW		 1644
1645 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1b439f01
LB		 1646 outp +=
1647 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
9392bd98
CW		 1648 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1649 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1650
c98d5d94
LB		 1651 /* print per-package data only for 1st core in package */
1652 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1653 goto done;
1654
0b2bb692 1655 /* PkgTmp */
812db3f7 1656 if (DO_BIC(BIC_PkgTmp))
6168c2e0 1657 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
889facbe 1658
fdf676e5 1659 /* GFXrc6 */
812db3f7 1660 if (DO_BIC(BIC_GFX_rc6)) {
ba3dec99 1661 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
6168c2e0 1662 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
9185e988 1663 } else {
6168c2e0 1664 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1b439f01 1665 p->gfx_rc6_ms / 10.0 / interval_float);
9185e988
LB		 1666 }
1667 }
fdf676e5 1668
27d47356 1669 /* GFXMHz */
812db3f7 1670 if (DO_BIC(BIC_GFXMHz))
6168c2e0 1671 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
27d47356 1672
b4b91569
RA		 1673 /* GFXACTMHz */
1674 if (DO_BIC(BIC_GFXACTMHz))
1675 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz);
1676
0b2bb692 1677 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
a99d8730 1678 if (DO_BIC(BIC_Totl_c0))
1b439f01 1679 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc);
a99d8730 1680 if (DO_BIC(BIC_Any_c0))
1b439f01 1681 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc);
a99d8730 1682 if (DO_BIC(BIC_GFX_c0))
1b439f01 1683 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc);
a99d8730 1684 if (DO_BIC(BIC_CPUGFX))
1b439f01 1685 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc);
0b2bb692 1686
0f47c08d 1687 if (DO_BIC(BIC_Pkgpc2))
1b439f01 1688 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc);
0f47c08d 1689 if (DO_BIC(BIC_Pkgpc3))
1b439f01 1690 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc);
0f47c08d 1691 if (DO_BIC(BIC_Pkgpc6))
1b439f01 1692 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc);
0f47c08d 1693 if (DO_BIC(BIC_Pkgpc7))
1b439f01 1694 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc);
0f47c08d 1695 if (DO_BIC(BIC_Pkgpc8))
1b439f01 1696 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc);
0f47c08d 1697 if (DO_BIC(BIC_Pkgpc9))
1b439f01 1698 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc);
0f47c08d 1699 if (DO_BIC(BIC_Pkgpc10))
1b439f01 1700 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc);
889facbe 1701
be0e54c4 1702 if (DO_BIC(BIC_CPU_LPI))
1b439f01
LB		 1703 outp +=
1704 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
be0e54c4 1705 if (DO_BIC(BIC_SYS_LPI))
1b439f01
LB		 1706 outp +=
1707 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
be0e54c4 1708
812db3f7 1709 if (DO_BIC(BIC_PkgWatt))
1b439f01
LB		 1710 outp +=
1711 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
eae97e05 1712
9392bd98 1713 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1b439f01
LB		 1714 outp +=
1715 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
812db3f7 1716 if (DO_BIC(BIC_GFXWatt))
1b439f01
LB		 1717 outp +=
1718 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
812db3f7 1719 if (DO_BIC(BIC_RAMWatt))
1b439f01
LB		 1720 outp +=
1721 sprintf(outp, fmt8, (printed++ ? delim : ""),
1722 p->energy_dram * rapl_dram_energy_units / interval_float);
812db3f7 1723 if (DO_BIC(BIC_Pkg_J))
6168c2e0 1724 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
9392bd98 1725 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 1726 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
812db3f7 1727 if (DO_BIC(BIC_GFX_J))
6168c2e0 1728 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
812db3f7 1729 if (DO_BIC(BIC_RAM_J))
6168c2e0 1730 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
812db3f7 1731 if (DO_BIC(BIC_PKG__))
1b439f01
LB		 1732 outp +=
1733 sprintf(outp, fmt8, (printed++ ? delim : ""),
1734 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
812db3f7 1735 if (DO_BIC(BIC_RAM__))
1b439f01
LB		 1736 outp +=
1737 sprintf(outp, fmt8, (printed++ ? delim : ""),
1738 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
a5c6d65d
LB		 1739 /* UncMHz */
1740 if (DO_BIC(BIC_UNCORE_MHZ))
1741 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz);
812db3f7 1742
388e9c81
LB		 1743 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1744 if (mp->format == FORMAT_RAW) {
1745 if (mp->width == 32)
1b439f01
LB		 1746 outp +=
1747 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]);
388e9c81 1748 else
6168c2e0 1749 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
388e9c81 1750 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1751 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1752 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
0de6c0df 1753 else
6168c2e0 1754 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
388e9c81 1755 } else if (mp->format == FORMAT_PERCENT) {
1b439f01 1756 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc);
388e9c81
LB		 1757 }
1758 }
1759
c98d5d94 1760done:
94d6ab4b
LB		 1761 if (*(outp - 1) != '\n')
1762 outp += sprintf(outp, "\n");
c98d5d94
LB		 1763
1764 return 0;
103a8fea
LB		 1765}
1766
b7d8c148 1767void flush_output_stdout(void)
c98d5d94 1768{
b7d8c148
LB		 1769 FILE *filep;
1770
1771 if (outf == stderr)
1772 filep = stdout;
1773 else
1774 filep = outf;
1775
1776 fputs(output_buffer, filep);
1777 fflush(filep);
1778
c98d5d94
LB		 1779 outp = output_buffer;
1780}
1b439f01 1781
b7d8c148 1782void flush_output_stderr(void)
c98d5d94 1783{
b7d8c148
LB		 1784 fputs(output_buffer, outf);
1785 fflush(outf);
c98d5d94
LB		 1786 outp = output_buffer;
1787}
1b439f01 1788
c98d5d94 1789void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1790{
c7e399f8 1791 static int count;
103a8fea 1792
c7e399f8 1793 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only)
c8ade361 1794 print_header("\t");
103a8fea 1795
9d83601a 1796 format_counters(&average.threads, &average.cores, &average.packages);
103a8fea 1797
c7e399f8 1798 count++;
e23da037
LB		 1799
1800 if (summary_only)
1801 return;
1802
c98d5d94 1803 for_all_cpus(format_counters, t, c, p);
103a8fea
LB		 1804}
1805
889facbe 1806#define DELTA_WRAP32(new, old) \
7c2ccc50 1807 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32);
889facbe 1808
1b439f01 1809int delta_package(struct pkg_data *new, struct pkg_data *old)
c98d5d94 1810{
388e9c81
LB		 1811 int i;
1812 struct msr_counter *mp;
0b2bb692 1813
a99d8730 1814 if (DO_BIC(BIC_Totl_c0))
0b2bb692 1815 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
a99d8730 1816 if (DO_BIC(BIC_Any_c0))
0b2bb692 1817 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
a99d8730 1818 if (DO_BIC(BIC_GFX_c0))
0b2bb692 1819 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
a99d8730 1820 if (DO_BIC(BIC_CPUGFX))
0b2bb692 1821 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
a99d8730 1822
c98d5d94 1823 old->pc2 = new->pc2 - old->pc2;
0f47c08d 1824 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1825 old->pc3 = new->pc3 - old->pc3;
0f47c08d 1826 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1827 old->pc6 = new->pc6 - old->pc6;
0f47c08d 1828 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1829 old->pc7 = new->pc7 - old->pc7;
ca58710f
KCA		 1830 old->pc8 = new->pc8 - old->pc8;
1831 old->pc9 = new->pc9 - old->pc9;
1832 old->pc10 = new->pc10 - old->pc10;
be0e54c4
LB		 1833 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
1834 old->sys_lpi = new->sys_lpi - old->sys_lpi;
889facbe
LB		 1835 old->pkg_temp_c = new->pkg_temp_c;
1836
9185e988 1837 /* flag an error when rc6 counter resets/wraps */
1b439f01 1838 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
9185e988
LB		 1839 old->gfx_rc6_ms = -1;
1840 else
1841 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1842
a5c6d65d 1843 old->uncore_mhz = new->uncore_mhz;
27d47356 1844 old->gfx_mhz = new->gfx_mhz;
b4b91569 1845 old->gfx_act_mhz = new->gfx_act_mhz;
27d47356 1846
87e15da9
CY		 1847 old->energy_pkg = new->energy_pkg - old->energy_pkg;
1848 old->energy_cores = new->energy_cores - old->energy_cores;
1849 old->energy_gfx = new->energy_gfx - old->energy_gfx;
1850 old->energy_dram = new->energy_dram - old->energy_dram;
1851 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status;
1852 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status;
ba3dec99 1853
388e9c81
LB		 1854 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1855 if (mp->format == FORMAT_RAW)
1856 old->counter[i] = new->counter[i];
1857 else
1858 old->counter[i] = new->counter[i] - old->counter[i];
1859 }
1860
ba3dec99 1861 return 0;
c98d5d94 1862}
103a8fea 1863
1b439f01 1864void delta_core(struct core_data *new, struct core_data *old)
103a8fea 1865{
388e9c81
LB		 1866 int i;
1867 struct msr_counter *mp;
1868
c98d5d94
LB		 1869 old->c3 = new->c3 - old->c3;
1870 old->c6 = new->c6 - old->c6;
1871 old->c7 = new->c7 - old->c7;
889facbe 1872 old->core_temp_c = new->core_temp_c;
eae97e05 1873 old->core_throt_cnt = new->core_throt_cnt;
0539ba11 1874 old->mc6_us = new->mc6_us - old->mc6_us;
388e9c81 1875
9392bd98
CW		 1876 DELTA_WRAP32(new->core_energy, old->core_energy);
1877
388e9c81
LB		 1878 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1879 if (mp->format == FORMAT_RAW)
1880 old->counter[i] = new->counter[i];
1881 else
1882 old->counter[i] = new->counter[i] - old->counter[i];
1883 }
c98d5d94 1884}
103a8fea 1885
1e9042b9
SP		 1886int soft_c1_residency_display(int bic)
1887{
1888 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr)
1889 return 0;
1890
1891 return DO_BIC_READ(bic);
1892}
1893
c3ae331d
LB		 1894/*
1895 * old = new - old
1896 */
1b439f01 1897int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta)
c98d5d94 1898{
388e9c81
LB		 1899 int i;
1900 struct msr_counter *mp;
1901
4c2122d4
LB		 1902 /* we run cpuid just the 1st time, copy the results */
1903 if (DO_BIC(BIC_APIC))
1904 new->apic_id = old->apic_id;
1905 if (DO_BIC(BIC_X2APIC))
1906 new->x2apic_id = old->x2apic_id;
1907
3f44a5c6
LB		 1908 /*
1909 * the timestamps from start of measurement interval are in "old"
1910 * the timestamp from end of measurement interval are in "new"
1911 * over-write old w/ new so we can print end of interval values
1912 */
1913
d4794f25 1914 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
3f44a5c6
LB		 1915 old->tv_begin = new->tv_begin;
1916 old->tv_end = new->tv_end;
1917
c98d5d94
LB		 1918 old->tsc = new->tsc - old->tsc;
1919
1920 /* check for TSC < 1 Mcycles over interval */
b2c95d90
JT		 1921 if (old->tsc < (1000 * 1000))
1922 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1923 "You can disable all c-states by booting with \"idle=poll\"\n"
1924 "or just the deep ones with \"processor.max_cstate=1\"");
103a8fea 1925
c98d5d94 1926 old->c1 = new->c1 - old->c1;
103a8fea 1927
1b439f01 1928 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
a729617c
LB		 1929 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1930 old->aperf = new->aperf - old->aperf;
1931 old->mperf = new->mperf - old->mperf;
1932 } else {
ba3dec99 1933 return -1;
103a8fea 1934 }
c98d5d94 1935 }
103a8fea 1936
144b44b1
LB		 1937 if (use_c1_residency_msr) {
1938 /*
1939 * Some models have a dedicated C1 residency MSR,
1940 * which should be more accurate than the derivation below.
1941 */
1942 } else {
1943 /*
1944 * As counter collection is not atomic,
1945 * it is possible for mperf's non-halted cycles + idle states
1946 * to exceed TSC's all cycles: show c1 = 0% in that case.
1947 */
95149369 1948 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
144b44b1
LB		 1949 old->c1 = 0;
1950 else {
1951 /* normal case, derive c1 */
008d396e 1952 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1b439f01 1953 - core_delta->c6 - core_delta->c7;
144b44b1 1954 }
c98d5d94 1955 }
c3ae331d 1956
c98d5d94 1957 if (old->mperf == 0) {
b7d8c148
LB		 1958 if (debug > 1)
1959 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
c98d5d94 1960 old->mperf = 1; /* divide by 0 protection */
103a8fea 1961 }
c98d5d94 1962
2af4f9b8
LB		 1963 if (DO_BIC(BIC_IPC))
1964 old->instr_count = new->instr_count - old->instr_count;
1965
812db3f7 1966 if (DO_BIC(BIC_IRQ))
562a2d37
LB		 1967 old->irq_count = new->irq_count - old->irq_count;
1968
812db3f7 1969 if (DO_BIC(BIC_SMI))
1ed51011 1970 old->smi_count = new->smi_count - old->smi_count;
ba3dec99 1971
388e9c81
LB		 1972 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1973 if (mp->format == FORMAT_RAW)
1974 old->counter[i] = new->counter[i];
1975 else
1976 old->counter[i] = new->counter[i] - old->counter[i];
1977 }
ba3dec99 1978 return 0;
c98d5d94
LB		 1979}
1980
1981int delta_cpu(struct thread_data *t, struct core_data *c,
1b439f01 1982 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2)
c98d5d94 1983{
ba3dec99
LB		 1984 int retval = 0;
1985
c98d5d94
LB		 1986 /* calculate core delta only for 1st thread in core */
1987 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1988 delta_core(c, c2);
1989
1990 /* always calculate thread delta */
ba3dec99
LB		 1991 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1992 if (retval)
1993 return retval;
c98d5d94
LB		 1994
1995 /* calculate package delta only for 1st core in package */
1996 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
ba3dec99 1997 retval = delta_package(p, p2);
c98d5d94 1998
ba3dec99 1999 return retval;
103a8fea
LB		 2000}
2001
c98d5d94
LB		 2002void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2003{
388e9c81 2004 int i;
1b439f01 2005 struct msr_counter *mp;
388e9c81 2006
3f44a5c6
LB		 2007 t->tv_begin.tv_sec = 0;
2008 t->tv_begin.tv_usec = 0;
2009 t->tv_end.tv_sec = 0;
2010 t->tv_end.tv_usec = 0;
d4794f25
YG		 2011 t->tv_delta.tv_sec = 0;
2012 t->tv_delta.tv_usec = 0;
3f44a5c6 2013
c98d5d94
LB		 2014 t->tsc = 0;
2015 t->aperf = 0;
2016 t->mperf = 0;
2017 t->c1 = 0;
2018
2af4f9b8
LB		 2019 t->instr_count = 0;
2020
562a2d37
LB		 2021 t->irq_count = 0;
2022 t->smi_count = 0;
2023
c98d5d94
LB		 2024 /* tells format_counters to dump all fields from this set */
2025 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
2026
2027 c->c3 = 0;
2028 c->c6 = 0;
2029 c->c7 = 0;
0539ba11 2030 c->mc6_us = 0;
889facbe 2031 c->core_temp_c = 0;
9392bd98 2032 c->core_energy = 0;
eae97e05 2033 c->core_throt_cnt = 0;
c98d5d94 2034
0b2bb692
LB		 2035 p->pkg_wtd_core_c0 = 0;
2036 p->pkg_any_core_c0 = 0;
2037 p->pkg_any_gfxe_c0 = 0;
2038 p->pkg_both_core_gfxe_c0 = 0;
2039
c98d5d94 2040 p->pc2 = 0;
0f47c08d 2041 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 2042 p->pc3 = 0;
0f47c08d 2043 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 2044 p->pc6 = 0;
0f47c08d 2045 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 2046 p->pc7 = 0;
ca58710f
KCA		 2047 p->pc8 = 0;
2048 p->pc9 = 0;
2049 p->pc10 = 0;
be0e54c4
LB		 2050 p->cpu_lpi = 0;
2051 p->sys_lpi = 0;
889facbe
LB		 2052
2053 p->energy_pkg = 0;
2054 p->energy_dram = 0;
2055 p->energy_cores = 0;
2056 p->energy_gfx = 0;
2057 p->rapl_pkg_perf_status = 0;
2058 p->rapl_dram_perf_status = 0;
2059 p->pkg_temp_c = 0;
27d47356 2060
fdf676e5 2061 p->gfx_rc6_ms = 0;
a5c6d65d 2062 p->uncore_mhz = 0;
27d47356 2063 p->gfx_mhz = 0;
b4b91569 2064 p->gfx_act_mhz = 0;
388e9c81
LB		 2065 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
2066 t->counter[i] = 0;
2067
2068 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
2069 c->counter[i] = 0;
2070
2071 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
2072 p->counter[i] = 0;
c98d5d94 2073}
1b439f01
LB		 2074
2075int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 2076{
388e9c81
LB		 2077 int i;
2078 struct msr_counter *mp;
2079
4c2122d4
LB		 2080 /* copy un-changing apic_id's */
2081 if (DO_BIC(BIC_APIC))
2082 average.threads.apic_id = t->apic_id;
2083 if (DO_BIC(BIC_X2APIC))
2084 average.threads.x2apic_id = t->x2apic_id;
2085
3f44a5c6
LB		 2086 /* remember first tv_begin */
2087 if (average.threads.tv_begin.tv_sec == 0)
2088 average.threads.tv_begin = t->tv_begin;
2089
2090 /* remember last tv_end */
2091 average.threads.tv_end = t->tv_end;
2092
c98d5d94
LB		 2093 average.threads.tsc += t->tsc;
2094 average.threads.aperf += t->aperf;
2095 average.threads.mperf += t->mperf;
2096 average.threads.c1 += t->c1;
103a8fea 2097
2af4f9b8
LB		 2098 average.threads.instr_count += t->instr_count;
2099
562a2d37
LB		 2100 average.threads.irq_count += t->irq_count;
2101 average.threads.smi_count += t->smi_count;
2102
388e9c81
LB		 2103 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2104 if (mp->format == FORMAT_RAW)
2105 continue;
2106 average.threads.counter[i] += t->counter[i];
2107 }
2108
c98d5d94
LB		 2109 /* sum per-core values only for 1st thread in core */
2110 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2111 return 0;
103a8fea 2112
c98d5d94
LB		 2113 average.cores.c3 += c->c3;
2114 average.cores.c6 += c->c6;
2115 average.cores.c7 += c->c7;
0539ba11 2116 average.cores.mc6_us += c->mc6_us;
c98d5d94 2117
889facbe 2118 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
eae97e05 2119 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt);
889facbe 2120
9392bd98
CW		 2121 average.cores.core_energy += c->core_energy;
2122
388e9c81
LB		 2123 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2124 if (mp->format == FORMAT_RAW)
2125 continue;
2126 average.cores.counter[i] += c->counter[i];
2127 }
2128
c98d5d94
LB		 2129 /* sum per-pkg values only for 1st core in pkg */
2130 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2131 return 0;
2132
a99d8730 2133 if (DO_BIC(BIC_Totl_c0))
0b2bb692 2134 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
a99d8730 2135 if (DO_BIC(BIC_Any_c0))
0b2bb692 2136 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
a99d8730 2137 if (DO_BIC(BIC_GFX_c0))
0b2bb692 2138 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
a99d8730 2139 if (DO_BIC(BIC_CPUGFX))
0b2bb692 2140 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
0b2bb692 2141
c98d5d94 2142 average.packages.pc2 += p->pc2;
0f47c08d 2143 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 2144 average.packages.pc3 += p->pc3;
0f47c08d 2145 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 2146 average.packages.pc6 += p->pc6;
0f47c08d 2147 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 2148 average.packages.pc7 += p->pc7;
ca58710f
KCA		 2149 average.packages.pc8 += p->pc8;
2150 average.packages.pc9 += p->pc9;
2151 average.packages.pc10 += p->pc10;
c98d5d94 2152
be0e54c4
LB		 2153 average.packages.cpu_lpi = p->cpu_lpi;
2154 average.packages.sys_lpi = p->sys_lpi;
2155
889facbe
LB		 2156 average.packages.energy_pkg += p->energy_pkg;
2157 average.packages.energy_dram += p->energy_dram;
2158 average.packages.energy_cores += p->energy_cores;
2159 average.packages.energy_gfx += p->energy_gfx;
2160
fdf676e5 2161 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
a5c6d65d 2162 average.packages.uncore_mhz = p->uncore_mhz;
27d47356 2163 average.packages.gfx_mhz = p->gfx_mhz;
b4b91569 2164 average.packages.gfx_act_mhz = p->gfx_act_mhz;
27d47356 2165
889facbe
LB		 2166 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
2167
2168 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
2169 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
388e9c81
LB		 2170
2171 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2172 if (mp->format == FORMAT_RAW)
2173 continue;
2174 average.packages.counter[i] += p->counter[i];
2175 }
c98d5d94
LB		 2176 return 0;
2177}
1b439f01 2178
c98d5d94
LB		 2179/*
2180 * sum the counters for all cpus in the system
2181 * compute the weighted average
2182 */
1b439f01 2183void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p)
c98d5d94 2184{
388e9c81
LB		 2185 int i;
2186 struct msr_counter *mp;
2187
c98d5d94
LB		 2188 clear_counters(&average.threads, &average.cores, &average.packages);
2189
2190 for_all_cpus(sum_counters, t, c, p);
2191
d4794f25
YG		 2192 /* Use the global time delta for the average. */
2193 average.threads.tv_delta = tv_delta;
2194
c98d5d94
LB		 2195 average.threads.tsc /= topo.num_cpus;
2196 average.threads.aperf /= topo.num_cpus;
2197 average.threads.mperf /= topo.num_cpus;
2af4f9b8 2198 average.threads.instr_count /= topo.num_cpus;
c98d5d94
LB		 2199 average.threads.c1 /= topo.num_cpus;
2200
0de6c0df
LB		 2201 if (average.threads.irq_count > 9999999)
2202 sums_need_wide_columns = 1;
2203
c98d5d94
LB		 2204 average.cores.c3 /= topo.num_cores;
2205 average.cores.c6 /= topo.num_cores;
2206 average.cores.c7 /= topo.num_cores;
0539ba11 2207 average.cores.mc6_us /= topo.num_cores;
c98d5d94 2208
a99d8730 2209 if (DO_BIC(BIC_Totl_c0))
0b2bb692 2210 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
a99d8730 2211 if (DO_BIC(BIC_Any_c0))
0b2bb692 2212 average.packages.pkg_any_core_c0 /= topo.num_packages;
a99d8730 2213 if (DO_BIC(BIC_GFX_c0))
0b2bb692 2214 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
a99d8730 2215 if (DO_BIC(BIC_CPUGFX))
0b2bb692 2216 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
0b2bb692 2217
c98d5d94 2218 average.packages.pc2 /= topo.num_packages;
0f47c08d 2219 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 2220 average.packages.pc3 /= topo.num_packages;
0f47c08d 2221 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 2222 average.packages.pc6 /= topo.num_packages;
0f47c08d 2223 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 2224 average.packages.pc7 /= topo.num_packages;
ca58710f
KCA		 2225
2226 average.packages.pc8 /= topo.num_packages;
2227 average.packages.pc9 /= topo.num_packages;
2228 average.packages.pc10 /= topo.num_packages;
388e9c81
LB		 2229
2230 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2231 if (mp->format == FORMAT_RAW)
2232 continue;
0de6c0df
LB		 2233 if (mp->type == COUNTER_ITEMS) {
2234 if (average.threads.counter[i] > 9999999)
2235 sums_need_wide_columns = 1;
41618e63 2236 continue;
0de6c0df 2237 }
388e9c81
LB		 2238 average.threads.counter[i] /= topo.num_cpus;
2239 }
2240 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2241 if (mp->format == FORMAT_RAW)
2242 continue;
0de6c0df
LB		 2243 if (mp->type == COUNTER_ITEMS) {
2244 if (average.cores.counter[i] > 9999999)
2245 sums_need_wide_columns = 1;
2246 }
388e9c81
LB		 2247 average.cores.counter[i] /= topo.num_cores;
2248 }
2249 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2250 if (mp->format == FORMAT_RAW)
2251 continue;
0de6c0df
LB		 2252 if (mp->type == COUNTER_ITEMS) {
2253 if (average.packages.counter[i] > 9999999)
2254 sums_need_wide_columns = 1;
2255 }
388e9c81
LB		 2256 average.packages.counter[i] /= topo.num_packages;
2257 }
103a8fea
LB		 2258}
2259
c98d5d94 2260static unsigned long long rdtsc(void)
103a8fea 2261{
c98d5d94 2262 unsigned int low, high;
15aaa346 2263
1b439f01 2264 asm volatile ("rdtsc":"=a" (low), "=d"(high));
15aaa346 2265
c98d5d94
LB		 2266 return low | ((unsigned long long)high) << 32;
2267}
15aaa346 2268
495c7654
LB		 2269/*
2270 * Open a file, and exit on failure
2271 */
2272FILE *fopen_or_die(const char *path, const char *mode)
2273{
2274 FILE *filep = fopen(path, mode);
2275
2276 if (!filep)
2277 err(1, "%s: open failed", path);
2278 return filep;
2279}
1b439f01 2280
495c7654
LB		 2281/*
2282 * snapshot_sysfs_counter()
2283 *
2284 * return snapshot of given counter
2285 */
2286unsigned long long snapshot_sysfs_counter(char *path)
2287{
2288 FILE *fp;
2289 int retval;
2290 unsigned long long counter;
2291
2292 fp = fopen_or_die(path, "r");
2293
2294 retval = fscanf(fp, "%lld", &counter);
2295 if (retval != 1)
2296 err(1, "snapshot_sysfs_counter(%s)", path);
2297
2298 fclose(fp);
2299
2300 return counter;
2301}
2302
2303int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
2304{
2305 if (mp->msr_num != 0) {
2306 if (get_msr(cpu, mp->msr_num, counterp))
2307 return -1;
2308 } else {
46c27978 2309 char path[128 + PATH_BYTES];
41618e63
LB		 2310
2311 if (mp->flags & SYSFS_PERCPU) {
1b439f01 2312 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path);
41618e63
LB		 2313
2314 *counterp = snapshot_sysfs_counter(path);
2315 } else {
2316 *counterp = snapshot_sysfs_counter(mp->path);
2317 }
495c7654
LB		 2318 }
2319
2320 return 0;
2321}
2322
a5c6d65d
LB		 2323unsigned long long get_uncore_mhz(int package, int die)
2324{
2325 char path[128];
2326
2327 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package,
2328 die);
2329
2330 return (snapshot_sysfs_counter(path) / 1000);
2331}
2332
6d6501d9
BP		 2333int get_epb(int cpu)
2334{
2335 char path[128 + PATH_BYTES];
7f1b11ba 2336 unsigned long long msr;
6d6501d9
BP		 2337 int ret, epb = -1;
2338 FILE *fp;
2339
2340 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu);
2341
7f1b11ba
BP		 2342 fp = fopen(path, "r");
2343 if (!fp)
2344 goto msr_fallback;
6d6501d9
BP		 2345
2346 ret = fscanf(fp, "%d", &epb);
2347 if (ret != 1)
2348 err(1, "%s(%s)", __func__, path);
2349
2350 fclose(fp);
2351
2352 return epb;
7f1b11ba
BP		 2353
2354msr_fallback:
2355 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
2356
2357 return msr & 0xf;
6d6501d9
BP		 2358}
2359
4c2122d4
LB		 2360void get_apic_id(struct thread_data *t)
2361{
34041551 2362 unsigned int eax, ebx, ecx, edx;
4c2122d4 2363
34041551
LB		 2364 if (DO_BIC(BIC_APIC)) {
2365 eax = ebx = ecx = edx = 0;
2366 __cpuid(1, eax, ebx, ecx, edx);
4c2122d4 2367
34041551
LB		 2368 t->apic_id = (ebx >> 24) & 0xff;
2369 }
2370
2371 if (!DO_BIC(BIC_X2APIC))
4c2122d4
LB		 2372 return;
2373
c1c10cc7 2374 if (authentic_amd || hygon_genuine) {
34041551 2375 unsigned int topology_extensions;
4c2122d4 2376
34041551
LB		 2377 if (max_extended_level < 0x8000001e)
2378 return;
4c2122d4 2379
34041551
LB		 2380 eax = ebx = ecx = edx = 0;
2381 __cpuid(0x80000001, eax, ebx, ecx, edx);
1b439f01 2382 topology_extensions = ecx & (1 << 22);
34041551
LB		 2383
2384 if (topology_extensions == 0)
2385 return;
2386
2387 eax = ebx = ecx = edx = 0;
2388 __cpuid(0x8000001e, eax, ebx, ecx, edx);
2389
2390 t->x2apic_id = eax;
4c2122d4 2391 return;
34041551 2392 }
4c2122d4 2393
34041551
LB		 2394 if (!genuine_intel)
2395 return;
2396
2397 if (max_level < 0xb)
4c2122d4
LB		 2398 return;
2399
2400 ecx = 0;
2401 __cpuid(0xb, eax, ebx, ecx, edx);
2402 t->x2apic_id = edx;
2403
34041551 2404 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
1b439f01 2405 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id);
4c2122d4
LB		 2406}
2407
eae97e05
CY		 2408int get_core_throt_cnt(int cpu, unsigned long long *cnt)
2409{
2410 char path[128 + PATH_BYTES];
2411 unsigned long long tmp;
2412 FILE *fp;
2413 int ret;
2414
2415 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu);
2416 fp = fopen(path, "r");
2417 if (!fp)
2418 return -1;
2419 ret = fscanf(fp, "%lld", &tmp);
5e5fd36c 2420 fclose(fp);
eae97e05
CY		 2421 if (ret != 1)
2422 return -1;
eae97e05
CY		 2423 *cnt = tmp;
2424
2425 return 0;
2426}
2427
c98d5d94
LB		 2428/*
2429 * get_counters(...)
2430 * migrate to cpu
2431 * acquire and record local counters for that cpu
2432 */
2433int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2434{
2435 int cpu = t->cpu_id;
889facbe 2436 unsigned long long msr;
0102b067 2437 int aperf_mperf_retry_count = 0;
388e9c81
LB		 2438 struct msr_counter *mp;
2439 int i;
88c3281f 2440
e52966c0 2441 if (cpu_migrate(cpu)) {
3d7772ea 2442 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu);
c98d5d94 2443 return -1;
e52966c0 2444 }
15aaa346 2445
d4794f25
YG		 2446 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
2447
4c2122d4
LB		 2448 if (first_counter_read)
2449 get_apic_id(t);
0102b067 2450retry:
c98d5d94
LB		 2451 t->tsc = rdtsc(); /* we are running on local CPU of interest */
2452
1b439f01 2453 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
0102b067
LB		 2454 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
2455
2456 /*
2457 * The TSC, APERF and MPERF must be read together for
2458 * APERF/MPERF and MPERF/TSC to give accurate results.
2459 *
2460 * Unfortunately, APERF and MPERF are read by
2461 * individual system call, so delays may occur
2462 * between them. If the time to read them
2463 * varies by a large amount, we re-read them.
2464 */
2465
2466 /*
2467 * This initial dummy APERF read has been seen to
2468 * reduce jitter in the subsequent reads.
2469 */
2470
2471 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2472 return -3;
2473
2474 t->tsc = rdtsc(); /* re-read close to APERF */
2475
2476 tsc_before = t->tsc;
2477
9c63a650 2478 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
c98d5d94 2479 return -3;
0102b067
LB		 2480
2481 tsc_between = rdtsc();
2482
9c63a650 2483 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
c98d5d94 2484 return -4;
0102b067
LB		 2485
2486 tsc_after = rdtsc();
2487
2488 aperf_time = tsc_between - tsc_before;
2489 mperf_time = tsc_after - tsc_between;
2490
2491 /*
2492 * If the system call latency to read APERF and MPERF
2493 * differ by more than 2x, then try again.
2494 */
2495 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
2496 aperf_mperf_retry_count++;
2497 if (aperf_mperf_retry_count < 5)
2498 goto retry;
2499 else
1b439f01 2500 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time);
0102b067
LB		 2501 }
2502 aperf_mperf_retry_count = 0;
2503
b2b34dfe
HC		 2504 t->aperf = t->aperf * aperf_mperf_multiplier;
2505 t->mperf = t->mperf * aperf_mperf_multiplier;
c98d5d94
LB		 2506 }
2507
2af4f9b8
LB		 2508 if (DO_BIC(BIC_IPC))
2509 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long))
2510 return -4;
2511
812db3f7 2512 if (DO_BIC(BIC_IRQ))
562a2d37 2513 t->irq_count = irqs_per_cpu[cpu];
812db3f7 2514 if (DO_BIC(BIC_SMI)) {
1ed51011
LB		 2515 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
2516 return -5;
2517 t->smi_count = msr & 0xFFFFFFFF;
2518 }
0539ba11 2519 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
144b44b1
LB		 2520 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
2521 return -6;
2522 }
2523
388e9c81 2524 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
495c7654 2525 if (get_mp(cpu, mp, &t->counter[i]))
388e9c81
LB		 2526 return -10;
2527 }
2528
c98d5d94
LB		 2529 /* collect core counters only for 1st thread in core */
2530 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
f4fdf2b4 2531 goto done;
c98d5d94 2532
1e9042b9 2533 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
c98d5d94
LB		 2534 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
2535 return -6;
144b44b1
LB		 2536 }
2537
1e9042b9 2538 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) {
c98d5d94
LB		 2539 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
2540 return -7;
137f01b3 2541 } else if (do_knl_cstates && soft_c1_residency_display(BIC_CPU_c6)) {
fb5d4327
DC		 2542 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
2543 return -7;
c98d5d94
LB		 2544 }
2545
7ab5ff49 2546 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) {
c98d5d94
LB		 2547 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
2548 return -8;
7ab5ff49
ZR		 2549 else if (t->is_atom) {
2550 /*
2551 * For Atom CPUs that has core cstate deeper than c6,
2552 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper.
2553 * Minus CC7 (and deeper cstates) residency to get
2554 * accturate cc6 residency.
2555 */
2556 c->c6 -= c->c7;
2557 }
2558 }
c98d5d94 2559
0539ba11
LB		 2560 if (DO_BIC(BIC_Mod_c6))
2561 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
2562 return -8;
2563
812db3f7 2564 if (DO_BIC(BIC_CoreTmp)) {
889facbe
LB		 2565 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2566 return -9;
55279aef 2567 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F);
889facbe
LB		 2568 }
2569
eae97e05
CY		 2570 if (DO_BIC(BIC_CORE_THROT_CNT))
2571 get_core_throt_cnt(cpu, &c->core_throt_cnt);
2572
9392bd98
CW		 2573 if (do_rapl & RAPL_AMD_F17H) {
2574 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
2575 return -14;
2576 c->core_energy = msr & 0xFFFFFFFF;
2577 }
2578
388e9c81 2579 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
495c7654 2580 if (get_mp(cpu, mp, &c->counter[i]))
388e9c81
LB		 2581 return -10;
2582 }
889facbe 2583
c98d5d94
LB		 2584 /* collect package counters only for 1st core in package */
2585 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
f4fdf2b4 2586 goto done;
c98d5d94 2587
a99d8730 2588 if (DO_BIC(BIC_Totl_c0)) {
0b2bb692
LB		 2589 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
2590 return -10;
a99d8730
LB		 2591 }
2592 if (DO_BIC(BIC_Any_c0)) {
0b2bb692
LB		 2593 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
2594 return -11;
a99d8730
LB		 2595 }
2596 if (DO_BIC(BIC_GFX_c0)) {
0b2bb692
LB		 2597 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
2598 return -12;
a99d8730
LB		 2599 }
2600 if (DO_BIC(BIC_CPUGFX)) {
0b2bb692
LB		 2601 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
2602 return -13;
2603 }
0f47c08d 2604 if (DO_BIC(BIC_Pkgpc3))
c98d5d94
LB		 2605 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
2606 return -9;
0f47c08d 2607 if (DO_BIC(BIC_Pkgpc6)) {
0539ba11
LB		 2608 if (do_slm_cstates) {
2609 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
2610 return -10;
2611 } else {
2612 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
2613 return -10;
2614 }
2615 }
2616
0f47c08d 2617 if (DO_BIC(BIC_Pkgpc2))
c98d5d94
LB		 2618 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
2619 return -11;
0f47c08d 2620 if (DO_BIC(BIC_Pkgpc7))
c98d5d94
LB		 2621 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
2622 return -12;
0f47c08d 2623 if (DO_BIC(BIC_Pkgpc8))
ca58710f
KCA		 2624 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
2625 return -13;
0f47c08d 2626 if (DO_BIC(BIC_Pkgpc9))
ca58710f
KCA		 2627 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
2628 return -13;
0f47c08d 2629 if (DO_BIC(BIC_Pkgpc10))
ca58710f
KCA		 2630 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
2631 return -13;
0f47c08d 2632
be0e54c4
LB		 2633 if (DO_BIC(BIC_CPU_LPI))
2634 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
2635 if (DO_BIC(BIC_SYS_LPI))
2636 p->sys_lpi = cpuidle_cur_sys_lpi_us;
2637
889facbe 2638 if (do_rapl & RAPL_PKG) {
9972d5d8 2639 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr))
889facbe 2640 return -13;
9972d5d8 2641 p->energy_pkg = msr;
889facbe 2642 }
9148494c 2643 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
9972d5d8 2644 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr))
889facbe 2645 return -14;
9972d5d8 2646 p->energy_cores = msr;
889facbe
LB		 2647 }
2648 if (do_rapl & RAPL_DRAM) {
9972d5d8 2649 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
889facbe 2650 return -15;
9972d5d8 2651 p->energy_dram = msr;
889facbe
LB		 2652 }
2653 if (do_rapl & RAPL_GFX) {
9972d5d8 2654 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr))
889facbe 2655 return -16;
9972d5d8 2656 p->energy_gfx = msr;
889facbe
LB		 2657 }
2658 if (do_rapl & RAPL_PKG_PERF_STATUS) {
9972d5d8 2659 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr))
889facbe 2660 return -16;
9972d5d8 2661 p->rapl_pkg_perf_status = msr;
889facbe
LB		 2662 }
2663 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
9972d5d8 2664 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr))
889facbe 2665 return -16;
9972d5d8 2666 p->rapl_dram_perf_status = msr;
889facbe 2667 }
3316f99a 2668 if (do_rapl & RAPL_AMD_F17H) {
9972d5d8 2669 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr))
3316f99a 2670 return -13;
9972d5d8 2671 p->energy_pkg = msr;
3316f99a 2672 }
812db3f7 2673 if (DO_BIC(BIC_PkgTmp)) {
889facbe
LB		 2674 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2675 return -17;
55279aef 2676 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F);
889facbe 2677 }
fdf676e5 2678
812db3f7 2679 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 2680 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2681
a5c6d65d
LB		 2682 /* n.b. assume die0 uncore frequency applies to whole package */
2683 if (DO_BIC(BIC_UNCORE_MHZ))
2684 p->uncore_mhz = get_uncore_mhz(p->package_id, 0);
2685
812db3f7 2686 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 2687 p->gfx_mhz = gfx_cur_mhz;
2688
b4b91569
RA		 2689 if (DO_BIC(BIC_GFXACTMHz))
2690 p->gfx_act_mhz = gfx_act_mhz;
2691
388e9c81 2692 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
495c7654 2693 if (get_mp(cpu, mp, &p->counter[i]))
388e9c81
LB		 2694 return -10;
2695 }
f4fdf2b4
LB		 2696done:
2697 gettimeofday(&t->tv_end, (struct timezone *)NULL);
388e9c81 2698
15aaa346 2699 return 0;
103a8fea
LB		 2700}
2701
ee7e38e3
LB		 2702/*
2703 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2704 * If you change the values, note they are used both in comparisons
2705 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2706 */
2707
1b439f01
LB		 2708#define PCLUKN 0 /* Unknown */
2709#define PCLRSV 1 /* Reserved */
2710#define PCL__0 2 /* PC0 */
2711#define PCL__1 3 /* PC1 */
2712#define PCL__2 4 /* PC2 */
2713#define PCL__3 5 /* PC3 */
2714#define PCL__4 6 /* PC4 */
2715#define PCL__6 7 /* PC6 */
2716#define PCL_6N 8 /* PC6 No Retention */
2717#define PCL_6R 9 /* PC6 Retention */
2718#define PCL__7 10 /* PC7 */
2719#define PCL_7S 11 /* PC7 Shrink */
2720#define PCL__8 12 /* PC8 */
2721#define PCL__9 13 /* PC9 */
2722#define PCL_10 14 /* PC10 */
2723#define PCLUNL 15 /* Unlimited */
ee7e38e3
LB		 2724
2725int pkg_cstate_limit = PCLUKN;
2726char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1b439f01
LB		 2727 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"
2728};
a2b7b749 2729
1b439f01
LB		 2730int nhm_pkg_cstate_limits[16] =
2731 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2732 PCLRSV, PCLRSV
2733};
2734
1b439f01
LB		 2735int snb_pkg_cstate_limits[16] =
2736 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2737 PCLRSV, PCLRSV
2738};
2739
1b439f01
LB		 2740int hsw_pkg_cstate_limits[16] =
2741 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2742 PCLRSV, PCLRSV
2743};
2744
1b439f01
LB		 2745int slv_pkg_cstate_limits[16] =
2746 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2747 PCL__6, PCL__7
2748};
2749
1b439f01
LB		 2750int amt_pkg_cstate_limits[16] =
2751 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2752 PCLRSV, PCLRSV
2753};
2754
1b439f01
LB		 2755int phi_pkg_cstate_limits[16] =
2756 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2757 PCLRSV, PCLRSV
2758};
2759
1b439f01
LB		 2760int glm_pkg_cstate_limits[16] =
2761 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2762 PCLRSV, PCLRSV
2763};
2764
1b439f01
LB		 2765int skx_pkg_cstate_limits[16] =
2766 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2767 PCLRSV, PCLRSV
2768};
2769
1b439f01 2770int icx_pkg_cstate_limits[16] =
a1b6f487 2771 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2772 PCLRSV, PCLRSV
2773};
1b439f01 2774
3989fc89
ZR		 2775void probe_cst_limit(void)
2776{
2777 unsigned long long msr;
2778 int *pkg_cstate_limits;
2779
fcfa1ce0 2780 if (!platform->has_nhm_msrs)
3989fc89
ZR		 2781 return;
2782
2783 switch (platform->cst_limit) {
2784 case CST_LIMIT_NHM:
2785 pkg_cstate_limits = nhm_pkg_cstate_limits;
2786 break;
2787 case CST_LIMIT_SNB:
2788 pkg_cstate_limits = snb_pkg_cstate_limits;
2789 break;
2790 case CST_LIMIT_HSW:
2791 pkg_cstate_limits = hsw_pkg_cstate_limits;
2792 break;
2793 case CST_LIMIT_SKX:
2794 pkg_cstate_limits = skx_pkg_cstate_limits;
2795 break;
2796 case CST_LIMIT_ICX:
2797 pkg_cstate_limits = icx_pkg_cstate_limits;
2798 break;
2799 case CST_LIMIT_SLV:
2800 pkg_cstate_limits = slv_pkg_cstate_limits;
2801 break;
2802 case CST_LIMIT_AMT:
2803 pkg_cstate_limits = amt_pkg_cstate_limits;
2804 break;
2805 case CST_LIMIT_KNL:
2806 pkg_cstate_limits = phi_pkg_cstate_limits;
2807 break;
2808 case CST_LIMIT_GMT:
2809 pkg_cstate_limits = glm_pkg_cstate_limits;
2810 break;
2811 default:
2812 return;
2813 }
2814
2815 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2816 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2817}
2818
1b439f01 2819static void calculate_tsc_tweak()
a2b7b749 2820{
a2b7b749
LB		 2821 tsc_tweak = base_hz / tsc_hz;
2822}
2823
aeb01e6d
CY		 2824void prewake_cstate_probe(unsigned int family, unsigned int model);
2825
1b439f01 2826static void dump_nhm_platform_info(void)
103a8fea
LB		 2827{
2828 unsigned long long msr;
2829 unsigned int ratio;
2830
ec0adc53 2831 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
103a8fea 2832
b7d8c148 2833 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
6574a5d5 2834
103a8fea 2835 ratio = (msr >> 40) & 0xFF;
1b439f01 2836 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk);
103a8fea
LB		 2837
2838 ratio = (msr >> 8) & 0xFF;
1b439f01 2839 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
103a8fea 2840
7ce7d5de 2841 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
b7d8c148 2842 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
bfae2052 2843 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
67920418 2844
aeb01e6d
CY		 2845 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
2846 if (dis_cstate_prewake)
1b439f01 2847 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN");
aeb01e6d 2848
fcd17211
LB		 2849 return;
2850}
2851
1b439f01 2852static void dump_hsw_turbo_ratio_limits(void)
fcd17211
LB		 2853{
2854 unsigned long long msr;
2855 unsigned int ratio;
2856
7ce7d5de 2857 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
fcd17211 2858
b7d8c148 2859 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
fcd17211
LB		 2860
2861 ratio = (msr >> 8) & 0xFF;
2862 if (ratio)
1b439f01 2863 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2864
2865 ratio = (msr >> 0) & 0xFF;
2866 if (ratio)
1b439f01 2867 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2868 return;
2869}
2870
1b439f01 2871static void dump_ivt_turbo_ratio_limits(void)
fcd17211
LB		 2872{
2873 unsigned long long msr;
2874 unsigned int ratio;
6574a5d5 2875
7ce7d5de 2876 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
6574a5d5 2877
b7d8c148 2878 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 2879
2880 ratio = (msr >> 56) & 0xFF;
2881 if (ratio)
1b439f01 2882 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2883
2884 ratio = (msr >> 48) & 0xFF;
2885 if (ratio)
1b439f01 2886 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2887
2888 ratio = (msr >> 40) & 0xFF;
2889 if (ratio)
1b439f01 2890 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2891
2892 ratio = (msr >> 32) & 0xFF;
2893 if (ratio)
1b439f01 2894 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2895
2896 ratio = (msr >> 24) & 0xFF;
2897 if (ratio)
1b439f01 2898 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2899
2900 ratio = (msr >> 16) & 0xFF;
2901 if (ratio)
1b439f01 2902 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2903
2904 ratio = (msr >> 8) & 0xFF;
2905 if (ratio)
1b439f01 2906 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2907
2908 ratio = (msr >> 0) & 0xFF;
2909 if (ratio)
1b439f01 2910 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2911 return;
2912}
1b439f01 2913
31e07522
LB		 2914int has_turbo_ratio_group_limits(int family, int model)
2915{
2916
2917 if (!genuine_intel)
2918 return 0;
2919
9878bf7a
LB		 2920 if (family != 6)
2921 return 0;
2922
31e07522
LB		 2923 switch (model) {
2924 case INTEL_FAM6_ATOM_GOLDMONT:
2925 case INTEL_FAM6_SKYLAKE_X:
25368d7c 2926 case INTEL_FAM6_ICELAKE_X:
684e40e9 2927 case INTEL_FAM6_SAPPHIRERAPIDS_X:
5ebb34ed 2928 case INTEL_FAM6_ATOM_GOLDMONT_D:
20de0dab 2929 case INTEL_FAM6_ATOM_TREMONT_D:
31e07522 2930 return 1;
9878bf7a
LB		 2931 default:
2932 return 0;
31e07522 2933 }
31e07522 2934}
6574a5d5 2935
4af184ee 2936static void dump_turbo_ratio_limits(int trl_msr_offset, int family, int model)
fcd17211 2937{
31e07522 2938 unsigned long long msr, core_counts;
5d622845 2939 int shift;
103a8fea 2940
4af184ee
LB		 2941 get_msr(base_cpu, trl_msr_offset, &msr);
2942 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n",
884a1f95 2943 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr);
6574a5d5 2944
31e07522
LB		 2945 if (has_turbo_ratio_group_limits(family, model)) {
2946 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
2947 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
2948 } else {
2949 core_counts = 0x0807060504030201;
2950 }
2951
5d622845
LB		 2952 for (shift = 56; shift >= 0; shift -= 8) {
2953 unsigned int ratio, group_size;
6574a5d5 2954
5d622845
LB		 2955 ratio = (msr >> shift) & 0xFF;
2956 group_size = (core_counts >> shift) & 0xFF;
2957 if (ratio)
2958 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2959 ratio, bclk, ratio * bclk, group_size);
2960 }
103a8fea 2961
fcd17211
LB		 2962 return;
2963}
3a9a941d 2964
1b439f01 2965static void dump_atom_turbo_ratio_limits(void)
0f7887c4
LB		 2966{
2967 unsigned long long msr;
2968 unsigned int ratio;
2969
2970 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
2971 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2972
2973 ratio = (msr >> 0) & 0x3F;
2974 if (ratio)
1b439f01 2975 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2976
2977 ratio = (msr >> 8) & 0x3F;
2978 if (ratio)
1b439f01 2979 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2980
2981 ratio = (msr >> 16) & 0x3F;
2982 if (ratio)
1b439f01 2983 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2984
2985 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
2986 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2987
2988 ratio = (msr >> 24) & 0x3F;
2989 if (ratio)
1b439f01 2990 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2991
2992 ratio = (msr >> 16) & 0x3F;
2993 if (ratio)
1b439f01 2994 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2995
2996 ratio = (msr >> 8) & 0x3F;
2997 if (ratio)
1b439f01 2998 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2999
3000 ratio = (msr >> 0) & 0x3F;
3001 if (ratio)
1b439f01 3002 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 3003}
3004
1b439f01 3005static void dump_knl_turbo_ratio_limits(void)
fb5d4327 3006{
cbf97aba
HC		 3007 const unsigned int buckets_no = 7;
3008
fb5d4327 3009 unsigned long long msr;
cbf97aba
HC		 3010 int delta_cores, delta_ratio;
3011 int i, b_nr;
3012 unsigned int cores[buckets_no];
3013 unsigned int ratio[buckets_no];
fb5d4327 3014
ebf5926a 3015 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
fb5d4327 3016
1b439f01 3017 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
fb5d4327 3018
1e3ec5cd 3019 /*
fb5d4327 3020 * Turbo encoding in KNL is as follows:
cbf97aba
HC		 3021 * [0] -- Reserved
3022 * [7:1] -- Base value of number of active cores of bucket 1.
fb5d4327
DC		 3023 * [15:8] -- Base value of freq ratio of bucket 1.
3024 * [20:16] -- +ve delta of number of active cores of bucket 2.
3025 * i.e. active cores of bucket 2 =
3026 * active cores of bucket 1 + delta
3027 * [23:21] -- Negative delta of freq ratio of bucket 2.
3028 * i.e. freq ratio of bucket 2 =
3029 * freq ratio of bucket 1 - delta
3030 * [28:24]-- +ve delta of number of active cores of bucket 3.
3031 * [31:29]-- -ve delta of freq ratio of bucket 3.
3032 * [36:32]-- +ve delta of number of active cores of bucket 4.
3033 * [39:37]-- -ve delta of freq ratio of bucket 4.
3034 * [44:40]-- +ve delta of number of active cores of bucket 5.
3035 * [47:45]-- -ve delta of freq ratio of bucket 5.
3036 * [52:48]-- +ve delta of number of active cores of bucket 6.
3037 * [55:53]-- -ve delta of freq ratio of bucket 6.
3038 * [60:56]-- +ve delta of number of active cores of bucket 7.
3039 * [63:61]-- -ve delta of freq ratio of bucket 7.
3040 */
cbf97aba
HC		 3041
3042 b_nr = 0;
3043 cores[b_nr] = (msr & 0xFF) >> 1;
3044 ratio[b_nr] = (msr >> 8) & 0xFF;
3045
3046 for (i = 16; i < 64; i += 8) {
fb5d4327 3047 delta_cores = (msr >> i) & 0x1F;
cbf97aba
HC		 3048 delta_ratio = (msr >> (i + 5)) & 0x7;
3049
3050 cores[b_nr + 1] = cores[b_nr] + delta_cores;
3051 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
3052 b_nr++;
fb5d4327 3053 }
cbf97aba
HC		 3054
3055 for (i = buckets_no - 1; i >= 0; i--)
3056 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
b7d8c148 3057 fprintf(outf,
710f273b 3058 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
cbf97aba 3059 ratio[i], bclk, ratio[i] * bclk, cores[i]);
fb5d4327
DC		 3060}
3061
1b439f01 3062static void dump_nhm_cst_cfg(void)
fcd17211
LB		 3063{
3064 unsigned long long msr;
3065
1df2e55a 3066 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
fcd17211 3067
1df2e55a 3068 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
fcd17211 3069
3e8b62bf 3070 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
fcd17211
LB		 3071 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
3072 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
3073 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
3074 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1b439f01 3075 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);
ac980e13
AB		 3076
3077#define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
3078 if (has_automatic_cstate_conversion) {
1b439f01 3079 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
ac980e13
AB		 3080 }
3081
3082 fprintf(outf, ")\n");
3083
fcd17211 3084 return;
103a8fea
LB		 3085}
3086
1b439f01 3087static void dump_config_tdp(void)
6fb3143b
LB		 3088{
3089 unsigned long long msr;
3090
3091 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
b7d8c148 3092 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
685b535b 3093 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
6fb3143b
LB		 3094
3095 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
b7d8c148 3096 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
6fb3143b 3097 if (msr) {
685b535b
CY		 3098 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
3099 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
3100 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
3101 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 3102 }
b7d8c148 3103 fprintf(outf, ")\n");
6fb3143b
LB		 3104
3105 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
b7d8c148 3106 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
6fb3143b 3107 if (msr) {
685b535b
CY		 3108 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
3109 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
3110 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
3111 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 3112 }
b7d8c148 3113 fprintf(outf, ")\n");
6fb3143b
LB		 3114
3115 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
b7d8c148 3116 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
6fb3143b 3117 if ((msr) & 0x3)
b7d8c148
LB		 3118 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
3119 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
3120 fprintf(outf, ")\n");
36229897 3121
6fb3143b 3122 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
b7d8c148 3123 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
685b535b 3124 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
b7d8c148
LB		 3125 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
3126 fprintf(outf, ")\n");
6fb3143b 3127}
5a63426e 3128
1b439f01 3129unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
5a63426e
LB		 3130
3131void print_irtl(void)
3132{
3133 unsigned long long msr;
3134
3135 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
3136 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
3137 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3138 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3139
3140 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
3141 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
3142 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3143 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3144
3145 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
3146 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
3147 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3148 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3149
3150 if (!do_irtl_hsw)
3151 return;
3152
3153 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
3154 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
3155 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3156 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3157
3158 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
3159 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
3160 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3161 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3162
3163 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
3164 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
3165 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3166 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3167
3168}
1b439f01 3169
36229897
LB		 3170void free_fd_percpu(void)
3171{
3172 int i;
3173
01a67adf 3174 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
36229897
LB		 3175 if (fd_percpu[i] != 0)
3176 close(fd_percpu[i]);
3177 }
3178
3179 free(fd_percpu);
6fb3143b
LB		 3180}
3181
c98d5d94 3182void free_all_buffers(void)
103a8fea 3183{
0e2d8f05
LB		 3184 int i;
3185
c98d5d94
LB		 3186 CPU_FREE(cpu_present_set);
3187 cpu_present_set = NULL;
36229897 3188 cpu_present_setsize = 0;
103a8fea 3189
c98d5d94
LB		 3190 CPU_FREE(cpu_affinity_set);
3191 cpu_affinity_set = NULL;
3192 cpu_affinity_setsize = 0;
103a8fea 3193
c98d5d94
LB		 3194 free(thread_even);
3195 free(core_even);
3196 free(package_even);
103a8fea 3197
c98d5d94
LB		 3198 thread_even = NULL;
3199 core_even = NULL;
3200 package_even = NULL;
103a8fea 3201
c98d5d94
LB		 3202 free(thread_odd);
3203 free(core_odd);
3204 free(package_odd);
103a8fea 3205
c98d5d94
LB		 3206 thread_odd = NULL;
3207 core_odd = NULL;
3208 package_odd = NULL;
103a8fea 3209
c98d5d94
LB		 3210 free(output_buffer);
3211 output_buffer = NULL;
3212 outp = NULL;
36229897
LB		 3213
3214 free_fd_percpu();
562a2d37
LB		 3215
3216 free(irq_column_2_cpu);
3217 free(irqs_per_cpu);
0e2d8f05
LB		 3218
3219 for (i = 0; i <= topo.max_cpu_num; ++i) {
3220 if (cpus[i].put_ids)
3221 CPU_FREE(cpus[i].put_ids);
3222 }
3223 free(cpus);
103a8fea
LB		 3224}
3225
c98d5d94 3226/*
95aebc44 3227 * Parse a file containing a single int.
6de68fe1
LB		 3228 * Return 0 if file can not be opened
3229 * Exit if file can be opened, but can not be parsed
c98d5d94 3230 */
95aebc44 3231int parse_int_file(const char *fmt, ...)
103a8fea 3232{
95aebc44
JT		 3233 va_list args;
3234 char path[PATH_MAX];
c98d5d94 3235 FILE *filep;
95aebc44 3236 int value;
103a8fea 3237
95aebc44
JT		 3238 va_start(args, fmt);
3239 vsnprintf(path, sizeof(path), fmt, args);
3240 va_end(args);
6de68fe1
LB		 3241 filep = fopen(path, "r");
3242 if (!filep)
3243 return 0;
b2c95d90
JT		 3244 if (fscanf(filep, "%d", &value) != 1)
3245 err(1, "%s: failed to parse number from file", path);
c98d5d94 3246 fclose(filep);
95aebc44
JT		 3247 return value;
3248}
3249
c98d5d94
LB		 3250/*
3251 * cpu_is_first_core_in_package(cpu)
3252 * return 1 if given CPU is 1st core in package
3253 */
3254int cpu_is_first_core_in_package(int cpu)
103a8fea 3255{
95aebc44 3256 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
103a8fea
LB		 3257}
3258
3259int get_physical_package_id(int cpu)
3260{
95aebc44 3261 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
103a8fea
LB		 3262}
3263
6de68fe1
LB		 3264int get_die_id(int cpu)
3265{
3266 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
3267}
3268
103a8fea
LB		 3269int get_core_id(int cpu)
3270{
95aebc44 3271 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
103a8fea
LB		 3272}
3273
ef605741
PB		 3274void set_node_data(void)
3275{
2ffbb224
PB		 3276 int pkg, node, lnode, cpu, cpux;
3277 int cpu_count;
3278
3279 /* initialize logical_node_id */
3280 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
3281 cpus[cpu].logical_node_id = -1;
3282
3283 cpu_count = 0;
3284 for (pkg = 0; pkg < topo.num_packages; pkg++) {
3285 lnode = 0;
3286 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
3287 if (cpus[cpu].physical_package_id != pkg)
3288 continue;
3289 /* find a cpu with an unset logical_node_id */
3290 if (cpus[cpu].logical_node_id != -1)
3291 continue;
3292 cpus[cpu].logical_node_id = lnode;
3293 node = cpus[cpu].physical_node_id;
3294 cpu_count++;
3295 /*
3296 * find all matching cpus on this pkg and set
3297 * the logical_node_id
3298 */
3299 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
1b439f01 3300 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) {
2ffbb224
PB		 3301 cpus[cpux].logical_node_id = lnode;
3302 cpu_count++;
3303 }
3304 }
3305 lnode++;
3306 if (lnode > topo.nodes_per_pkg)
3307 topo.nodes_per_pkg = lnode;
3308 }
3309 if (cpu_count >= topo.max_cpu_num)
3310 break;
ef605741 3311 }
ef605741
PB		 3312}
3313
3314int get_physical_node_id(struct cpu_topology *thiscpu)
c98d5d94
LB		 3315{
3316 char path[80];
3317 FILE *filep;
0e2d8f05
LB		 3318 int i;
3319 int cpu = thiscpu->logical_cpu_id;
e275b388 3320
0e2d8f05 3321 for (i = 0; i <= topo.max_cpu_num; i++) {
1b439f01 3322 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i);
0e2d8f05
LB		 3323 filep = fopen(path, "r");
3324 if (!filep)
3325 continue;
3326 fclose(filep);
3327 return i;
e275b388 3328 }
0e2d8f05
LB		 3329 return -1;
3330}
c98d5d94 3331
0e2d8f05
LB		 3332int get_thread_siblings(struct cpu_topology *thiscpu)
3333{
3334 char path[80], character;
3335 FILE *filep;
3336 unsigned long map;
8cb48b32 3337 int so, shift, sib_core;
0e2d8f05
LB		 3338 int cpu = thiscpu->logical_cpu_id;
3339 int offset = topo.max_cpu_num + 1;
3340 size_t size;
8cb48b32 3341 int thread_id = 0;
0e2d8f05
LB		 3342
3343 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
8cb48b32
PB		 3344 if (thiscpu->thread_id < 0)
3345 thiscpu->thread_id = thread_id++;
0e2d8f05
LB		 3346 if (!thiscpu->put_ids)
3347 return -1;
3348
3349 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3350 CPU_ZERO_S(size, thiscpu->put_ids);
3351
1b439f01 3352 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
3d7772ea
LB		 3353 filep = fopen(path, "r");
3354
3355 if (!filep) {
3356 warnx("%s: open failed", path);
3357 return -1;
3358 }
0e2d8f05
LB		 3359 do {
3360 offset -= BITMASK_SIZE;
8173c336
BH		 3361 if (fscanf(filep, "%lx%c", &map, &character) != 2)
3362 err(1, "%s: failed to parse file", path);
0e2d8f05
LB		 3363 for (shift = 0; shift < BITMASK_SIZE; shift++) {
3364 if ((map >> shift) & 0x1) {
8cb48b32
PB		 3365 so = shift + offset;
3366 sib_core = get_core_id(so);
3367 if (sib_core == thiscpu->physical_core_id) {
3368 CPU_SET_S(so, size, thiscpu->put_ids);
1b439f01
LB		 3369 if ((so != cpu) && (cpus[so].thread_id < 0))
3370 cpus[so].thread_id = thread_id++;
8cb48b32 3371 }
0e2d8f05
LB		 3372 }
3373 }
e13da9a1 3374 } while (character == ',');
c98d5d94 3375 fclose(filep);
0e2d8f05
LB		 3376
3377 return CPU_COUNT_S(size, thiscpu->put_ids);
c98d5d94
LB		 3378}
3379
103a8fea 3380/*
c98d5d94
LB		 3381 * run func(thread, core, package) in topology order
3382 * skip non-present cpus
103a8fea
LB		 3383 */
3384
1b439f01
LB		 3385int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *,
3386 struct pkg_data *, struct thread_data *, struct core_data *,
3387 struct pkg_data *), struct thread_data *thread_base,
3388 struct core_data *core_base, struct pkg_data *pkg_base,
3389 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2)
c98d5d94 3390{
40f5cfe7 3391 int retval, pkg_no, node_no, core_no, thread_no;
c98d5d94
LB		 3392
3393 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
40f5cfe7 3394 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
1b439f01
LB		 3395 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
3396 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
40f5cfe7
PB		 3397 struct thread_data *t, *t2;
3398 struct core_data *c, *c2;
3399 struct pkg_data *p, *p2;
3400
1b439f01 3401 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
40f5cfe7
PB		 3402
3403 if (cpu_is_not_present(t->cpu_id))
3404 continue;
3405
1b439f01 3406 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no);
40f5cfe7 3407
1b439f01
LB		 3408 c = GET_CORE(core_base, core_no, node_no, pkg_no);
3409 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no);
40f5cfe7
PB		 3410
3411 p = GET_PKG(pkg_base, pkg_no);
3412 p2 = GET_PKG(pkg_base2, pkg_no);
3413
3414 retval = func(t, c, p, t2, c2, p2);
3415 if (retval)
3416 return retval;
3417 }
c98d5d94
LB		 3418 }
3419 }
3420 }
3421 return 0;
3422}
3423
3424/*
3425 * run func(cpu) on every cpu in /proc/stat
3426 * return max_cpu number
3427 */
1b439f01 3428int for_all_proc_cpus(int (func) (int))
103a8fea
LB		 3429{
3430 FILE *fp;
c98d5d94 3431 int cpu_num;
103a8fea
LB		 3432 int retval;
3433
57a42a34 3434 fp = fopen_or_die(proc_stat, "r");
103a8fea
LB		 3435
3436 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
b2c95d90
JT		 3437 if (retval != 0)
3438 err(1, "%s: failed to parse format", proc_stat);
103a8fea 3439
c98d5d94
LB		 3440 while (1) {
3441 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
103a8fea
LB		 3442 if (retval != 1)
3443 break;
3444
c98d5d94
LB		 3445 retval = func(cpu_num);
3446 if (retval) {
3447 fclose(fp);
1b439f01 3448 return (retval);
c98d5d94 3449 }
103a8fea
LB		 3450 }
3451 fclose(fp);
c98d5d94 3452 return 0;
103a8fea
LB		 3453}
3454
3455void re_initialize(void)
3456{
c98d5d94
LB		 3457 free_all_buffers();
3458 setup_all_buffers();
3d7772ea 3459 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
103a8fea
LB		 3460}
3461
843c5791
PB		 3462void set_max_cpu_num(void)
3463{
3464 FILE *filep;
8201a028 3465 int base_cpu;
843c5791 3466 unsigned long dummy;
8201a028 3467 char pathname[64];
843c5791 3468
8201a028
PB		 3469 base_cpu = sched_getcpu();
3470 if (base_cpu < 0)
3471 err(1, "cannot find calling cpu ID");
1b439f01 3472 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu);
8201a028
PB		 3473
3474 filep = fopen_or_die(pathname, "r");
843c5791 3475 topo.max_cpu_num = 0;
843c5791 3476 while (fscanf(filep, "%lx,", &dummy) == 1)
0e2d8f05 3477 topo.max_cpu_num += BITMASK_SIZE;
843c5791 3478 fclose(filep);
1b439f01 3479 topo.max_cpu_num--; /* 0 based */
843c5791 3480}
c98d5d94 3481
103a8fea 3482/*
c98d5d94
LB		 3483 * count_cpus()
3484 * remember the last one seen, it will be the max
103a8fea 3485 */
c98d5d94 3486int count_cpus(int cpu)
103a8fea 3487{
9878bf7a
LB		 3488 UNUSED(cpu);
3489
843c5791 3490 topo.num_cpus++;
c98d5d94
LB		 3491 return 0;
3492}
1b439f01 3493
c98d5d94
LB		 3494int mark_cpu_present(int cpu)
3495{
3496 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
15aaa346 3497 return 0;
103a8fea
LB		 3498}
3499
8cb48b32
PB		 3500int init_thread_id(int cpu)
3501{
3502 cpus[cpu].thread_id = -1;
3503 return 0;
3504}
3505
562a2d37
LB		 3506/*
3507 * snapshot_proc_interrupts()
3508 *
3509 * read and record summary of /proc/interrupts
3510 *
3511 * return 1 if config change requires a restart, else return 0
3512 */
3513int snapshot_proc_interrupts(void)
3514{
3515 static FILE *fp;
3516 int column, retval;
3517
3518 if (fp == NULL)
3519 fp = fopen_or_die("/proc/interrupts", "r");
3520 else
3521 rewind(fp);
3522
3523 /* read 1st line of /proc/interrupts to get cpu* name for each column */
3524 for (column = 0; column < topo.num_cpus; ++column) {
3525 int cpu_number;
3526
3527 retval = fscanf(fp, " CPU%d", &cpu_number);
3528 if (retval != 1)
3529 break;
3530
3531 if (cpu_number > topo.max_cpu_num) {
3532 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
3533 return 1;
3534 }
3535
3536 irq_column_2_cpu[column] = cpu_number;
3537 irqs_per_cpu[cpu_number] = 0;
3538 }
3539
3540 /* read /proc/interrupt count lines and sum up irqs per cpu */
3541 while (1) {
3542 int column;
3543 char buf[64];
3544
3545 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
3546 if (retval != 1)
3547 break;
3548
3549 /* read the count per cpu */
3550 for (column = 0; column < topo.num_cpus; ++column) {
3551
3552 int cpu_number, irq_count;
3553
3554 retval = fscanf(fp, " %d", &irq_count);
3555 if (retval != 1)
3556 break;
3557
3558 cpu_number = irq_column_2_cpu[column];
3559 irqs_per_cpu[cpu_number] += irq_count;
3560
3561 }
3562
1b439f01 3563 while (getc(fp) != '\n') ; /* flush interrupt description */
562a2d37
LB		 3564
3565 }
3566 return 0;
3567}
1b439f01 3568
fdf676e5
LB		 3569/*
3570 * snapshot_gfx_rc6_ms()
3571 *
3572 * record snapshot of
3573 * /sys/class/drm/card0/power/rc6_residency_ms
3574 *
3575 * return 1 if config change requires a restart, else return 0
3576 */
3577int snapshot_gfx_rc6_ms(void)
3578{
3579 FILE *fp;
3580 int retval;
3581
3582 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
3583
3584 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
3585 if (retval != 1)
3586 err(1, "GFX rc6");
3587
3588 fclose(fp);
3589
3590 return 0;
3591}
1b439f01 3592
27d47356
LB		 3593/*
3594 * snapshot_gfx_mhz()
3595 *
2c019d65
ZR		 3596 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
3597 * when /sys/class/drm/card0/gt_cur_freq_mhz is not available.
27d47356
LB		 3598 *
3599 * return 1 if config change requires a restart, else return 0
3600 */
3601int snapshot_gfx_mhz(void)
3602{
3603 static FILE *fp;
3604 int retval;
3605
2c019d65
ZR		 3606 if (fp == NULL) {
3607 fp = fopen("/sys/class/drm/card0/gt_cur_freq_mhz", "r");
3608 if (!fp)
3609 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
3610 } else {
27d47356 3611 rewind(fp);
22048c54
LB		 3612 fflush(fp);
3613 }
27d47356
LB		 3614
3615 retval = fscanf(fp, "%d", &gfx_cur_mhz);
3616 if (retval != 1)
3617 err(1, "GFX MHz");
3618
3619 return 0;
3620}
562a2d37 3621
b4b91569
RA		 3622/*
3623 * snapshot_gfx_cur_mhz()
3624 *
2c019d65
ZR		 3625 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz
3626 * when /sys/class/drm/card0/gt_act_freq_mhz is not available.
b4b91569
RA		 3627 *
3628 * return 1 if config change requires a restart, else return 0
3629 */
3630int snapshot_gfx_act_mhz(void)
3631{
3632 static FILE *fp;
3633 int retval;
3634
2c019d65
ZR		 3635 if (fp == NULL) {
3636 fp = fopen("/sys/class/drm/card0/gt_act_freq_mhz", "r");
3637 if (!fp)
3638 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r");
3639 } else {
b4b91569
RA		 3640 rewind(fp);
3641 fflush(fp);
3642 }
3643
3644 retval = fscanf(fp, "%d", &gfx_act_mhz);
3645 if (retval != 1)
3646 err(1, "GFX ACT MHz");
3647
3648 return 0;
3649}
3650
be0e54c4
LB		 3651/*
3652 * snapshot_cpu_lpi()
3653 *
3654 * record snapshot of
3655 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
be0e54c4
LB		 3656 */
3657int snapshot_cpu_lpi_us(void)
3658{
3659 FILE *fp;
3660 int retval;
3661
3662 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
3663
3664 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
5ea7647b
PB		 3665 if (retval != 1) {
3666 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
3667 BIC_NOT_PRESENT(BIC_CPU_LPI);
605736c6 3668 fclose(fp);
5ea7647b
PB		 3669 return -1;
3670 }
be0e54c4
LB		 3671
3672 fclose(fp);
3673
3674 return 0;
3675}
1b439f01 3676
be0e54c4
LB		 3677/*
3678 * snapshot_sys_lpi()
3679 *
1f81c5ef 3680 * record snapshot of sys_lpi_file
be0e54c4
LB		 3681 */
3682int snapshot_sys_lpi_us(void)
3683{
3684 FILE *fp;
3685 int retval;
3686
1f81c5ef 3687 fp = fopen_or_die(sys_lpi_file, "r");
be0e54c4
LB		 3688
3689 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
5ea7647b
PB		 3690 if (retval != 1) {
3691 fprintf(stderr, "Disabling Low Power Idle System output\n");
3692 BIC_NOT_PRESENT(BIC_SYS_LPI);
15423b95 3693 fclose(fp);
5ea7647b
PB		 3694 return -1;
3695 }
be0e54c4
LB		 3696 fclose(fp);
3697
3698 return 0;
3699}
1b439f01 3700
562a2d37
LB		 3701/*
3702 * snapshot /proc and /sys files
3703 *
3704 * return 1 if configuration restart needed, else return 0
3705 */
3706int snapshot_proc_sysfs_files(void)
3707{
218f0e8d
LB		 3708 if (DO_BIC(BIC_IRQ))
3709 if (snapshot_proc_interrupts())
3710 return 1;
562a2d37 3711
812db3f7 3712 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 3713 snapshot_gfx_rc6_ms();
3714
812db3f7 3715 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 3716 snapshot_gfx_mhz();
3717
b4b91569
RA		 3718 if (DO_BIC(BIC_GFXACTMHz))
3719 snapshot_gfx_act_mhz();
3720
be0e54c4
LB		 3721 if (DO_BIC(BIC_CPU_LPI))
3722 snapshot_cpu_lpi_us();
3723
3724 if (DO_BIC(BIC_SYS_LPI))
3725 snapshot_sys_lpi_us();
3726
562a2d37
LB		 3727 return 0;
3728}
3729
8aa2ed0b
LB		 3730int exit_requested;
3731
1b439f01 3732static void signal_handler(int signal)
8aa2ed0b
LB		 3733{
3734 switch (signal) {
3735 case SIGINT:
3736 exit_requested = 1;
3737 if (debug)
3738 fprintf(stderr, " SIGINT\n");
3739 break;
07211960
LB		 3740 case SIGUSR1:
3741 if (debug > 1)
3742 fprintf(stderr, "SIGUSR1\n");
3743 break;
8aa2ed0b
LB		 3744 }
3745}
3746
3747void setup_signal_handler(void)
3748{
3749 struct sigaction sa;
3750
3751 memset(&sa, 0, sizeof(sa));
3752
3753 sa.sa_handler = &signal_handler;
3754
3755 if (sigaction(SIGINT, &sa, NULL) < 0)
3756 err(1, "sigaction SIGINT");
07211960
LB		 3757 if (sigaction(SIGUSR1, &sa, NULL) < 0)
3758 err(1, "sigaction SIGUSR1");
8aa2ed0b 3759}
b9ad8ee0 3760
47936f94 3761void do_sleep(void)
b9ad8ee0 3762{
c026c236
AB		 3763 struct timeval tout;
3764 struct timespec rest;
b9ad8ee0
LB		 3765 fd_set readfds;
3766 int retval;
3767
3768 FD_ZERO(&readfds);
3769 FD_SET(0, &readfds);
3770
c026c236 3771 if (ignore_stdin) {
47936f94
AB		 3772 nanosleep(&interval_ts, NULL);
3773 return;
3774 }
b9ad8ee0 3775
c026c236
AB		 3776 tout = interval_tv;
3777 retval = select(1, &readfds, NULL, NULL, &tout);
b9ad8ee0
LB		 3778
3779 if (retval == 1) {
b9ad8ee0
LB		 3780 switch (getc(stdin)) {
3781 case 'q':
3782 exit_requested = 1;
3783 break;
c026c236
AB		 3784 case EOF:
3785 /*
3786 * 'stdin' is a pipe closed on the other end. There
3787 * won't be any further input.
3788 */
3789 ignore_stdin = 1;
3790 /* Sleep the rest of the time */
3791 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
3792 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
3793 nanosleep(&rest, NULL);
b9ad8ee0 3794 }
b9ad8ee0 3795 }
b9ad8ee0 3796}
47936f94 3797
87e15da9
CY		 3798int get_msr_sum(int cpu, off_t offset, unsigned long long *msr)
3799{
3800 int ret, idx;
3801 unsigned long long msr_cur, msr_last;
3802
3803 if (!per_cpu_msr_sum)
3804 return 1;
3805
3806 idx = offset_to_idx(offset);
3807 if (idx < 0)
3808 return idx;
3809 /* get_msr_sum() = sum + (get_msr() - last) */
3810 ret = get_msr(cpu, offset, &msr_cur);
3811 if (ret)
3812 return ret;
3813 msr_last = per_cpu_msr_sum[cpu].entries[idx].last;
3814 DELTA_WRAP32(msr_cur, msr_last);
3815 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum;
3816
3817 return 0;
3818}
3819
3820timer_t timerid;
3821
3822/* Timer callback, update the sum of MSRs periodically. */
3823static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3824{
3825 int i, ret;
3826 int cpu = t->cpu_id;
3827
9878bf7a
LB		 3828 UNUSED(c);
3829 UNUSED(p);
3830
87e15da9
CY		 3831 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) {
3832 unsigned long long msr_cur, msr_last;
13a779de 3833 off_t offset;
87e15da9
CY		 3834
3835 if (!idx_valid(i))
3836 continue;
3837 offset = idx_to_offset(i);
3838 if (offset < 0)
3839 continue;
3840 ret = get_msr(cpu, offset, &msr_cur);
3841 if (ret) {
1b439f01 3842 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset);
87e15da9
CY		 3843 continue;
3844 }
3845
3846 msr_last = per_cpu_msr_sum[cpu].entries[i].last;
3847 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff;
3848
3849 DELTA_WRAP32(msr_cur, msr_last);
3850 per_cpu_msr_sum[cpu].entries[i].sum += msr_last;
3851 }
3852 return 0;
3853}
3854
1b439f01 3855static void msr_record_handler(union sigval v)
87e15da9 3856{
9878bf7a
LB		 3857 UNUSED(v);
3858
87e15da9
CY		 3859 for_all_cpus(update_msr_sum, EVEN_COUNTERS);
3860}
3861
3862void msr_sum_record(void)
3863{
3864 struct itimerspec its;
3865 struct sigevent sev;
3866
3867 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array));
3868 if (!per_cpu_msr_sum) {
3869 fprintf(outf, "Can not allocate memory for long time MSR.\n");
3870 return;
3871 }
3872 /*
3873 * Signal handler might be restricted, so use thread notifier instead.
3874 */
3875 memset(&sev, 0, sizeof(struct sigevent));
3876 sev.sigev_notify = SIGEV_THREAD;
3877 sev.sigev_notify_function = msr_record_handler;
3878
3879 sev.sigev_value.sival_ptr = &timerid;
3880 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) {
3881 fprintf(outf, "Can not create timer.\n");
3882 goto release_msr;
3883 }
3884
3885 its.it_value.tv_sec = 0;
3886 its.it_value.tv_nsec = 1;
3887 /*
3888 * A wraparound time has been calculated early.
3889 * Some sources state that the peak power for a
3890 * microprocessor is usually 1.5 times the TDP rating,
3891 * use 2 * TDP for safety.
3892 */
3893 its.it_interval.tv_sec = rapl_joule_counter_range / 2;
3894 its.it_interval.tv_nsec = 0;
3895
3896 if (timer_settime(timerid, 0, &its, NULL) == -1) {
3897 fprintf(outf, "Can not set timer.\n");
3898 goto release_timer;
3899 }
3900 return;
3901
1b439f01 3902release_timer:
87e15da9 3903 timer_delete(timerid);
1b439f01 3904release_msr:
87e15da9
CY		 3905 free(per_cpu_msr_sum);
3906}
4c2122d4 3907
38c6663a
LB		 3908/*
3909 * set_my_sched_priority(pri)
3910 * return previous
3911 */
3912int set_my_sched_priority(int priority)
3913{
3914 int retval;
3915 int original_priority;
3916
3917 errno = 0;
3918 original_priority = getpriority(PRIO_PROCESS, 0);
3919 if (errno && (original_priority == -1))
3920 err(errno, "getpriority");
3921
3922 retval = setpriority(PRIO_PROCESS, 0, priority);
3923 if (retval)
de7839ee 3924 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname);
38c6663a
LB		 3925
3926 errno = 0;
3927 retval = getpriority(PRIO_PROCESS, 0);
3928 if (retval != priority)
164d7a96 3929 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority);
38c6663a
LB		 3930
3931 return original_priority;
3932}
3933
103a8fea
LB		 3934void turbostat_loop()
3935{
c98d5d94 3936 int retval;
e52966c0 3937 int restarted = 0;
9878bf7a 3938 unsigned int done_iters = 0;
c98d5d94 3939
8aa2ed0b
LB		 3940 setup_signal_handler();
3941
38c6663a
LB		 3942 /*
3943 * elevate own priority for interval mode
3944 */
3945 set_my_sched_priority(-20);
3946
103a8fea 3947restart:
e52966c0
LB		 3948 restarted++;
3949
562a2d37 3950 snapshot_proc_sysfs_files();
c98d5d94 3951 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
4c2122d4 3952 first_counter_read = 0;
d91bb17c
LB		 3953 if (retval < -1) {
3954 exit(retval);
3955 } else if (retval == -1) {
3d7772ea 3956 if (restarted > 10) {
e52966c0
LB		 3957 exit(retval);
3958 }
c98d5d94
LB		 3959 re_initialize();
3960 goto restart;
3961 }
e52966c0 3962 restarted = 0;
023fe0ac 3963 done_iters = 0;
103a8fea
LB		 3964 gettimeofday(&tv_even, (struct timezone *)NULL);
3965
3966 while (1) {
c98d5d94 3967 if (for_all_proc_cpus(cpu_is_not_present)) {
103a8fea
LB		 3968 re_initialize();
3969 goto restart;
3970 }
b9ad8ee0 3971 do_sleep();
562a2d37
LB		 3972 if (snapshot_proc_sysfs_files())
3973 goto restart;
c98d5d94 3974 retval = for_all_cpus(get_counters, ODD_COUNTERS);
d91bb17c
LB		 3975 if (retval < -1) {
3976 exit(retval);
3977 } else if (retval == -1) {
15aaa346
LB		 3978 re_initialize();
3979 goto restart;
3980 }
103a8fea 3981 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 3982 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 3983 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
3984 re_initialize();
3985 goto restart;
3986 }
c98d5d94
LB		 3987 compute_average(EVEN_COUNTERS);
3988 format_all_counters(EVEN_COUNTERS);
b7d8c148 3989 flush_output_stdout();
8aa2ed0b
LB		 3990 if (exit_requested)
3991 break;
023fe0ac
CY		 3992 if (num_iterations && ++done_iters >= num_iterations)
3993 break;
b9ad8ee0 3994 do_sleep();
562a2d37
LB		 3995 if (snapshot_proc_sysfs_files())
3996 goto restart;
c98d5d94 3997 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 3998 if (retval < -1) {
3999 exit(retval);
4000 } else if (retval == -1) {
103a8fea
LB		 4001 re_initialize();
4002 goto restart;
4003 }
103a8fea 4004 gettimeofday(&tv_even, (struct timezone *)NULL);
103a8fea 4005 timersub(&tv_even, &tv_odd, &tv_delta);
ba3dec99
LB		 4006 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
4007 re_initialize();
4008 goto restart;
4009 }
c98d5d94
LB		 4010 compute_average(ODD_COUNTERS);
4011 format_all_counters(ODD_COUNTERS);
b7d8c148 4012 flush_output_stdout();
8aa2ed0b
LB		 4013 if (exit_requested)
4014 break;
023fe0ac
CY		 4015 if (num_iterations && ++done_iters >= num_iterations)
4016 break;
103a8fea
LB		 4017 }
4018}
4019
4020void check_dev_msr()
4021{
4022 struct stat sb;
7ce7d5de 4023 char pathname[32];
103a8fea 4024
7ce7d5de
PB		 4025 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
4026 if (stat(pathname, &sb))
1b439f01 4027 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
a21d38c8 4028 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
103a8fea
LB		 4029}
4030
fcaa681c
LB		 4031/*
4032 * check for CAP_SYS_RAWIO
4033 * return 0 on success
4034 * return 1 on fail
4035 */
4036int check_for_cap_sys_rawio(void)
103a8fea 4037{
fcaa681c
LB		 4038 cap_t caps;
4039 cap_flag_value_t cap_flag_value;
98481e79 4040
fcaa681c
LB		 4041 caps = cap_get_proc();
4042 if (caps == NULL)
4043 err(-6, "cap_get_proc\n");
98481e79 4044
fcaa681c
LB		 4045 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
4046 err(-6, "cap_get\n");
4047
4048 if (cap_flag_value != CAP_SET) {
1b439f01 4049 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname);
fcaa681c 4050 return 1;
98481e79
LB		 4051 }
4052
fcaa681c
LB		 4053 if (cap_free(caps) == -1)
4054 err(-6, "cap_free\n");
4055
4056 return 0;
4057}
1b439f01 4058
fcaa681c
LB		 4059void check_permissions(void)
4060{
4061 int do_exit = 0;
4062 char pathname[32];
4063
4064 /* check for CAP_SYS_RAWIO */
4065 do_exit += check_for_cap_sys_rawio();
4066
98481e79 4067 /* test file permissions */
7ce7d5de
PB		 4068 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
4069 if (euidaccess(pathname, R_OK)) {
98481e79
LB		 4070 do_exit++;
4071 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
4072 }
4073
4074 /* if all else fails, thell them to be root */
4075 if (do_exit)
4076 if (getuid() != 0)
d7899447 4077 warnx("... or simply run as root");
98481e79
LB		 4078
4079 if (do_exit)
4080 exit(-6);
103a8fea
LB		 4081}
4082
71e84129
ZR		 4083void probe_bclk(void)
4084{
4085 unsigned long long msr;
4086 unsigned int base_ratio;
4087
fcfa1ce0 4088 if (!platform->has_nhm_msrs)
71e84129
ZR		 4089 return;
4090
4091 if (platform->bclk_freq == BCLK_100MHZ)
4092 bclk = 100.00;
4093 else if (platform->bclk_freq == BCLK_133MHZ)
4094 bclk = 133.33;
4095 else if (platform->bclk_freq == BCLK_SLV)
4096 bclk = slm_bclk();
4097 else
4098 return;
4099
4100 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
4101 base_ratio = (msr >> 8) & 0xFF;
4102
4103 base_hz = base_ratio * bclk * 1000000;
4104 has_base_hz = 1;
4105}
4106
0f7887c4 4107/*
495c7654 4108 * SLV client has support for unique MSRs:
0f7887c4
LB		 4109 *
4110 * MSR_CC6_DEMOTION_POLICY_CONFIG
4111 * MSR_MC6_DEMOTION_POLICY_CONFIG
4112 */
4113
4114int has_slv_msrs(unsigned int family, unsigned int model)
4115{
4116 if (!genuine_intel)
4117 return 0;
4118
9878bf7a
LB		 4119 if (family != 6)
4120 return 0;
4121
0f7887c4 4122 switch (model) {
f2c4db1b 4123 case INTEL_FAM6_ATOM_SILVERMONT:
0f7887c4
LB		 4124 return 1;
4125 }
4126 return 0;
4127}
1b439f01 4128
7170a374
LB		 4129int is_dnv(unsigned int family, unsigned int model)
4130{
4131
4132 if (!genuine_intel)
4133 return 0;
4134
9878bf7a
LB		 4135 if (family != 6)
4136 return 0;
4137
7170a374 4138 switch (model) {
5ebb34ed 4139 case INTEL_FAM6_ATOM_GOLDMONT_D:
7170a374
LB		 4140 return 1;
4141 }
4142 return 0;
4143}
1b439f01 4144
ade0ebac
LB		 4145int is_bdx(unsigned int family, unsigned int model)
4146{
4147
4148 if (!genuine_intel)
4149 return 0;
4150
9878bf7a
LB		 4151 if (family != 6)
4152 return 0;
4153
ade0ebac
LB		 4154 switch (model) {
4155 case INTEL_FAM6_BROADWELL_X:
ade0ebac
LB		 4156 return 1;
4157 }
4158 return 0;
4159}
1b439f01 4160
34c76197
LB		 4161int is_skx(unsigned int family, unsigned int model)
4162{
4163
4164 if (!genuine_intel)
4165 return 0;
4166
9878bf7a
LB		 4167 if (family != 6)
4168 return 0;
4169
34c76197
LB		 4170 switch (model) {
4171 case INTEL_FAM6_SKYLAKE_X:
4172 return 1;
4173 }
4174 return 0;
4175}
25368d7c
CY		 4176
4177int is_icx(unsigned int family, unsigned int model)
4178{
4179
4180 if (!genuine_intel)
4181 return 0;
4182
9878bf7a
LB		 4183 if (family != 6)
4184 return 0;
4185
25368d7c
CY		 4186 switch (model) {
4187 case INTEL_FAM6_ICELAKE_X:
4188 return 1;
4189 }
4190 return 0;
4191}
4192
684e40e9
AB		 4193int is_spr(unsigned int family, unsigned int model)
4194{
4195
4196 if (!genuine_intel)
4197 return 0;
4198
4199 if (family != 6)
4200 return 0;
4201
4202 switch (model) {
4203 case INTEL_FAM6_SAPPHIRERAPIDS_X:
4204 return 1;
4205 }
4206 return 0;
4207}
4208
f6708400
CY		 4209int is_ehl(unsigned int family, unsigned int model)
4210{
4211 if (!genuine_intel)
4212 return 0;
4213
9878bf7a
LB		 4214 if (family != 6)
4215 return 0;
4216
f6708400
CY		 4217 switch (model) {
4218 case INTEL_FAM6_ATOM_TREMONT:
4219 return 1;
4220 }
4221 return 0;
4222}
1b439f01 4223
20de0dab
AL		 4224int is_jvl(unsigned int family, unsigned int model)
4225{
4226 if (!genuine_intel)
4227 return 0;
4228
9878bf7a
LB		 4229 if (family != 6)
4230 return 0;
4231
20de0dab
AL		 4232 switch (model) {
4233 case INTEL_FAM6_ATOM_TREMONT_D:
4234 return 1;
4235 }
4236 return 0;
4237}
0f7887c4 4238
31e07522 4239int has_turbo_ratio_limit(unsigned int family, unsigned int model)
d7899447 4240{
0f7887c4
LB		 4241 if (has_slv_msrs(family, model))
4242 return 0;
4243
9878bf7a
LB		 4244 if (family != 6)
4245 return 0;
4246
d7899447 4247 switch (model) {
1b439f01 4248 /* Nehalem compatible, but do not include turbo-ratio limit support */
869ce69e 4249 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
869ce69e 4250 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
d7899447
LB		 4251 return 0;
4252 default:
4253 return 1;
4254 }
4255}
1b439f01 4256
0f7887c4
LB		 4257int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
4258{
4259 if (has_slv_msrs(family, model))
4260 return 1;
4261
4262 return 0;
4263}
1b439f01 4264
6574a5d5
LB		 4265int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
4266{
4267 if (!genuine_intel)
4268 return 0;
4269
4270 if (family != 6)
4271 return 0;
4272
4273 switch (model) {
869ce69e
LB		 4274 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
4275 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
fcd17211
LB		 4276 return 1;
4277 default:
4278 return 0;
4279 }
4280}
1b439f01 4281
fcd17211
LB		 4282int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
4283{
4284 if (!genuine_intel)
4285 return 0;
4286
4287 if (family != 6)
4288 return 0;
4289
4290 switch (model) {
869ce69e 4291 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
6574a5d5
LB		 4292 return 1;
4293 default:
4294 return 0;
4295 }
4296}
4297
fb5d4327
DC		 4298int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
4299{
4300 if (!genuine_intel)
4301 return 0;
4302
4303 if (family != 6)
4304 return 0;
4305
4306 switch (model) {
869ce69e 4307 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
fb5d4327
DC		 4308 return 1;
4309 default:
4310 return 0;
4311 }
4312}
1b439f01 4313
31e07522
LB		 4314int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
4315{
4316 if (!genuine_intel)
4317 return 0;
4318
4319 if (family != 6)
4320 return 0;
4321
4322 switch (model) {
4323 case INTEL_FAM6_ATOM_GOLDMONT:
4324 case INTEL_FAM6_SKYLAKE_X:
25368d7c 4325 case INTEL_FAM6_ICELAKE_X:
684e40e9 4326 case INTEL_FAM6_SAPPHIRERAPIDS_X:
31e07522
LB		 4327 return 1;
4328 default:
4329 return 0;
4330 }
4331}
1b439f01 4332
6fb3143b
LB		 4333int has_config_tdp(unsigned int family, unsigned int model)
4334{
4335 if (!genuine_intel)
4336 return 0;
4337
4338 if (family != 6)
4339 return 0;
4340
4341 switch (model) {
869ce69e 4342 case INTEL_FAM6_IVYBRIDGE: /* IVB */
c66f78a6 4343 case INTEL_FAM6_HASWELL: /* HSW */
869ce69e 4344 case INTEL_FAM6_HASWELL_X: /* HSX */
77e5517c 4345 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 4346 case INTEL_FAM6_HASWELL_G: /* HSW */
c66f78a6 4347 case INTEL_FAM6_BROADWELL: /* BDW */
5e741407 4348 case INTEL_FAM6_BROADWELL_G: /* BDW */
869ce69e 4349 case INTEL_FAM6_BROADWELL_X: /* BDX */
af239c44
PZ		 4350 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4351 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
869ce69e 4352 case INTEL_FAM6_SKYLAKE_X: /* SKX */
25368d7c 4353 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 4354 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
869ce69e 4355 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
6fb3143b
LB		 4356 return 1;
4357 default:
4358 return 0;
4359 }
4360}
4361
0b9a0b9b
ZR		 4362/*
4363 * tcc_offset_bits:
4364 * 0: Tcc Offset not supported (Default)
4365 * 6: Bit 29:24 of MSR_PLATFORM_INFO
4366 * 4: Bit 27:24 of MSR_PLATFORM_INFO
4367 */
4368void check_tcc_offset(int model)
4369{
4370 unsigned long long msr;
4371
4372 if (!genuine_intel)
4373 return;
4374
4375 switch (model) {
4376 case INTEL_FAM6_SKYLAKE_L:
b98a6d78 4377 case INTEL_FAM6_CANNONLAKE_L:
0b9a0b9b
ZR		 4378 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) {
4379 msr = (msr >> 30) & 1;
4380 if (msr)
4381 tcc_offset_bits = 6;
4382 }
4383 return;
4384 default:
4385 return;
4386 }
4387}
4388
1b439f01 4389static void remove_underbar(char *s)
fecb3bc8
DA		 4390{
4391 char *to = s;
4392
4393 while (*s) {
4394 if (*s != '_')
4395 *to++ = *s;
4396 s++;
4397 }
4398
4399 *to = 0;
4400}
4401
3ea8e52e 4402static void dump_turbo_ratio_info(unsigned int family, unsigned int model)
fcd17211 4403{
3ea8e52e 4404 if (!has_turbo)
fcd17211
LB		 4405 return;
4406
fcd17211
LB		 4407 if (has_hsw_turbo_ratio_limit(family, model))
4408 dump_hsw_turbo_ratio_limits();
4409
4410 if (has_ivt_turbo_ratio_limit(family, model))
4411 dump_ivt_turbo_ratio_limits();
4412
4af184ee
LB		 4413 if (has_turbo_ratio_limit(family, model)) {
4414 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT, family, model);
4415
4416 if (is_hybrid)
4417 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT, family, model);
4418 }
fcd17211 4419
0f7887c4
LB		 4420 if (has_atom_turbo_ratio_limit(family, model))
4421 dump_atom_turbo_ratio_limits();
4422
fb5d4327
DC		 4423 if (has_knl_turbo_ratio_limit(family, model))
4424 dump_knl_turbo_ratio_limits();
4425
6fb3143b
LB		 4426 if (has_config_tdp(family, model))
4427 dump_config_tdp();
3ea8e52e 4428}
6fb3143b 4429
3ea8e52e
AB		 4430static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
4431{
fcfa1ce0 4432 if (!platform->has_nhm_msrs)
3ea8e52e
AB		 4433 return;
4434
4435 dump_nhm_platform_info();
4436 dump_turbo_ratio_info(family, model);
fcd17211
LB		 4437 dump_nhm_cst_cfg();
4438}
4439
a5c6d65d
LB		 4440static int read_sysfs_int(char *path)
4441{
4442 FILE *input;
4443 int retval = -1;
4444
4445 input = fopen(path, "r");
4446 if (input == NULL) {
4447 if (debug)
4448 fprintf(outf, "NSFOD %s\n", path);
4449 return (-1);
4450 }
4451 if (fscanf(input, "%d", &retval) != 1)
4452 err(1, "%s: failed to read int from file", path);
4453 fclose(input);
4454
4455 return (retval);
4456}
4457
abdcbdb2
LB		 4458static void dump_sysfs_file(char *path)
4459{
4460 FILE *input;
4461 char cpuidle_buf[64];
4462
4463 input = fopen(path, "r");
4464 if (input == NULL) {
4465 if (debug)
4466 fprintf(outf, "NSFOD %s\n", path);
4467 return;
4468 }
4469 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input))
4470 err(1, "%s: failed to read file", path);
4471 fclose(input);
4472
4473 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf);
4474}
1b439f01 4475
a5c6d65d
LB		 4476static void intel_uncore_frequency_probe(void)
4477{
4478 int i, j;
4479 char path[128];
4480
4481 if (!genuine_intel)
4482 return;
4483
4484 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK))
4485 return;
4486
4d182748
ZR		 4487 /* Cluster level sysfs not supported yet. */
4488 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/uncore00", R_OK))
4489 return;
4490
a5c6d65d
LB		 4491 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK))
4492 BIC_PRESENT(BIC_UNCORE_MHZ);
4493
4494 if (quiet)
4495 return;
4496
4497 for (i = 0; i < topo.num_packages; ++i) {
4498 for (j = 0; j < topo.num_die; ++j) {
4499 int k, l;
4500
4501 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz",
4502 i, j);
4503 k = read_sysfs_int(path);
4504 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz",
4505 i, j);
4506 l = read_sysfs_int(path);
4507 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000);
4508
4509 sprintf(path,
4510 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz",
4511 i, j);
4512 k = read_sysfs_int(path);
4513 sprintf(path,
4514 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz",
4515 i, j);
4516 l = read_sysfs_int(path);
4517 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000);
4518 }
4519 }
4520}
4521
1b439f01 4522static void dump_sysfs_cstate_config(void)
41618e63
LB		 4523{
4524 char path[64];
4525 char name_buf[16];
4526 char desc[64];
4527 FILE *input;
4528 int state;
4529 char *sp;
4530
abdcbdb2
LB		 4531 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) {
4532 fprintf(outf, "cpuidle not loaded\n");
4533 return;
4534 }
4535
4536 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver");
4537 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor");
4538 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro");
4539
41618e63
LB		 4540 for (state = 0; state < 10; ++state) {
4541
1b439f01 4542 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 4543 input = fopen(path, "r");
4544 if (input == NULL)
4545 continue;
8173c336
BH		 4546 if (!fgets(name_buf, sizeof(name_buf), input))
4547 err(1, "%s: failed to read file", path);
41618e63 4548
1b439f01 4549 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 4550 sp = strchr(name_buf, '-');
4551 if (!sp)
4552 sp = strchrnul(name_buf, '\n');
4553 *sp = '\0';
41618e63
LB		 4554 fclose(input);
4555
fecb3bc8
DA		 4556 remove_underbar(name_buf);
4557
1b439f01 4558 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state);
41618e63
LB		 4559 input = fopen(path, "r");
4560 if (input == NULL)
4561 continue;
8173c336
BH		 4562 if (!fgets(desc, sizeof(desc), input))
4563 err(1, "%s: failed to read file", path);
41618e63
LB		 4564
4565 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
4566 fclose(input);
4567 }
4568}
1b439f01
LB		 4569
4570static void dump_sysfs_pstate_config(void)
7293fccd
LB		 4571{
4572 char path[64];
4573 char driver_buf[64];
4574 char governor_buf[64];
4575 FILE *input;
4576 int turbo;
4577
1b439f01 4578 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu);
7293fccd
LB		 4579 input = fopen(path, "r");
4580 if (input == NULL) {
0a42d235 4581 fprintf(outf, "NSFOD %s\n", path);
7293fccd
LB		 4582 return;
4583 }
8173c336
BH		 4584 if (!fgets(driver_buf, sizeof(driver_buf), input))
4585 err(1, "%s: failed to read file", path);
7293fccd
LB		 4586 fclose(input);
4587
1b439f01 4588 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu);
7293fccd
LB		 4589 input = fopen(path, "r");
4590 if (input == NULL) {
0a42d235 4591 fprintf(outf, "NSFOD %s\n", path);
7293fccd
LB		 4592 return;
4593 }
8173c336
BH		 4594 if (!fgets(governor_buf, sizeof(governor_buf), input))
4595 err(1, "%s: failed to read file", path);
7293fccd
LB		 4596 fclose(input);
4597
4598 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
4599 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
4600
4601 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
4602 input = fopen(path, "r");
4603 if (input != NULL) {
8173c336
BH		 4604 if (fscanf(input, "%d", &turbo) != 1)
4605 err(1, "%s: failed to parse number from file", path);
7293fccd
LB		 4606 fprintf(outf, "cpufreq boost: %d\n", turbo);
4607 fclose(input);
4608 }
4609
4610 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
4611 input = fopen(path, "r");
4612 if (input != NULL) {
8173c336
BH		 4613 if (fscanf(input, "%d", &turbo) != 1)
4614 err(1, "%s: failed to parse number from file", path);
7293fccd
LB		 4615 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
4616 fclose(input);
4617 }
4618}
41618e63 4619
889facbe
LB		 4620/*
4621 * print_epb()
4622 * Decode the ENERGY_PERF_BIAS MSR
4623 */
4624int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4625{
889facbe 4626 char *epb_string;
6d6501d9 4627 int cpu, epb;
889facbe 4628
9878bf7a
LB		 4629 UNUSED(c);
4630 UNUSED(p);
4631
889facbe
LB		 4632 if (!has_epb)
4633 return 0;
4634
4635 cpu = t->cpu_id;
4636
4637 /* EPB is per-package */
4638 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4639 return 0;
4640
4641 if (cpu_migrate(cpu)) {
3d7772ea 4642 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 4643 return -1;
4644 }
4645
6d6501d9
BP		 4646 epb = get_epb(cpu);
4647 if (epb < 0)
889facbe
LB		 4648 return 0;
4649
6d6501d9 4650 switch (epb) {
889facbe
LB		 4651 case ENERGY_PERF_BIAS_PERFORMANCE:
4652 epb_string = "performance";
4653 break;
4654 case ENERGY_PERF_BIAS_NORMAL:
4655 epb_string = "balanced";
4656 break;
4657 case ENERGY_PERF_BIAS_POWERSAVE:
4658 epb_string = "powersave";
4659 break;
4660 default:
4661 epb_string = "custom";
4662 break;
4663 }
6d6501d9 4664 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string);
889facbe
LB		 4665
4666 return 0;
4667}
1b439f01 4668
7f5c258e
LB		 4669/*
4670 * print_hwp()
4671 * Decode the MSR_HWP_CAPABILITIES
4672 */
4673int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4674{
4675 unsigned long long msr;
4676 int cpu;
4677
9878bf7a
LB		 4678 UNUSED(c);
4679 UNUSED(p);
4680
7f5c258e
LB		 4681 if (!has_hwp)
4682 return 0;
4683
4684 cpu = t->cpu_id;
4685
4686 /* MSR_HWP_CAPABILITIES is per-package */
4687 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4688 return 0;
4689
4690 if (cpu_migrate(cpu)) {
3d7772ea 4691 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu);
7f5c258e
LB		 4692 return -1;
4693 }
4694
4695 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
4696 return 0;
4697
1b439f01 4698 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-");
7f5c258e
LB		 4699
4700 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
4701 if ((msr & (1 << 0)) == 0)
4702 return 0;
4703
4704 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
4705 return 0;
4706
b7d8c148 4707 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
1b439f01
LB		 4708 "(high %d guar %d eff %d low %d)\n",
4709 cpu, msr,
4710 (unsigned int)HWP_HIGHEST_PERF(msr),
4711 (unsigned int)HWP_GUARANTEED_PERF(msr),
4712 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr));
7f5c258e
LB		 4713
4714 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
4715 return 0;
4716
b7d8c148 4717 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
1b439f01
LB		 4718 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
4719 cpu, msr,
4720 (unsigned int)(((msr) >> 0) & 0xff),
4721 (unsigned int)(((msr) >> 8) & 0xff),
4722 (unsigned int)(((msr) >> 16) & 0xff),
4723 (unsigned int)(((msr) >> 24) & 0xff),
4724 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1));
7f5c258e
LB		 4725
4726 if (has_hwp_pkg) {
4727 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
4728 return 0;
4729
b7d8c148 4730 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
6dbd25a2 4731 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
7f5c258e
LB		 4732 cpu, msr,
4733 (unsigned int)(((msr) >> 0) & 0xff),
4734 (unsigned int)(((msr) >> 8) & 0xff),
4735 (unsigned int)(((msr) >> 16) & 0xff),
1b439f01 4736 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3));
7f5c258e
LB		 4737 }
4738 if (has_hwp_notify) {
4739 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
4740 return 0;
4741
b7d8c148 4742 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
7f5c258e 4743 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
1b439f01 4744 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis");
7f5c258e
LB		 4745 }
4746 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
4747 return 0;
4748
b7d8c148 4749 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
1b439f01 4750 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
92c25393 4751 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-");
889facbe
LB		 4752
4753 return 0;
4754}
4755
3a9a941d
LB		 4756/*
4757 * print_perf_limit()
4758 */
4759int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4760{
4761 unsigned long long msr;
4762 int cpu;
4763
9878bf7a
LB		 4764 UNUSED(c);
4765 UNUSED(p);
4766
3a9a941d
LB		 4767 cpu = t->cpu_id;
4768
4769 /* per-package */
4770 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4771 return 0;
4772
4773 if (cpu_migrate(cpu)) {
3d7772ea 4774 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu);
3a9a941d
LB		 4775 return -1;
4776 }
4777
4778 if (do_core_perf_limit_reasons) {
4779 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4780 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4781 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
e33cbe85 4782 (msr & 1 << 15) ? "bit15, " : "",
3a9a941d 4783 (msr & 1 << 14) ? "bit14, " : "",
e33cbe85
LB		 4784 (msr & 1 << 13) ? "Transitions, " : "",
4785 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
4786 (msr & 1 << 11) ? "PkgPwrL2, " : "",
4787 (msr & 1 << 10) ? "PkgPwrL1, " : "",
4788 (msr & 1 << 9) ? "CorePwr, " : "",
4789 (msr & 1 << 8) ? "Amps, " : "",
4790 (msr & 1 << 6) ? "VR-Therm, " : "",
4791 (msr & 1 << 5) ? "Auto-HWP, " : "",
4792 (msr & 1 << 4) ? "Graphics, " : "",
4793 (msr & 1 << 2) ? "bit2, " : "",
1b439f01 4794 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : "");
b7d8c148 4795 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
e33cbe85 4796 (msr & 1 << 31) ? "bit31, " : "",
3a9a941d 4797 (msr & 1 << 30) ? "bit30, " : "",
e33cbe85
LB		 4798 (msr & 1 << 29) ? "Transitions, " : "",
4799 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
4800 (msr & 1 << 27) ? "PkgPwrL2, " : "",
4801 (msr & 1 << 26) ? "PkgPwrL1, " : "",
4802 (msr & 1 << 25) ? "CorePwr, " : "",
4803 (msr & 1 << 24) ? "Amps, " : "",
4804 (msr & 1 << 22) ? "VR-Therm, " : "",
4805 (msr & 1 << 21) ? "Auto-HWP, " : "",
4806 (msr & 1 << 20) ? "Graphics, " : "",
4807 (msr & 1 << 18) ? "bit18, " : "",
1b439f01 4808 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : "");
3a9a941d
LB		 4809
4810 }
4811 if (do_gfx_perf_limit_reasons) {
4812 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4813 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4814 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3a9a941d
LB		 4815 (msr & 1 << 0) ? "PROCHOT, " : "",
4816 (msr & 1 << 1) ? "ThermStatus, " : "",
4817 (msr & 1 << 4) ? "Graphics, " : "",
4818 (msr & 1 << 6) ? "VR-Therm, " : "",
4819 (msr & 1 << 8) ? "Amps, " : "",
4820 (msr & 1 << 9) ? "GFXPwr, " : "",
1b439f01 4821 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 4822 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3a9a941d
LB		 4823 (msr & 1 << 16) ? "PROCHOT, " : "",
4824 (msr & 1 << 17) ? "ThermStatus, " : "",
4825 (msr & 1 << 20) ? "Graphics, " : "",
4826 (msr & 1 << 22) ? "VR-Therm, " : "",
4827 (msr & 1 << 24) ? "Amps, " : "",
4828 (msr & 1 << 25) ? "GFXPwr, " : "",
1b439f01 4829 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
3a9a941d
LB		 4830 }
4831 if (do_ring_perf_limit_reasons) {
4832 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4833 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4834 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3a9a941d
LB		 4835 (msr & 1 << 0) ? "PROCHOT, " : "",
4836 (msr & 1 << 1) ? "ThermStatus, " : "",
4837 (msr & 1 << 6) ? "VR-Therm, " : "",
4838 (msr & 1 << 8) ? "Amps, " : "",
1b439f01 4839 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 4840 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3a9a941d
LB		 4841 (msr & 1 << 16) ? "PROCHOT, " : "",
4842 (msr & 1 << 17) ? "ThermStatus, " : "",
4843 (msr & 1 << 22) ? "VR-Therm, " : "",
4844 (msr & 1 << 24) ? "Amps, " : "",
1b439f01 4845 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
3a9a941d
LB		 4846 }
4847 return 0;
4848}
4849
889facbe 4850#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
1b439f01 4851#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
889facbe 4852
9392bd98 4853double get_tdp_intel(unsigned int model)
144b44b1
LB		 4854{
4855 unsigned long long msr;
4856
4857 if (do_rapl & RAPL_PKG_POWER_INFO)
7ce7d5de 4858 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
144b44b1
LB		 4859 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
4860
4861 switch (model) {
f2c4db1b 4862 case INTEL_FAM6_ATOM_SILVERMONT:
5ebb34ed 4863 case INTEL_FAM6_ATOM_SILVERMONT_D:
144b44b1
LB		 4864 return 30.0;
4865 default:
4866 return 135.0;
4867 }
4868}
4869
9392bd98
CW		 4870double get_tdp_amd(unsigned int family)
4871{
9878bf7a
LB		 4872 UNUSED(family);
4873
33eb8225
KP		 4874 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */
4875 return 280.0;
9392bd98
CW		 4876}
4877
40ee8e3b
AS		 4878/*
4879 * rapl_dram_energy_units_probe()
4880 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
4881 */
1b439f01 4882static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
40ee8e3b
AS		 4883{
4884 /* only called for genuine_intel, family 6 */
4885
4886 switch (model) {
869ce69e
LB		 4887 case INTEL_FAM6_HASWELL_X: /* HSX */
4888 case INTEL_FAM6_BROADWELL_X: /* BDX */
abdc75ab 4889 case INTEL_FAM6_SKYLAKE_X: /* SKX */
869ce69e 4890 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
6397b641 4891 case INTEL_FAM6_ICELAKE_X: /* ICX */
40ee8e3b
AS		 4892 return (rapl_dram_energy_units = 15.3 / 1000000);
4893 default:
4894 return (rapl_energy_units);
4895 }
4896}
4897
9392bd98 4898void rapl_probe_intel(unsigned int family, unsigned int model)
889facbe
LB		 4899{
4900 unsigned long long msr;
144b44b1 4901 unsigned int time_unit;
889facbe
LB		 4902 double tdp;
4903
889facbe
LB		 4904 if (family != 6)
4905 return;
4906
4907 switch (model) {
869ce69e
LB		 4908 case INTEL_FAM6_SANDYBRIDGE:
4909 case INTEL_FAM6_IVYBRIDGE:
c66f78a6 4910 case INTEL_FAM6_HASWELL: /* HSW */
77e5517c 4911 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 4912 case INTEL_FAM6_HASWELL_G: /* HSW */
c66f78a6 4913 case INTEL_FAM6_BROADWELL: /* BDW */
5e741407 4914 case INTEL_FAM6_BROADWELL_G: /* BDW */
144b44b1 4915 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4916 if (rapl_joules) {
4917 BIC_PRESENT(BIC_Pkg_J);
4918 BIC_PRESENT(BIC_Cor_J);
4919 BIC_PRESENT(BIC_GFX_J);
4920 } else {
4921 BIC_PRESENT(BIC_PkgWatt);
4922 BIC_PRESENT(BIC_CorWatt);
4923 BIC_PRESENT(BIC_GFXWatt);
4924 }
889facbe 4925 break;
869ce69e 4926 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 4927 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
e4085d54 4928 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4929 if (rapl_joules)
4930 BIC_PRESENT(BIC_Pkg_J);
4931 else
4932 BIC_PRESENT(BIC_PkgWatt);
e4085d54 4933 break;
f6708400 4934 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
1b439f01
LB		 4935 do_rapl =
4936 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4937 | RAPL_GFX | RAPL_PKG_POWER_INFO;
f6708400
CY		 4938 if (rapl_joules) {
4939 BIC_PRESENT(BIC_Pkg_J);
4940 BIC_PRESENT(BIC_Cor_J);
4941 BIC_PRESENT(BIC_RAM_J);
4942 BIC_PRESENT(BIC_GFX_J);
4943 } else {
4944 BIC_PRESENT(BIC_PkgWatt);
4945 BIC_PRESENT(BIC_CorWatt);
4946 BIC_PRESENT(BIC_RAMWatt);
4947 BIC_PRESENT(BIC_GFXWatt);
4948 }
4949 break;
20de0dab
AL		 4950 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
4951 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
4952 BIC_PRESENT(BIC_PKG__);
4953 if (rapl_joules)
4954 BIC_PRESENT(BIC_Pkg_J);
4955 else
4956 BIC_PRESENT(BIC_PkgWatt);
4957 break;
af239c44
PZ		 4958 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4959 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
1b439f01
LB		 4960 do_rapl =
4961 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4962 | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4963 BIC_PRESENT(BIC_PKG__);
4964 BIC_PRESENT(BIC_RAM__);
4965 if (rapl_joules) {
4966 BIC_PRESENT(BIC_Pkg_J);
4967 BIC_PRESENT(BIC_Cor_J);
4968 BIC_PRESENT(BIC_RAM_J);
81824921 4969 BIC_PRESENT(BIC_GFX_J);
812db3f7
LB		 4970 } else {
4971 BIC_PRESENT(BIC_PkgWatt);
4972 BIC_PRESENT(BIC_CorWatt);
4973 BIC_PRESENT(BIC_RAMWatt);
81824921 4974 BIC_PRESENT(BIC_GFXWatt);
812db3f7 4975 }
0b2bb692 4976 break;
869ce69e
LB		 4977 case INTEL_FAM6_HASWELL_X: /* HSX */
4978 case INTEL_FAM6_BROADWELL_X: /* BDX */
869ce69e 4979 case INTEL_FAM6_SKYLAKE_X: /* SKX */
25368d7c 4980 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 4981 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
869ce69e 4982 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
1b439f01
LB		 4983 do_rapl =
4984 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4985 RAPL_PKG_POWER_INFO;
812db3f7
LB		 4986 BIC_PRESENT(BIC_PKG__);
4987 BIC_PRESENT(BIC_RAM__);
4988 if (rapl_joules) {
4989 BIC_PRESENT(BIC_Pkg_J);
4990 BIC_PRESENT(BIC_RAM_J);
4991 } else {
4992 BIC_PRESENT(BIC_PkgWatt);
4993 BIC_PRESENT(BIC_RAMWatt);
4994 }
e6f9bb3c 4995 break;
869ce69e
LB		 4996 case INTEL_FAM6_SANDYBRIDGE_X:
4997 case INTEL_FAM6_IVYBRIDGE_X:
1b439f01
LB		 4998 do_rapl =
4999 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS |
5000 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 5001 BIC_PRESENT(BIC_PKG__);
5002 BIC_PRESENT(BIC_RAM__);
5003 if (rapl_joules) {
5004 BIC_PRESENT(BIC_Pkg_J);
5005 BIC_PRESENT(BIC_Cor_J);
5006 BIC_PRESENT(BIC_RAM_J);
5007 } else {
5008 BIC_PRESENT(BIC_PkgWatt);
5009 BIC_PRESENT(BIC_CorWatt);
5010 BIC_PRESENT(BIC_RAMWatt);
5011 }
144b44b1 5012 break;
f2c4db1b 5013 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5ebb34ed 5014 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
9148494c 5015 do_rapl = RAPL_PKG | RAPL_CORES;
812db3f7
LB		 5016 if (rapl_joules) {
5017 BIC_PRESENT(BIC_Pkg_J);
5018 BIC_PRESENT(BIC_Cor_J);
5019 } else {
5020 BIC_PRESENT(BIC_PkgWatt);
5021 BIC_PRESENT(BIC_CorWatt);
5022 }
889facbe 5023 break;
5ebb34ed 5024 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
1b439f01
LB		 5025 do_rapl =
5026 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
5027 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
812db3f7
LB		 5028 BIC_PRESENT(BIC_PKG__);
5029 BIC_PRESENT(BIC_RAM__);
5030 if (rapl_joules) {
5031 BIC_PRESENT(BIC_Pkg_J);
5032 BIC_PRESENT(BIC_Cor_J);
5033 BIC_PRESENT(BIC_RAM_J);
5034 } else {
5035 BIC_PRESENT(BIC_PkgWatt);
5036 BIC_PRESENT(BIC_CorWatt);
5037 BIC_PRESENT(BIC_RAMWatt);
5038 }
0f644909 5039 break;
889facbe
LB		 5040 default:
5041 return;
5042 }
5043
5044 /* units on package 0, verify later other packages match */
7ce7d5de 5045 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
889facbe
LB		 5046 return;
5047
5048 rapl_power_units = 1.0 / (1 << (msr & 0xF));
f2c4db1b 5049 if (model == INTEL_FAM6_ATOM_SILVERMONT)
144b44b1
LB		 5050 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
5051 else
5052 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
889facbe 5053
40ee8e3b
AS		 5054 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
5055
144b44b1
LB		 5056 time_unit = msr >> 16 & 0xF;
5057 if (time_unit == 0)
5058 time_unit = 0xA;
889facbe 5059
144b44b1 5060 rapl_time_units = 1.0 / (1 << (time_unit));
889facbe 5061
9392bd98 5062 tdp = get_tdp_intel(model);
889facbe 5063
144b44b1 5064 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
96e47158 5065 if (!quiet)
b7d8c148 5066 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
9392bd98 5067}
889facbe 5068
9392bd98
CW		 5069void rapl_probe_amd(unsigned int family, unsigned int model)
5070{
5071 unsigned long long msr;
5072 unsigned int eax, ebx, ecx, edx;
5073 unsigned int has_rapl = 0;
5074 double tdp;
5075
9878bf7a
LB		 5076 UNUSED(model);
5077
9392bd98
CW		 5078 if (max_extended_level >= 0x80000007) {
5079 __cpuid(0x80000007, eax, ebx, ecx, edx);
33eb8225 5080 /* RAPL (Fam 17h+) */
9392bd98
CW		 5081 has_rapl = edx & (1 << 14);
5082 }
5083
33eb8225 5084 if (!has_rapl || family < 0x17)
9392bd98
CW		 5085 return;
5086
33eb8225
KP		 5087 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY;
5088 if (rapl_joules) {
5089 BIC_PRESENT(BIC_Pkg_J);
5090 BIC_PRESENT(BIC_Cor_J);
5091 } else {
5092 BIC_PRESENT(BIC_PkgWatt);
5093 BIC_PRESENT(BIC_CorWatt);
9392bd98
CW		 5094 }
5095
5096 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
5097 return;
5098
5099 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
5100 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
5101 rapl_power_units = ldexp(1.0, -(msr & 0xf));
5102
9cfa8e04 5103 tdp = get_tdp_amd(family);
9392bd98
CW		 5104
5105 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
5106 if (!quiet)
5107 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
5108}
5109
5110/*
5111 * rapl_probe()
5112 *
5113 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
5114 */
5115void rapl_probe(unsigned int family, unsigned int model)
5116{
5117 if (genuine_intel)
5118 rapl_probe_intel(family, model);
c1c10cc7 5119 if (authentic_amd || hygon_genuine)
9392bd98 5120 rapl_probe_amd(family, model);
889facbe
LB		 5121}
5122
1b69317d 5123void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3a9a941d
LB		 5124{
5125 if (!genuine_intel)
5126 return;
5127
5128 if (family != 6)
5129 return;
5130
5131 switch (model) {
c66f78a6 5132 case INTEL_FAM6_HASWELL: /* HSW */
77e5517c 5133 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 5134 case INTEL_FAM6_HASWELL_G: /* HSW */
3a9a941d 5135 do_gfx_perf_limit_reasons = 1;
9878bf7a 5136 /* FALLTHRU */
869ce69e 5137 case INTEL_FAM6_HASWELL_X: /* HSX */
3a9a941d
LB		 5138 do_core_perf_limit_reasons = 1;
5139 do_ring_perf_limit_reasons = 1;
5140 default:
5141 return;
5142 }
5143}
5144
ac980e13
AB		 5145void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
5146{
eade39b2
AB		 5147 if (family != 6)
5148 return;
5149
5150 switch (model) {
5151 case INTEL_FAM6_BROADWELL_X:
5152 case INTEL_FAM6_SKYLAKE_X:
ac980e13 5153 has_automatic_cstate_conversion = 1;
eade39b2 5154 }
ac980e13
AB		 5155}
5156
aeb01e6d
CY		 5157void prewake_cstate_probe(unsigned int family, unsigned int model)
5158{
684e40e9 5159 if (is_icx(family, model) || is_spr(family, model))
aeb01e6d
CY		 5160 dis_cstate_prewake = 1;
5161}
5162
889facbe
LB		 5163int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5164{
5165 unsigned long long msr;
f4896fa5 5166 unsigned int dts, dts2;
889facbe
LB		 5167 int cpu;
5168
9878bf7a
LB		 5169 UNUSED(c);
5170 UNUSED(p);
5171
889facbe
LB		 5172 if (!(do_dts || do_ptm))
5173 return 0;
5174
5175 cpu = t->cpu_id;
5176
5177 /* DTS is per-core, no need to print for each thread */
388e9c81 5178 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
889facbe
LB		 5179 return 0;
5180
5181 if (cpu_migrate(cpu)) {
3d7772ea 5182 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 5183 return -1;
5184 }
5185
5186 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
5187 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
5188 return 0;
5189
5190 dts = (msr >> 16) & 0x7F;
1b439f01 5191 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts);
889facbe 5192
889facbe
LB		 5193 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
5194 return 0;
5195
5196 dts = (msr >> 16) & 0x7F;
5197 dts2 = (msr >> 8) & 0x7F;
b7d8c148 5198 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
55279aef 5199 cpu, msr, tj_max - dts, tj_max - dts2);
889facbe
LB		 5200 }
5201
f4896fa5 5202 if (do_dts && debug) {
889facbe
LB		 5203 unsigned int resolution;
5204
5205 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
5206 return 0;
5207
5208 dts = (msr >> 16) & 0x7F;
5209 resolution = (msr >> 27) & 0xF;
b7d8c148 5210 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
55279aef 5211 cpu, msr, tj_max - dts, resolution);
889facbe 5212
889facbe
LB		 5213 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
5214 return 0;
5215
5216 dts = (msr >> 16) & 0x7F;
5217 dts2 = (msr >> 8) & 0x7F;
b7d8c148 5218 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
55279aef 5219 cpu, msr, tj_max - dts, tj_max - dts2);
889facbe
LB		 5220 }
5221
5222 return 0;
5223}
36229897 5224
889facbe
LB		 5225void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
5226{
6b398625 5227 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n",
889facbe
LB		 5228 cpu, label,
5229 ((msr >> 15) & 1) ? "EN" : "DIS",
5230 ((msr >> 0) & 0x7FFF) * rapl_power_units,
1b439f01 5231 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
889facbe
LB		 5232 (((msr >> 16) & 1) ? "EN" : "DIS"));
5233
5234 return;
5235}
5236
5237int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5238{
5239 unsigned long long msr;
9392bd98 5240 const char *msr_name;
889facbe 5241 int cpu;
889facbe 5242
9878bf7a
LB		 5243 UNUSED(c);
5244 UNUSED(p);
5245
889facbe
LB		 5246 if (!do_rapl)
5247 return 0;
5248
5249 /* RAPL counters are per package, so print only for 1st thread/package */
5250 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
5251 return 0;
5252
5253 cpu = t->cpu_id;
5254 if (cpu_migrate(cpu)) {
3d7772ea 5255 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 5256 return -1;
5257 }
5258
9392bd98
CW		 5259 if (do_rapl & RAPL_AMD_F17H) {
5260 msr_name = "MSR_RAPL_PWR_UNIT";
5261 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
5262 return -1;
5263 } else {
5264 msr_name = "MSR_RAPL_POWER_UNIT";
5265 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
5266 return -1;
5267 }
889facbe 5268
9392bd98 5269 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
96e47158
LB		 5270 rapl_power_units, rapl_energy_units, rapl_time_units);
5271
144b44b1
LB		 5272 if (do_rapl & RAPL_PKG_POWER_INFO) {
5273
889facbe 5274 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
1b439f01 5275 return -5;
889facbe 5276
b7d8c148 5277 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe 5278 cpu, msr,
1b439f01 5279 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
889facbe
LB		 5280 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5281 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5282 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
5283
144b44b1
LB		 5284 }
5285 if (do_rapl & RAPL_PKG) {
5286
889facbe
LB		 5287 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
5288 return -9;
5289
b7d8c148 5290 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
96e47158 5291 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
889facbe
LB		 5292
5293 print_power_limit_msr(cpu, msr, "PKG Limit #1");
6b398625 5294 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n",
889facbe
LB		 5295 cpu,
5296 ((msr >> 47) & 1) ? "EN" : "DIS",
5297 ((msr >> 32) & 0x7FFF) * rapl_power_units,
1b439f01 5298 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
889facbe 5299 ((msr >> 48) & 1) ? "EN" : "DIS");
f52ba931
SP		 5300
5301 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
5302 return -9;
5303
5304 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr);
5305 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n",
164d7a96 5306 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN");
889facbe
LB		 5307 }
5308
0b2bb692 5309 if (do_rapl & RAPL_DRAM_POWER_INFO) {
889facbe 5310 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
1b439f01 5311 return -6;
889facbe 5312
b7d8c148 5313 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe 5314 cpu, msr,
1b439f01 5315 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
889facbe
LB		 5316 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5317 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5318 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
0b2bb692
LB		 5319 }
5320 if (do_rapl & RAPL_DRAM) {
889facbe
LB		 5321 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
5322 return -9;
b7d8c148 5323 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5324 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
889facbe
LB		 5325
5326 print_power_limit_msr(cpu, msr, "DRAM Limit");
5327 }
144b44b1 5328 if (do_rapl & RAPL_CORE_POLICY) {
96e47158
LB		 5329 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
5330 return -7;
889facbe 5331
96e47158 5332 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
144b44b1 5333 }
9148494c 5334 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
96e47158
LB		 5335 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
5336 return -9;
5337 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5338 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
96e47158 5339 print_power_limit_msr(cpu, msr, "Cores Limit");
889facbe
LB		 5340 }
5341 if (do_rapl & RAPL_GFX) {
96e47158
LB		 5342 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
5343 return -8;
889facbe 5344
96e47158 5345 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
889facbe 5346
96e47158
LB		 5347 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
5348 return -9;
5349 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5350 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
96e47158 5351 print_power_limit_msr(cpu, msr, "GFX Limit");
889facbe
LB		 5352 }
5353 return 0;
5354}
5355
d7899447
LB		 5356/*
5357 * SNB adds support for additional MSRs:
5358 *
5359 * MSR_PKG_C7_RESIDENCY 0x000003fa
5360 * MSR_CORE_C7_RESIDENCY 0x000003fe
5361 * MSR_PKG_C2_RESIDENCY 0x0000060d
5362 */
103a8fea 5363
d7899447 5364int has_snb_msrs(unsigned int family, unsigned int model)
103a8fea
LB		 5365{
5366 if (!genuine_intel)
5367 return 0;
5368
9878bf7a
LB		 5369 if (family != 6)
5370 return 0;
5371
103a8fea 5372 switch (model) {
869ce69e
LB		 5373 case INTEL_FAM6_SANDYBRIDGE:
5374 case INTEL_FAM6_SANDYBRIDGE_X:
1b439f01
LB		 5375 case INTEL_FAM6_IVYBRIDGE: /* IVB */
5376 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
5377 case INTEL_FAM6_HASWELL: /* HSW */
5378 case INTEL_FAM6_HASWELL_X: /* HSW */
5379 case INTEL_FAM6_HASWELL_L: /* HSW */
5380 case INTEL_FAM6_HASWELL_G: /* HSW */
5381 case INTEL_FAM6_BROADWELL: /* BDW */
5382 case INTEL_FAM6_BROADWELL_G: /* BDW */
5383 case INTEL_FAM6_BROADWELL_X: /* BDX */
5384 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5385 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5386 case INTEL_FAM6_SKYLAKE_X: /* SKX */
5387 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 5388 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
1b439f01 5389 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5390 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5ebb34ed 5391 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
1b439f01
LB		 5392 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
5393 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
103a8fea
LB		 5394 return 1;
5395 }
5396 return 0;
5397}
5398
d7899447 5399/*
570992fc 5400 * HSW ULT added support for C8/C9/C10 MSRs:
d7899447 5401 *
5a63426e
LB		 5402 * MSR_PKG_C8_RESIDENCY 0x00000630
5403 * MSR_PKG_C9_RESIDENCY 0x00000631
5404 * MSR_PKG_C10_RESIDENCY 0x00000632
5405 *
5406 * MSR_PKGC8_IRTL 0x00000633
5407 * MSR_PKGC9_IRTL 0x00000634
5408 * MSR_PKGC10_IRTL 0x00000635
5409 *
d7899447 5410 */
570992fc 5411int has_c8910_msrs(unsigned int family, unsigned int model)
ca58710f
KCA		 5412{
5413 if (!genuine_intel)
5414 return 0;
5415
9878bf7a
LB		 5416 if (family != 6)
5417 return 0;
5418
ca58710f 5419 switch (model) {
77e5517c 5420 case INTEL_FAM6_HASWELL_L: /* HSW */
c66f78a6 5421 case INTEL_FAM6_BROADWELL: /* BDW */
af239c44
PZ		 5422 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5423 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
869ce69e 5424 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5425 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
f6708400 5426 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
0b2bb692
LB		 5427 return 1;
5428 }
5429 return 0;
5430}
5431
5432/*
5433 * SKL adds support for additional MSRS:
5434 *
5435 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
5436 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
5437 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
5438 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
5439 */
5440int has_skl_msrs(unsigned int family, unsigned int model)
5441{
5442 if (!genuine_intel)
5443 return 0;
5444
9878bf7a
LB		 5445 if (family != 6)
5446 return 0;
5447
0b2bb692 5448 switch (model) {
af239c44
PZ		 5449 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5450 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
ca58710f
KCA		 5451 return 1;
5452 }
5453 return 0;
5454}
5455
144b44b1
LB		 5456int is_slm(unsigned int family, unsigned int model)
5457{
5458 if (!genuine_intel)
5459 return 0;
9878bf7a
LB		 5460
5461 if (family != 6)
5462 return 0;
5463
144b44b1 5464 switch (model) {
f2c4db1b 5465 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5ebb34ed 5466 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
144b44b1
LB		 5467 return 1;
5468 }
5469 return 0;
5470}
5471
fb5d4327
DC		 5472int is_knl(unsigned int family, unsigned int model)
5473{
5474 if (!genuine_intel)
5475 return 0;
9878bf7a
LB		 5476
5477 if (family != 6)
5478 return 0;
5479
fb5d4327 5480 switch (model) {
869ce69e 5481 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
fb5d4327
DC		 5482 return 1;
5483 }
5484 return 0;
5485}
5486
997e5395
SP		 5487int is_cnl(unsigned int family, unsigned int model)
5488{
5489 if (!genuine_intel)
5490 return 0;
5491
9878bf7a
LB		 5492 if (family != 6)
5493 return 0;
5494
997e5395 5495 switch (model) {
1b439f01 5496 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
997e5395
SP		 5497 return 1;
5498 }
5499
5500 return 0;
5501}
5502
b2b34dfe
HC		 5503unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
5504{
5505 if (is_knl(family, model))
5506 return 1024;
5507 return 1;
5508}
5509
7ab5ff49
ZR		 5510int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5511{
5512 unsigned int eax, ebx, ecx, edx;
5513
9878bf7a
LB		 5514 UNUSED(c);
5515 UNUSED(p);
5516
7ab5ff49
ZR		 5517 if (!genuine_intel)
5518 return 0;
5519
5520 if (cpu_migrate(t->cpu_id)) {
5521 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id);
5522 return -1;
5523 }
5524
5525 if (max_level < 0x1a)
5526 return 0;
5527
5528 __cpuid(0x1a, eax, ebx, ecx, edx);
5529 eax = (eax >> 24) & 0xFF;
1b439f01 5530 if (eax == 0x20)
7ab5ff49
ZR		 5531 t->is_atom = true;
5532 return 0;
5533}
5534
889facbe
LB		 5535/*
5536 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
5537 * the Thermal Control Circuit (TCC) activates.
5538 * This is usually equal to tjMax.
5539 *
5540 * Older processors do not have this MSR, so there we guess,
5541 * but also allow cmdline over-ride with -T.
5542 *
5543 * Several MSR temperature values are in units of degrees-C
5544 * below this value, including the Digital Thermal Sensor (DTS),
5545 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
5546 */
b2b94be7 5547int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
889facbe
LB		 5548{
5549 unsigned long long msr;
55279aef 5550 unsigned int tcc_default, tcc_offset;
b2b94be7 5551 int cpu;
6ff7cb37 5552
9878bf7a
LB		 5553 UNUSED(c);
5554 UNUSED(p);
5555
55279aef 5556 /* tj_max is used only for dts or ptm */
889facbe
LB		 5557 if (!(do_dts || do_ptm))
5558 return 0;
5559
5560 /* this is a per-package concept */
5561 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
5562 return 0;
5563
b2b94be7
LB		 5564 cpu = t->cpu_id;
5565 if (cpu_migrate(cpu)) {
5566 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
5567 return -1;
5568 }
5569
55279aef
ZR		 5570 if (tj_max_override != 0) {
5571 tj_max = tj_max_override;
1b439f01 5572 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max);
889facbe
LB		 5573 return 0;
5574 }
5575
b2b94be7 5576 /* Temperature Target MSR is Nehalem and newer only */
fcfa1ce0 5577 if (!platform->has_nhm_msrs)
b2b94be7
LB		 5578 goto guess;
5579
5580 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
5581 goto guess;
5582
55279aef 5583 tcc_default = (msr >> 16) & 0xFF;
b2b94be7 5584
0b9a0b9b
ZR		 5585 if (!quiet) {
5586 switch (tcc_offset_bits) {
5587 case 4:
5588 tcc_offset = (msr >> 24) & 0xF;
5589 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
1b439f01 5590 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
0b9a0b9b
ZR		 5591 break;
5592 case 6:
5593 tcc_offset = (msr >> 24) & 0x3F;
5594 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
1b439f01 5595 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
0b9a0b9b
ZR		 5596 break;
5597 default:
1b439f01 5598 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default);
0b9a0b9b
ZR		 5599 break;
5600 }
5601 }
b2b94be7 5602
55279aef 5603 if (!tcc_default)
b2b94be7
LB		 5604 goto guess;
5605
55279aef 5606 tj_max = tcc_default;
b2b94be7
LB		 5607
5608 return 0;
889facbe 5609
b2b94be7 5610guess:
55279aef 5611 tj_max = TJMAX_DEFAULT;
1b439f01 5612 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max);
889facbe
LB		 5613
5614 return 0;
5615}
69807a63 5616
aa8d8cc7
LB		 5617void decode_feature_control_msr(void)
5618{
5619 unsigned long long msr;
5620
f6505c88 5621 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
aa8d8cc7 5622 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
1b439f01 5623 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");
aa8d8cc7
LB		 5624}
5625
69807a63
LB		 5626void decode_misc_enable_msr(void)
5627{
5628 unsigned long long msr;
5629
f26b1519
LB		 5630 if (!genuine_intel)
5631 return;
5632
69807a63 5633 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
e6512624 5634 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
69807a63 5635 base_cpu, msr,
e6512624
LB		 5636 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
5637 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
fd3933ca 5638 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
e6512624
LB		 5639 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
5640 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
69807a63
LB		 5641}
5642
33148d67
LB		 5643void decode_misc_feature_control(void)
5644{
5645 unsigned long long msr;
5646
778fc34a 5647 if (!platform->has_msr_misc_feature_control)
33148d67
LB		 5648 return;
5649
5650 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
1b439f01
LB		 5651 fprintf(outf,
5652 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
5653 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "",
5654 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");
33148d67 5655}
1b439f01 5656
f0057310
LB		 5657/*
5658 * Decode MSR_MISC_PWR_MGMT
5659 *
5660 * Decode the bits according to the Nehalem documentation
5661 * bit[0] seems to continue to have same meaning going forward
5662 * bit[1] less so...
5663 */
5664void decode_misc_pwr_mgmt_msr(void)
5665{
5666 unsigned long long msr;
5667
3dd0e754 5668 if (!platform->has_msr_misc_pwr_mgmt)
cf4cbe53
LB		 5669 return;
5670
f0057310 5671 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
ddadb8ad 5672 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
f0057310 5673 base_cpu, msr,
1b439f01 5674 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");
f0057310 5675}
1b439f01 5676
71616c8e
LB		 5677/*
5678 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
5679 *
5680 * This MSRs are present on Silvermont processors,
5681 * Intel Atom processor E3000 series (Baytrail), and friends.
5682 */
5683void decode_c6_demotion_policy_msr(void)
5684{
5685 unsigned long long msr;
5686
5687 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
5688 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
5689 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5690
5691 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
5692 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
5693 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5694}
7f5c258e 5695
f5a4c76a
LB		 5696/*
5697 * When models are the same, for the purpose of turbostat, reuse
5698 */
5699unsigned int intel_model_duplicates(unsigned int model)
5700{
5701
1b439f01 5702 switch (model) {
f5a4c76a 5703 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
6d306d6e 5704 case INTEL_FAM6_NEHALEM_G: /* Core i7 and i5 Processor - Nehalem */
f5a4c76a
LB		 5705 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
5706 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
5707 return INTEL_FAM6_NEHALEM;
5708
f5a4c76a
LB		 5709 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
5710 return INTEL_FAM6_NEHALEM_EX;
5711
5712 case INTEL_FAM6_XEON_PHI_KNM:
5713 return INTEL_FAM6_XEON_PHI_KNL;
5714
5ebb34ed 5715 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
f5a4c76a
LB		 5716 return INTEL_FAM6_BROADWELL_X;
5717
c66f78a6 5718 case INTEL_FAM6_SKYLAKE:
af239c44 5719 case INTEL_FAM6_KABYLAKE_L:
c66f78a6 5720 case INTEL_FAM6_KABYLAKE:
081c5432
CY		 5721 case INTEL_FAM6_COMETLAKE_L:
5722 case INTEL_FAM6_COMETLAKE:
af239c44 5723 return INTEL_FAM6_SKYLAKE_L;
937807d3 5724
af239c44 5725 case INTEL_FAM6_ICELAKE_L:
d93ea567 5726 case INTEL_FAM6_ICELAKE_NNPI:
4bf7132a
CY		 5727 case INTEL_FAM6_TIGERLAKE_L:
5728 case INTEL_FAM6_TIGERLAKE:
e7af1ed3
LB		 5729 case INTEL_FAM6_ROCKETLAKE:
5730 case INTEL_FAM6_LAKEFIELD:
5731 case INTEL_FAM6_ALDERLAKE:
5683460b 5732 case INTEL_FAM6_ALDERLAKE_L:
882cdb06 5733 case INTEL_FAM6_ATOM_GRACEMONT:
fb5e29df 5734 case INTEL_FAM6_RAPTORLAKE:
6f9cf553 5735 case INTEL_FAM6_RAPTORLAKE_P:
9b1c2ecf 5736 case INTEL_FAM6_RAPTORLAKE_S:
8e45a9bf
ZR		 5737 case INTEL_FAM6_METEORLAKE:
5738 case INTEL_FAM6_METEORLAKE_L:
af239c44 5739 return INTEL_FAM6_CANNONLAKE_L;
b62b3184 5740
d7814c30
CY		 5741 case INTEL_FAM6_ATOM_TREMONT_L:
5742 return INTEL_FAM6_ATOM_TREMONT;
5743
6c5c6560 5744 case INTEL_FAM6_ICELAKE_D:
25368d7c 5745 return INTEL_FAM6_ICELAKE_X;
93cac415
ZR		 5746
5747 case INTEL_FAM6_EMERALDRAPIDS_X:
5748 return INTEL_FAM6_SAPPHIRERAPIDS_X;
f5a4c76a
LB		 5749 }
5750 return model;
5751}
d76bb7a0
LB		 5752
5753void print_dev_latency(void)
5754{
5755 char *path = "/dev/cpu_dma_latency";
5756 int fd;
5757 int value;
5758 int retval;
5759
5760 fd = open(path, O_RDONLY);
5761 if (fd < 0) {
de7839ee 5762 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
d76bb7a0
LB		 5763 return;
5764 }
5765
5766 retval = read(fd, (void *)&value, sizeof(int));
5767 if (retval != sizeof(int)) {
6cbfedc7 5768 warn("read failed %s", path);
d76bb7a0
LB		 5769 close(fd);
5770 return;
5771 }
1b439f01 5772 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained");
d76bb7a0
LB		 5773
5774 close(fd);
5775}
5776
2af4f9b8 5777/*
2db0e5eb 5778 * Linux-perf manages the HW instructions-retired counter
2af4f9b8
LB		 5779 * by enabling when requested, and hiding rollover
5780 */
5781void linux_perf_init(void)
5782{
5783 if (!BIC_IS_ENABLED(BIC_IPC))
5784 return;
5785
5786 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK))
5787 return;
5788
5789 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5790 if (fd_instr_count_percpu == NULL)
5791 err(-1, "calloc fd_instr_count_percpu");
5792
5793 BIC_PRESENT(BIC_IPC);
5794}
5795
fcd17211 5796void process_cpuid()
103a8fea 5797{
34041551
LB		 5798 unsigned int eax, ebx, ecx, edx;
5799 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
ed0757b8 5800 unsigned long long ucode_patch = 0;
103a8fea
LB		 5801
5802 eax = ebx = ecx = edx = 0;
5803
5aea2f7f 5804 __cpuid(0, max_level, ebx, ecx, edx);
103a8fea 5805
34041551 5806 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
103a8fea 5807 genuine_intel = 1;
34041551
LB		 5808 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
5809 authentic_amd = 1;
c1c10cc7
PW		 5810 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
5811 hygon_genuine = 1;
103a8fea 5812
96e47158 5813 if (!quiet)
ed0757b8
LB		 5814 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n",
5815 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level);
103a8fea 5816
5aea2f7f 5817 __cpuid(1, fms, ebx, ecx, edx);
103a8fea
LB		 5818 family = (fms >> 8) & 0xf;
5819 model = (fms >> 4) & 0xf;
5820 stepping = fms & 0xf;
5aa3d1a2
CW		 5821 if (family == 0xf)
5822 family += (fms >> 20) & 0xff;
5823 if (family >= 6)
103a8fea 5824 model += ((fms >> 16) & 0xf) << 4;
34041551
LB		 5825 ecx_flags = ecx;
5826 edx_flags = edx;
103a8fea 5827
ed0757b8 5828 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
6cbfedc7 5829 warnx("get_msr(UCODE)");
ed0757b8 5830
103a8fea
LB		 5831 /*
5832 * check max extended function levels of CPUID.
5833 * This is needed to check for invariant TSC.
5834 * This check is valid for both Intel and AMD.
5835 */
5836 ebx = ecx = edx = 0;
5aea2f7f 5837 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
103a8fea 5838
34041551 5839 if (!quiet) {
ed0757b8 5840 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n",
1b439f01
LB		 5841 family, model, stepping, family, model, stepping,
5842 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));
ed0757b8 5843 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);
34041551
LB		 5844 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
5845 ecx_flags & (1 << 0) ? "SSE3" : "-",
5846 ecx_flags & (1 << 3) ? "MONITOR" : "-",
5847 ecx_flags & (1 << 6) ? "SMX" : "-",
5848 ecx_flags & (1 << 7) ? "EIST" : "-",
5849 ecx_flags & (1 << 8) ? "TM2" : "-",
5850 edx_flags & (1 << 4) ? "TSC" : "-",
5851 edx_flags & (1 << 5) ? "MSR" : "-",
5852 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
1b439f01 5853 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-");
34041551 5854 }
b98a6d78 5855
45232ab1 5856 probe_platform_features(family, model);
b98a6d78 5857 if (genuine_intel)
f5a4c76a 5858 model = intel_model_duplicates(model);
34041551
LB		 5859
5860 if (!(edx_flags & (1 << 5)))
5861 errx(1, "CPUID: no MSR");
5862
61a87ba7 5863 if (max_extended_level >= 0x80000007) {
103a8fea 5864
d7899447
LB		 5865 /*
5866 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
5867 * this check is valid for both Intel and AMD
5868 */
5aea2f7f 5869 __cpuid(0x80000007, eax, ebx, ecx, edx);
d7899447
LB		 5870 has_invariant_tsc = edx & (1 << 8);
5871 }
103a8fea
LB		 5872
5873 /*
5874 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
5875 * this check is valid for both Intel and AMD
5876 */
5877
5aea2f7f 5878 __cpuid(0x6, eax, ebx, ecx, edx);
8209e054 5879 has_aperf = ecx & (1 << 0);
812db3f7
LB		 5880 if (has_aperf) {
5881 BIC_PRESENT(BIC_Avg_MHz);
5882 BIC_PRESENT(BIC_Busy);
5883 BIC_PRESENT(BIC_Bzy_MHz);
5884 }
889facbe 5885 do_dts = eax & (1 << 0);
812db3f7
LB		 5886 if (do_dts)
5887 BIC_PRESENT(BIC_CoreTmp);
b3a34e93 5888 has_turbo = eax & (1 << 1);
889facbe 5889 do_ptm = eax & (1 << 6);
812db3f7
LB		 5890 if (do_ptm)
5891 BIC_PRESENT(BIC_PkgTmp);
7f5c258e
LB		 5892 has_hwp = eax & (1 << 7);
5893 has_hwp_notify = eax & (1 << 8);
5894 has_hwp_activity_window = eax & (1 << 9);
5895 has_hwp_epp = eax & (1 << 10);
5896 has_hwp_pkg = eax & (1 << 11);
889facbe
LB		 5897 has_epb = ecx & (1 << 3);
5898
96e47158 5899 if (!quiet)
b3a34e93 5900 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
7f5c258e
LB		 5901 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
5902 has_aperf ? "" : "No-",
b3a34e93 5903 has_turbo ? "" : "No-",
7f5c258e
LB		 5904 do_dts ? "" : "No-",
5905 do_ptm ? "" : "No-",
5906 has_hwp ? "" : "No-",
5907 has_hwp_notify ? "" : "No-",
5908 has_hwp_activity_window ? "" : "No-",
1b439f01 5909 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-");
103a8fea 5910
96e47158 5911 if (!quiet)
69807a63
LB		 5912 decode_misc_enable_msr();
5913
96e47158 5914 if (max_level >= 0x7 && !quiet) {
aa8d8cc7 5915 int has_sgx;
103a8fea 5916
aa8d8cc7
LB		 5917 ecx = 0;
5918
5919 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
5920
5921 has_sgx = ebx & (1 << 2);
774627c5
LB		 5922
5923 is_hybrid = edx & (1 << 15);
5924
5925 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-");
aa8d8cc7
LB		 5926
5927 if (has_sgx)
5928 decode_feature_control_msr();
5929 }
5930
61a87ba7 5931 if (max_level >= 0x15) {
8a5bdf41
LB		 5932 unsigned int eax_crystal;
5933 unsigned int ebx_tsc;
5934
5935 /*
5936 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
5937 */
5938 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5aea2f7f 5939 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
8a5bdf41
LB		 5940
5941 if (ebx_tsc != 0) {
5942
96e47158 5943 if (!quiet && (ebx != 0))
b7d8c148 5944 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
8a5bdf41
LB		 5945 eax_crystal, ebx_tsc, crystal_hz);
5946
5947 if (crystal_hz == 0)
1b439f01 5948 switch (model) {
af239c44 5949 case INTEL_FAM6_SKYLAKE_L: /* SKL */
e8efbc80
LB		 5950 crystal_hz = 24000000; /* 24.0 MHz */
5951 break;
5ebb34ed 5952 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
ec53e594
LB		 5953 crystal_hz = 25000000; /* 25.0 MHz */
5954 break;
869ce69e 5955 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5956 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
e8efbc80 5957 crystal_hz = 19200000; /* 19.2 MHz */
8a5bdf41
LB		 5958 break;
5959 default:
5960 crystal_hz = 0;
1b439f01 5961 }
8a5bdf41
LB		 5962
5963 if (crystal_hz) {
1b439f01 5964 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal;
96e47158 5965 if (!quiet)
b7d8c148 5966 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
1b439f01 5967 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
8a5bdf41
LB		 5968 }
5969 }
5970 }
61a87ba7
LB		 5971 if (max_level >= 0x16) {
5972 unsigned int base_mhz, max_mhz, bus_mhz, edx;
5973
5974 /*
5975 * CPUID 16H Base MHz, Max MHz, Bus MHz
5976 */
5977 base_mhz = max_mhz = bus_mhz = edx = 0;
5978
5aea2f7f 5979 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
96e47158 5980 if (!quiet)
b7d8c148 5981 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
61a87ba7
LB		 5982 base_mhz, max_mhz, bus_mhz);
5983 }
8a5bdf41 5984
b2b34dfe
HC		 5985 if (has_aperf)
5986 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
5987
812db3f7
LB		 5988 BIC_PRESENT(BIC_IRQ);
5989 BIC_PRESENT(BIC_TSC_MHz);
5990
3989fc89 5991 probe_cst_limit();
fcfa1ce0 5992 if (platform->has_nhm_msrs) {
812db3f7
LB		 5993 BIC_PRESENT(BIC_CPU_c1);
5994 BIC_PRESENT(BIC_CPU_c3);
5995 BIC_PRESENT(BIC_CPU_c6);
5996 BIC_PRESENT(BIC_SMI);
5997 }
71e84129 5998 probe_bclk();
d7899447 5999 do_snb_cstates = has_snb_msrs(family, model);
812db3f7
LB		 6000
6001 if (do_snb_cstates)
6002 BIC_PRESENT(BIC_CPU_c7);
6003
5a63426e 6004 do_irtl_snb = has_snb_msrs(family, model);
0f47c08d
LB		 6005 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
6006 BIC_PRESENT(BIC_Pkgpc2);
6007 if (pkg_cstate_limit >= PCL__3)
6008 BIC_PRESENT(BIC_Pkgpc3);
6009 if (pkg_cstate_limit >= PCL__6)
6010 BIC_PRESENT(BIC_Pkgpc6);
6011 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
6012 BIC_PRESENT(BIC_Pkgpc7);
0539ba11 6013 if (has_slv_msrs(family, model)) {
0f47c08d
LB		 6014 BIC_NOT_PRESENT(BIC_Pkgpc2);
6015 BIC_NOT_PRESENT(BIC_Pkgpc3);
6016 BIC_PRESENT(BIC_Pkgpc6);
6017 BIC_NOT_PRESENT(BIC_Pkgpc7);
0539ba11
LB		 6018 BIC_PRESENT(BIC_Mod_c6);
6019 use_c1_residency_msr = 1;
6020 }
20de0dab
AL		 6021 if (is_jvl(family, model)) {
6022 BIC_NOT_PRESENT(BIC_CPU_c3);
6023 BIC_NOT_PRESENT(BIC_CPU_c7);
6024 BIC_NOT_PRESENT(BIC_Pkgpc2);
6025 BIC_NOT_PRESENT(BIC_Pkgpc3);
6026 BIC_NOT_PRESENT(BIC_Pkgpc6);
6027 BIC_NOT_PRESENT(BIC_Pkgpc7);
6028 }
7170a374
LB		 6029 if (is_dnv(family, model)) {
6030 BIC_PRESENT(BIC_CPU_c1);
6031 BIC_NOT_PRESENT(BIC_CPU_c3);
6032 BIC_NOT_PRESENT(BIC_Pkgpc3);
6033 BIC_NOT_PRESENT(BIC_CPU_c7);
6034 BIC_NOT_PRESENT(BIC_Pkgpc7);
6035 use_c1_residency_msr = 1;
6036 }
684e40e9 6037 if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) {
34c76197
LB		 6038 BIC_NOT_PRESENT(BIC_CPU_c3);
6039 BIC_NOT_PRESENT(BIC_Pkgpc3);
6040 BIC_NOT_PRESENT(BIC_CPU_c7);
6041 BIC_NOT_PRESENT(BIC_Pkgpc7);
6042 }
ade0ebac
LB		 6043 if (is_bdx(family, model)) {
6044 BIC_NOT_PRESENT(BIC_CPU_c7);
6045 BIC_NOT_PRESENT(BIC_Pkgpc7);
6046 }
570992fc 6047 if (has_c8910_msrs(family, model)) {
c315a09b
LB		 6048 if (pkg_cstate_limit >= PCL__8)
6049 BIC_PRESENT(BIC_Pkgpc8);
6050 if (pkg_cstate_limit >= PCL__9)
6051 BIC_PRESENT(BIC_Pkgpc9);
6052 if (pkg_cstate_limit >= PCL_10)
6053 BIC_PRESENT(BIC_Pkgpc10);
0f47c08d 6054 }
570992fc 6055 do_irtl_hsw = has_c8910_msrs(family, model);
a99d8730
LB		 6056 if (has_skl_msrs(family, model)) {
6057 BIC_PRESENT(BIC_Totl_c0);
6058 BIC_PRESENT(BIC_Any_c0);
6059 BIC_PRESENT(BIC_GFX_c0);
6060 BIC_PRESENT(BIC_CPUGFX);
6061 }
144b44b1 6062 do_slm_cstates = is_slm(family, model);
1b439f01 6063 do_knl_cstates = is_knl(family, model);
103a8fea 6064
1b439f01 6065 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model))
562855ee 6066 BIC_NOT_PRESENT(BIC_CPU_c3);
103a8fea 6067
96e47158 6068 if (!quiet)
f0057310
LB		 6069 decode_misc_pwr_mgmt_msr();
6070
96e47158 6071 if (!quiet && has_slv_msrs(family, model))
71616c8e
LB		 6072 decode_c6_demotion_policy_msr();
6073
889facbe 6074 rapl_probe(family, model);
3a9a941d 6075 perf_limit_reasons_probe(family, model);
ac980e13 6076 automatic_cstate_conversion_probe(family, model);
b61b7d8c 6077 prewake_cstate_probe(family, model);
889facbe 6078
b98a6d78 6079 check_tcc_offset(model);
0b9a0b9b 6080
96e47158 6081 if (!quiet)
1b69317d 6082 dump_cstate_pstate_config_info(family, model);
a5c6d65d 6083 intel_uncore_frequency_probe();
fcd17211 6084
d76bb7a0
LB		 6085 if (!quiet)
6086 print_dev_latency();
41618e63
LB		 6087 if (!quiet)
6088 dump_sysfs_cstate_config();
7293fccd
LB		 6089 if (!quiet)
6090 dump_sysfs_pstate_config();
41618e63 6091
8c69da29 6092 if (has_skl_msrs(family, model) || is_ehl(family, model))
a2b7b749
LB		 6093 calculate_tsc_tweak();
6094
812db3f7
LB		 6095 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
6096 BIC_PRESENT(BIC_GFX_rc6);
fdf676e5 6097
2c019d65
ZR		 6098 if (!access("/sys/class/drm/card0/gt_cur_freq_mhz", R_OK) ||
6099 !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
812db3f7 6100 BIC_PRESENT(BIC_GFXMHz);
27d47356 6101
2c019d65
ZR		 6102 if (!access("/sys/class/drm/card0/gt_act_freq_mhz", R_OK) ||
6103 !access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK))
b4b91569
RA		 6104 BIC_PRESENT(BIC_GFXACTMHz);
6105
be0e54c4
LB		 6106 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
6107 BIC_PRESENT(BIC_CPU_LPI);
6108 else
6109 BIC_NOT_PRESENT(BIC_CPU_LPI);
6110
eae97e05
CY		 6111 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK))
6112 BIC_PRESENT(BIC_CORE_THROT_CNT);
6113 else
6114 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT);
6115
1f81c5ef
LB		 6116 if (!access(sys_lpi_file_sysfs, R_OK)) {
6117 sys_lpi_file = sys_lpi_file_sysfs;
be0e54c4 6118 BIC_PRESENT(BIC_SYS_LPI);
1f81c5ef
LB		 6119 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
6120 sys_lpi_file = sys_lpi_file_debugfs;
6121 BIC_PRESENT(BIC_SYS_LPI);
6122 } else {
6123 sys_lpi_file_sysfs = NULL;
be0e54c4 6124 BIC_NOT_PRESENT(BIC_SYS_LPI);
1f81c5ef 6125 }
be0e54c4 6126
96e47158 6127 if (!quiet)
33148d67
LB		 6128 decode_misc_feature_control();
6129
889facbe 6130 return;
103a8fea
LB		 6131}
6132
103a8fea
LB		 6133/*
6134 * in /dev/cpu/ return success for names that are numbers
6135 * ie. filter out ".", "..", "microcode".
6136 */
6137int dir_filter(const struct dirent *dirp)
6138{
6139 if (isdigit(dirp->d_name[0]))
6140 return 1;
6141 else
6142 return 0;
6143}
6144
c98d5d94
LB		 6145void topology_probe()
6146{
6147 int i;
6148 int max_core_id = 0;
6149 int max_package_id = 0;
6de68fe1 6150 int max_die_id = 0;
c98d5d94 6151 int max_siblings = 0;
c98d5d94
LB		 6152
6153 /* Initialize num_cpus, max_cpu_num */
843c5791 6154 set_max_cpu_num();
c98d5d94 6155 topo.num_cpus = 0;
c98d5d94
LB		 6156 for_all_proc_cpus(count_cpus);
6157 if (!summary_only && topo.num_cpus > 1)
812db3f7 6158 BIC_PRESENT(BIC_CPU);
c98d5d94 6159
d8af6f5f 6160 if (debug > 1)
b7d8c148 6161 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
c98d5d94 6162
1b439f01 6163 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
b2c95d90
JT		 6164 if (cpus == NULL)
6165 err(1, "calloc cpus");
c98d5d94
LB		 6166
6167 /*
6168 * Allocate and initialize cpu_present_set
6169 */
6170 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 6171 if (cpu_present_set == NULL)
6172 err(3, "CPU_ALLOC");
c98d5d94
LB		 6173 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
6174 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
6175 for_all_proc_cpus(mark_cpu_present);
6176
1ef7d21a
LB		 6177 /*
6178 * Validate that all cpus in cpu_subset are also in cpu_present_set
6179 */
6180 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
6181 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
6182 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
6183 err(1, "cpu%d not present", i);
6184 }
6185
c98d5d94
LB		 6186 /*
6187 * Allocate and initialize cpu_affinity_set
6188 */
6189 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 6190 if (cpu_affinity_set == NULL)
6191 err(3, "CPU_ALLOC");
c98d5d94
LB		 6192 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
6193 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
6194
8cb48b32 6195 for_all_proc_cpus(init_thread_id);
c98d5d94
LB		 6196
6197 /*
6198 * For online cpus
6199 * find max_core_id, max_package_id
6200 */
6201 for (i = 0; i <= topo.max_cpu_num; ++i) {
6202 int siblings;
6203
6204 if (cpu_is_not_present(i)) {
d8af6f5f 6205 if (debug > 1)
b7d8c148 6206 fprintf(outf, "cpu%d NOT PRESENT\n", i);
c98d5d94
LB		 6207 continue;
6208 }
c98d5d94 6209
0e2d8f05
LB		 6210 cpus[i].logical_cpu_id = i;
6211
6212 /* get package information */
c98d5d94
LB		 6213 cpus[i].physical_package_id = get_physical_package_id(i);
6214 if (cpus[i].physical_package_id > max_package_id)
6215 max_package_id = cpus[i].physical_package_id;
6216
6de68fe1
LB		 6217 /* get die information */
6218 cpus[i].die_id = get_die_id(i);
6219 if (cpus[i].die_id > max_die_id)
6220 max_die_id = cpus[i].die_id;
6221
0e2d8f05 6222 /* get numa node information */
ef605741
PB		 6223 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
6224 if (cpus[i].physical_node_id > topo.max_node_num)
6225 topo.max_node_num = cpus[i].physical_node_id;
0e2d8f05
LB		 6226
6227 /* get core information */
6228 cpus[i].physical_core_id = get_core_id(i);
6229 if (cpus[i].physical_core_id > max_core_id)
6230 max_core_id = cpus[i].physical_core_id;
6231
6232 /* get thread information */
6233 siblings = get_thread_siblings(&cpus[i]);
c98d5d94
LB		 6234 if (siblings > max_siblings)
6235 max_siblings = siblings;
4f206a0f 6236 if (cpus[i].thread_id == 0)
8cb48b32 6237 topo.num_cores++;
c98d5d94 6238 }
ef605741 6239
70a9c6e8 6240 topo.cores_per_node = max_core_id + 1;
d8af6f5f 6241 if (debug > 1)
1b439f01 6242 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node);
70a9c6e8 6243 if (!summary_only && topo.cores_per_node > 1)
812db3f7 6244 BIC_PRESENT(BIC_Core);
c98d5d94 6245
6de68fe1
LB		 6246 topo.num_die = max_die_id + 1;
6247 if (debug > 1)
1b439f01 6248 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die);
6de68fe1
LB		 6249 if (!summary_only && topo.num_die > 1)
6250 BIC_PRESENT(BIC_Die);
6251
c98d5d94 6252 topo.num_packages = max_package_id + 1;
d8af6f5f 6253 if (debug > 1)
1b439f01 6254 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages);
7da6e3e2 6255 if (!summary_only && topo.num_packages > 1)
812db3f7 6256 BIC_PRESENT(BIC_Package);
c98d5d94 6257
ef605741
PB		 6258 set_node_data();
6259 if (debug > 1)
70a9c6e8 6260 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
01235041
PB		 6261 if (!summary_only && topo.nodes_per_pkg > 1)
6262 BIC_PRESENT(BIC_Node);
ef605741 6263
70a9c6e8 6264 topo.threads_per_core = max_siblings;
d8af6f5f 6265 if (debug > 1)
b7d8c148 6266 fprintf(outf, "max_siblings %d\n", max_siblings);
2ffbb224
PB		 6267
6268 if (debug < 1)
6269 return;
6270
6271 for (i = 0; i <= topo.max_cpu_num; ++i) {
0ec712e3
LB		 6272 if (cpu_is_not_present(i))
6273 continue;
2ffbb224 6274 fprintf(outf,
6de68fe1
LB		 6275 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
6276 i, cpus[i].physical_package_id, cpus[i].die_id,
1b439f01 6277 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id);
2ffbb224
PB		 6278 }
6279
c98d5d94
LB		 6280}
6281
1b439f01 6282void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
c98d5d94
LB		 6283{
6284 int i;
1b439f01 6285 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages;
40f5cfe7 6286 int num_threads = topo.threads_per_core * num_cores;
c98d5d94 6287
40f5cfe7 6288 *t = calloc(num_threads, sizeof(struct thread_data));
c98d5d94
LB		 6289 if (*t == NULL)
6290 goto error;
6291
40f5cfe7 6292 for (i = 0; i < num_threads; i++)
c98d5d94
LB		 6293 (*t)[i].cpu_id = -1;
6294
40f5cfe7 6295 *c = calloc(num_cores, sizeof(struct core_data));
c98d5d94
LB		 6296 if (*c == NULL)
6297 goto error;
6298
40f5cfe7 6299 for (i = 0; i < num_cores; i++)
c98d5d94
LB		 6300 (*c)[i].core_id = -1;
6301
678a3bd1 6302 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
c98d5d94
LB		 6303 if (*p == NULL)
6304 goto error;
6305
6306 for (i = 0; i < topo.num_packages; i++)
6307 (*p)[i].package_id = i;
6308
6309 return;
6310error:
b2c95d90 6311 err(1, "calloc counters");
c98d5d94 6312}
1b439f01 6313
c98d5d94
LB		 6314/*
6315 * init_counter()
6316 *
c98d5d94 6317 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
c98d5d94 6318 */
1b439f01 6319void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id)
c98d5d94 6320{
8cb48b32 6321 int pkg_id = cpus[cpu_id].physical_package_id;
40f5cfe7 6322 int node_id = cpus[cpu_id].logical_node_id;
8cb48b32
PB		 6323 int core_id = cpus[cpu_id].physical_core_id;
6324 int thread_id = cpus[cpu_id].thread_id;
c98d5d94
LB		 6325 struct thread_data *t;
6326 struct core_data *c;
6327 struct pkg_data *p;
6328
42dd4520
NC		 6329 /* Workaround for systems where physical_node_id==-1
6330 * and logical_node_id==(-1 - topo.num_cpus)
6331 */
6332 if (node_id < 0)
6333 node_id = 0;
6334
40f5cfe7
PB		 6335 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
6336 c = GET_CORE(core_base, core_id, node_id, pkg_id);
8cb48b32 6337 p = GET_PKG(pkg_base, pkg_id);
c98d5d94
LB		 6338
6339 t->cpu_id = cpu_id;
8cb48b32 6340 if (thread_id == 0) {
c98d5d94
LB		 6341 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
6342 if (cpu_is_first_core_in_package(cpu_id))
6343 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
6344 }
6345
8cb48b32
PB		 6346 c->core_id = core_id;
6347 p->package_id = pkg_id;
c98d5d94
LB		 6348}
6349
c98d5d94
LB		 6350int initialize_counters(int cpu_id)
6351{
8cb48b32
PB		 6352 init_counter(EVEN_COUNTERS, cpu_id);
6353 init_counter(ODD_COUNTERS, cpu_id);
c98d5d94
LB		 6354 return 0;
6355}
6356
6357void allocate_output_buffer()
6358{
eeb71c95 6359 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
c98d5d94 6360 outp = output_buffer;
b2c95d90
JT		 6361 if (outp == NULL)
6362 err(-1, "calloc output buffer");
c98d5d94 6363}
1b439f01 6364
36229897
LB		 6365void allocate_fd_percpu(void)
6366{
01a67adf 6367 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
36229897
LB		 6368 if (fd_percpu == NULL)
6369 err(-1, "calloc fd_percpu");
6370}
1b439f01 6371
562a2d37
LB		 6372void allocate_irq_buffers(void)
6373{
6374 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
6375 if (irq_column_2_cpu == NULL)
6376 err(-1, "calloc %d", topo.num_cpus);
c98d5d94 6377
01a67adf 6378 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
562a2d37 6379 if (irqs_per_cpu == NULL)
01a67adf 6380 err(-1, "calloc %d", topo.max_cpu_num + 1);
562a2d37 6381}
1b439f01 6382
c98d5d94
LB		 6383void setup_all_buffers(void)
6384{
6385 topology_probe();
562a2d37 6386 allocate_irq_buffers();
36229897 6387 allocate_fd_percpu();
c98d5d94
LB		 6388 allocate_counters(&thread_even, &core_even, &package_even);
6389 allocate_counters(&thread_odd, &core_odd, &package_odd);
6390 allocate_output_buffer();
6391 for_all_proc_cpus(initialize_counters);
6392}
3b4d5c7f 6393
7ce7d5de
PB		 6394void set_base_cpu(void)
6395{
6396 base_cpu = sched_getcpu();
6397 if (base_cpu < 0)
6398 err(-ENODEV, "No valid cpus found");
6399
6400 if (debug > 1)
b7d8c148 6401 fprintf(outf, "base_cpu = %d\n", base_cpu);
7ce7d5de
PB		 6402}
6403
103a8fea
LB		 6404void turbostat_init()
6405{
7ce7d5de
PB		 6406 setup_all_buffers();
6407 set_base_cpu();
103a8fea 6408 check_dev_msr();
98481e79 6409 check_permissions();
fcd17211 6410 process_cpuid();
2af4f9b8 6411 linux_perf_init();
103a8fea 6412
96e47158 6413 if (!quiet)
7f5c258e
LB		 6414 for_all_cpus(print_hwp, ODD_COUNTERS);
6415
96e47158 6416 if (!quiet)
889facbe
LB		 6417 for_all_cpus(print_epb, ODD_COUNTERS);
6418
96e47158 6419 if (!quiet)
3a9a941d
LB		 6420 for_all_cpus(print_perf_limit, ODD_COUNTERS);
6421
96e47158 6422 if (!quiet)
889facbe
LB		 6423 for_all_cpus(print_rapl, ODD_COUNTERS);
6424
6425 for_all_cpus(set_temperature_target, ODD_COUNTERS);
6426
7ab5ff49
ZR		 6427 for_all_cpus(get_cpu_type, ODD_COUNTERS);
6428 for_all_cpus(get_cpu_type, EVEN_COUNTERS);
6429
96e47158 6430 if (!quiet)
889facbe 6431 for_all_cpus(print_thermal, ODD_COUNTERS);
5a63426e 6432
96e47158 6433 if (!quiet && do_irtl_snb)
5a63426e 6434 print_irtl();
164d7a96
LB		 6435
6436 if (DO_BIC(BIC_IPC))
6437 (void)get_instr_count_fd(base_cpu);
103a8fea
LB		 6438}
6439
6440int fork_it(char **argv)
6441{
103a8fea 6442 pid_t child_pid;
d91bb17c 6443 int status;
d15cf7c1 6444
218f0e8d 6445 snapshot_proc_sysfs_files();
d91bb17c 6446 status = for_all_cpus(get_counters, EVEN_COUNTERS);
4c2122d4 6447 first_counter_read = 0;
d91bb17c
LB		 6448 if (status)
6449 exit(status);
c98d5d94
LB		 6450 /* clear affinity side-effect of get_counters() */
6451 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
103a8fea
LB		 6452 gettimeofday(&tv_even, (struct timezone *)NULL);
6453
6454 child_pid = fork();
6455 if (!child_pid) {
6456 /* child */
6457 execvp(argv[0], argv);
0815a3d0 6458 err(errno, "exec %s", argv[0]);
103a8fea 6459 } else {
103a8fea
LB		 6460
6461 /* parent */
b2c95d90
JT		 6462 if (child_pid == -1)
6463 err(1, "fork");
103a8fea
LB		 6464
6465 signal(SIGINT, SIG_IGN);
6466 signal(SIGQUIT, SIG_IGN);
b2c95d90
JT		 6467 if (waitpid(child_pid, &status, 0) == -1)
6468 err(status, "waitpid");
2a954966
DA		 6469
6470 if (WIFEXITED(status))
6471 status = WEXITSTATUS(status);
103a8fea 6472 }
c98d5d94
LB		 6473 /*
6474 * n.b. fork_it() does not check for errors from for_all_cpus()
6475 * because re-starting is problematic when forking
6476 */
218f0e8d 6477 snapshot_proc_sysfs_files();
c98d5d94 6478 for_all_cpus(get_counters, ODD_COUNTERS);
103a8fea 6479 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 6480 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 6481 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
6482 fprintf(outf, "%s: Counter reset detected\n", progname);
6483 else {
6484 compute_average(EVEN_COUNTERS);
6485 format_all_counters(EVEN_COUNTERS);
6486 }
103a8fea 6487
1b439f01 6488 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0);
b7d8c148
LB		 6489
6490 flush_output_stderr();
103a8fea 6491
d91bb17c 6492 return status;
103a8fea
LB		 6493}
6494
3b4d5c7f
AS		 6495int get_and_dump_counters(void)
6496{
6497 int status;
6498
218f0e8d 6499 snapshot_proc_sysfs_files();
3b4d5c7f
AS		 6500 status = for_all_cpus(get_counters, ODD_COUNTERS);
6501 if (status)
6502 return status;
6503
6504 status = for_all_cpus(dump_counters, ODD_COUNTERS);
6505 if (status)
6506 return status;
6507
b7d8c148 6508 flush_output_stdout();
3b4d5c7f
AS		 6509
6510 return status;
6511}
6512
1b439f01
LB		 6513void print_version()
6514{
de7839ee 6515 fprintf(outf, "turbostat version 2023.03.17 - Len Brown <lenb@kernel.org>\n");
d8af6f5f
LB		 6516}
6517
03331233
CY		 6518#define COMMAND_LINE_SIZE 2048
6519
6520void print_bootcmd(void)
6521{
6522 char bootcmd[COMMAND_LINE_SIZE];
6523 FILE *fp;
6524 int ret;
6525
6526 memset(bootcmd, 0, COMMAND_LINE_SIZE);
6527 fp = fopen("/proc/cmdline", "r");
6528 if (!fp)
6529 return;
6530
6531 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp);
6532 if (ret) {
6533 bootcmd[ret] = '\0';
6534 /* the last character is already '\n' */
6535 fprintf(outf, "Kernel command line: %s", bootcmd);
6536 }
6537
6538 fclose(fp);
6539}
6540
495c7654 6541int add_counter(unsigned int msr_num, char *path, char *name,
1b439f01
LB		 6542 unsigned int width, enum counter_scope scope,
6543 enum counter_type type, enum counter_format format, int flags)
388e9c81
LB		 6544{
6545 struct msr_counter *msrp;
6546
6547 msrp = calloc(1, sizeof(struct msr_counter));
6548 if (msrp == NULL) {
6549 perror("calloc");
6550 exit(1);
6551 }
6552
6553 msrp->msr_num = msr_num;
d8d005ba 6554 strncpy(msrp->name, name, NAME_BYTES - 1);
495c7654 6555 if (path)
d8d005ba 6556 strncpy(msrp->path, path, PATH_BYTES - 1);
388e9c81
LB		 6557 msrp->width = width;
6558 msrp->type = type;
6559 msrp->format = format;
41618e63 6560 msrp->flags = flags;
388e9c81
LB		 6561
6562 switch (scope) {
6563
6564 case SCOPE_CPU:
388e9c81
LB		 6565 msrp->next = sys.tp;
6566 sys.tp = msrp;
678a3bd1 6567 sys.added_thread_counters++;
0748eaf0 6568 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
1b439f01 6569 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6570 exit(-1);
6571 }
388e9c81
LB		 6572 break;
6573
6574 case SCOPE_CORE:
388e9c81
LB		 6575 msrp->next = sys.cp;
6576 sys.cp = msrp;
678a3bd1
LB		 6577 sys.added_core_counters++;
6578 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
1b439f01 6579 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6580 exit(-1);
6581 }
388e9c81
LB		 6582 break;
6583
6584 case SCOPE_PACKAGE:
388e9c81
LB		 6585 msrp->next = sys.pp;
6586 sys.pp = msrp;
678a3bd1
LB		 6587 sys.added_package_counters++;
6588 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
1b439f01 6589 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6590 exit(-1);
6591 }
388e9c81
LB		 6592 break;
6593 }
6594
6595 return 0;
6596}
6597
6598void parse_add_command(char *add_command)
6599{
6600 int msr_num = 0;
495c7654 6601 char *path = NULL;
0f47c08d 6602 char name_buffer[NAME_BYTES] = "";
388e9c81
LB		 6603 int width = 64;
6604 int fail = 0;
6605 enum counter_scope scope = SCOPE_CPU;
6606 enum counter_type type = COUNTER_CYCLES;
6607 enum counter_format format = FORMAT_DELTA;
6608
6609 while (add_command) {
6610
6611 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
6612 goto next;
6613
6614 if (sscanf(add_command, "msr%d", &msr_num) == 1)
6615 goto next;
6616
495c7654
LB		 6617 if (*add_command == '/') {
6618 path = add_command;
6619 goto next;
6620 }
6621
388e9c81
LB		 6622 if (sscanf(add_command, "u%d", &width) == 1) {
6623 if ((width == 32) || (width == 64))
6624 goto next;
6625 width = 64;
6626 }
6627 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
6628 scope = SCOPE_CPU;
6629 goto next;
6630 }
6631 if (!strncmp(add_command, "core", strlen("core"))) {
6632 scope = SCOPE_CORE;
6633 goto next;
6634 }
6635 if (!strncmp(add_command, "package", strlen("package"))) {
6636 scope = SCOPE_PACKAGE;
6637 goto next;
6638 }
6639 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
6640 type = COUNTER_CYCLES;
6641 goto next;
6642 }
6643 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
6644 type = COUNTER_SECONDS;
6645 goto next;
6646 }
41618e63
LB		 6647 if (!strncmp(add_command, "usec", strlen("usec"))) {
6648 type = COUNTER_USEC;
6649 goto next;
6650 }
388e9c81
LB		 6651 if (!strncmp(add_command, "raw", strlen("raw"))) {
6652 format = FORMAT_RAW;
6653 goto next;
6654 }
6655 if (!strncmp(add_command, "delta", strlen("delta"))) {
6656 format = FORMAT_DELTA;
6657 goto next;
6658 }
6659 if (!strncmp(add_command, "percent", strlen("percent"))) {
6660 format = FORMAT_PERCENT;
6661 goto next;
6662 }
6663
6664 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
6665 char *eos;
6666
6667 eos = strchr(name_buffer, ',');
6668 if (eos)
6669 *eos = '\0';
6670 goto next;
6671 }
6672
6673next:
6674 add_command = strchr(add_command, ',');
495c7654
LB		 6675 if (add_command) {
6676 *add_command = '\0';
388e9c81 6677 add_command++;
495c7654 6678 }
388e9c81
LB		 6679
6680 }
495c7654
LB		 6681 if ((msr_num == 0) && (path == NULL)) {
6682 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
388e9c81
LB		 6683 fail++;
6684 }
6685
6686 /* generate default column header */
6687 if (*name_buffer == '\0') {
5f3aea57
LB		 6688 if (width == 32)
6689 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6690 else
6691 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
388e9c81
LB		 6692 }
6693
41618e63 6694 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
388e9c81
LB		 6695 fail++;
6696
6697 if (fail) {
6698 help();
6699 exit(1);
6700 }
6701}
41618e63 6702
0fc521bc
ZLCH		 6703int is_deferred_add(char *name)
6704{
6705 int i;
6706
6707 for (i = 0; i < deferred_add_index; ++i)
6708 if (!strcmp(name, deferred_add_names[i]))
6709 return 1;
6710 return 0;
6711}
6712
dd778a5e
LB		 6713int is_deferred_skip(char *name)
6714{
6715 int i;
6716
6717 for (i = 0; i < deferred_skip_index; ++i)
6718 if (!strcmp(name, deferred_skip_names[i]))
6719 return 1;
6720 return 0;
6721}
6722
41618e63
LB		 6723void probe_sysfs(void)
6724{
6725 char path[64];
6726 char name_buf[16];
6727 FILE *input;
6728 int state;
6729 char *sp;
6730
0748eaf0 6731 for (state = 10; state >= 0; --state) {
41618e63 6732
1b439f01 6733 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 6734 input = fopen(path, "r");
6735 if (input == NULL)
6736 continue;
8173c336
BH		 6737 if (!fgets(name_buf, sizeof(name_buf), input))
6738 err(1, "%s: failed to read file", path);
41618e63 6739
1b439f01 6740 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 6741 sp = strchr(name_buf, '-');
6742 if (!sp)
6743 sp = strchrnul(name_buf, '\n');
6744 *sp = '%';
6745 *(sp + 1) = '\0';
6746
fecb3bc8
DA		 6747 remove_underbar(name_buf);
6748
41618e63
LB		 6749 fclose(input);
6750
6751 sprintf(path, "cpuidle/state%d/time", state);
6752
0fc521bc
ZLCH		 6753 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6754 continue;
6755
dd778a5e
LB		 6756 if (is_deferred_skip(name_buf))
6757 continue;
6758
1b439f01 6759 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU);
41618e63
LB		 6760 }
6761
0748eaf0 6762 for (state = 10; state >= 0; --state) {
41618e63 6763
1b439f01 6764 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 6765 input = fopen(path, "r");
6766 if (input == NULL)
6767 continue;
8173c336
BH		 6768 if (!fgets(name_buf, sizeof(name_buf), input))
6769 err(1, "%s: failed to read file", path);
1b439f01 6770 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 6771 sp = strchr(name_buf, '-');
6772 if (!sp)
6773 sp = strchrnul(name_buf, '\n');
6774 *sp = '\0';
6775 fclose(input);
fecb3bc8
DA		 6776
6777 remove_underbar(name_buf);
41618e63
LB		 6778
6779 sprintf(path, "cpuidle/state%d/usage", state);
6780
0fc521bc
ZLCH		 6781 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6782 continue;
6783
dd778a5e
LB		 6784 if (is_deferred_skip(name_buf))
6785 continue;
6786
1b439f01 6787 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU);
41618e63
LB		 6788 }
6789
6790}
6791
1ef7d21a
LB		 6792/*
6793 * parse cpuset with following syntax
6794 * 1,2,4..6,8-10 and set bits in cpu_subset
6795 */
6796void parse_cpu_command(char *optarg)
6797{
6798 unsigned int start, end;
6799 char *next;
6800
4e4e1e7c
LB		 6801 if (!strcmp(optarg, "core")) {
6802 if (cpu_subset)
6803 goto error;
6804 show_core_only++;
6805 return;
6806 }
6807 if (!strcmp(optarg, "package")) {
6808 if (cpu_subset)
6809 goto error;
6810 show_pkg_only++;
6811 return;
6812 }
6813 if (show_core_only || show_pkg_only)
6814 goto error;
6815
1ef7d21a
LB		 6816 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
6817 if (cpu_subset == NULL)
6818 err(3, "CPU_ALLOC");
6819 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
6820
6821 CPU_ZERO_S(cpu_subset_size, cpu_subset);
6822
6823 next = optarg;
6824
6825 while (next && *next) {
6826
6827 if (*next == '-') /* no negative cpu numbers */
6828 goto error;
6829
6830 start = strtoul(next, &next, 10);
6831
6832 if (start >= CPU_SUBSET_MAXCPUS)
6833 goto error;
6834 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6835
6836 if (*next == '\0')
6837 break;
6838
6839 if (*next == ',') {
6840 next += 1;
6841 continue;
6842 }
6843
6844 if (*next == '-') {
6845 next += 1; /* start range */
6846 } else if (*next == '.') {
6847 next += 1;
6848 if (*next == '.')
6849 next += 1; /* start range */
6850 else
6851 goto error;
6852 }
6853
6854 end = strtoul(next, &next, 10);
6855 if (end <= start)
6856 goto error;
6857
6858 while (++start <= end) {
6859 if (start >= CPU_SUBSET_MAXCPUS)
6860 goto error;
6861 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6862 }
6863
6864 if (*next == ',')
6865 next += 1;
6866 else if (*next != '\0')
6867 goto error;
6868 }
6869
6870 return;
6871
6872error:
4e4e1e7c
LB		 6873 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
6874 help();
1ef7d21a
LB		 6875 exit(-1);
6876}
6877
103a8fea
LB		 6878void cmdline(int argc, char **argv)
6879{
6880 int opt;
d8af6f5f
LB		 6881 int option_index = 0;
6882 static struct option long_options[] = {
1b439f01
LB		 6883 { "add", required_argument, 0, 'a' },
6884 { "cpu", required_argument, 0, 'c' },
6885 { "Dump", no_argument, 0, 'D' },
6886 { "debug", no_argument, 0, 'd' }, /* internal, not documented */
6887 { "enable", required_argument, 0, 'e' },
6888 { "interval", required_argument, 0, 'i' },
6889 { "IPC", no_argument, 0, 'I' },
6890 { "num_iterations", required_argument, 0, 'n' },
c7e399f8 6891 { "header_iterations", required_argument, 0, 'N' },
1b439f01
LB		 6892 { "help", no_argument, 0, 'h' },
6893 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help
6894 { "Joules", no_argument, 0, 'J' },
6895 { "list", no_argument, 0, 'l' },
6896 { "out", required_argument, 0, 'o' },
6897 { "quiet", no_argument, 0, 'q' },
6898 { "show", required_argument, 0, 's' },
6899 { "Summary", no_argument, 0, 'S' },
6900 { "TCC", required_argument, 0, 'T' },
6901 { "version", no_argument, 0, 'v' },
6902 { 0, 0, 0, 0 }
d8af6f5f 6903 };
103a8fea
LB		 6904
6905 progname = argv[0];
6906
1b439f01 6907 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) {
103a8fea 6908 switch (opt) {
388e9c81
LB		 6909 case 'a':
6910 parse_add_command(optarg);
6911 break;
1ef7d21a
LB		 6912 case 'c':
6913 parse_cpu_command(optarg);
6914 break;
d8af6f5f 6915 case 'D':
3b4d5c7f
AS		 6916 dump_only++;
6917 break;
3f44a5c6
LB		 6918 case 'e':
6919 /* --enable specified counter */
4c2122d4 6920 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
3f44a5c6 6921 break;
d8af6f5f
LB		 6922 case 'd':
6923 debug++;
3f44a5c6 6924 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
103a8fea 6925 break;
812db3f7 6926 case 'H':
3f44a5c6
LB		 6927 /*
6928 * --hide: do not show those specified
6929 * multiple invocations simply clear more bits in enabled mask
6930 */
6931 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
812db3f7 6932 break;
d8af6f5f
LB		 6933 case 'h':
6934 default:
6935 help();
6936 exit(1);
103a8fea 6937 case 'i':
2a0609c0
LB		 6938 {
6939 double interval = strtod(optarg, NULL);
6940
6941 if (interval < 0.001) {
1b439f01 6942 fprintf(outf, "interval %f seconds is too small\n", interval);
2a0609c0
LB		 6943 exit(2);
6944 }
6945
47936f94 6946 interval_tv.tv_sec = interval_ts.tv_sec = interval;
b9ad8ee0 6947 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
47936f94 6948 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
2a0609c0 6949 }
103a8fea 6950 break;
d8af6f5f
LB		 6951 case 'J':
6952 rapl_joules++;
8e180f3c 6953 break;
c8ade361 6954 case 'l':
3f44a5c6 6955 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
c8ade361
LB		 6956 list_header_only++;
6957 quiet++;
6958 break;
b7d8c148
LB		 6959 case 'o':
6960 outf = fopen_or_die(optarg, "w");
6961 break;
96e47158
LB		 6962 case 'q':
6963 quiet = 1;
6964 break;
023fe0ac
CY		 6965 case 'n':
6966 num_iterations = strtod(optarg, NULL);
6967
6968 if (num_iterations <= 0) {
1b439f01 6969 fprintf(outf, "iterations %d should be positive number\n", num_iterations);
023fe0ac
CY		 6970 exit(2);
6971 }
6972 break;
c7e399f8
ZLCH		 6973 case 'N':
6974 header_iterations = strtod(optarg, NULL);
6975
6976 if (header_iterations <= 0) {
164d7a96 6977 fprintf(outf, "iterations %d should be positive number\n", header_iterations);
c7e399f8 6978 exit(2);
023fe0ac
CY		 6979 }
6980 break;
812db3f7 6981 case 's':
3f44a5c6
LB		 6982 /*
6983 * --show: show only those specified
6984 * The 1st invocation will clear and replace the enabled mask
6985 * subsequent invocations can add to it.
6986 */
6987 if (shown == 0)
6988 bic_enabled = bic_lookup(optarg, SHOW_LIST);
6989 else
6990 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
6991 shown = 1;
812db3f7 6992 break;
d8af6f5f
LB		 6993 case 'S':
6994 summary_only++;
889facbe
LB		 6995 break;
6996 case 'T':
55279aef 6997 tj_max_override = atoi(optarg);
889facbe 6998 break;
d8af6f5f
LB		 6999 case 'v':
7000 print_version();
7001 exit(0);
5c56be9a 7002 break;
103a8fea
LB		 7003 }
7004 }
7005}
7006
7007int main(int argc, char **argv)
7008{
b7d8c148 7009 outf = stderr;
103a8fea
LB		 7010 cmdline(argc, argv);
7011
03331233 7012 if (!quiet) {
d8af6f5f 7013 print_version();
03331233
CY		 7014 print_bootcmd();
7015 }
103a8fea 7016
41618e63
LB		 7017 probe_sysfs();
7018
103a8fea
LB		 7019 turbostat_init();
7020
6799ba84
DM		 7021 msr_sum_record();
7022
3b4d5c7f
AS		 7023 /* dump counters and exit */
7024 if (dump_only)
7025 return get_and_dump_counters();
7026
c8ade361
LB		 7027 /* list header and exit */
7028 if (list_header_only) {
7029 print_header(",");
7030 flush_output_stdout();
7031 return 0;
7032 }
7033
103a8fea
LB		 7034 /*
7035 * if any params left, it must be a command to fork
7036 */
7037 if (argc - optind)
7038 return fork_it(argv + optind);
7039 else
7040 turbostat_loop();
7041
7042 return 0;
7043}
Linux 6.x block layer and io_uring tree(s)