Commit | Line | Data |
---|---|---|
103a8fea LB |
1 | /* |
2 | * turbostat -- show CPU frequency and C-state residency | |
3 | * on modern Intel turbo-capable processors. | |
4 | * | |
144b44b1 | 5 | * Copyright (c) 2013 Intel Corporation. |
103a8fea LB |
6 | * Len Brown <len.brown@intel.com> |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
20 | */ | |
21 | ||
88c3281f | 22 | #define _GNU_SOURCE |
b731f311 | 23 | #include MSRHEADER |
869ce69e | 24 | #include INTEL_FAMILY_HEADER |
95aebc44 | 25 | #include <stdarg.h> |
103a8fea | 26 | #include <stdio.h> |
b2c95d90 | 27 | #include <err.h> |
103a8fea LB |
28 | #include <unistd.h> |
29 | #include <sys/types.h> | |
30 | #include <sys/wait.h> | |
31 | #include <sys/stat.h> | |
32 | #include <sys/resource.h> | |
33 | #include <fcntl.h> | |
34 | #include <signal.h> | |
35 | #include <sys/time.h> | |
36 | #include <stdlib.h> | |
d8af6f5f | 37 | #include <getopt.h> |
103a8fea LB |
38 | #include <dirent.h> |
39 | #include <string.h> | |
40 | #include <ctype.h> | |
88c3281f | 41 | #include <sched.h> |
2a0609c0 | 42 | #include <time.h> |
2b92865e | 43 | #include <cpuid.h> |
98481e79 LB |
44 | #include <linux/capability.h> |
45 | #include <errno.h> | |
103a8fea | 46 | |
103a8fea | 47 | char *proc_stat = "/proc/stat"; |
b7d8c148 | 48 | FILE *outf; |
36229897 | 49 | int *fd_percpu; |
2a0609c0 | 50 | struct timespec interval_ts = {5, 0}; |
d8af6f5f | 51 | unsigned int debug; |
96e47158 | 52 | unsigned int quiet; |
d8af6f5f LB |
53 | unsigned int rapl_joules; |
54 | unsigned int summary_only; | |
55 | unsigned int dump_only; | |
103a8fea | 56 | unsigned int do_snb_cstates; |
fb5d4327 | 57 | unsigned int do_knl_cstates; |
0b2bb692 | 58 | unsigned int do_skl_residency; |
144b44b1 LB |
59 | unsigned int do_slm_cstates; |
60 | unsigned int use_c1_residency_msr; | |
103a8fea | 61 | unsigned int has_aperf; |
889facbe | 62 | unsigned int has_epb; |
5a63426e LB |
63 | unsigned int do_irtl_snb; |
64 | unsigned int do_irtl_hsw; | |
fc04cc67 | 65 | unsigned int units = 1000000; /* MHz etc */ |
103a8fea LB |
66 | unsigned int genuine_intel; |
67 | unsigned int has_invariant_tsc; | |
d7899447 | 68 | unsigned int do_nhm_platform_info; |
cf4cbe53 | 69 | unsigned int no_MSR_MISC_PWR_MGMT; |
b2b34dfe | 70 | unsigned int aperf_mperf_multiplier = 1; |
103a8fea | 71 | double bclk; |
a2b7b749 | 72 | double base_hz; |
21ed5574 | 73 | unsigned int has_base_hz; |
a2b7b749 | 74 | double tsc_tweak = 1.0; |
c98d5d94 LB |
75 | unsigned int show_pkg_only; |
76 | unsigned int show_core_only; | |
77 | char *output_buffer, *outp; | |
889facbe LB |
78 | unsigned int do_rapl; |
79 | unsigned int do_dts; | |
80 | unsigned int do_ptm; | |
fdf676e5 | 81 | unsigned long long gfx_cur_rc6_ms; |
27d47356 | 82 | unsigned int gfx_cur_mhz; |
889facbe LB |
83 | unsigned int tcc_activation_temp; |
84 | unsigned int tcc_activation_temp_override; | |
40ee8e3b AS |
85 | double rapl_power_units, rapl_time_units; |
86 | double rapl_dram_energy_units, rapl_energy_units; | |
889facbe | 87 | double rapl_joule_counter_range; |
3a9a941d LB |
88 | unsigned int do_core_perf_limit_reasons; |
89 | unsigned int do_gfx_perf_limit_reasons; | |
90 | unsigned int do_ring_perf_limit_reasons; | |
8a5bdf41 LB |
91 | unsigned int crystal_hz; |
92 | unsigned long long tsc_hz; | |
7ce7d5de | 93 | int base_cpu; |
21ed5574 | 94 | double discover_bclk(unsigned int family, unsigned int model); |
7f5c258e LB |
95 | unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ |
96 | /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ | |
97 | unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ | |
98 | unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ | |
99 | unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ | |
100 | unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ | |
33148d67 | 101 | unsigned int has_misc_feature_control; |
889facbe | 102 | |
e6f9bb3c LB |
103 | #define RAPL_PKG (1 << 0) |
104 | /* 0x610 MSR_PKG_POWER_LIMIT */ | |
105 | /* 0x611 MSR_PKG_ENERGY_STATUS */ | |
106 | #define RAPL_PKG_PERF_STATUS (1 << 1) | |
107 | /* 0x613 MSR_PKG_PERF_STATUS */ | |
108 | #define RAPL_PKG_POWER_INFO (1 << 2) | |
109 | /* 0x614 MSR_PKG_POWER_INFO */ | |
110 | ||
111 | #define RAPL_DRAM (1 << 3) | |
112 | /* 0x618 MSR_DRAM_POWER_LIMIT */ | |
113 | /* 0x619 MSR_DRAM_ENERGY_STATUS */ | |
e6f9bb3c LB |
114 | #define RAPL_DRAM_PERF_STATUS (1 << 4) |
115 | /* 0x61b MSR_DRAM_PERF_STATUS */ | |
0b2bb692 LB |
116 | #define RAPL_DRAM_POWER_INFO (1 << 5) |
117 | /* 0x61c MSR_DRAM_POWER_INFO */ | |
e6f9bb3c | 118 | |
9148494c | 119 | #define RAPL_CORES_POWER_LIMIT (1 << 6) |
e6f9bb3c | 120 | /* 0x638 MSR_PP0_POWER_LIMIT */ |
0b2bb692 | 121 | #define RAPL_CORE_POLICY (1 << 7) |
e6f9bb3c LB |
122 | /* 0x63a MSR_PP0_POLICY */ |
123 | ||
0b2bb692 | 124 | #define RAPL_GFX (1 << 8) |
e6f9bb3c LB |
125 | /* 0x640 MSR_PP1_POWER_LIMIT */ |
126 | /* 0x641 MSR_PP1_ENERGY_STATUS */ | |
127 | /* 0x642 MSR_PP1_POLICY */ | |
9148494c JP |
128 | |
129 | #define RAPL_CORES_ENERGY_STATUS (1 << 9) | |
130 | /* 0x639 MSR_PP0_ENERGY_STATUS */ | |
131 | #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) | |
889facbe LB |
132 | #define TJMAX_DEFAULT 100 |
133 | ||
134 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) | |
103a8fea | 135 | |
388e9c81 LB |
136 | /* |
137 | * buffer size used by sscanf() for added column names | |
138 | * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters | |
139 | */ | |
140 | #define NAME_BYTES 20 | |
141 | ||
103a8fea LB |
142 | int backwards_count; |
143 | char *progname; | |
103a8fea | 144 | |
c98d5d94 LB |
145 | cpu_set_t *cpu_present_set, *cpu_affinity_set; |
146 | size_t cpu_present_setsize, cpu_affinity_setsize; | |
678a3bd1 | 147 | #define MAX_ADDED_COUNTERS 16 |
c98d5d94 LB |
148 | |
149 | struct thread_data { | |
150 | unsigned long long tsc; | |
151 | unsigned long long aperf; | |
152 | unsigned long long mperf; | |
144b44b1 | 153 | unsigned long long c1; |
562a2d37 | 154 | unsigned int irq_count; |
1ed51011 | 155 | unsigned int smi_count; |
c98d5d94 LB |
156 | unsigned int cpu_id; |
157 | unsigned int flags; | |
158 | #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 | |
159 | #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 | |
678a3bd1 | 160 | unsigned long long counter[MAX_ADDED_COUNTERS]; |
c98d5d94 LB |
161 | } *thread_even, *thread_odd; |
162 | ||
163 | struct core_data { | |
164 | unsigned long long c3; | |
165 | unsigned long long c6; | |
166 | unsigned long long c7; | |
0539ba11 | 167 | unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ |
889facbe | 168 | unsigned int core_temp_c; |
c98d5d94 | 169 | unsigned int core_id; |
678a3bd1 | 170 | unsigned long long counter[MAX_ADDED_COUNTERS]; |
c98d5d94 LB |
171 | } *core_even, *core_odd; |
172 | ||
173 | struct pkg_data { | |
174 | unsigned long long pc2; | |
175 | unsigned long long pc3; | |
176 | unsigned long long pc6; | |
177 | unsigned long long pc7; | |
ca58710f KCA |
178 | unsigned long long pc8; |
179 | unsigned long long pc9; | |
180 | unsigned long long pc10; | |
0b2bb692 LB |
181 | unsigned long long pkg_wtd_core_c0; |
182 | unsigned long long pkg_any_core_c0; | |
183 | unsigned long long pkg_any_gfxe_c0; | |
184 | unsigned long long pkg_both_core_gfxe_c0; | |
9185e988 | 185 | long long gfx_rc6_ms; |
27d47356 | 186 | unsigned int gfx_mhz; |
c98d5d94 | 187 | unsigned int package_id; |
889facbe LB |
188 | unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ |
189 | unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ | |
190 | unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ | |
191 | unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ | |
192 | unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ | |
193 | unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ | |
194 | unsigned int pkg_temp_c; | |
678a3bd1 | 195 | unsigned long long counter[MAX_ADDED_COUNTERS]; |
c98d5d94 LB |
196 | } *package_even, *package_odd; |
197 | ||
198 | #define ODD_COUNTERS thread_odd, core_odd, package_odd | |
199 | #define EVEN_COUNTERS thread_even, core_even, package_even | |
200 | ||
201 | #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ | |
202 | (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ | |
203 | topo.num_threads_per_core + \ | |
204 | (core_no) * topo.num_threads_per_core + (thread_no)) | |
205 | #define GET_CORE(core_base, core_no, pkg_no) \ | |
206 | (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) | |
207 | #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) | |
208 | ||
388e9c81 LB |
209 | enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; |
210 | enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS}; | |
211 | enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; | |
212 | ||
213 | struct msr_counter { | |
214 | unsigned int msr_num; | |
215 | char name[NAME_BYTES]; | |
216 | unsigned int width; | |
217 | enum counter_type type; | |
218 | enum counter_format format; | |
219 | struct msr_counter *next; | |
812db3f7 LB |
220 | unsigned int flags; |
221 | #define FLAGS_HIDE (1 << 0) | |
222 | #define FLAGS_SHOW (1 << 1) | |
388e9c81 LB |
223 | }; |
224 | ||
225 | struct sys_counters { | |
678a3bd1 LB |
226 | unsigned int added_thread_counters; |
227 | unsigned int added_core_counters; | |
228 | unsigned int added_package_counters; | |
388e9c81 LB |
229 | struct msr_counter *tp; |
230 | struct msr_counter *cp; | |
231 | struct msr_counter *pp; | |
232 | } sys; | |
233 | ||
c98d5d94 LB |
234 | struct system_summary { |
235 | struct thread_data threads; | |
236 | struct core_data cores; | |
237 | struct pkg_data packages; | |
388e9c81 | 238 | } average; |
c98d5d94 LB |
239 | |
240 | ||
241 | struct topo_params { | |
242 | int num_packages; | |
243 | int num_cpus; | |
244 | int num_cores; | |
245 | int max_cpu_num; | |
246 | int num_cores_per_pkg; | |
247 | int num_threads_per_core; | |
248 | } topo; | |
249 | ||
250 | struct timeval tv_even, tv_odd, tv_delta; | |
251 | ||
562a2d37 LB |
252 | int *irq_column_2_cpu; /* /proc/interrupts column numbers */ |
253 | int *irqs_per_cpu; /* indexed by cpu_num */ | |
254 | ||
c98d5d94 LB |
255 | void setup_all_buffers(void); |
256 | ||
257 | int cpu_is_not_present(int cpu) | |
d15cf7c1 | 258 | { |
c98d5d94 | 259 | return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); |
d15cf7c1 | 260 | } |
88c3281f | 261 | /* |
c98d5d94 LB |
262 | * run func(thread, core, package) in topology order |
263 | * skip non-present cpus | |
88c3281f | 264 | */ |
c98d5d94 LB |
265 | |
266 | int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), | |
267 | struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) | |
88c3281f | 268 | { |
c98d5d94 | 269 | int retval, pkg_no, core_no, thread_no; |
d15cf7c1 | 270 | |
c98d5d94 LB |
271 | for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { |
272 | for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { | |
273 | for (thread_no = 0; thread_no < | |
274 | topo.num_threads_per_core; ++thread_no) { | |
275 | struct thread_data *t; | |
276 | struct core_data *c; | |
277 | struct pkg_data *p; | |
88c3281f | 278 | |
c98d5d94 LB |
279 | t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); |
280 | ||
281 | if (cpu_is_not_present(t->cpu_id)) | |
282 | continue; | |
283 | ||
284 | c = GET_CORE(core_base, core_no, pkg_no); | |
285 | p = GET_PKG(pkg_base, pkg_no); | |
286 | ||
287 | retval = func(t, c, p); | |
288 | if (retval) | |
289 | return retval; | |
290 | } | |
291 | } | |
292 | } | |
293 | return 0; | |
88c3281f LB |
294 | } |
295 | ||
296 | int cpu_migrate(int cpu) | |
297 | { | |
c98d5d94 LB |
298 | CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); |
299 | CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); | |
300 | if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) | |
88c3281f LB |
301 | return -1; |
302 | else | |
303 | return 0; | |
304 | } | |
36229897 | 305 | int get_msr_fd(int cpu) |
103a8fea | 306 | { |
103a8fea LB |
307 | char pathname[32]; |
308 | int fd; | |
309 | ||
36229897 LB |
310 | fd = fd_percpu[cpu]; |
311 | ||
312 | if (fd) | |
313 | return fd; | |
314 | ||
103a8fea LB |
315 | sprintf(pathname, "/dev/cpu/%d/msr", cpu); |
316 | fd = open(pathname, O_RDONLY); | |
15aaa346 | 317 | if (fd < 0) |
98481e79 | 318 | err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); |
103a8fea | 319 | |
36229897 LB |
320 | fd_percpu[cpu] = fd; |
321 | ||
322 | return fd; | |
323 | } | |
324 | ||
325 | int get_msr(int cpu, off_t offset, unsigned long long *msr) | |
326 | { | |
327 | ssize_t retval; | |
328 | ||
329 | retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); | |
15aaa346 | 330 | |
98481e79 | 331 | if (retval != sizeof *msr) |
cf4cbe53 | 332 | err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); |
15aaa346 LB |
333 | |
334 | return 0; | |
103a8fea LB |
335 | } |
336 | ||
fc04cc67 | 337 | /* |
812db3f7 LB |
338 | * Each string in this array is compared in --show and --hide cmdline. |
339 | * Thus, strings that are proper sub-sets must follow their more specific peers. | |
fc04cc67 | 340 | */ |
812db3f7 LB |
341 | struct msr_counter bic[] = { |
342 | { 0x0, "Package" }, | |
343 | { 0x0, "Avg_MHz" }, | |
344 | { 0x0, "Bzy_MHz" }, | |
345 | { 0x0, "TSC_MHz" }, | |
346 | { 0x0, "IRQ" }, | |
347 | { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL}, | |
348 | { 0x0, "Busy%" }, | |
349 | { 0x0, "CPU%c1" }, | |
350 | { 0x0, "CPU%c3" }, | |
351 | { 0x0, "CPU%c6" }, | |
352 | { 0x0, "CPU%c7" }, | |
353 | { 0x0, "ThreadC" }, | |
354 | { 0x0, "CoreTmp" }, | |
355 | { 0x0, "CoreCnt" }, | |
356 | { 0x0, "PkgTmp" }, | |
357 | { 0x0, "GFX%rc6" }, | |
358 | { 0x0, "GFXMHz" }, | |
359 | { 0x0, "Pkg%pc2" }, | |
360 | { 0x0, "Pkg%pc3" }, | |
361 | { 0x0, "Pkg%pc6" }, | |
362 | { 0x0, "Pkg%pc7" }, | |
0f47c08d LB |
363 | { 0x0, "Pkg%pc8" }, |
364 | { 0x0, "Pkg%pc9" }, | |
365 | { 0x0, "Pkg%pc10" }, | |
812db3f7 LB |
366 | { 0x0, "PkgWatt" }, |
367 | { 0x0, "CorWatt" }, | |
368 | { 0x0, "GFXWatt" }, | |
369 | { 0x0, "PkgCnt" }, | |
370 | { 0x0, "RAMWatt" }, | |
371 | { 0x0, "PKG_%" }, | |
372 | { 0x0, "RAM_%" }, | |
373 | { 0x0, "Pkg_J" }, | |
374 | { 0x0, "Cor_J" }, | |
375 | { 0x0, "GFX_J" }, | |
376 | { 0x0, "RAM_J" }, | |
377 | { 0x0, "Core" }, | |
378 | { 0x0, "CPU" }, | |
0539ba11 | 379 | { 0x0, "Mod%c6" }, |
812db3f7 LB |
380 | }; |
381 | ||
382 | #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) | |
383 | #define BIC_Package (1ULL << 0) | |
384 | #define BIC_Avg_MHz (1ULL << 1) | |
385 | #define BIC_Bzy_MHz (1ULL << 2) | |
386 | #define BIC_TSC_MHz (1ULL << 3) | |
387 | #define BIC_IRQ (1ULL << 4) | |
388 | #define BIC_SMI (1ULL << 5) | |
389 | #define BIC_Busy (1ULL << 6) | |
390 | #define BIC_CPU_c1 (1ULL << 7) | |
391 | #define BIC_CPU_c3 (1ULL << 8) | |
392 | #define BIC_CPU_c6 (1ULL << 9) | |
393 | #define BIC_CPU_c7 (1ULL << 10) | |
394 | #define BIC_ThreadC (1ULL << 11) | |
395 | #define BIC_CoreTmp (1ULL << 12) | |
396 | #define BIC_CoreCnt (1ULL << 13) | |
397 | #define BIC_PkgTmp (1ULL << 14) | |
398 | #define BIC_GFX_rc6 (1ULL << 15) | |
399 | #define BIC_GFXMHz (1ULL << 16) | |
400 | #define BIC_Pkgpc2 (1ULL << 17) | |
401 | #define BIC_Pkgpc3 (1ULL << 18) | |
402 | #define BIC_Pkgpc6 (1ULL << 19) | |
403 | #define BIC_Pkgpc7 (1ULL << 20) | |
0f47c08d LB |
404 | #define BIC_Pkgpc8 (1ULL << 21) |
405 | #define BIC_Pkgpc9 (1ULL << 22) | |
406 | #define BIC_Pkgpc10 (1ULL << 23) | |
407 | #define BIC_PkgWatt (1ULL << 24) | |
408 | #define BIC_CorWatt (1ULL << 25) | |
409 | #define BIC_GFXWatt (1ULL << 26) | |
410 | #define BIC_PkgCnt (1ULL << 27) | |
411 | #define BIC_RAMWatt (1ULL << 28) | |
412 | #define BIC_PKG__ (1ULL << 29) | |
413 | #define BIC_RAM__ (1ULL << 30) | |
414 | #define BIC_Pkg_J (1ULL << 31) | |
415 | #define BIC_Cor_J (1ULL << 32) | |
416 | #define BIC_GFX_J (1ULL << 33) | |
417 | #define BIC_RAM_J (1ULL << 34) | |
418 | #define BIC_Core (1ULL << 35) | |
419 | #define BIC_CPU (1ULL << 36) | |
420 | #define BIC_Mod_c6 (1ULL << 37) | |
812db3f7 LB |
421 | |
422 | unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL; | |
423 | unsigned long long bic_present; | |
424 | ||
425 | #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) | |
426 | #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) | |
0f47c08d | 427 | #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) |
812db3f7 LB |
428 | |
429 | /* | |
430 | * bic_lookup | |
431 | * for all the strings in comma separate name_list, | |
432 | * set the approprate bit in return value. | |
433 | */ | |
434 | unsigned long long bic_lookup(char *name_list) | |
435 | { | |
436 | int i; | |
437 | unsigned long long retval = 0; | |
438 | ||
439 | while (name_list) { | |
440 | char *comma; | |
441 | ||
442 | comma = strchr(name_list, ','); | |
443 | ||
444 | if (comma) | |
445 | *comma = '\0'; | |
446 | ||
447 | for (i = 0; i < MAX_BIC; ++i) { | |
448 | if (!strcmp(name_list, bic[i].name)) { | |
449 | retval |= (1ULL << i); | |
450 | break; | |
451 | } | |
452 | } | |
453 | if (i == MAX_BIC) { | |
454 | fprintf(stderr, "Invalid counter name: %s\n", name_list); | |
455 | exit(-1); | |
456 | } | |
457 | ||
458 | name_list = comma; | |
459 | if (name_list) | |
460 | name_list++; | |
461 | ||
462 | } | |
463 | return retval; | |
464 | } | |
fc04cc67 | 465 | |
a829eb4d | 466 | void print_header(void) |
103a8fea | 467 | { |
388e9c81 LB |
468 | struct msr_counter *mp; |
469 | ||
812db3f7 | 470 | if (DO_BIC(BIC_Package)) |
3d109de2 | 471 | outp += sprintf(outp, "\tPackage"); |
812db3f7 | 472 | if (DO_BIC(BIC_Core)) |
3d109de2 | 473 | outp += sprintf(outp, "\tCore"); |
812db3f7 | 474 | if (DO_BIC(BIC_CPU)) |
3d109de2 | 475 | outp += sprintf(outp, "\tCPU"); |
812db3f7 | 476 | if (DO_BIC(BIC_Avg_MHz)) |
3d109de2 | 477 | outp += sprintf(outp, "\tAvg_MHz"); |
812db3f7 | 478 | if (DO_BIC(BIC_Busy)) |
3d109de2 | 479 | outp += sprintf(outp, "\tBusy%%"); |
812db3f7 | 480 | if (DO_BIC(BIC_Bzy_MHz)) |
3d109de2 | 481 | outp += sprintf(outp, "\tBzy_MHz"); |
812db3f7 LB |
482 | if (DO_BIC(BIC_TSC_MHz)) |
483 | outp += sprintf(outp, "\tTSC_MHz"); | |
1cc21f7b | 484 | |
812db3f7 | 485 | if (DO_BIC(BIC_IRQ)) |
3d109de2 | 486 | outp += sprintf(outp, "\tIRQ"); |
812db3f7 | 487 | if (DO_BIC(BIC_SMI)) |
3d109de2 | 488 | outp += sprintf(outp, "\tSMI"); |
1cc21f7b | 489 | |
812db3f7 | 490 | if (DO_BIC(BIC_CPU_c1)) |
3d109de2 | 491 | outp += sprintf(outp, "\tCPU%%c1"); |
889facbe | 492 | |
388e9c81 LB |
493 | for (mp = sys.tp; mp; mp = mp->next) { |
494 | if (mp->format == FORMAT_RAW) { | |
495 | if (mp->width == 64) | |
496 | outp += sprintf(outp, "\t%18.18s", mp->name); | |
497 | else | |
498 | outp += sprintf(outp, "\t%10.10s", mp->name); | |
499 | } else { | |
500 | outp += sprintf(outp, "\t%-7.7s", mp->name); | |
501 | } | |
502 | } | |
503 | ||
812db3f7 | 504 | if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) |
678a3bd1 | 505 | outp += sprintf(outp, "\tCPU%%c3"); |
812db3f7 | 506 | if (DO_BIC(BIC_CPU_c6)) |
678a3bd1 | 507 | outp += sprintf(outp, "\tCPU%%c6"); |
812db3f7 | 508 | if (DO_BIC(BIC_CPU_c7)) |
678a3bd1 LB |
509 | outp += sprintf(outp, "\tCPU%%c7"); |
510 | ||
0539ba11 LB |
511 | if (DO_BIC(BIC_Mod_c6)) |
512 | outp += sprintf(outp, "\tMod%%c6"); | |
678a3bd1 | 513 | |
812db3f7 | 514 | if (DO_BIC(BIC_CoreTmp)) |
3d109de2 | 515 | outp += sprintf(outp, "\tCoreTmp"); |
388e9c81 LB |
516 | |
517 | for (mp = sys.cp; mp; mp = mp->next) { | |
518 | if (mp->format == FORMAT_RAW) { | |
519 | if (mp->width == 64) | |
520 | outp += sprintf(outp, "\t%18.18s", mp->name); | |
521 | else | |
522 | outp += sprintf(outp, "\t%10.10s", mp->name); | |
523 | } else { | |
524 | outp += sprintf(outp, "\t%-7.7s", mp->name); | |
525 | } | |
526 | } | |
527 | ||
812db3f7 | 528 | if (DO_BIC(BIC_PkgTmp)) |
3d109de2 | 529 | outp += sprintf(outp, "\tPkgTmp"); |
889facbe | 530 | |
812db3f7 | 531 | if (DO_BIC(BIC_GFX_rc6)) |
3d109de2 | 532 | outp += sprintf(outp, "\tGFX%%rc6"); |
fdf676e5 | 533 | |
812db3f7 | 534 | if (DO_BIC(BIC_GFXMHz)) |
3d109de2 | 535 | outp += sprintf(outp, "\tGFXMHz"); |
27d47356 | 536 | |
0b2bb692 | 537 | if (do_skl_residency) { |
3d109de2 LB |
538 | outp += sprintf(outp, "\tTotl%%C0"); |
539 | outp += sprintf(outp, "\tAny%%C0"); | |
540 | outp += sprintf(outp, "\tGFX%%C0"); | |
541 | outp += sprintf(outp, "\tCPUGFX%%"); | |
0b2bb692 LB |
542 | } |
543 | ||
0f47c08d | 544 | if (DO_BIC(BIC_Pkgpc2)) |
3d109de2 | 545 | outp += sprintf(outp, "\tPkg%%pc2"); |
0f47c08d | 546 | if (DO_BIC(BIC_Pkgpc3)) |
3d109de2 | 547 | outp += sprintf(outp, "\tPkg%%pc3"); |
0f47c08d | 548 | if (DO_BIC(BIC_Pkgpc6)) |
3d109de2 | 549 | outp += sprintf(outp, "\tPkg%%pc6"); |
0f47c08d | 550 | if (DO_BIC(BIC_Pkgpc7)) |
3d109de2 | 551 | outp += sprintf(outp, "\tPkg%%pc7"); |
0f47c08d | 552 | if (DO_BIC(BIC_Pkgpc8)) |
3d109de2 | 553 | outp += sprintf(outp, "\tPkg%%pc8"); |
0f47c08d | 554 | if (DO_BIC(BIC_Pkgpc9)) |
3d109de2 | 555 | outp += sprintf(outp, "\tPkg%%pc9"); |
0f47c08d | 556 | if (DO_BIC(BIC_Pkgpc10)) |
3d109de2 | 557 | outp += sprintf(outp, "\tPk%%pc10"); |
103a8fea | 558 | |
5c56be9a | 559 | if (do_rapl && !rapl_joules) { |
812db3f7 | 560 | if (DO_BIC(BIC_PkgWatt)) |
3d109de2 | 561 | outp += sprintf(outp, "\tPkgWatt"); |
812db3f7 | 562 | if (DO_BIC(BIC_CorWatt)) |
3d109de2 | 563 | outp += sprintf(outp, "\tCorWatt"); |
812db3f7 | 564 | if (DO_BIC(BIC_GFXWatt)) |
3d109de2 | 565 | outp += sprintf(outp, "\tGFXWatt"); |
812db3f7 | 566 | if (DO_BIC(BIC_RAMWatt)) |
3d109de2 | 567 | outp += sprintf(outp, "\tRAMWatt"); |
812db3f7 | 568 | if (DO_BIC(BIC_PKG__)) |
3d109de2 | 569 | outp += sprintf(outp, "\tPKG_%%"); |
812db3f7 | 570 | if (DO_BIC(BIC_RAM__)) |
3d109de2 | 571 | outp += sprintf(outp, "\tRAM_%%"); |
d7899447 | 572 | } else if (do_rapl && rapl_joules) { |
812db3f7 | 573 | if (DO_BIC(BIC_Pkg_J)) |
3d109de2 | 574 | outp += sprintf(outp, "\tPkg_J"); |
812db3f7 | 575 | if (DO_BIC(BIC_Cor_J)) |
3d109de2 | 576 | outp += sprintf(outp, "\tCor_J"); |
812db3f7 | 577 | if (DO_BIC(BIC_GFX_J)) |
3d109de2 | 578 | outp += sprintf(outp, "\tGFX_J"); |
812db3f7 | 579 | if (DO_BIC(BIC_RAM_J)) |
3d109de2 | 580 | outp += sprintf(outp, "\tRAM_J"); |
812db3f7 | 581 | if (DO_BIC(BIC_PKG__)) |
3d109de2 | 582 | outp += sprintf(outp, "\tPKG_%%"); |
812db3f7 | 583 | if (DO_BIC(BIC_RAM__)) |
3d109de2 | 584 | outp += sprintf(outp, "\tRAM_%%"); |
5c56be9a | 585 | } |
388e9c81 LB |
586 | for (mp = sys.pp; mp; mp = mp->next) { |
587 | if (mp->format == FORMAT_RAW) { | |
588 | if (mp->width == 64) | |
589 | outp += sprintf(outp, "\t%18.18s", mp->name); | |
590 | else | |
591 | outp += sprintf(outp, "\t%10.10s", mp->name); | |
592 | } else { | |
593 | outp += sprintf(outp, "\t%-7.7s", mp->name); | |
594 | } | |
595 | } | |
596 | ||
c98d5d94 | 597 | outp += sprintf(outp, "\n"); |
103a8fea LB |
598 | } |
599 | ||
c98d5d94 LB |
600 | int dump_counters(struct thread_data *t, struct core_data *c, |
601 | struct pkg_data *p) | |
103a8fea | 602 | { |
388e9c81 LB |
603 | int i; |
604 | struct msr_counter *mp; | |
605 | ||
3b4d5c7f | 606 | outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); |
c98d5d94 LB |
607 | |
608 | if (t) { | |
3b4d5c7f AS |
609 | outp += sprintf(outp, "CPU: %d flags 0x%x\n", |
610 | t->cpu_id, t->flags); | |
611 | outp += sprintf(outp, "TSC: %016llX\n", t->tsc); | |
612 | outp += sprintf(outp, "aperf: %016llX\n", t->aperf); | |
613 | outp += sprintf(outp, "mperf: %016llX\n", t->mperf); | |
614 | outp += sprintf(outp, "c1: %016llX\n", t->c1); | |
6886fee4 | 615 | |
812db3f7 | 616 | if (DO_BIC(BIC_IRQ)) |
562a2d37 | 617 | outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); |
812db3f7 | 618 | if (DO_BIC(BIC_SMI)) |
3b4d5c7f | 619 | outp += sprintf(outp, "SMI: %08X\n", t->smi_count); |
388e9c81 LB |
620 | |
621 | for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { | |
622 | outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", | |
623 | i, mp->msr_num, t->counter[i]); | |
624 | } | |
c98d5d94 | 625 | } |
103a8fea | 626 | |
c98d5d94 | 627 | if (c) { |
3b4d5c7f AS |
628 | outp += sprintf(outp, "core: %d\n", c->core_id); |
629 | outp += sprintf(outp, "c3: %016llX\n", c->c3); | |
630 | outp += sprintf(outp, "c6: %016llX\n", c->c6); | |
631 | outp += sprintf(outp, "c7: %016llX\n", c->c7); | |
632 | outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); | |
388e9c81 LB |
633 | |
634 | for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { | |
635 | outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", | |
636 | i, mp->msr_num, c->counter[i]); | |
637 | } | |
0539ba11 | 638 | outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); |
c98d5d94 | 639 | } |
103a8fea | 640 | |
c98d5d94 | 641 | if (p) { |
3b4d5c7f | 642 | outp += sprintf(outp, "package: %d\n", p->package_id); |
0b2bb692 LB |
643 | |
644 | outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); | |
645 | outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); | |
646 | outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); | |
647 | outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); | |
648 | ||
3b4d5c7f | 649 | outp += sprintf(outp, "pc2: %016llX\n", p->pc2); |
0f47c08d | 650 | if (DO_BIC(BIC_Pkgpc3)) |
ee7e38e3 | 651 | outp += sprintf(outp, "pc3: %016llX\n", p->pc3); |
0f47c08d | 652 | if (DO_BIC(BIC_Pkgpc6)) |
ee7e38e3 | 653 | outp += sprintf(outp, "pc6: %016llX\n", p->pc6); |
0f47c08d | 654 | if (DO_BIC(BIC_Pkgpc7)) |
ee7e38e3 | 655 | outp += sprintf(outp, "pc7: %016llX\n", p->pc7); |
3b4d5c7f AS |
656 | outp += sprintf(outp, "pc8: %016llX\n", p->pc8); |
657 | outp += sprintf(outp, "pc9: %016llX\n", p->pc9); | |
658 | outp += sprintf(outp, "pc10: %016llX\n", p->pc10); | |
659 | outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); | |
660 | outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); | |
661 | outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); | |
662 | outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); | |
663 | outp += sprintf(outp, "Throttle PKG: %0X\n", | |
664 | p->rapl_pkg_perf_status); | |
665 | outp += sprintf(outp, "Throttle RAM: %0X\n", | |
666 | p->rapl_dram_perf_status); | |
667 | outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); | |
388e9c81 LB |
668 | |
669 | for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { | |
670 | outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", | |
671 | i, mp->msr_num, p->counter[i]); | |
672 | } | |
c98d5d94 | 673 | } |
3b4d5c7f AS |
674 | |
675 | outp += sprintf(outp, "\n"); | |
676 | ||
c98d5d94 | 677 | return 0; |
103a8fea LB |
678 | } |
679 | ||
e23da037 LB |
680 | /* |
681 | * column formatting convention & formats | |
e23da037 | 682 | */ |
c98d5d94 LB |
683 | int format_counters(struct thread_data *t, struct core_data *c, |
684 | struct pkg_data *p) | |
103a8fea | 685 | { |
008d396e | 686 | double interval_float, tsc; |
fc04cc67 | 687 | char *fmt8; |
388e9c81 LB |
688 | int i; |
689 | struct msr_counter *mp; | |
103a8fea | 690 | |
c98d5d94 LB |
691 | /* if showing only 1st thread in core and this isn't one, bail out */ |
692 | if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
693 | return 0; | |
694 | ||
695 | /* if showing only 1st thread in pkg and this isn't one, bail out */ | |
696 | if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
697 | return 0; | |
698 | ||
103a8fea LB |
699 | interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; |
700 | ||
008d396e LB |
701 | tsc = t->tsc * tsc_tweak; |
702 | ||
c98d5d94 LB |
703 | /* topo columns, print blanks on 1st (average) line */ |
704 | if (t == &average.threads) { | |
812db3f7 | 705 | if (DO_BIC(BIC_Package)) |
3d109de2 | 706 | outp += sprintf(outp, "\t-"); |
812db3f7 | 707 | if (DO_BIC(BIC_Core)) |
3d109de2 | 708 | outp += sprintf(outp, "\t-"); |
812db3f7 | 709 | if (DO_BIC(BIC_CPU)) |
3d109de2 | 710 | outp += sprintf(outp, "\t-"); |
103a8fea | 711 | } else { |
812db3f7 | 712 | if (DO_BIC(BIC_Package)) { |
c98d5d94 | 713 | if (p) |
3d109de2 | 714 | outp += sprintf(outp, "\t%d", p->package_id); |
c98d5d94 | 715 | else |
3d109de2 | 716 | outp += sprintf(outp, "\t-"); |
c98d5d94 | 717 | } |
812db3f7 | 718 | if (DO_BIC(BIC_Core)) { |
c98d5d94 | 719 | if (c) |
3d109de2 | 720 | outp += sprintf(outp, "\t%d", c->core_id); |
c98d5d94 | 721 | else |
3d109de2 | 722 | outp += sprintf(outp, "\t-"); |
c98d5d94 | 723 | } |
812db3f7 | 724 | if (DO_BIC(BIC_CPU)) |
3d109de2 | 725 | outp += sprintf(outp, "\t%d", t->cpu_id); |
103a8fea | 726 | } |
fc04cc67 | 727 | |
812db3f7 | 728 | if (DO_BIC(BIC_Avg_MHz)) |
3d109de2 | 729 | outp += sprintf(outp, "\t%.0f", |
fc04cc67 LB |
730 | 1.0 / units * t->aperf / interval_float); |
731 | ||
812db3f7 | 732 | if (DO_BIC(BIC_Busy)) |
008d396e | 733 | outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/tsc); |
103a8fea | 734 | |
812db3f7 | 735 | if (DO_BIC(BIC_Bzy_MHz)) { |
21ed5574 | 736 | if (has_base_hz) |
3d109de2 | 737 | outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf); |
21ed5574 | 738 | else |
3d109de2 | 739 | outp += sprintf(outp, "\t%.0f", |
008d396e | 740 | tsc / units * t->aperf / t->mperf / interval_float); |
21ed5574 | 741 | } |
103a8fea | 742 | |
812db3f7 LB |
743 | if (DO_BIC(BIC_TSC_MHz)) |
744 | outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float); | |
103a8fea | 745 | |
562a2d37 | 746 | /* IRQ */ |
812db3f7 | 747 | if (DO_BIC(BIC_IRQ)) |
3d109de2 | 748 | outp += sprintf(outp, "\t%d", t->irq_count); |
562a2d37 | 749 | |
1cc21f7b | 750 | /* SMI */ |
812db3f7 | 751 | if (DO_BIC(BIC_SMI)) |
3d109de2 | 752 | outp += sprintf(outp, "\t%d", t->smi_count); |
1cc21f7b | 753 | |
678a3bd1 | 754 | /* C1 */ |
812db3f7 | 755 | if (DO_BIC(BIC_CPU_c1)) |
008d396e | 756 | outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/tsc); |
c98d5d94 | 757 | |
678a3bd1 | 758 | /* Added counters */ |
388e9c81 LB |
759 | for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { |
760 | if (mp->format == FORMAT_RAW) { | |
761 | if (mp->width == 32) | |
762 | outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]); | |
763 | else | |
764 | outp += sprintf(outp, "\t0x%016llx", t->counter[i]); | |
765 | } else if (mp->format == FORMAT_DELTA) { | |
678a3bd1 | 766 | outp += sprintf(outp, "\t%lld", t->counter[i]); |
388e9c81 | 767 | } else if (mp->format == FORMAT_PERCENT) { |
008d396e | 768 | outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/tsc); |
388e9c81 LB |
769 | } |
770 | } | |
771 | ||
678a3bd1 LB |
772 | /* print per-core data only for 1st thread in core */ |
773 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
774 | goto done; | |
775 | ||
812db3f7 | 776 | if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) |
008d396e | 777 | outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/tsc); |
812db3f7 | 778 | if (DO_BIC(BIC_CPU_c6)) |
008d396e | 779 | outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/tsc); |
812db3f7 | 780 | if (DO_BIC(BIC_CPU_c7)) |
008d396e | 781 | outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/tsc); |
678a3bd1 | 782 | |
0539ba11 LB |
783 | /* Mod%c6 */ |
784 | if (DO_BIC(BIC_Mod_c6)) | |
008d396e | 785 | outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / tsc); |
0539ba11 | 786 | |
812db3f7 | 787 | if (DO_BIC(BIC_CoreTmp)) |
3d109de2 | 788 | outp += sprintf(outp, "\t%d", c->core_temp_c); |
889facbe | 789 | |
388e9c81 LB |
790 | for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { |
791 | if (mp->format == FORMAT_RAW) { | |
792 | if (mp->width == 32) | |
793 | outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]); | |
794 | else | |
795 | outp += sprintf(outp, "\t0x%016llx", c->counter[i]); | |
796 | } else if (mp->format == FORMAT_DELTA) { | |
678a3bd1 | 797 | outp += sprintf(outp, "\t%lld", c->counter[i]); |
388e9c81 | 798 | } else if (mp->format == FORMAT_PERCENT) { |
008d396e | 799 | outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/tsc); |
388e9c81 LB |
800 | } |
801 | } | |
802 | ||
c98d5d94 LB |
803 | /* print per-package data only for 1st core in package */ |
804 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
805 | goto done; | |
806 | ||
0b2bb692 | 807 | /* PkgTmp */ |
812db3f7 | 808 | if (DO_BIC(BIC_PkgTmp)) |
3d109de2 | 809 | outp += sprintf(outp, "\t%d", p->pkg_temp_c); |
889facbe | 810 | |
fdf676e5 | 811 | /* GFXrc6 */ |
812db3f7 | 812 | if (DO_BIC(BIC_GFX_rc6)) { |
ba3dec99 | 813 | if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ |
3d109de2 | 814 | outp += sprintf(outp, "\t**.**"); |
9185e988 | 815 | } else { |
3d109de2 | 816 | outp += sprintf(outp, "\t%.2f", |
9185e988 LB |
817 | p->gfx_rc6_ms / 10.0 / interval_float); |
818 | } | |
819 | } | |
fdf676e5 | 820 | |
27d47356 | 821 | /* GFXMHz */ |
812db3f7 | 822 | if (DO_BIC(BIC_GFXMHz)) |
3d109de2 | 823 | outp += sprintf(outp, "\t%d", p->gfx_mhz); |
27d47356 | 824 | |
0b2bb692 LB |
825 | /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ |
826 | if (do_skl_residency) { | |
008d396e LB |
827 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/tsc); |
828 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/tsc); | |
829 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/tsc); | |
830 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/tsc); | |
0b2bb692 LB |
831 | } |
832 | ||
0f47c08d | 833 | if (DO_BIC(BIC_Pkgpc2)) |
008d396e | 834 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/tsc); |
0f47c08d | 835 | if (DO_BIC(BIC_Pkgpc3)) |
008d396e | 836 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/tsc); |
0f47c08d | 837 | if (DO_BIC(BIC_Pkgpc6)) |
008d396e | 838 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/tsc); |
0f47c08d | 839 | if (DO_BIC(BIC_Pkgpc7)) |
008d396e | 840 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/tsc); |
0f47c08d | 841 | if (DO_BIC(BIC_Pkgpc8)) |
008d396e | 842 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/tsc); |
0f47c08d | 843 | if (DO_BIC(BIC_Pkgpc9)) |
008d396e | 844 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/tsc); |
0f47c08d | 845 | if (DO_BIC(BIC_Pkgpc10)) |
008d396e | 846 | outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/tsc); |
889facbe LB |
847 | |
848 | /* | |
849 | * If measurement interval exceeds minimum RAPL Joule Counter range, | |
850 | * indicate that results are suspect by printing "**" in fraction place. | |
851 | */ | |
fc04cc67 | 852 | if (interval_float < rapl_joule_counter_range) |
3d109de2 | 853 | fmt8 = "\t%.2f"; |
fc04cc67 | 854 | else |
e975db5d | 855 | fmt8 = "%6.0f**"; |
889facbe | 856 | |
812db3f7 LB |
857 | if (DO_BIC(BIC_PkgWatt)) |
858 | outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); | |
859 | if (DO_BIC(BIC_CorWatt)) | |
860 | outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); | |
861 | if (DO_BIC(BIC_GFXWatt)) | |
862 | outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); | |
863 | if (DO_BIC(BIC_RAMWatt)) | |
864 | outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); | |
865 | if (DO_BIC(BIC_Pkg_J)) | |
866 | outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units); | |
867 | if (DO_BIC(BIC_Cor_J)) | |
868 | outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units); | |
869 | if (DO_BIC(BIC_GFX_J)) | |
870 | outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units); | |
871 | if (DO_BIC(BIC_RAM_J)) | |
872 | outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units); | |
873 | if (DO_BIC(BIC_PKG__)) | |
874 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); | |
875 | if (DO_BIC(BIC_RAM__)) | |
876 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); | |
877 | ||
388e9c81 LB |
878 | for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { |
879 | if (mp->format == FORMAT_RAW) { | |
880 | if (mp->width == 32) | |
881 | outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]); | |
882 | else | |
883 | outp += sprintf(outp, "\t0x%016llx", p->counter[i]); | |
884 | } else if (mp->format == FORMAT_DELTA) { | |
678a3bd1 | 885 | outp += sprintf(outp, "\t%lld", p->counter[i]); |
388e9c81 | 886 | } else if (mp->format == FORMAT_PERCENT) { |
008d396e | 887 | outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/tsc); |
388e9c81 LB |
888 | } |
889 | } | |
890 | ||
c98d5d94 | 891 | done: |
c98d5d94 LB |
892 | outp += sprintf(outp, "\n"); |
893 | ||
894 | return 0; | |
103a8fea LB |
895 | } |
896 | ||
b7d8c148 | 897 | void flush_output_stdout(void) |
c98d5d94 | 898 | { |
b7d8c148 LB |
899 | FILE *filep; |
900 | ||
901 | if (outf == stderr) | |
902 | filep = stdout; | |
903 | else | |
904 | filep = outf; | |
905 | ||
906 | fputs(output_buffer, filep); | |
907 | fflush(filep); | |
908 | ||
c98d5d94 LB |
909 | outp = output_buffer; |
910 | } | |
b7d8c148 | 911 | void flush_output_stderr(void) |
c98d5d94 | 912 | { |
b7d8c148 LB |
913 | fputs(output_buffer, outf); |
914 | fflush(outf); | |
c98d5d94 LB |
915 | outp = output_buffer; |
916 | } | |
917 | void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
103a8fea | 918 | { |
e23da037 | 919 | static int printed; |
103a8fea | 920 | |
e23da037 LB |
921 | if (!printed || !summary_only) |
922 | print_header(); | |
103a8fea | 923 | |
c98d5d94 LB |
924 | if (topo.num_cpus > 1) |
925 | format_counters(&average.threads, &average.cores, | |
926 | &average.packages); | |
103a8fea | 927 | |
e23da037 LB |
928 | printed = 1; |
929 | ||
930 | if (summary_only) | |
931 | return; | |
932 | ||
c98d5d94 | 933 | for_all_cpus(format_counters, t, c, p); |
103a8fea LB |
934 | } |
935 | ||
889facbe LB |
936 | #define DELTA_WRAP32(new, old) \ |
937 | if (new > old) { \ | |
938 | old = new - old; \ | |
939 | } else { \ | |
940 | old = 0x100000000 + new - old; \ | |
941 | } | |
942 | ||
ba3dec99 | 943 | int |
c98d5d94 LB |
944 | delta_package(struct pkg_data *new, struct pkg_data *old) |
945 | { | |
388e9c81 LB |
946 | int i; |
947 | struct msr_counter *mp; | |
0b2bb692 LB |
948 | |
949 | if (do_skl_residency) { | |
950 | old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; | |
951 | old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; | |
952 | old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; | |
953 | old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; | |
954 | } | |
c98d5d94 | 955 | old->pc2 = new->pc2 - old->pc2; |
0f47c08d | 956 | if (DO_BIC(BIC_Pkgpc3)) |
ee7e38e3 | 957 | old->pc3 = new->pc3 - old->pc3; |
0f47c08d | 958 | if (DO_BIC(BIC_Pkgpc6)) |
ee7e38e3 | 959 | old->pc6 = new->pc6 - old->pc6; |
0f47c08d | 960 | if (DO_BIC(BIC_Pkgpc7)) |
ee7e38e3 | 961 | old->pc7 = new->pc7 - old->pc7; |
ca58710f KCA |
962 | old->pc8 = new->pc8 - old->pc8; |
963 | old->pc9 = new->pc9 - old->pc9; | |
964 | old->pc10 = new->pc10 - old->pc10; | |
889facbe LB |
965 | old->pkg_temp_c = new->pkg_temp_c; |
966 | ||
9185e988 LB |
967 | /* flag an error when rc6 counter resets/wraps */ |
968 | if (old->gfx_rc6_ms > new->gfx_rc6_ms) | |
969 | old->gfx_rc6_ms = -1; | |
970 | else | |
971 | old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; | |
972 | ||
27d47356 LB |
973 | old->gfx_mhz = new->gfx_mhz; |
974 | ||
889facbe LB |
975 | DELTA_WRAP32(new->energy_pkg, old->energy_pkg); |
976 | DELTA_WRAP32(new->energy_cores, old->energy_cores); | |
977 | DELTA_WRAP32(new->energy_gfx, old->energy_gfx); | |
978 | DELTA_WRAP32(new->energy_dram, old->energy_dram); | |
979 | DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); | |
980 | DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); | |
ba3dec99 | 981 | |
388e9c81 LB |
982 | for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { |
983 | if (mp->format == FORMAT_RAW) | |
984 | old->counter[i] = new->counter[i]; | |
985 | else | |
986 | old->counter[i] = new->counter[i] - old->counter[i]; | |
987 | } | |
988 | ||
ba3dec99 | 989 | return 0; |
c98d5d94 | 990 | } |
103a8fea | 991 | |
c98d5d94 LB |
992 | void |
993 | delta_core(struct core_data *new, struct core_data *old) | |
103a8fea | 994 | { |
388e9c81 LB |
995 | int i; |
996 | struct msr_counter *mp; | |
997 | ||
c98d5d94 LB |
998 | old->c3 = new->c3 - old->c3; |
999 | old->c6 = new->c6 - old->c6; | |
1000 | old->c7 = new->c7 - old->c7; | |
889facbe | 1001 | old->core_temp_c = new->core_temp_c; |
0539ba11 | 1002 | old->mc6_us = new->mc6_us - old->mc6_us; |
388e9c81 LB |
1003 | |
1004 | for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { | |
1005 | if (mp->format == FORMAT_RAW) | |
1006 | old->counter[i] = new->counter[i]; | |
1007 | else | |
1008 | old->counter[i] = new->counter[i] - old->counter[i]; | |
1009 | } | |
c98d5d94 | 1010 | } |
103a8fea | 1011 | |
c3ae331d LB |
1012 | /* |
1013 | * old = new - old | |
1014 | */ | |
ba3dec99 | 1015 | int |
c98d5d94 LB |
1016 | delta_thread(struct thread_data *new, struct thread_data *old, |
1017 | struct core_data *core_delta) | |
1018 | { | |
388e9c81 LB |
1019 | int i; |
1020 | struct msr_counter *mp; | |
1021 | ||
c98d5d94 LB |
1022 | old->tsc = new->tsc - old->tsc; |
1023 | ||
1024 | /* check for TSC < 1 Mcycles over interval */ | |
b2c95d90 JT |
1025 | if (old->tsc < (1000 * 1000)) |
1026 | errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" | |
1027 | "You can disable all c-states by booting with \"idle=poll\"\n" | |
1028 | "or just the deep ones with \"processor.max_cstate=1\""); | |
103a8fea | 1029 | |
c98d5d94 | 1030 | old->c1 = new->c1 - old->c1; |
103a8fea | 1031 | |
812db3f7 | 1032 | if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { |
a729617c LB |
1033 | if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { |
1034 | old->aperf = new->aperf - old->aperf; | |
1035 | old->mperf = new->mperf - old->mperf; | |
1036 | } else { | |
ba3dec99 | 1037 | return -1; |
103a8fea | 1038 | } |
c98d5d94 | 1039 | } |
103a8fea | 1040 | |
103a8fea | 1041 | |
144b44b1 LB |
1042 | if (use_c1_residency_msr) { |
1043 | /* | |
1044 | * Some models have a dedicated C1 residency MSR, | |
1045 | * which should be more accurate than the derivation below. | |
1046 | */ | |
1047 | } else { | |
1048 | /* | |
1049 | * As counter collection is not atomic, | |
1050 | * it is possible for mperf's non-halted cycles + idle states | |
1051 | * to exceed TSC's all cycles: show c1 = 0% in that case. | |
1052 | */ | |
1053 | if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) | |
1054 | old->c1 = 0; | |
1055 | else { | |
1056 | /* normal case, derive c1 */ | |
008d396e | 1057 | old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 |
c98d5d94 | 1058 | - core_delta->c6 - core_delta->c7; |
144b44b1 | 1059 | } |
c98d5d94 | 1060 | } |
c3ae331d | 1061 | |
c98d5d94 | 1062 | if (old->mperf == 0) { |
b7d8c148 LB |
1063 | if (debug > 1) |
1064 | fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); | |
c98d5d94 | 1065 | old->mperf = 1; /* divide by 0 protection */ |
103a8fea | 1066 | } |
c98d5d94 | 1067 | |
812db3f7 | 1068 | if (DO_BIC(BIC_IRQ)) |
562a2d37 LB |
1069 | old->irq_count = new->irq_count - old->irq_count; |
1070 | ||
812db3f7 | 1071 | if (DO_BIC(BIC_SMI)) |
1ed51011 | 1072 | old->smi_count = new->smi_count - old->smi_count; |
ba3dec99 | 1073 | |
388e9c81 LB |
1074 | for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { |
1075 | if (mp->format == FORMAT_RAW) | |
1076 | old->counter[i] = new->counter[i]; | |
1077 | else | |
1078 | old->counter[i] = new->counter[i] - old->counter[i]; | |
1079 | } | |
ba3dec99 | 1080 | return 0; |
c98d5d94 LB |
1081 | } |
1082 | ||
1083 | int delta_cpu(struct thread_data *t, struct core_data *c, | |
1084 | struct pkg_data *p, struct thread_data *t2, | |
1085 | struct core_data *c2, struct pkg_data *p2) | |
1086 | { | |
ba3dec99 LB |
1087 | int retval = 0; |
1088 | ||
c98d5d94 LB |
1089 | /* calculate core delta only for 1st thread in core */ |
1090 | if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) | |
1091 | delta_core(c, c2); | |
1092 | ||
1093 | /* always calculate thread delta */ | |
ba3dec99 LB |
1094 | retval = delta_thread(t, t2, c2); /* c2 is core delta */ |
1095 | if (retval) | |
1096 | return retval; | |
c98d5d94 LB |
1097 | |
1098 | /* calculate package delta only for 1st core in package */ | |
1099 | if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) | |
ba3dec99 | 1100 | retval = delta_package(p, p2); |
c98d5d94 | 1101 | |
ba3dec99 | 1102 | return retval; |
103a8fea LB |
1103 | } |
1104 | ||
c98d5d94 LB |
1105 | void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) |
1106 | { | |
388e9c81 LB |
1107 | int i; |
1108 | struct msr_counter *mp; | |
1109 | ||
c98d5d94 LB |
1110 | t->tsc = 0; |
1111 | t->aperf = 0; | |
1112 | t->mperf = 0; | |
1113 | t->c1 = 0; | |
1114 | ||
562a2d37 LB |
1115 | t->irq_count = 0; |
1116 | t->smi_count = 0; | |
1117 | ||
c98d5d94 LB |
1118 | /* tells format_counters to dump all fields from this set */ |
1119 | t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; | |
1120 | ||
1121 | c->c3 = 0; | |
1122 | c->c6 = 0; | |
1123 | c->c7 = 0; | |
0539ba11 | 1124 | c->mc6_us = 0; |
889facbe | 1125 | c->core_temp_c = 0; |
c98d5d94 | 1126 | |
0b2bb692 LB |
1127 | p->pkg_wtd_core_c0 = 0; |
1128 | p->pkg_any_core_c0 = 0; | |
1129 | p->pkg_any_gfxe_c0 = 0; | |
1130 | p->pkg_both_core_gfxe_c0 = 0; | |
1131 | ||
c98d5d94 | 1132 | p->pc2 = 0; |
0f47c08d | 1133 | if (DO_BIC(BIC_Pkgpc3)) |
ee7e38e3 | 1134 | p->pc3 = 0; |
0f47c08d | 1135 | if (DO_BIC(BIC_Pkgpc6)) |
ee7e38e3 | 1136 | p->pc6 = 0; |
0f47c08d | 1137 | if (DO_BIC(BIC_Pkgpc7)) |
ee7e38e3 | 1138 | p->pc7 = 0; |
ca58710f KCA |
1139 | p->pc8 = 0; |
1140 | p->pc9 = 0; | |
1141 | p->pc10 = 0; | |
889facbe LB |
1142 | |
1143 | p->energy_pkg = 0; | |
1144 | p->energy_dram = 0; | |
1145 | p->energy_cores = 0; | |
1146 | p->energy_gfx = 0; | |
1147 | p->rapl_pkg_perf_status = 0; | |
1148 | p->rapl_dram_perf_status = 0; | |
1149 | p->pkg_temp_c = 0; | |
27d47356 | 1150 | |
fdf676e5 | 1151 | p->gfx_rc6_ms = 0; |
27d47356 | 1152 | p->gfx_mhz = 0; |
388e9c81 LB |
1153 | for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) |
1154 | t->counter[i] = 0; | |
1155 | ||
1156 | for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) | |
1157 | c->counter[i] = 0; | |
1158 | ||
1159 | for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) | |
1160 | p->counter[i] = 0; | |
c98d5d94 LB |
1161 | } |
1162 | int sum_counters(struct thread_data *t, struct core_data *c, | |
1163 | struct pkg_data *p) | |
103a8fea | 1164 | { |
388e9c81 LB |
1165 | int i; |
1166 | struct msr_counter *mp; | |
1167 | ||
c98d5d94 LB |
1168 | average.threads.tsc += t->tsc; |
1169 | average.threads.aperf += t->aperf; | |
1170 | average.threads.mperf += t->mperf; | |
1171 | average.threads.c1 += t->c1; | |
103a8fea | 1172 | |
562a2d37 LB |
1173 | average.threads.irq_count += t->irq_count; |
1174 | average.threads.smi_count += t->smi_count; | |
1175 | ||
388e9c81 LB |
1176 | for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { |
1177 | if (mp->format == FORMAT_RAW) | |
1178 | continue; | |
1179 | average.threads.counter[i] += t->counter[i]; | |
1180 | } | |
1181 | ||
c98d5d94 LB |
1182 | /* sum per-core values only for 1st thread in core */ |
1183 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
1184 | return 0; | |
103a8fea | 1185 | |
c98d5d94 LB |
1186 | average.cores.c3 += c->c3; |
1187 | average.cores.c6 += c->c6; | |
1188 | average.cores.c7 += c->c7; | |
0539ba11 | 1189 | average.cores.mc6_us += c->mc6_us; |
c98d5d94 | 1190 | |
889facbe LB |
1191 | average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); |
1192 | ||
388e9c81 LB |
1193 | for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { |
1194 | if (mp->format == FORMAT_RAW) | |
1195 | continue; | |
1196 | average.cores.counter[i] += c->counter[i]; | |
1197 | } | |
1198 | ||
c98d5d94 LB |
1199 | /* sum per-pkg values only for 1st core in pkg */ |
1200 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
1201 | return 0; | |
1202 | ||
0b2bb692 LB |
1203 | if (do_skl_residency) { |
1204 | average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; | |
1205 | average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; | |
1206 | average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; | |
1207 | average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; | |
1208 | } | |
1209 | ||
c98d5d94 | 1210 | average.packages.pc2 += p->pc2; |
0f47c08d | 1211 | if (DO_BIC(BIC_Pkgpc3)) |
ee7e38e3 | 1212 | average.packages.pc3 += p->pc3; |
0f47c08d | 1213 | if (DO_BIC(BIC_Pkgpc6)) |
ee7e38e3 | 1214 | average.packages.pc6 += p->pc6; |
0f47c08d | 1215 | if (DO_BIC(BIC_Pkgpc7)) |
ee7e38e3 | 1216 | average.packages.pc7 += p->pc7; |
ca58710f KCA |
1217 | average.packages.pc8 += p->pc8; |
1218 | average.packages.pc9 += p->pc9; | |
1219 | average.packages.pc10 += p->pc10; | |
c98d5d94 | 1220 | |
889facbe LB |
1221 | average.packages.energy_pkg += p->energy_pkg; |
1222 | average.packages.energy_dram += p->energy_dram; | |
1223 | average.packages.energy_cores += p->energy_cores; | |
1224 | average.packages.energy_gfx += p->energy_gfx; | |
1225 | ||
fdf676e5 | 1226 | average.packages.gfx_rc6_ms = p->gfx_rc6_ms; |
27d47356 LB |
1227 | average.packages.gfx_mhz = p->gfx_mhz; |
1228 | ||
889facbe LB |
1229 | average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); |
1230 | ||
1231 | average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; | |
1232 | average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; | |
388e9c81 LB |
1233 | |
1234 | for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { | |
1235 | if (mp->format == FORMAT_RAW) | |
1236 | continue; | |
1237 | average.packages.counter[i] += p->counter[i]; | |
1238 | } | |
c98d5d94 LB |
1239 | return 0; |
1240 | } | |
1241 | /* | |
1242 | * sum the counters for all cpus in the system | |
1243 | * compute the weighted average | |
1244 | */ | |
1245 | void compute_average(struct thread_data *t, struct core_data *c, | |
1246 | struct pkg_data *p) | |
1247 | { | |
388e9c81 LB |
1248 | int i; |
1249 | struct msr_counter *mp; | |
1250 | ||
c98d5d94 LB |
1251 | clear_counters(&average.threads, &average.cores, &average.packages); |
1252 | ||
1253 | for_all_cpus(sum_counters, t, c, p); | |
1254 | ||
1255 | average.threads.tsc /= topo.num_cpus; | |
1256 | average.threads.aperf /= topo.num_cpus; | |
1257 | average.threads.mperf /= topo.num_cpus; | |
1258 | average.threads.c1 /= topo.num_cpus; | |
1259 | ||
1260 | average.cores.c3 /= topo.num_cores; | |
1261 | average.cores.c6 /= topo.num_cores; | |
1262 | average.cores.c7 /= topo.num_cores; | |
0539ba11 | 1263 | average.cores.mc6_us /= topo.num_cores; |
c98d5d94 | 1264 | |
0b2bb692 LB |
1265 | if (do_skl_residency) { |
1266 | average.packages.pkg_wtd_core_c0 /= topo.num_packages; | |
1267 | average.packages.pkg_any_core_c0 /= topo.num_packages; | |
1268 | average.packages.pkg_any_gfxe_c0 /= topo.num_packages; | |
1269 | average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; | |
1270 | } | |
1271 | ||
c98d5d94 | 1272 | average.packages.pc2 /= topo.num_packages; |
0f47c08d | 1273 | if (DO_BIC(BIC_Pkgpc3)) |
ee7e38e3 | 1274 | average.packages.pc3 /= topo.num_packages; |
0f47c08d | 1275 | if (DO_BIC(BIC_Pkgpc6)) |
ee7e38e3 | 1276 | average.packages.pc6 /= topo.num_packages; |
0f47c08d | 1277 | if (DO_BIC(BIC_Pkgpc7)) |
ee7e38e3 | 1278 | average.packages.pc7 /= topo.num_packages; |
ca58710f KCA |
1279 | |
1280 | average.packages.pc8 /= topo.num_packages; | |
1281 | average.packages.pc9 /= topo.num_packages; | |
1282 | average.packages.pc10 /= topo.num_packages; | |
388e9c81 LB |
1283 | |
1284 | for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { | |
1285 | if (mp->format == FORMAT_RAW) | |
1286 | continue; | |
1287 | average.threads.counter[i] /= topo.num_cpus; | |
1288 | } | |
1289 | for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { | |
1290 | if (mp->format == FORMAT_RAW) | |
1291 | continue; | |
1292 | average.cores.counter[i] /= topo.num_cores; | |
1293 | } | |
1294 | for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { | |
1295 | if (mp->format == FORMAT_RAW) | |
1296 | continue; | |
1297 | average.packages.counter[i] /= topo.num_packages; | |
1298 | } | |
103a8fea LB |
1299 | } |
1300 | ||
c98d5d94 | 1301 | static unsigned long long rdtsc(void) |
103a8fea | 1302 | { |
c98d5d94 | 1303 | unsigned int low, high; |
15aaa346 | 1304 | |
c98d5d94 | 1305 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
15aaa346 | 1306 | |
c98d5d94 LB |
1307 | return low | ((unsigned long long)high) << 32; |
1308 | } | |
15aaa346 | 1309 | |
c98d5d94 LB |
1310 | /* |
1311 | * get_counters(...) | |
1312 | * migrate to cpu | |
1313 | * acquire and record local counters for that cpu | |
1314 | */ | |
1315 | int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
1316 | { | |
1317 | int cpu = t->cpu_id; | |
889facbe | 1318 | unsigned long long msr; |
0102b067 | 1319 | int aperf_mperf_retry_count = 0; |
388e9c81 LB |
1320 | struct msr_counter *mp; |
1321 | int i; | |
88c3281f | 1322 | |
e52966c0 | 1323 | if (cpu_migrate(cpu)) { |
b7d8c148 | 1324 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
c98d5d94 | 1325 | return -1; |
e52966c0 | 1326 | } |
15aaa346 | 1327 | |
0102b067 | 1328 | retry: |
c98d5d94 LB |
1329 | t->tsc = rdtsc(); /* we are running on local CPU of interest */ |
1330 | ||
812db3f7 | 1331 | if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { |
0102b067 LB |
1332 | unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; |
1333 | ||
1334 | /* | |
1335 | * The TSC, APERF and MPERF must be read together for | |
1336 | * APERF/MPERF and MPERF/TSC to give accurate results. | |
1337 | * | |
1338 | * Unfortunately, APERF and MPERF are read by | |
1339 | * individual system call, so delays may occur | |
1340 | * between them. If the time to read them | |
1341 | * varies by a large amount, we re-read them. | |
1342 | */ | |
1343 | ||
1344 | /* | |
1345 | * This initial dummy APERF read has been seen to | |
1346 | * reduce jitter in the subsequent reads. | |
1347 | */ | |
1348 | ||
1349 | if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) | |
1350 | return -3; | |
1351 | ||
1352 | t->tsc = rdtsc(); /* re-read close to APERF */ | |
1353 | ||
1354 | tsc_before = t->tsc; | |
1355 | ||
9c63a650 | 1356 | if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) |
c98d5d94 | 1357 | return -3; |
0102b067 LB |
1358 | |
1359 | tsc_between = rdtsc(); | |
1360 | ||
9c63a650 | 1361 | if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) |
c98d5d94 | 1362 | return -4; |
0102b067 LB |
1363 | |
1364 | tsc_after = rdtsc(); | |
1365 | ||
1366 | aperf_time = tsc_between - tsc_before; | |
1367 | mperf_time = tsc_after - tsc_between; | |
1368 | ||
1369 | /* | |
1370 | * If the system call latency to read APERF and MPERF | |
1371 | * differ by more than 2x, then try again. | |
1372 | */ | |
1373 | if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { | |
1374 | aperf_mperf_retry_count++; | |
1375 | if (aperf_mperf_retry_count < 5) | |
1376 | goto retry; | |
1377 | else | |
1378 | warnx("cpu%d jitter %lld %lld", | |
1379 | cpu, aperf_time, mperf_time); | |
1380 | } | |
1381 | aperf_mperf_retry_count = 0; | |
1382 | ||
b2b34dfe HC |
1383 | t->aperf = t->aperf * aperf_mperf_multiplier; |
1384 | t->mperf = t->mperf * aperf_mperf_multiplier; | |
c98d5d94 LB |
1385 | } |
1386 | ||
812db3f7 | 1387 | if (DO_BIC(BIC_IRQ)) |
562a2d37 | 1388 | t->irq_count = irqs_per_cpu[cpu]; |
812db3f7 | 1389 | if (DO_BIC(BIC_SMI)) { |
1ed51011 LB |
1390 | if (get_msr(cpu, MSR_SMI_COUNT, &msr)) |
1391 | return -5; | |
1392 | t->smi_count = msr & 0xFFFFFFFF; | |
1393 | } | |
0539ba11 | 1394 | if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { |
144b44b1 LB |
1395 | if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) |
1396 | return -6; | |
1397 | } | |
1398 | ||
388e9c81 LB |
1399 | for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { |
1400 | if (get_msr(cpu, mp->msr_num, &t->counter[i])) | |
1401 | return -10; | |
1402 | } | |
1403 | ||
1404 | ||
c98d5d94 LB |
1405 | /* collect core counters only for 1st thread in core */ |
1406 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
1407 | return 0; | |
1408 | ||
812db3f7 | 1409 | if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) { |
c98d5d94 LB |
1410 | if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) |
1411 | return -6; | |
144b44b1 LB |
1412 | } |
1413 | ||
812db3f7 | 1414 | if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { |
c98d5d94 LB |
1415 | if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) |
1416 | return -7; | |
fb5d4327 DC |
1417 | } else if (do_knl_cstates) { |
1418 | if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) | |
1419 | return -7; | |
c98d5d94 LB |
1420 | } |
1421 | ||
812db3f7 | 1422 | if (DO_BIC(BIC_CPU_c7)) |
c98d5d94 LB |
1423 | if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) |
1424 | return -8; | |
1425 | ||
0539ba11 LB |
1426 | if (DO_BIC(BIC_Mod_c6)) |
1427 | if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) | |
1428 | return -8; | |
1429 | ||
812db3f7 | 1430 | if (DO_BIC(BIC_CoreTmp)) { |
889facbe LB |
1431 | if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) |
1432 | return -9; | |
1433 | c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); | |
1434 | } | |
1435 | ||
388e9c81 LB |
1436 | for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { |
1437 | if (get_msr(cpu, mp->msr_num, &c->counter[i])) | |
1438 | return -10; | |
1439 | } | |
889facbe | 1440 | |
c98d5d94 LB |
1441 | /* collect package counters only for 1st core in package */ |
1442 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
1443 | return 0; | |
1444 | ||
0b2bb692 LB |
1445 | if (do_skl_residency) { |
1446 | if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) | |
1447 | return -10; | |
1448 | if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) | |
1449 | return -11; | |
1450 | if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) | |
1451 | return -12; | |
1452 | if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) | |
1453 | return -13; | |
1454 | } | |
0f47c08d | 1455 | if (DO_BIC(BIC_Pkgpc3)) |
c98d5d94 LB |
1456 | if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) |
1457 | return -9; | |
0f47c08d | 1458 | if (DO_BIC(BIC_Pkgpc6)) { |
0539ba11 LB |
1459 | if (do_slm_cstates) { |
1460 | if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) | |
1461 | return -10; | |
1462 | } else { | |
1463 | if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) | |
1464 | return -10; | |
1465 | } | |
1466 | } | |
1467 | ||
0f47c08d | 1468 | if (DO_BIC(BIC_Pkgpc2)) |
c98d5d94 LB |
1469 | if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) |
1470 | return -11; | |
0f47c08d | 1471 | if (DO_BIC(BIC_Pkgpc7)) |
c98d5d94 LB |
1472 | if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) |
1473 | return -12; | |
0f47c08d | 1474 | if (DO_BIC(BIC_Pkgpc8)) |
ca58710f KCA |
1475 | if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) |
1476 | return -13; | |
0f47c08d | 1477 | if (DO_BIC(BIC_Pkgpc9)) |
ca58710f KCA |
1478 | if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) |
1479 | return -13; | |
0f47c08d | 1480 | if (DO_BIC(BIC_Pkgpc10)) |
ca58710f KCA |
1481 | if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) |
1482 | return -13; | |
0f47c08d | 1483 | |
889facbe LB |
1484 | if (do_rapl & RAPL_PKG) { |
1485 | if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) | |
1486 | return -13; | |
1487 | p->energy_pkg = msr & 0xFFFFFFFF; | |
1488 | } | |
9148494c | 1489 | if (do_rapl & RAPL_CORES_ENERGY_STATUS) { |
889facbe LB |
1490 | if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) |
1491 | return -14; | |
1492 | p->energy_cores = msr & 0xFFFFFFFF; | |
1493 | } | |
1494 | if (do_rapl & RAPL_DRAM) { | |
1495 | if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) | |
1496 | return -15; | |
1497 | p->energy_dram = msr & 0xFFFFFFFF; | |
1498 | } | |
1499 | if (do_rapl & RAPL_GFX) { | |
1500 | if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) | |
1501 | return -16; | |
1502 | p->energy_gfx = msr & 0xFFFFFFFF; | |
1503 | } | |
1504 | if (do_rapl & RAPL_PKG_PERF_STATUS) { | |
1505 | if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) | |
1506 | return -16; | |
1507 | p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; | |
1508 | } | |
1509 | if (do_rapl & RAPL_DRAM_PERF_STATUS) { | |
1510 | if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) | |
1511 | return -16; | |
1512 | p->rapl_dram_perf_status = msr & 0xFFFFFFFF; | |
1513 | } | |
812db3f7 | 1514 | if (DO_BIC(BIC_PkgTmp)) { |
889facbe LB |
1515 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) |
1516 | return -17; | |
1517 | p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); | |
1518 | } | |
fdf676e5 | 1519 | |
812db3f7 | 1520 | if (DO_BIC(BIC_GFX_rc6)) |
fdf676e5 LB |
1521 | p->gfx_rc6_ms = gfx_cur_rc6_ms; |
1522 | ||
812db3f7 | 1523 | if (DO_BIC(BIC_GFXMHz)) |
27d47356 LB |
1524 | p->gfx_mhz = gfx_cur_mhz; |
1525 | ||
388e9c81 LB |
1526 | for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { |
1527 | if (get_msr(cpu, mp->msr_num, &p->counter[i])) | |
1528 | return -10; | |
1529 | } | |
1530 | ||
15aaa346 | 1531 | return 0; |
103a8fea LB |
1532 | } |
1533 | ||
ee7e38e3 LB |
1534 | /* |
1535 | * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: | |
1536 | * If you change the values, note they are used both in comparisons | |
1537 | * (>= PCL__7) and to index pkg_cstate_limit_strings[]. | |
1538 | */ | |
1539 | ||
1540 | #define PCLUKN 0 /* Unknown */ | |
1541 | #define PCLRSV 1 /* Reserved */ | |
1542 | #define PCL__0 2 /* PC0 */ | |
1543 | #define PCL__1 3 /* PC1 */ | |
1544 | #define PCL__2 4 /* PC2 */ | |
1545 | #define PCL__3 5 /* PC3 */ | |
1546 | #define PCL__4 6 /* PC4 */ | |
1547 | #define PCL__6 7 /* PC6 */ | |
1548 | #define PCL_6N 8 /* PC6 No Retention */ | |
1549 | #define PCL_6R 9 /* PC6 Retention */ | |
1550 | #define PCL__7 10 /* PC7 */ | |
1551 | #define PCL_7S 11 /* PC7 Shrink */ | |
0b2bb692 LB |
1552 | #define PCL__8 12 /* PC8 */ |
1553 | #define PCL__9 13 /* PC9 */ | |
1554 | #define PCLUNL 14 /* Unlimited */ | |
ee7e38e3 LB |
1555 | |
1556 | int pkg_cstate_limit = PCLUKN; | |
1557 | char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", | |
0b2bb692 | 1558 | "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; |
ee7e38e3 | 1559 | |
e9257f5f LB |
1560 | int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; |
1561 | int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; | |
1562 | int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; | |
0539ba11 | 1563 | int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; |
f2642888 | 1564 | int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; |
e9257f5f | 1565 | int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; |
e4085d54 | 1566 | int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; |
d8ebb442 | 1567 | int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; |
ee7e38e3 | 1568 | |
a2b7b749 LB |
1569 | |
1570 | static void | |
1571 | calculate_tsc_tweak() | |
1572 | { | |
a2b7b749 LB |
1573 | tsc_tweak = base_hz / tsc_hz; |
1574 | } | |
1575 | ||
fcd17211 LB |
1576 | static void |
1577 | dump_nhm_platform_info(void) | |
103a8fea LB |
1578 | { |
1579 | unsigned long long msr; | |
1580 | unsigned int ratio; | |
1581 | ||
ec0adc53 | 1582 | get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); |
103a8fea | 1583 | |
b7d8c148 | 1584 | fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); |
6574a5d5 | 1585 | |
103a8fea | 1586 | ratio = (msr >> 40) & 0xFF; |
710f273b | 1587 | fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", |
103a8fea LB |
1588 | ratio, bclk, ratio * bclk); |
1589 | ||
1590 | ratio = (msr >> 8) & 0xFF; | |
710f273b | 1591 | fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", |
103a8fea LB |
1592 | ratio, bclk, ratio * bclk); |
1593 | ||
7ce7d5de | 1594 | get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); |
b7d8c148 | 1595 | fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", |
bfae2052 | 1596 | base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); |
67920418 | 1597 | |
fcd17211 LB |
1598 | return; |
1599 | } | |
1600 | ||
1601 | static void | |
1602 | dump_hsw_turbo_ratio_limits(void) | |
1603 | { | |
1604 | unsigned long long msr; | |
1605 | unsigned int ratio; | |
1606 | ||
7ce7d5de | 1607 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); |
fcd17211 | 1608 | |
b7d8c148 | 1609 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); |
fcd17211 LB |
1610 | |
1611 | ratio = (msr >> 8) & 0xFF; | |
1612 | if (ratio) | |
710f273b | 1613 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", |
fcd17211 LB |
1614 | ratio, bclk, ratio * bclk); |
1615 | ||
1616 | ratio = (msr >> 0) & 0xFF; | |
1617 | if (ratio) | |
710f273b | 1618 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", |
fcd17211 LB |
1619 | ratio, bclk, ratio * bclk); |
1620 | return; | |
1621 | } | |
1622 | ||
1623 | static void | |
1624 | dump_ivt_turbo_ratio_limits(void) | |
1625 | { | |
1626 | unsigned long long msr; | |
1627 | unsigned int ratio; | |
6574a5d5 | 1628 | |
7ce7d5de | 1629 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); |
6574a5d5 | 1630 | |
b7d8c148 | 1631 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); |
6574a5d5 LB |
1632 | |
1633 | ratio = (msr >> 56) & 0xFF; | |
1634 | if (ratio) | |
710f273b | 1635 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", |
6574a5d5 LB |
1636 | ratio, bclk, ratio * bclk); |
1637 | ||
1638 | ratio = (msr >> 48) & 0xFF; | |
1639 | if (ratio) | |
710f273b | 1640 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", |
6574a5d5 LB |
1641 | ratio, bclk, ratio * bclk); |
1642 | ||
1643 | ratio = (msr >> 40) & 0xFF; | |
1644 | if (ratio) | |
710f273b | 1645 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", |
6574a5d5 LB |
1646 | ratio, bclk, ratio * bclk); |
1647 | ||
1648 | ratio = (msr >> 32) & 0xFF; | |
1649 | if (ratio) | |
710f273b | 1650 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", |
6574a5d5 LB |
1651 | ratio, bclk, ratio * bclk); |
1652 | ||
1653 | ratio = (msr >> 24) & 0xFF; | |
1654 | if (ratio) | |
710f273b | 1655 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", |
6574a5d5 LB |
1656 | ratio, bclk, ratio * bclk); |
1657 | ||
1658 | ratio = (msr >> 16) & 0xFF; | |
1659 | if (ratio) | |
710f273b | 1660 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", |
6574a5d5 LB |
1661 | ratio, bclk, ratio * bclk); |
1662 | ||
1663 | ratio = (msr >> 8) & 0xFF; | |
1664 | if (ratio) | |
710f273b | 1665 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", |
6574a5d5 LB |
1666 | ratio, bclk, ratio * bclk); |
1667 | ||
1668 | ratio = (msr >> 0) & 0xFF; | |
1669 | if (ratio) | |
710f273b | 1670 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", |
6574a5d5 | 1671 | ratio, bclk, ratio * bclk); |
fcd17211 LB |
1672 | return; |
1673 | } | |
31e07522 LB |
1674 | int has_turbo_ratio_group_limits(int family, int model) |
1675 | { | |
1676 | ||
1677 | if (!genuine_intel) | |
1678 | return 0; | |
1679 | ||
1680 | switch (model) { | |
1681 | case INTEL_FAM6_ATOM_GOLDMONT: | |
1682 | case INTEL_FAM6_SKYLAKE_X: | |
1683 | case INTEL_FAM6_ATOM_DENVERTON: | |
1684 | return 1; | |
1685 | } | |
1686 | return 0; | |
1687 | } | |
6574a5d5 | 1688 | |
fcd17211 | 1689 | static void |
31e07522 | 1690 | dump_turbo_ratio_limits(int family, int model) |
fcd17211 | 1691 | { |
31e07522 LB |
1692 | unsigned long long msr, core_counts; |
1693 | unsigned int ratio, group_size; | |
103a8fea | 1694 | |
7ce7d5de | 1695 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); |
b7d8c148 | 1696 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); |
6574a5d5 | 1697 | |
31e07522 LB |
1698 | if (has_turbo_ratio_group_limits(family, model)) { |
1699 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); | |
1700 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); | |
1701 | } else { | |
1702 | core_counts = 0x0807060504030201; | |
1703 | } | |
1704 | ||
6574a5d5 | 1705 | ratio = (msr >> 56) & 0xFF; |
31e07522 | 1706 | group_size = (core_counts >> 56) & 0xFF; |
6574a5d5 | 1707 | if (ratio) |
31e07522 LB |
1708 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1709 | ratio, bclk, ratio * bclk, group_size); | |
6574a5d5 LB |
1710 | |
1711 | ratio = (msr >> 48) & 0xFF; | |
31e07522 | 1712 | group_size = (core_counts >> 48) & 0xFF; |
6574a5d5 | 1713 | if (ratio) |
31e07522 LB |
1714 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1715 | ratio, bclk, ratio * bclk, group_size); | |
6574a5d5 LB |
1716 | |
1717 | ratio = (msr >> 40) & 0xFF; | |
31e07522 | 1718 | group_size = (core_counts >> 40) & 0xFF; |
6574a5d5 | 1719 | if (ratio) |
31e07522 LB |
1720 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1721 | ratio, bclk, ratio * bclk, group_size); | |
6574a5d5 LB |
1722 | |
1723 | ratio = (msr >> 32) & 0xFF; | |
31e07522 | 1724 | group_size = (core_counts >> 32) & 0xFF; |
6574a5d5 | 1725 | if (ratio) |
31e07522 LB |
1726 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1727 | ratio, bclk, ratio * bclk, group_size); | |
6574a5d5 | 1728 | |
103a8fea | 1729 | ratio = (msr >> 24) & 0xFF; |
31e07522 | 1730 | group_size = (core_counts >> 24) & 0xFF; |
103a8fea | 1731 | if (ratio) |
31e07522 LB |
1732 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1733 | ratio, bclk, ratio * bclk, group_size); | |
103a8fea LB |
1734 | |
1735 | ratio = (msr >> 16) & 0xFF; | |
31e07522 | 1736 | group_size = (core_counts >> 16) & 0xFF; |
103a8fea | 1737 | if (ratio) |
31e07522 LB |
1738 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1739 | ratio, bclk, ratio * bclk, group_size); | |
103a8fea LB |
1740 | |
1741 | ratio = (msr >> 8) & 0xFF; | |
31e07522 | 1742 | group_size = (core_counts >> 8) & 0xFF; |
103a8fea | 1743 | if (ratio) |
31e07522 LB |
1744 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1745 | ratio, bclk, ratio * bclk, group_size); | |
103a8fea LB |
1746 | |
1747 | ratio = (msr >> 0) & 0xFF; | |
31e07522 | 1748 | group_size = (core_counts >> 0) & 0xFF; |
103a8fea | 1749 | if (ratio) |
31e07522 LB |
1750 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
1751 | ratio, bclk, ratio * bclk, group_size); | |
fcd17211 LB |
1752 | return; |
1753 | } | |
3a9a941d | 1754 | |
0f7887c4 LB |
1755 | static void |
1756 | dump_atom_turbo_ratio_limits(void) | |
1757 | { | |
1758 | unsigned long long msr; | |
1759 | unsigned int ratio; | |
1760 | ||
1761 | get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); | |
1762 | fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); | |
1763 | ||
1764 | ratio = (msr >> 0) & 0x3F; | |
1765 | if (ratio) | |
1766 | fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", | |
1767 | ratio, bclk, ratio * bclk); | |
1768 | ||
1769 | ratio = (msr >> 8) & 0x3F; | |
1770 | if (ratio) | |
1771 | fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", | |
1772 | ratio, bclk, ratio * bclk); | |
1773 | ||
1774 | ratio = (msr >> 16) & 0x3F; | |
1775 | if (ratio) | |
1776 | fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", | |
1777 | ratio, bclk, ratio * bclk); | |
1778 | ||
1779 | get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); | |
1780 | fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); | |
1781 | ||
1782 | ratio = (msr >> 24) & 0x3F; | |
1783 | if (ratio) | |
1784 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", | |
1785 | ratio, bclk, ratio * bclk); | |
1786 | ||
1787 | ratio = (msr >> 16) & 0x3F; | |
1788 | if (ratio) | |
1789 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", | |
1790 | ratio, bclk, ratio * bclk); | |
1791 | ||
1792 | ratio = (msr >> 8) & 0x3F; | |
1793 | if (ratio) | |
1794 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", | |
1795 | ratio, bclk, ratio * bclk); | |
1796 | ||
1797 | ratio = (msr >> 0) & 0x3F; | |
1798 | if (ratio) | |
1799 | fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", | |
1800 | ratio, bclk, ratio * bclk); | |
1801 | } | |
1802 | ||
fb5d4327 DC |
1803 | static void |
1804 | dump_knl_turbo_ratio_limits(void) | |
1805 | { | |
cbf97aba HC |
1806 | const unsigned int buckets_no = 7; |
1807 | ||
fb5d4327 | 1808 | unsigned long long msr; |
cbf97aba HC |
1809 | int delta_cores, delta_ratio; |
1810 | int i, b_nr; | |
1811 | unsigned int cores[buckets_no]; | |
1812 | unsigned int ratio[buckets_no]; | |
fb5d4327 | 1813 | |
ebf5926a | 1814 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); |
fb5d4327 | 1815 | |
b7d8c148 | 1816 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", |
bfae2052 | 1817 | base_cpu, msr); |
fb5d4327 DC |
1818 | |
1819 | /** | |
1820 | * Turbo encoding in KNL is as follows: | |
cbf97aba HC |
1821 | * [0] -- Reserved |
1822 | * [7:1] -- Base value of number of active cores of bucket 1. | |
fb5d4327 DC |
1823 | * [15:8] -- Base value of freq ratio of bucket 1. |
1824 | * [20:16] -- +ve delta of number of active cores of bucket 2. | |
1825 | * i.e. active cores of bucket 2 = | |
1826 | * active cores of bucket 1 + delta | |
1827 | * [23:21] -- Negative delta of freq ratio of bucket 2. | |
1828 | * i.e. freq ratio of bucket 2 = | |
1829 | * freq ratio of bucket 1 - delta | |
1830 | * [28:24]-- +ve delta of number of active cores of bucket 3. | |
1831 | * [31:29]-- -ve delta of freq ratio of bucket 3. | |
1832 | * [36:32]-- +ve delta of number of active cores of bucket 4. | |
1833 | * [39:37]-- -ve delta of freq ratio of bucket 4. | |
1834 | * [44:40]-- +ve delta of number of active cores of bucket 5. | |
1835 | * [47:45]-- -ve delta of freq ratio of bucket 5. | |
1836 | * [52:48]-- +ve delta of number of active cores of bucket 6. | |
1837 | * [55:53]-- -ve delta of freq ratio of bucket 6. | |
1838 | * [60:56]-- +ve delta of number of active cores of bucket 7. | |
1839 | * [63:61]-- -ve delta of freq ratio of bucket 7. | |
1840 | */ | |
cbf97aba HC |
1841 | |
1842 | b_nr = 0; | |
1843 | cores[b_nr] = (msr & 0xFF) >> 1; | |
1844 | ratio[b_nr] = (msr >> 8) & 0xFF; | |
1845 | ||
1846 | for (i = 16; i < 64; i += 8) { | |
fb5d4327 | 1847 | delta_cores = (msr >> i) & 0x1F; |
cbf97aba HC |
1848 | delta_ratio = (msr >> (i + 5)) & 0x7; |
1849 | ||
1850 | cores[b_nr + 1] = cores[b_nr] + delta_cores; | |
1851 | ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; | |
1852 | b_nr++; | |
fb5d4327 | 1853 | } |
cbf97aba HC |
1854 | |
1855 | for (i = buckets_no - 1; i >= 0; i--) | |
1856 | if (i > 0 ? ratio[i] != ratio[i - 1] : 1) | |
b7d8c148 | 1857 | fprintf(outf, |
710f273b | 1858 | "%d * %.1f = %.1f MHz max turbo %d active cores\n", |
cbf97aba | 1859 | ratio[i], bclk, ratio[i] * bclk, cores[i]); |
fb5d4327 DC |
1860 | } |
1861 | ||
fcd17211 LB |
1862 | static void |
1863 | dump_nhm_cst_cfg(void) | |
1864 | { | |
1865 | unsigned long long msr; | |
1866 | ||
1df2e55a | 1867 | get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); |
fcd17211 LB |
1868 | |
1869 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) | |
1870 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) | |
1871 | ||
1df2e55a | 1872 | fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); |
fcd17211 | 1873 | |
b7d8c148 | 1874 | fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", |
fcd17211 LB |
1875 | (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", |
1876 | (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", | |
1877 | (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", | |
1878 | (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", | |
1879 | (msr & (1 << 15)) ? "" : "UN", | |
6c34f160 | 1880 | (unsigned int)msr & 0xF, |
fcd17211 LB |
1881 | pkg_cstate_limit_strings[pkg_cstate_limit]); |
1882 | return; | |
103a8fea LB |
1883 | } |
1884 | ||
6fb3143b LB |
1885 | static void |
1886 | dump_config_tdp(void) | |
1887 | { | |
1888 | unsigned long long msr; | |
1889 | ||
1890 | get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); | |
b7d8c148 | 1891 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); |
685b535b | 1892 | fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); |
6fb3143b LB |
1893 | |
1894 | get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); | |
b7d8c148 | 1895 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); |
6fb3143b | 1896 | if (msr) { |
685b535b CY |
1897 | fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); |
1898 | fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); | |
1899 | fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); | |
1900 | fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); | |
6fb3143b | 1901 | } |
b7d8c148 | 1902 | fprintf(outf, ")\n"); |
6fb3143b LB |
1903 | |
1904 | get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); | |
b7d8c148 | 1905 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); |
6fb3143b | 1906 | if (msr) { |
685b535b CY |
1907 | fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); |
1908 | fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); | |
1909 | fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); | |
1910 | fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); | |
6fb3143b | 1911 | } |
b7d8c148 | 1912 | fprintf(outf, ")\n"); |
6fb3143b LB |
1913 | |
1914 | get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); | |
b7d8c148 | 1915 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); |
6fb3143b | 1916 | if ((msr) & 0x3) |
b7d8c148 LB |
1917 | fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); |
1918 | fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); | |
1919 | fprintf(outf, ")\n"); | |
36229897 | 1920 | |
6fb3143b | 1921 | get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); |
b7d8c148 | 1922 | fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); |
685b535b | 1923 | fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); |
b7d8c148 LB |
1924 | fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); |
1925 | fprintf(outf, ")\n"); | |
6fb3143b | 1926 | } |
5a63426e LB |
1927 | |
1928 | unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; | |
1929 | ||
1930 | void print_irtl(void) | |
1931 | { | |
1932 | unsigned long long msr; | |
1933 | ||
1934 | get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); | |
1935 | fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); | |
1936 | fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", | |
1937 | (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); | |
1938 | ||
1939 | get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); | |
1940 | fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); | |
1941 | fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", | |
1942 | (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); | |
1943 | ||
1944 | get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); | |
1945 | fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); | |
1946 | fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", | |
1947 | (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); | |
1948 | ||
1949 | if (!do_irtl_hsw) | |
1950 | return; | |
1951 | ||
1952 | get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); | |
1953 | fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); | |
1954 | fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", | |
1955 | (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); | |
1956 | ||
1957 | get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); | |
1958 | fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); | |
1959 | fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", | |
1960 | (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); | |
1961 | ||
1962 | get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); | |
1963 | fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); | |
1964 | fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", | |
1965 | (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); | |
1966 | ||
1967 | } | |
36229897 LB |
1968 | void free_fd_percpu(void) |
1969 | { | |
1970 | int i; | |
1971 | ||
01a67adf | 1972 | for (i = 0; i < topo.max_cpu_num + 1; ++i) { |
36229897 LB |
1973 | if (fd_percpu[i] != 0) |
1974 | close(fd_percpu[i]); | |
1975 | } | |
1976 | ||
1977 | free(fd_percpu); | |
6fb3143b LB |
1978 | } |
1979 | ||
c98d5d94 | 1980 | void free_all_buffers(void) |
103a8fea | 1981 | { |
c98d5d94 LB |
1982 | CPU_FREE(cpu_present_set); |
1983 | cpu_present_set = NULL; | |
36229897 | 1984 | cpu_present_setsize = 0; |
103a8fea | 1985 | |
c98d5d94 LB |
1986 | CPU_FREE(cpu_affinity_set); |
1987 | cpu_affinity_set = NULL; | |
1988 | cpu_affinity_setsize = 0; | |
103a8fea | 1989 | |
c98d5d94 LB |
1990 | free(thread_even); |
1991 | free(core_even); | |
1992 | free(package_even); | |
103a8fea | 1993 | |
c98d5d94 LB |
1994 | thread_even = NULL; |
1995 | core_even = NULL; | |
1996 | package_even = NULL; | |
103a8fea | 1997 | |
c98d5d94 LB |
1998 | free(thread_odd); |
1999 | free(core_odd); | |
2000 | free(package_odd); | |
103a8fea | 2001 | |
c98d5d94 LB |
2002 | thread_odd = NULL; |
2003 | core_odd = NULL; | |
2004 | package_odd = NULL; | |
103a8fea | 2005 | |
c98d5d94 LB |
2006 | free(output_buffer); |
2007 | output_buffer = NULL; | |
2008 | outp = NULL; | |
36229897 LB |
2009 | |
2010 | free_fd_percpu(); | |
562a2d37 LB |
2011 | |
2012 | free(irq_column_2_cpu); | |
2013 | free(irqs_per_cpu); | |
103a8fea LB |
2014 | } |
2015 | ||
57a42a34 JT |
2016 | /* |
2017 | * Open a file, and exit on failure | |
2018 | */ | |
2019 | FILE *fopen_or_die(const char *path, const char *mode) | |
2020 | { | |
b7d8c148 | 2021 | FILE *filep = fopen(path, mode); |
b2c95d90 JT |
2022 | if (!filep) |
2023 | err(1, "%s: open failed", path); | |
57a42a34 JT |
2024 | return filep; |
2025 | } | |
2026 | ||
c98d5d94 | 2027 | /* |
95aebc44 | 2028 | * Parse a file containing a single int. |
c98d5d94 | 2029 | */ |
95aebc44 | 2030 | int parse_int_file(const char *fmt, ...) |
103a8fea | 2031 | { |
95aebc44 JT |
2032 | va_list args; |
2033 | char path[PATH_MAX]; | |
c98d5d94 | 2034 | FILE *filep; |
95aebc44 | 2035 | int value; |
103a8fea | 2036 | |
95aebc44 JT |
2037 | va_start(args, fmt); |
2038 | vsnprintf(path, sizeof(path), fmt, args); | |
2039 | va_end(args); | |
57a42a34 | 2040 | filep = fopen_or_die(path, "r"); |
b2c95d90 JT |
2041 | if (fscanf(filep, "%d", &value) != 1) |
2042 | err(1, "%s: failed to parse number from file", path); | |
c98d5d94 | 2043 | fclose(filep); |
95aebc44 JT |
2044 | return value; |
2045 | } | |
2046 | ||
2047 | /* | |
e275b388 DC |
2048 | * get_cpu_position_in_core(cpu) |
2049 | * return the position of the CPU among its HT siblings in the core | |
2050 | * return -1 if the sibling is not in list | |
95aebc44 | 2051 | */ |
e275b388 | 2052 | int get_cpu_position_in_core(int cpu) |
95aebc44 | 2053 | { |
e275b388 DC |
2054 | char path[64]; |
2055 | FILE *filep; | |
2056 | int this_cpu; | |
2057 | char character; | |
2058 | int i; | |
2059 | ||
2060 | sprintf(path, | |
2061 | "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", | |
2062 | cpu); | |
2063 | filep = fopen(path, "r"); | |
2064 | if (filep == NULL) { | |
2065 | perror(path); | |
2066 | exit(1); | |
2067 | } | |
2068 | ||
2069 | for (i = 0; i < topo.num_threads_per_core; i++) { | |
2070 | fscanf(filep, "%d", &this_cpu); | |
2071 | if (this_cpu == cpu) { | |
2072 | fclose(filep); | |
2073 | return i; | |
2074 | } | |
2075 | ||
2076 | /* Account for no separator after last thread*/ | |
2077 | if (i != (topo.num_threads_per_core - 1)) | |
2078 | fscanf(filep, "%c", &character); | |
2079 | } | |
2080 | ||
2081 | fclose(filep); | |
2082 | return -1; | |
103a8fea LB |
2083 | } |
2084 | ||
c98d5d94 LB |
2085 | /* |
2086 | * cpu_is_first_core_in_package(cpu) | |
2087 | * return 1 if given CPU is 1st core in package | |
2088 | */ | |
2089 | int cpu_is_first_core_in_package(int cpu) | |
103a8fea | 2090 | { |
95aebc44 | 2091 | return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); |
103a8fea LB |
2092 | } |
2093 | ||
2094 | int get_physical_package_id(int cpu) | |
2095 | { | |
95aebc44 | 2096 | return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); |
103a8fea LB |
2097 | } |
2098 | ||
2099 | int get_core_id(int cpu) | |
2100 | { | |
95aebc44 | 2101 | return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); |
103a8fea LB |
2102 | } |
2103 | ||
c98d5d94 LB |
2104 | int get_num_ht_siblings(int cpu) |
2105 | { | |
2106 | char path[80]; | |
2107 | FILE *filep; | |
e275b388 DC |
2108 | int sib1; |
2109 | int matches = 0; | |
c98d5d94 | 2110 | char character; |
e275b388 DC |
2111 | char str[100]; |
2112 | char *ch; | |
c98d5d94 LB |
2113 | |
2114 | sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); | |
57a42a34 | 2115 | filep = fopen_or_die(path, "r"); |
e275b388 | 2116 | |
c98d5d94 LB |
2117 | /* |
2118 | * file format: | |
e275b388 DC |
2119 | * A ',' separated or '-' separated set of numbers |
2120 | * (eg 1-2 or 1,3,4,5) | |
c98d5d94 | 2121 | */ |
e275b388 DC |
2122 | fscanf(filep, "%d%c\n", &sib1, &character); |
2123 | fseek(filep, 0, SEEK_SET); | |
2124 | fgets(str, 100, filep); | |
2125 | ch = strchr(str, character); | |
2126 | while (ch != NULL) { | |
2127 | matches++; | |
2128 | ch = strchr(ch+1, character); | |
2129 | } | |
c98d5d94 LB |
2130 | |
2131 | fclose(filep); | |
e275b388 | 2132 | return matches+1; |
c98d5d94 LB |
2133 | } |
2134 | ||
103a8fea | 2135 | /* |
c98d5d94 LB |
2136 | * run func(thread, core, package) in topology order |
2137 | * skip non-present cpus | |
103a8fea LB |
2138 | */ |
2139 | ||
c98d5d94 LB |
2140 | int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, |
2141 | struct pkg_data *, struct thread_data *, struct core_data *, | |
2142 | struct pkg_data *), struct thread_data *thread_base, | |
2143 | struct core_data *core_base, struct pkg_data *pkg_base, | |
2144 | struct thread_data *thread_base2, struct core_data *core_base2, | |
2145 | struct pkg_data *pkg_base2) | |
2146 | { | |
2147 | int retval, pkg_no, core_no, thread_no; | |
2148 | ||
2149 | for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { | |
2150 | for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { | |
2151 | for (thread_no = 0; thread_no < | |
2152 | topo.num_threads_per_core; ++thread_no) { | |
2153 | struct thread_data *t, *t2; | |
2154 | struct core_data *c, *c2; | |
2155 | struct pkg_data *p, *p2; | |
2156 | ||
2157 | t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); | |
2158 | ||
2159 | if (cpu_is_not_present(t->cpu_id)) | |
2160 | continue; | |
2161 | ||
2162 | t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); | |
2163 | ||
2164 | c = GET_CORE(core_base, core_no, pkg_no); | |
2165 | c2 = GET_CORE(core_base2, core_no, pkg_no); | |
2166 | ||
2167 | p = GET_PKG(pkg_base, pkg_no); | |
2168 | p2 = GET_PKG(pkg_base2, pkg_no); | |
2169 | ||
2170 | retval = func(t, c, p, t2, c2, p2); | |
2171 | if (retval) | |
2172 | return retval; | |
2173 | } | |
2174 | } | |
2175 | } | |
2176 | return 0; | |
2177 | } | |
2178 | ||
2179 | /* | |
2180 | * run func(cpu) on every cpu in /proc/stat | |
2181 | * return max_cpu number | |
2182 | */ | |
2183 | int for_all_proc_cpus(int (func)(int)) | |
103a8fea LB |
2184 | { |
2185 | FILE *fp; | |
c98d5d94 | 2186 | int cpu_num; |
103a8fea LB |
2187 | int retval; |
2188 | ||
57a42a34 | 2189 | fp = fopen_or_die(proc_stat, "r"); |
103a8fea LB |
2190 | |
2191 | retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); | |
b2c95d90 JT |
2192 | if (retval != 0) |
2193 | err(1, "%s: failed to parse format", proc_stat); | |
103a8fea | 2194 | |
c98d5d94 LB |
2195 | while (1) { |
2196 | retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); | |
103a8fea LB |
2197 | if (retval != 1) |
2198 | break; | |
2199 | ||
c98d5d94 LB |
2200 | retval = func(cpu_num); |
2201 | if (retval) { | |
2202 | fclose(fp); | |
2203 | return(retval); | |
2204 | } | |
103a8fea LB |
2205 | } |
2206 | fclose(fp); | |
c98d5d94 | 2207 | return 0; |
103a8fea LB |
2208 | } |
2209 | ||
2210 | void re_initialize(void) | |
2211 | { | |
c98d5d94 LB |
2212 | free_all_buffers(); |
2213 | setup_all_buffers(); | |
2214 | printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); | |
103a8fea LB |
2215 | } |
2216 | ||
c98d5d94 | 2217 | |
103a8fea | 2218 | /* |
c98d5d94 LB |
2219 | * count_cpus() |
2220 | * remember the last one seen, it will be the max | |
103a8fea | 2221 | */ |
c98d5d94 | 2222 | int count_cpus(int cpu) |
103a8fea | 2223 | { |
c98d5d94 LB |
2224 | if (topo.max_cpu_num < cpu) |
2225 | topo.max_cpu_num = cpu; | |
103a8fea | 2226 | |
c98d5d94 LB |
2227 | topo.num_cpus += 1; |
2228 | return 0; | |
2229 | } | |
2230 | int mark_cpu_present(int cpu) | |
2231 | { | |
2232 | CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); | |
15aaa346 | 2233 | return 0; |
103a8fea LB |
2234 | } |
2235 | ||
562a2d37 LB |
2236 | /* |
2237 | * snapshot_proc_interrupts() | |
2238 | * | |
2239 | * read and record summary of /proc/interrupts | |
2240 | * | |
2241 | * return 1 if config change requires a restart, else return 0 | |
2242 | */ | |
2243 | int snapshot_proc_interrupts(void) | |
2244 | { | |
2245 | static FILE *fp; | |
2246 | int column, retval; | |
2247 | ||
2248 | if (fp == NULL) | |
2249 | fp = fopen_or_die("/proc/interrupts", "r"); | |
2250 | else | |
2251 | rewind(fp); | |
2252 | ||
2253 | /* read 1st line of /proc/interrupts to get cpu* name for each column */ | |
2254 | for (column = 0; column < topo.num_cpus; ++column) { | |
2255 | int cpu_number; | |
2256 | ||
2257 | retval = fscanf(fp, " CPU%d", &cpu_number); | |
2258 | if (retval != 1) | |
2259 | break; | |
2260 | ||
2261 | if (cpu_number > topo.max_cpu_num) { | |
2262 | warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); | |
2263 | return 1; | |
2264 | } | |
2265 | ||
2266 | irq_column_2_cpu[column] = cpu_number; | |
2267 | irqs_per_cpu[cpu_number] = 0; | |
2268 | } | |
2269 | ||
2270 | /* read /proc/interrupt count lines and sum up irqs per cpu */ | |
2271 | while (1) { | |
2272 | int column; | |
2273 | char buf[64]; | |
2274 | ||
2275 | retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ | |
2276 | if (retval != 1) | |
2277 | break; | |
2278 | ||
2279 | /* read the count per cpu */ | |
2280 | for (column = 0; column < topo.num_cpus; ++column) { | |
2281 | ||
2282 | int cpu_number, irq_count; | |
2283 | ||
2284 | retval = fscanf(fp, " %d", &irq_count); | |
2285 | if (retval != 1) | |
2286 | break; | |
2287 | ||
2288 | cpu_number = irq_column_2_cpu[column]; | |
2289 | irqs_per_cpu[cpu_number] += irq_count; | |
2290 | ||
2291 | } | |
2292 | ||
2293 | while (getc(fp) != '\n') | |
2294 | ; /* flush interrupt description */ | |
2295 | ||
2296 | } | |
2297 | return 0; | |
2298 | } | |
fdf676e5 LB |
2299 | /* |
2300 | * snapshot_gfx_rc6_ms() | |
2301 | * | |
2302 | * record snapshot of | |
2303 | * /sys/class/drm/card0/power/rc6_residency_ms | |
2304 | * | |
2305 | * return 1 if config change requires a restart, else return 0 | |
2306 | */ | |
2307 | int snapshot_gfx_rc6_ms(void) | |
2308 | { | |
2309 | FILE *fp; | |
2310 | int retval; | |
2311 | ||
2312 | fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); | |
2313 | ||
2314 | retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); | |
2315 | if (retval != 1) | |
2316 | err(1, "GFX rc6"); | |
2317 | ||
2318 | fclose(fp); | |
2319 | ||
2320 | return 0; | |
2321 | } | |
27d47356 LB |
2322 | /* |
2323 | * snapshot_gfx_mhz() | |
2324 | * | |
2325 | * record snapshot of | |
2326 | * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz | |
2327 | * | |
2328 | * return 1 if config change requires a restart, else return 0 | |
2329 | */ | |
2330 | int snapshot_gfx_mhz(void) | |
2331 | { | |
2332 | static FILE *fp; | |
2333 | int retval; | |
2334 | ||
2335 | if (fp == NULL) | |
2336 | fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); | |
2337 | else | |
2338 | rewind(fp); | |
2339 | ||
2340 | retval = fscanf(fp, "%d", &gfx_cur_mhz); | |
2341 | if (retval != 1) | |
2342 | err(1, "GFX MHz"); | |
2343 | ||
2344 | return 0; | |
2345 | } | |
562a2d37 LB |
2346 | |
2347 | /* | |
2348 | * snapshot /proc and /sys files | |
2349 | * | |
2350 | * return 1 if configuration restart needed, else return 0 | |
2351 | */ | |
2352 | int snapshot_proc_sysfs_files(void) | |
2353 | { | |
2354 | if (snapshot_proc_interrupts()) | |
2355 | return 1; | |
2356 | ||
812db3f7 | 2357 | if (DO_BIC(BIC_GFX_rc6)) |
fdf676e5 LB |
2358 | snapshot_gfx_rc6_ms(); |
2359 | ||
812db3f7 | 2360 | if (DO_BIC(BIC_GFXMHz)) |
27d47356 LB |
2361 | snapshot_gfx_mhz(); |
2362 | ||
562a2d37 LB |
2363 | return 0; |
2364 | } | |
2365 | ||
103a8fea LB |
2366 | void turbostat_loop() |
2367 | { | |
c98d5d94 | 2368 | int retval; |
e52966c0 | 2369 | int restarted = 0; |
c98d5d94 | 2370 | |
103a8fea | 2371 | restart: |
e52966c0 LB |
2372 | restarted++; |
2373 | ||
562a2d37 | 2374 | snapshot_proc_sysfs_files(); |
c98d5d94 | 2375 | retval = for_all_cpus(get_counters, EVEN_COUNTERS); |
d91bb17c LB |
2376 | if (retval < -1) { |
2377 | exit(retval); | |
2378 | } else if (retval == -1) { | |
e52966c0 LB |
2379 | if (restarted > 1) { |
2380 | exit(retval); | |
2381 | } | |
c98d5d94 LB |
2382 | re_initialize(); |
2383 | goto restart; | |
2384 | } | |
e52966c0 | 2385 | restarted = 0; |
103a8fea LB |
2386 | gettimeofday(&tv_even, (struct timezone *)NULL); |
2387 | ||
2388 | while (1) { | |
c98d5d94 | 2389 | if (for_all_proc_cpus(cpu_is_not_present)) { |
103a8fea LB |
2390 | re_initialize(); |
2391 | goto restart; | |
2392 | } | |
2a0609c0 | 2393 | nanosleep(&interval_ts, NULL); |
562a2d37 LB |
2394 | if (snapshot_proc_sysfs_files()) |
2395 | goto restart; | |
c98d5d94 | 2396 | retval = for_all_cpus(get_counters, ODD_COUNTERS); |
d91bb17c LB |
2397 | if (retval < -1) { |
2398 | exit(retval); | |
2399 | } else if (retval == -1) { | |
15aaa346 LB |
2400 | re_initialize(); |
2401 | goto restart; | |
2402 | } | |
103a8fea | 2403 | gettimeofday(&tv_odd, (struct timezone *)NULL); |
103a8fea | 2404 | timersub(&tv_odd, &tv_even, &tv_delta); |
ba3dec99 LB |
2405 | if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { |
2406 | re_initialize(); | |
2407 | goto restart; | |
2408 | } | |
c98d5d94 LB |
2409 | compute_average(EVEN_COUNTERS); |
2410 | format_all_counters(EVEN_COUNTERS); | |
b7d8c148 | 2411 | flush_output_stdout(); |
2a0609c0 | 2412 | nanosleep(&interval_ts, NULL); |
562a2d37 LB |
2413 | if (snapshot_proc_sysfs_files()) |
2414 | goto restart; | |
c98d5d94 | 2415 | retval = for_all_cpus(get_counters, EVEN_COUNTERS); |
d91bb17c LB |
2416 | if (retval < -1) { |
2417 | exit(retval); | |
2418 | } else if (retval == -1) { | |
103a8fea LB |
2419 | re_initialize(); |
2420 | goto restart; | |
2421 | } | |
103a8fea | 2422 | gettimeofday(&tv_even, (struct timezone *)NULL); |
103a8fea | 2423 | timersub(&tv_even, &tv_odd, &tv_delta); |
ba3dec99 LB |
2424 | if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { |
2425 | re_initialize(); | |
2426 | goto restart; | |
2427 | } | |
c98d5d94 LB |
2428 | compute_average(ODD_COUNTERS); |
2429 | format_all_counters(ODD_COUNTERS); | |
b7d8c148 | 2430 | flush_output_stdout(); |
103a8fea LB |
2431 | } |
2432 | } | |
2433 | ||
2434 | void check_dev_msr() | |
2435 | { | |
2436 | struct stat sb; | |
7ce7d5de | 2437 | char pathname[32]; |
103a8fea | 2438 | |
7ce7d5de PB |
2439 | sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); |
2440 | if (stat(pathname, &sb)) | |
a21d38c8 LB |
2441 | if (system("/sbin/modprobe msr > /dev/null 2>&1")) |
2442 | err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); | |
103a8fea LB |
2443 | } |
2444 | ||
98481e79 | 2445 | void check_permissions() |
103a8fea | 2446 | { |
98481e79 LB |
2447 | struct __user_cap_header_struct cap_header_data; |
2448 | cap_user_header_t cap_header = &cap_header_data; | |
2449 | struct __user_cap_data_struct cap_data_data; | |
2450 | cap_user_data_t cap_data = &cap_data_data; | |
2451 | extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); | |
2452 | int do_exit = 0; | |
7ce7d5de | 2453 | char pathname[32]; |
98481e79 LB |
2454 | |
2455 | /* check for CAP_SYS_RAWIO */ | |
2456 | cap_header->pid = getpid(); | |
2457 | cap_header->version = _LINUX_CAPABILITY_VERSION; | |
2458 | if (capget(cap_header, cap_data) < 0) | |
2459 | err(-6, "capget(2) failed"); | |
2460 | ||
2461 | if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { | |
2462 | do_exit++; | |
2463 | warnx("capget(CAP_SYS_RAWIO) failed," | |
2464 | " try \"# setcap cap_sys_rawio=ep %s\"", progname); | |
2465 | } | |
2466 | ||
2467 | /* test file permissions */ | |
7ce7d5de PB |
2468 | sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); |
2469 | if (euidaccess(pathname, R_OK)) { | |
98481e79 LB |
2470 | do_exit++; |
2471 | warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); | |
2472 | } | |
2473 | ||
2474 | /* if all else fails, thell them to be root */ | |
2475 | if (do_exit) | |
2476 | if (getuid() != 0) | |
d7899447 | 2477 | warnx("... or simply run as root"); |
98481e79 LB |
2478 | |
2479 | if (do_exit) | |
2480 | exit(-6); | |
103a8fea LB |
2481 | } |
2482 | ||
d7899447 LB |
2483 | /* |
2484 | * NHM adds support for additional MSRs: | |
2485 | * | |
2486 | * MSR_SMI_COUNT 0x00000034 | |
2487 | * | |
ec0adc53 | 2488 | * MSR_PLATFORM_INFO 0x000000ce |
1df2e55a | 2489 | * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 |
d7899447 | 2490 | * |
cf4cbe53 LB |
2491 | * MSR_MISC_PWR_MGMT 0x000001aa |
2492 | * | |
d7899447 LB |
2493 | * MSR_PKG_C3_RESIDENCY 0x000003f8 |
2494 | * MSR_PKG_C6_RESIDENCY 0x000003f9 | |
2495 | * MSR_CORE_C3_RESIDENCY 0x000003fc | |
2496 | * MSR_CORE_C6_RESIDENCY 0x000003fd | |
2497 | * | |
ee7e38e3 | 2498 | * Side effect: |
1df2e55a | 2499 | * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL |
33148d67 | 2500 | * sets has_misc_feature_control |
d7899447 | 2501 | */ |
ee7e38e3 | 2502 | int probe_nhm_msrs(unsigned int family, unsigned int model) |
103a8fea | 2503 | { |
ee7e38e3 | 2504 | unsigned long long msr; |
21ed5574 | 2505 | unsigned int base_ratio; |
ee7e38e3 LB |
2506 | int *pkg_cstate_limits; |
2507 | ||
103a8fea LB |
2508 | if (!genuine_intel) |
2509 | return 0; | |
2510 | ||
2511 | if (family != 6) | |
2512 | return 0; | |
2513 | ||
21ed5574 LB |
2514 | bclk = discover_bclk(family, model); |
2515 | ||
103a8fea | 2516 | switch (model) { |
869ce69e LB |
2517 | case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ |
2518 | case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ | |
103a8fea | 2519 | case 0x1F: /* Core i7 and i5 Processor - Nehalem */ |
869ce69e LB |
2520 | case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ |
2521 | case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ | |
2522 | case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ | |
2523 | case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ | |
ee7e38e3 LB |
2524 | pkg_cstate_limits = nhm_pkg_cstate_limits; |
2525 | break; | |
869ce69e LB |
2526 | case INTEL_FAM6_SANDYBRIDGE: /* SNB */ |
2527 | case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ | |
2528 | case INTEL_FAM6_IVYBRIDGE: /* IVB */ | |
2529 | case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ | |
ee7e38e3 | 2530 | pkg_cstate_limits = snb_pkg_cstate_limits; |
33148d67 | 2531 | has_misc_feature_control = 1; |
ee7e38e3 | 2532 | break; |
869ce69e LB |
2533 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ |
2534 | case INTEL_FAM6_HASWELL_X: /* HSX */ | |
2535 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | |
2536 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | |
2537 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | |
2538 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | |
2539 | case INTEL_FAM6_BROADWELL_X: /* BDX */ | |
2540 | case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ | |
2541 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ | |
2542 | case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ | |
2543 | case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ | |
2544 | case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ | |
ee7e38e3 | 2545 | pkg_cstate_limits = hsw_pkg_cstate_limits; |
33148d67 | 2546 | has_misc_feature_control = 1; |
ee7e38e3 | 2547 | break; |
d8ebb442 LB |
2548 | case INTEL_FAM6_SKYLAKE_X: /* SKX */ |
2549 | pkg_cstate_limits = skx_pkg_cstate_limits; | |
33148d67 | 2550 | has_misc_feature_control = 1; |
d8ebb442 | 2551 | break; |
869ce69e | 2552 | case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ |
cf4cbe53 | 2553 | no_MSR_MISC_PWR_MGMT = 1; |
869ce69e | 2554 | case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ |
ee7e38e3 LB |
2555 | pkg_cstate_limits = slv_pkg_cstate_limits; |
2556 | break; | |
869ce69e | 2557 | case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ |
ee7e38e3 | 2558 | pkg_cstate_limits = amt_pkg_cstate_limits; |
cf4cbe53 | 2559 | no_MSR_MISC_PWR_MGMT = 1; |
ee7e38e3 | 2560 | break; |
869ce69e | 2561 | case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ |
005c82d6 | 2562 | case INTEL_FAM6_XEON_PHI_KNM: |
ee7e38e3 LB |
2563 | pkg_cstate_limits = phi_pkg_cstate_limits; |
2564 | break; | |
869ce69e | 2565 | case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ |
ac01ac13 | 2566 | case INTEL_FAM6_ATOM_GEMINI_LAKE: |
869ce69e | 2567 | case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ |
e4085d54 LB |
2568 | pkg_cstate_limits = bxt_pkg_cstate_limits; |
2569 | break; | |
103a8fea LB |
2570 | default: |
2571 | return 0; | |
2572 | } | |
1df2e55a | 2573 | get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); |
e9257f5f | 2574 | pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; |
ee7e38e3 | 2575 | |
ec0adc53 | 2576 | get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); |
21ed5574 LB |
2577 | base_ratio = (msr >> 8) & 0xFF; |
2578 | ||
2579 | base_hz = base_ratio * bclk * 1000000; | |
2580 | has_base_hz = 1; | |
ee7e38e3 | 2581 | return 1; |
103a8fea | 2582 | } |
0f7887c4 LB |
2583 | /* |
2584 | * SLV client has supporet for unique MSRs: | |
2585 | * | |
2586 | * MSR_CC6_DEMOTION_POLICY_CONFIG | |
2587 | * MSR_MC6_DEMOTION_POLICY_CONFIG | |
2588 | */ | |
2589 | ||
2590 | int has_slv_msrs(unsigned int family, unsigned int model) | |
2591 | { | |
2592 | if (!genuine_intel) | |
2593 | return 0; | |
2594 | ||
2595 | switch (model) { | |
2596 | case INTEL_FAM6_ATOM_SILVERMONT1: | |
2597 | case INTEL_FAM6_ATOM_MERRIFIELD: | |
2598 | case INTEL_FAM6_ATOM_MOOREFIELD: | |
2599 | return 1; | |
2600 | } | |
2601 | return 0; | |
2602 | } | |
7170a374 LB |
2603 | int is_dnv(unsigned int family, unsigned int model) |
2604 | { | |
2605 | ||
2606 | if (!genuine_intel) | |
2607 | return 0; | |
2608 | ||
2609 | switch (model) { | |
2610 | case INTEL_FAM6_ATOM_DENVERTON: | |
2611 | return 1; | |
2612 | } | |
2613 | return 0; | |
2614 | } | |
ade0ebac LB |
2615 | int is_bdx(unsigned int family, unsigned int model) |
2616 | { | |
2617 | ||
2618 | if (!genuine_intel) | |
2619 | return 0; | |
2620 | ||
2621 | switch (model) { | |
2622 | case INTEL_FAM6_BROADWELL_X: | |
2623 | case INTEL_FAM6_BROADWELL_XEON_D: | |
2624 | return 1; | |
2625 | } | |
2626 | return 0; | |
2627 | } | |
34c76197 LB |
2628 | int is_skx(unsigned int family, unsigned int model) |
2629 | { | |
2630 | ||
2631 | if (!genuine_intel) | |
2632 | return 0; | |
2633 | ||
2634 | switch (model) { | |
2635 | case INTEL_FAM6_SKYLAKE_X: | |
2636 | return 1; | |
2637 | } | |
2638 | return 0; | |
2639 | } | |
0f7887c4 | 2640 | |
31e07522 | 2641 | int has_turbo_ratio_limit(unsigned int family, unsigned int model) |
d7899447 | 2642 | { |
0f7887c4 LB |
2643 | if (has_slv_msrs(family, model)) |
2644 | return 0; | |
2645 | ||
d7899447 LB |
2646 | switch (model) { |
2647 | /* Nehalem compatible, but do not include turbo-ratio limit support */ | |
869ce69e LB |
2648 | case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ |
2649 | case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ | |
2650 | case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ | |
005c82d6 | 2651 | case INTEL_FAM6_XEON_PHI_KNM: |
d7899447 LB |
2652 | return 0; |
2653 | default: | |
2654 | return 1; | |
2655 | } | |
2656 | } | |
0f7887c4 LB |
2657 | int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) |
2658 | { | |
2659 | if (has_slv_msrs(family, model)) | |
2660 | return 1; | |
2661 | ||
2662 | return 0; | |
2663 | } | |
6574a5d5 LB |
2664 | int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) |
2665 | { | |
2666 | if (!genuine_intel) | |
2667 | return 0; | |
2668 | ||
2669 | if (family != 6) | |
2670 | return 0; | |
2671 | ||
2672 | switch (model) { | |
869ce69e LB |
2673 | case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ |
2674 | case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ | |
fcd17211 LB |
2675 | return 1; |
2676 | default: | |
2677 | return 0; | |
2678 | } | |
2679 | } | |
2680 | int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) | |
2681 | { | |
2682 | if (!genuine_intel) | |
2683 | return 0; | |
2684 | ||
2685 | if (family != 6) | |
2686 | return 0; | |
2687 | ||
2688 | switch (model) { | |
869ce69e | 2689 | case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ |
6574a5d5 LB |
2690 | return 1; |
2691 | default: | |
2692 | return 0; | |
2693 | } | |
2694 | } | |
2695 | ||
fb5d4327 DC |
2696 | int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) |
2697 | { | |
2698 | if (!genuine_intel) | |
2699 | return 0; | |
2700 | ||
2701 | if (family != 6) | |
2702 | return 0; | |
2703 | ||
2704 | switch (model) { | |
869ce69e | 2705 | case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ |
005c82d6 | 2706 | case INTEL_FAM6_XEON_PHI_KNM: |
fb5d4327 DC |
2707 | return 1; |
2708 | default: | |
2709 | return 0; | |
2710 | } | |
2711 | } | |
31e07522 LB |
2712 | int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) |
2713 | { | |
2714 | if (!genuine_intel) | |
2715 | return 0; | |
2716 | ||
2717 | if (family != 6) | |
2718 | return 0; | |
2719 | ||
2720 | switch (model) { | |
2721 | case INTEL_FAM6_ATOM_GOLDMONT: | |
2722 | case INTEL_FAM6_SKYLAKE_X: | |
2723 | return 1; | |
2724 | default: | |
2725 | return 0; | |
2726 | } | |
2727 | } | |
6fb3143b LB |
2728 | int has_config_tdp(unsigned int family, unsigned int model) |
2729 | { | |
2730 | if (!genuine_intel) | |
2731 | return 0; | |
2732 | ||
2733 | if (family != 6) | |
2734 | return 0; | |
2735 | ||
2736 | switch (model) { | |
869ce69e LB |
2737 | case INTEL_FAM6_IVYBRIDGE: /* IVB */ |
2738 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | |
2739 | case INTEL_FAM6_HASWELL_X: /* HSX */ | |
2740 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | |
2741 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | |
2742 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | |
2743 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | |
2744 | case INTEL_FAM6_BROADWELL_X: /* BDX */ | |
2745 | case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ | |
2746 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ | |
2747 | case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ | |
2748 | case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ | |
2749 | case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ | |
2750 | case INTEL_FAM6_SKYLAKE_X: /* SKX */ | |
2751 | ||
2752 | case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ | |
005c82d6 | 2753 | case INTEL_FAM6_XEON_PHI_KNM: |
6fb3143b LB |
2754 | return 1; |
2755 | default: | |
2756 | return 0; | |
2757 | } | |
2758 | } | |
2759 | ||
fcd17211 | 2760 | static void |
1b69317d | 2761 | dump_cstate_pstate_config_info(unsigned int family, unsigned int model) |
fcd17211 LB |
2762 | { |
2763 | if (!do_nhm_platform_info) | |
2764 | return; | |
2765 | ||
2766 | dump_nhm_platform_info(); | |
2767 | ||
2768 | if (has_hsw_turbo_ratio_limit(family, model)) | |
2769 | dump_hsw_turbo_ratio_limits(); | |
2770 | ||
2771 | if (has_ivt_turbo_ratio_limit(family, model)) | |
2772 | dump_ivt_turbo_ratio_limits(); | |
2773 | ||
31e07522 LB |
2774 | if (has_turbo_ratio_limit(family, model)) |
2775 | dump_turbo_ratio_limits(family, model); | |
fcd17211 | 2776 | |
0f7887c4 LB |
2777 | if (has_atom_turbo_ratio_limit(family, model)) |
2778 | dump_atom_turbo_ratio_limits(); | |
2779 | ||
fb5d4327 DC |
2780 | if (has_knl_turbo_ratio_limit(family, model)) |
2781 | dump_knl_turbo_ratio_limits(); | |
2782 | ||
6fb3143b LB |
2783 | if (has_config_tdp(family, model)) |
2784 | dump_config_tdp(); | |
2785 | ||
fcd17211 LB |
2786 | dump_nhm_cst_cfg(); |
2787 | } | |
2788 | ||
2789 | ||
889facbe LB |
2790 | /* |
2791 | * print_epb() | |
2792 | * Decode the ENERGY_PERF_BIAS MSR | |
2793 | */ | |
2794 | int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2795 | { | |
2796 | unsigned long long msr; | |
2797 | char *epb_string; | |
2798 | int cpu; | |
2799 | ||
2800 | if (!has_epb) | |
2801 | return 0; | |
2802 | ||
2803 | cpu = t->cpu_id; | |
2804 | ||
2805 | /* EPB is per-package */ | |
2806 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2807 | return 0; | |
2808 | ||
2809 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2810 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
2811 | return -1; |
2812 | } | |
2813 | ||
2814 | if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) | |
2815 | return 0; | |
2816 | ||
e9be7dd6 | 2817 | switch (msr & 0xF) { |
889facbe LB |
2818 | case ENERGY_PERF_BIAS_PERFORMANCE: |
2819 | epb_string = "performance"; | |
2820 | break; | |
2821 | case ENERGY_PERF_BIAS_NORMAL: | |
2822 | epb_string = "balanced"; | |
2823 | break; | |
2824 | case ENERGY_PERF_BIAS_POWERSAVE: | |
2825 | epb_string = "powersave"; | |
2826 | break; | |
2827 | default: | |
2828 | epb_string = "custom"; | |
2829 | break; | |
2830 | } | |
b7d8c148 | 2831 | fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); |
889facbe LB |
2832 | |
2833 | return 0; | |
2834 | } | |
7f5c258e LB |
2835 | /* |
2836 | * print_hwp() | |
2837 | * Decode the MSR_HWP_CAPABILITIES | |
2838 | */ | |
2839 | int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2840 | { | |
2841 | unsigned long long msr; | |
2842 | int cpu; | |
2843 | ||
2844 | if (!has_hwp) | |
2845 | return 0; | |
2846 | ||
2847 | cpu = t->cpu_id; | |
2848 | ||
2849 | /* MSR_HWP_CAPABILITIES is per-package */ | |
2850 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2851 | return 0; | |
2852 | ||
2853 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2854 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
7f5c258e LB |
2855 | return -1; |
2856 | } | |
2857 | ||
2858 | if (get_msr(cpu, MSR_PM_ENABLE, &msr)) | |
2859 | return 0; | |
2860 | ||
b7d8c148 | 2861 | fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", |
7f5c258e LB |
2862 | cpu, msr, (msr & (1 << 0)) ? "" : "No-"); |
2863 | ||
2864 | /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ | |
2865 | if ((msr & (1 << 0)) == 0) | |
2866 | return 0; | |
2867 | ||
2868 | if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) | |
2869 | return 0; | |
2870 | ||
b7d8c148 | 2871 | fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " |
7f5c258e LB |
2872 | "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", |
2873 | cpu, msr, | |
2874 | (unsigned int)HWP_HIGHEST_PERF(msr), | |
2875 | (unsigned int)HWP_GUARANTEED_PERF(msr), | |
2876 | (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), | |
2877 | (unsigned int)HWP_LOWEST_PERF(msr)); | |
2878 | ||
2879 | if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) | |
2880 | return 0; | |
2881 | ||
b7d8c148 | 2882 | fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " |
7f5c258e LB |
2883 | "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", |
2884 | cpu, msr, | |
2885 | (unsigned int)(((msr) >> 0) & 0xff), | |
2886 | (unsigned int)(((msr) >> 8) & 0xff), | |
2887 | (unsigned int)(((msr) >> 16) & 0xff), | |
2888 | (unsigned int)(((msr) >> 24) & 0xff), | |
2889 | (unsigned int)(((msr) >> 32) & 0xff3), | |
2890 | (unsigned int)(((msr) >> 42) & 0x1)); | |
2891 | ||
2892 | if (has_hwp_pkg) { | |
2893 | if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) | |
2894 | return 0; | |
2895 | ||
b7d8c148 | 2896 | fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " |
7f5c258e LB |
2897 | "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", |
2898 | cpu, msr, | |
2899 | (unsigned int)(((msr) >> 0) & 0xff), | |
2900 | (unsigned int)(((msr) >> 8) & 0xff), | |
2901 | (unsigned int)(((msr) >> 16) & 0xff), | |
2902 | (unsigned int)(((msr) >> 24) & 0xff), | |
2903 | (unsigned int)(((msr) >> 32) & 0xff3)); | |
2904 | } | |
2905 | if (has_hwp_notify) { | |
2906 | if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) | |
2907 | return 0; | |
2908 | ||
b7d8c148 | 2909 | fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " |
7f5c258e LB |
2910 | "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", |
2911 | cpu, msr, | |
2912 | ((msr) & 0x1) ? "EN" : "Dis", | |
2913 | ((msr) & 0x2) ? "EN" : "Dis"); | |
2914 | } | |
2915 | if (get_msr(cpu, MSR_HWP_STATUS, &msr)) | |
2916 | return 0; | |
2917 | ||
b7d8c148 | 2918 | fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " |
7f5c258e LB |
2919 | "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", |
2920 | cpu, msr, | |
2921 | ((msr) & 0x1) ? "" : "No-", | |
2922 | ((msr) & 0x2) ? "" : "No-"); | |
889facbe LB |
2923 | |
2924 | return 0; | |
2925 | } | |
2926 | ||
3a9a941d LB |
2927 | /* |
2928 | * print_perf_limit() | |
2929 | */ | |
2930 | int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2931 | { | |
2932 | unsigned long long msr; | |
2933 | int cpu; | |
2934 | ||
2935 | cpu = t->cpu_id; | |
2936 | ||
2937 | /* per-package */ | |
2938 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2939 | return 0; | |
2940 | ||
2941 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2942 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
3a9a941d LB |
2943 | return -1; |
2944 | } | |
2945 | ||
2946 | if (do_core_perf_limit_reasons) { | |
2947 | get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); | |
b7d8c148 LB |
2948 | fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); |
2949 | fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", | |
e33cbe85 | 2950 | (msr & 1 << 15) ? "bit15, " : "", |
3a9a941d | 2951 | (msr & 1 << 14) ? "bit14, " : "", |
e33cbe85 LB |
2952 | (msr & 1 << 13) ? "Transitions, " : "", |
2953 | (msr & 1 << 12) ? "MultiCoreTurbo, " : "", | |
2954 | (msr & 1 << 11) ? "PkgPwrL2, " : "", | |
2955 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
2956 | (msr & 1 << 9) ? "CorePwr, " : "", | |
2957 | (msr & 1 << 8) ? "Amps, " : "", | |
2958 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
2959 | (msr & 1 << 5) ? "Auto-HWP, " : "", | |
2960 | (msr & 1 << 4) ? "Graphics, " : "", | |
2961 | (msr & 1 << 2) ? "bit2, " : "", | |
2962 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
2963 | (msr & 1 << 0) ? "PROCHOT, " : ""); | |
b7d8c148 | 2964 | fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", |
e33cbe85 | 2965 | (msr & 1 << 31) ? "bit31, " : "", |
3a9a941d | 2966 | (msr & 1 << 30) ? "bit30, " : "", |
e33cbe85 LB |
2967 | (msr & 1 << 29) ? "Transitions, " : "", |
2968 | (msr & 1 << 28) ? "MultiCoreTurbo, " : "", | |
2969 | (msr & 1 << 27) ? "PkgPwrL2, " : "", | |
2970 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
2971 | (msr & 1 << 25) ? "CorePwr, " : "", | |
2972 | (msr & 1 << 24) ? "Amps, " : "", | |
2973 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
2974 | (msr & 1 << 21) ? "Auto-HWP, " : "", | |
2975 | (msr & 1 << 20) ? "Graphics, " : "", | |
2976 | (msr & 1 << 18) ? "bit18, " : "", | |
2977 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
2978 | (msr & 1 << 16) ? "PROCHOT, " : ""); | |
3a9a941d LB |
2979 | |
2980 | } | |
2981 | if (do_gfx_perf_limit_reasons) { | |
2982 | get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); | |
b7d8c148 LB |
2983 | fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); |
2984 | fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", | |
3a9a941d LB |
2985 | (msr & 1 << 0) ? "PROCHOT, " : "", |
2986 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
2987 | (msr & 1 << 4) ? "Graphics, " : "", | |
2988 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
2989 | (msr & 1 << 8) ? "Amps, " : "", | |
2990 | (msr & 1 << 9) ? "GFXPwr, " : "", | |
2991 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
2992 | (msr & 1 << 11) ? "PkgPwrL2, " : ""); | |
b7d8c148 | 2993 | fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", |
3a9a941d LB |
2994 | (msr & 1 << 16) ? "PROCHOT, " : "", |
2995 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
2996 | (msr & 1 << 20) ? "Graphics, " : "", | |
2997 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
2998 | (msr & 1 << 24) ? "Amps, " : "", | |
2999 | (msr & 1 << 25) ? "GFXPwr, " : "", | |
3000 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
3001 | (msr & 1 << 27) ? "PkgPwrL2, " : ""); | |
3002 | } | |
3003 | if (do_ring_perf_limit_reasons) { | |
3004 | get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); | |
b7d8c148 LB |
3005 | fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); |
3006 | fprintf(outf, " (Active: %s%s%s%s%s%s)", | |
3a9a941d LB |
3007 | (msr & 1 << 0) ? "PROCHOT, " : "", |
3008 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
3009 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
3010 | (msr & 1 << 8) ? "Amps, " : "", | |
3011 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
3012 | (msr & 1 << 11) ? "PkgPwrL2, " : ""); | |
b7d8c148 | 3013 | fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", |
3a9a941d LB |
3014 | (msr & 1 << 16) ? "PROCHOT, " : "", |
3015 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
3016 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
3017 | (msr & 1 << 24) ? "Amps, " : "", | |
3018 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
3019 | (msr & 1 << 27) ? "PkgPwrL2, " : ""); | |
3020 | } | |
3021 | return 0; | |
3022 | } | |
3023 | ||
889facbe LB |
3024 | #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ |
3025 | #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ | |
3026 | ||
1b69317d | 3027 | double get_tdp(unsigned int model) |
144b44b1 LB |
3028 | { |
3029 | unsigned long long msr; | |
3030 | ||
3031 | if (do_rapl & RAPL_PKG_POWER_INFO) | |
7ce7d5de | 3032 | if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) |
144b44b1 LB |
3033 | return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; |
3034 | ||
3035 | switch (model) { | |
869ce69e LB |
3036 | case INTEL_FAM6_ATOM_SILVERMONT1: |
3037 | case INTEL_FAM6_ATOM_SILVERMONT2: | |
144b44b1 LB |
3038 | return 30.0; |
3039 | default: | |
3040 | return 135.0; | |
3041 | } | |
3042 | } | |
3043 | ||
40ee8e3b AS |
3044 | /* |
3045 | * rapl_dram_energy_units_probe() | |
3046 | * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. | |
3047 | */ | |
3048 | static double | |
3049 | rapl_dram_energy_units_probe(int model, double rapl_energy_units) | |
3050 | { | |
3051 | /* only called for genuine_intel, family 6 */ | |
3052 | ||
3053 | switch (model) { | |
869ce69e LB |
3054 | case INTEL_FAM6_HASWELL_X: /* HSX */ |
3055 | case INTEL_FAM6_BROADWELL_X: /* BDX */ | |
3056 | case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ | |
3057 | case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ | |
005c82d6 | 3058 | case INTEL_FAM6_XEON_PHI_KNM: |
40ee8e3b AS |
3059 | return (rapl_dram_energy_units = 15.3 / 1000000); |
3060 | default: | |
3061 | return (rapl_energy_units); | |
3062 | } | |
3063 | } | |
3064 | ||
144b44b1 | 3065 | |
889facbe LB |
3066 | /* |
3067 | * rapl_probe() | |
3068 | * | |
144b44b1 | 3069 | * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units |
889facbe LB |
3070 | */ |
3071 | void rapl_probe(unsigned int family, unsigned int model) | |
3072 | { | |
3073 | unsigned long long msr; | |
144b44b1 | 3074 | unsigned int time_unit; |
889facbe LB |
3075 | double tdp; |
3076 | ||
3077 | if (!genuine_intel) | |
3078 | return; | |
3079 | ||
3080 | if (family != 6) | |
3081 | return; | |
3082 | ||
3083 | switch (model) { | |
869ce69e LB |
3084 | case INTEL_FAM6_SANDYBRIDGE: |
3085 | case INTEL_FAM6_IVYBRIDGE: | |
3086 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | |
3087 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | |
3088 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | |
3089 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | |
3090 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | |
144b44b1 | 3091 | do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; |
812db3f7 LB |
3092 | if (rapl_joules) { |
3093 | BIC_PRESENT(BIC_Pkg_J); | |
3094 | BIC_PRESENT(BIC_Cor_J); | |
3095 | BIC_PRESENT(BIC_GFX_J); | |
3096 | } else { | |
3097 | BIC_PRESENT(BIC_PkgWatt); | |
3098 | BIC_PRESENT(BIC_CorWatt); | |
3099 | BIC_PRESENT(BIC_GFXWatt); | |
3100 | } | |
889facbe | 3101 | break; |
869ce69e | 3102 | case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ |
ac01ac13 | 3103 | case INTEL_FAM6_ATOM_GEMINI_LAKE: |
e4085d54 | 3104 | do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; |
812db3f7 LB |
3105 | if (rapl_joules) |
3106 | BIC_PRESENT(BIC_Pkg_J); | |
3107 | else | |
3108 | BIC_PRESENT(BIC_PkgWatt); | |
e4085d54 | 3109 | break; |
869ce69e LB |
3110 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ |
3111 | case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ | |
3112 | case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ | |
3113 | case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ | |
0b2bb692 | 3114 | do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; |
812db3f7 LB |
3115 | BIC_PRESENT(BIC_PKG__); |
3116 | BIC_PRESENT(BIC_RAM__); | |
3117 | if (rapl_joules) { | |
3118 | BIC_PRESENT(BIC_Pkg_J); | |
3119 | BIC_PRESENT(BIC_Cor_J); | |
3120 | BIC_PRESENT(BIC_RAM_J); | |
3121 | } else { | |
3122 | BIC_PRESENT(BIC_PkgWatt); | |
3123 | BIC_PRESENT(BIC_CorWatt); | |
3124 | BIC_PRESENT(BIC_RAMWatt); | |
3125 | } | |
0b2bb692 | 3126 | break; |
869ce69e LB |
3127 | case INTEL_FAM6_HASWELL_X: /* HSX */ |
3128 | case INTEL_FAM6_BROADWELL_X: /* BDX */ | |
3129 | case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ | |
3130 | case INTEL_FAM6_SKYLAKE_X: /* SKX */ | |
3131 | case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ | |
005c82d6 | 3132 | case INTEL_FAM6_XEON_PHI_KNM: |
0b2bb692 | 3133 | do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; |
812db3f7 LB |
3134 | BIC_PRESENT(BIC_PKG__); |
3135 | BIC_PRESENT(BIC_RAM__); | |
3136 | if (rapl_joules) { | |
3137 | BIC_PRESENT(BIC_Pkg_J); | |
3138 | BIC_PRESENT(BIC_RAM_J); | |
3139 | } else { | |
3140 | BIC_PRESENT(BIC_PkgWatt); | |
3141 | BIC_PRESENT(BIC_RAMWatt); | |
3142 | } | |
e6f9bb3c | 3143 | break; |
869ce69e LB |
3144 | case INTEL_FAM6_SANDYBRIDGE_X: |
3145 | case INTEL_FAM6_IVYBRIDGE_X: | |
0b2bb692 | 3146 | do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; |
812db3f7 LB |
3147 | BIC_PRESENT(BIC_PKG__); |
3148 | BIC_PRESENT(BIC_RAM__); | |
3149 | if (rapl_joules) { | |
3150 | BIC_PRESENT(BIC_Pkg_J); | |
3151 | BIC_PRESENT(BIC_Cor_J); | |
3152 | BIC_PRESENT(BIC_RAM_J); | |
3153 | } else { | |
3154 | BIC_PRESENT(BIC_PkgWatt); | |
3155 | BIC_PRESENT(BIC_CorWatt); | |
3156 | BIC_PRESENT(BIC_RAMWatt); | |
3157 | } | |
144b44b1 | 3158 | break; |
869ce69e LB |
3159 | case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ |
3160 | case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ | |
9148494c | 3161 | do_rapl = RAPL_PKG | RAPL_CORES; |
812db3f7 LB |
3162 | if (rapl_joules) { |
3163 | BIC_PRESENT(BIC_Pkg_J); | |
3164 | BIC_PRESENT(BIC_Cor_J); | |
3165 | } else { | |
3166 | BIC_PRESENT(BIC_PkgWatt); | |
3167 | BIC_PRESENT(BIC_CorWatt); | |
3168 | } | |
889facbe | 3169 | break; |
869ce69e | 3170 | case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ |
0f644909 | 3171 | do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; |
812db3f7 LB |
3172 | BIC_PRESENT(BIC_PKG__); |
3173 | BIC_PRESENT(BIC_RAM__); | |
3174 | if (rapl_joules) { | |
3175 | BIC_PRESENT(BIC_Pkg_J); | |
3176 | BIC_PRESENT(BIC_Cor_J); | |
3177 | BIC_PRESENT(BIC_RAM_J); | |
3178 | } else { | |
3179 | BIC_PRESENT(BIC_PkgWatt); | |
3180 | BIC_PRESENT(BIC_CorWatt); | |
3181 | BIC_PRESENT(BIC_RAMWatt); | |
3182 | } | |
0f644909 | 3183 | break; |
889facbe LB |
3184 | default: |
3185 | return; | |
3186 | } | |
3187 | ||
3188 | /* units on package 0, verify later other packages match */ | |
7ce7d5de | 3189 | if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) |
889facbe LB |
3190 | return; |
3191 | ||
3192 | rapl_power_units = 1.0 / (1 << (msr & 0xF)); | |
869ce69e | 3193 | if (model == INTEL_FAM6_ATOM_SILVERMONT1) |
144b44b1 LB |
3194 | rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; |
3195 | else | |
3196 | rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); | |
889facbe | 3197 | |
40ee8e3b AS |
3198 | rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); |
3199 | ||
144b44b1 LB |
3200 | time_unit = msr >> 16 & 0xF; |
3201 | if (time_unit == 0) | |
3202 | time_unit = 0xA; | |
889facbe | 3203 | |
144b44b1 | 3204 | rapl_time_units = 1.0 / (1 << (time_unit)); |
889facbe | 3205 | |
144b44b1 | 3206 | tdp = get_tdp(model); |
889facbe | 3207 | |
144b44b1 | 3208 | rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; |
96e47158 | 3209 | if (!quiet) |
b7d8c148 | 3210 | fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); |
889facbe LB |
3211 | |
3212 | return; | |
3213 | } | |
3214 | ||
1b69317d | 3215 | void perf_limit_reasons_probe(unsigned int family, unsigned int model) |
3a9a941d LB |
3216 | { |
3217 | if (!genuine_intel) | |
3218 | return; | |
3219 | ||
3220 | if (family != 6) | |
3221 | return; | |
3222 | ||
3223 | switch (model) { | |
869ce69e LB |
3224 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ |
3225 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | |
3226 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | |
3a9a941d | 3227 | do_gfx_perf_limit_reasons = 1; |
869ce69e | 3228 | case INTEL_FAM6_HASWELL_X: /* HSX */ |
3a9a941d LB |
3229 | do_core_perf_limit_reasons = 1; |
3230 | do_ring_perf_limit_reasons = 1; | |
3231 | default: | |
3232 | return; | |
3233 | } | |
3234 | } | |
3235 | ||
889facbe LB |
3236 | int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) |
3237 | { | |
3238 | unsigned long long msr; | |
3239 | unsigned int dts; | |
3240 | int cpu; | |
3241 | ||
3242 | if (!(do_dts || do_ptm)) | |
3243 | return 0; | |
3244 | ||
3245 | cpu = t->cpu_id; | |
3246 | ||
3247 | /* DTS is per-core, no need to print for each thread */ | |
388e9c81 | 3248 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) |
889facbe LB |
3249 | return 0; |
3250 | ||
3251 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 3252 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
3253 | return -1; |
3254 | } | |
3255 | ||
3256 | if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { | |
3257 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) | |
3258 | return 0; | |
3259 | ||
3260 | dts = (msr >> 16) & 0x7F; | |
b7d8c148 | 3261 | fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", |
889facbe LB |
3262 | cpu, msr, tcc_activation_temp - dts); |
3263 | ||
3264 | #ifdef THERM_DEBUG | |
3265 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) | |
3266 | return 0; | |
3267 | ||
3268 | dts = (msr >> 16) & 0x7F; | |
3269 | dts2 = (msr >> 8) & 0x7F; | |
b7d8c148 | 3270 | fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", |
889facbe LB |
3271 | cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); |
3272 | #endif | |
3273 | } | |
3274 | ||
3275 | ||
3276 | if (do_dts) { | |
3277 | unsigned int resolution; | |
3278 | ||
3279 | if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) | |
3280 | return 0; | |
3281 | ||
3282 | dts = (msr >> 16) & 0x7F; | |
3283 | resolution = (msr >> 27) & 0xF; | |
b7d8c148 | 3284 | fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", |
889facbe LB |
3285 | cpu, msr, tcc_activation_temp - dts, resolution); |
3286 | ||
3287 | #ifdef THERM_DEBUG | |
3288 | if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) | |
3289 | return 0; | |
3290 | ||
3291 | dts = (msr >> 16) & 0x7F; | |
3292 | dts2 = (msr >> 8) & 0x7F; | |
b7d8c148 | 3293 | fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", |
889facbe LB |
3294 | cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); |
3295 | #endif | |
3296 | } | |
3297 | ||
3298 | return 0; | |
3299 | } | |
36229897 | 3300 | |
889facbe LB |
3301 | void print_power_limit_msr(int cpu, unsigned long long msr, char *label) |
3302 | { | |
b7d8c148 | 3303 | fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", |
889facbe LB |
3304 | cpu, label, |
3305 | ((msr >> 15) & 1) ? "EN" : "DIS", | |
3306 | ((msr >> 0) & 0x7FFF) * rapl_power_units, | |
3307 | (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, | |
3308 | (((msr >> 16) & 1) ? "EN" : "DIS")); | |
3309 | ||
3310 | return; | |
3311 | } | |
3312 | ||
3313 | int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
3314 | { | |
3315 | unsigned long long msr; | |
3316 | int cpu; | |
889facbe LB |
3317 | |
3318 | if (!do_rapl) | |
3319 | return 0; | |
3320 | ||
3321 | /* RAPL counters are per package, so print only for 1st thread/package */ | |
3322 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
3323 | return 0; | |
3324 | ||
3325 | cpu = t->cpu_id; | |
3326 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 3327 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
3328 | return -1; |
3329 | } | |
3330 | ||
3331 | if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) | |
3332 | return -1; | |
3333 | ||
96e47158 LB |
3334 | fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr, |
3335 | rapl_power_units, rapl_energy_units, rapl_time_units); | |
3336 | ||
144b44b1 LB |
3337 | if (do_rapl & RAPL_PKG_POWER_INFO) { |
3338 | ||
889facbe LB |
3339 | if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) |
3340 | return -5; | |
3341 | ||
3342 | ||
b7d8c148 | 3343 | fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", |
889facbe LB |
3344 | cpu, msr, |
3345 | ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
3346 | ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
3347 | ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
3348 | ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); | |
3349 | ||
144b44b1 LB |
3350 | } |
3351 | if (do_rapl & RAPL_PKG) { | |
3352 | ||
889facbe LB |
3353 | if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) |
3354 | return -9; | |
3355 | ||
b7d8c148 | 3356 | fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", |
96e47158 | 3357 | cpu, msr, (msr >> 63) & 1 ? "" : "UN"); |
889facbe LB |
3358 | |
3359 | print_power_limit_msr(cpu, msr, "PKG Limit #1"); | |
b7d8c148 | 3360 | fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", |
889facbe LB |
3361 | cpu, |
3362 | ((msr >> 47) & 1) ? "EN" : "DIS", | |
3363 | ((msr >> 32) & 0x7FFF) * rapl_power_units, | |
3364 | (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, | |
3365 | ((msr >> 48) & 1) ? "EN" : "DIS"); | |
3366 | } | |
3367 | ||
0b2bb692 | 3368 | if (do_rapl & RAPL_DRAM_POWER_INFO) { |
889facbe LB |
3369 | if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) |
3370 | return -6; | |
3371 | ||
b7d8c148 | 3372 | fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", |
889facbe LB |
3373 | cpu, msr, |
3374 | ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
3375 | ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
3376 | ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
3377 | ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); | |
0b2bb692 LB |
3378 | } |
3379 | if (do_rapl & RAPL_DRAM) { | |
889facbe LB |
3380 | if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) |
3381 | return -9; | |
b7d8c148 | 3382 | fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", |
96e47158 | 3383 | cpu, msr, (msr >> 31) & 1 ? "" : "UN"); |
889facbe LB |
3384 | |
3385 | print_power_limit_msr(cpu, msr, "DRAM Limit"); | |
3386 | } | |
144b44b1 | 3387 | if (do_rapl & RAPL_CORE_POLICY) { |
96e47158 LB |
3388 | if (get_msr(cpu, MSR_PP0_POLICY, &msr)) |
3389 | return -7; | |
889facbe | 3390 | |
96e47158 | 3391 | fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); |
144b44b1 | 3392 | } |
9148494c | 3393 | if (do_rapl & RAPL_CORES_POWER_LIMIT) { |
96e47158 LB |
3394 | if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) |
3395 | return -9; | |
3396 | fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", | |
3397 | cpu, msr, (msr >> 31) & 1 ? "" : "UN"); | |
3398 | print_power_limit_msr(cpu, msr, "Cores Limit"); | |
889facbe LB |
3399 | } |
3400 | if (do_rapl & RAPL_GFX) { | |
96e47158 LB |
3401 | if (get_msr(cpu, MSR_PP1_POLICY, &msr)) |
3402 | return -8; | |
889facbe | 3403 | |
96e47158 | 3404 | fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); |
889facbe | 3405 | |
96e47158 LB |
3406 | if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) |
3407 | return -9; | |
3408 | fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", | |
3409 | cpu, msr, (msr >> 31) & 1 ? "" : "UN"); | |
3410 | print_power_limit_msr(cpu, msr, "GFX Limit"); | |
889facbe LB |
3411 | } |
3412 | return 0; | |
3413 | } | |
3414 | ||
d7899447 LB |
3415 | /* |
3416 | * SNB adds support for additional MSRs: | |
3417 | * | |
3418 | * MSR_PKG_C7_RESIDENCY 0x000003fa | |
3419 | * MSR_CORE_C7_RESIDENCY 0x000003fe | |
3420 | * MSR_PKG_C2_RESIDENCY 0x0000060d | |
3421 | */ | |
103a8fea | 3422 | |
d7899447 | 3423 | int has_snb_msrs(unsigned int family, unsigned int model) |
103a8fea LB |
3424 | { |
3425 | if (!genuine_intel) | |
3426 | return 0; | |
3427 | ||
3428 | switch (model) { | |
869ce69e LB |
3429 | case INTEL_FAM6_SANDYBRIDGE: |
3430 | case INTEL_FAM6_SANDYBRIDGE_X: | |
3431 | case INTEL_FAM6_IVYBRIDGE: /* IVB */ | |
3432 | case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ | |
3433 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | |
3434 | case INTEL_FAM6_HASWELL_X: /* HSW */ | |
3435 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | |
3436 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | |
3437 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | |
3438 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | |
3439 | case INTEL_FAM6_BROADWELL_X: /* BDX */ | |
3440 | case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ | |
3441 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ | |
3442 | case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ | |
3443 | case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ | |
3444 | case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ | |
3445 | case INTEL_FAM6_SKYLAKE_X: /* SKX */ | |
3446 | case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ | |
ac01ac13 | 3447 | case INTEL_FAM6_ATOM_GEMINI_LAKE: |
5bbac26e | 3448 | case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ |
103a8fea LB |
3449 | return 1; |
3450 | } | |
3451 | return 0; | |
3452 | } | |
3453 | ||
d7899447 LB |
3454 | /* |
3455 | * HSW adds support for additional MSRs: | |
3456 | * | |
5a63426e LB |
3457 | * MSR_PKG_C8_RESIDENCY 0x00000630 |
3458 | * MSR_PKG_C9_RESIDENCY 0x00000631 | |
3459 | * MSR_PKG_C10_RESIDENCY 0x00000632 | |
3460 | * | |
3461 | * MSR_PKGC8_IRTL 0x00000633 | |
3462 | * MSR_PKGC9_IRTL 0x00000634 | |
3463 | * MSR_PKGC10_IRTL 0x00000635 | |
3464 | * | |
d7899447 LB |
3465 | */ |
3466 | int has_hsw_msrs(unsigned int family, unsigned int model) | |
ca58710f KCA |
3467 | { |
3468 | if (!genuine_intel) | |
3469 | return 0; | |
3470 | ||
3471 | switch (model) { | |
869ce69e LB |
3472 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ |
3473 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | |
3474 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ | |
3475 | case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ | |
3476 | case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ | |
3477 | case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ | |
3478 | case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ | |
ac01ac13 | 3479 | case INTEL_FAM6_ATOM_GEMINI_LAKE: |
0b2bb692 LB |
3480 | return 1; |
3481 | } | |
3482 | return 0; | |
3483 | } | |
3484 | ||
3485 | /* | |
3486 | * SKL adds support for additional MSRS: | |
3487 | * | |
3488 | * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 | |
3489 | * MSR_PKG_ANY_CORE_C0_RES 0x00000659 | |
3490 | * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A | |
3491 | * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B | |
3492 | */ | |
3493 | int has_skl_msrs(unsigned int family, unsigned int model) | |
3494 | { | |
3495 | if (!genuine_intel) | |
3496 | return 0; | |
3497 | ||
3498 | switch (model) { | |
869ce69e LB |
3499 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ |
3500 | case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ | |
3501 | case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ | |
3502 | case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ | |
ca58710f KCA |
3503 | return 1; |
3504 | } | |
3505 | return 0; | |
3506 | } | |
3507 | ||
144b44b1 LB |
3508 | int is_slm(unsigned int family, unsigned int model) |
3509 | { | |
3510 | if (!genuine_intel) | |
3511 | return 0; | |
3512 | switch (model) { | |
869ce69e LB |
3513 | case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ |
3514 | case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ | |
144b44b1 LB |
3515 | return 1; |
3516 | } | |
3517 | return 0; | |
3518 | } | |
3519 | ||
fb5d4327 DC |
3520 | int is_knl(unsigned int family, unsigned int model) |
3521 | { | |
3522 | if (!genuine_intel) | |
3523 | return 0; | |
3524 | switch (model) { | |
869ce69e | 3525 | case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ |
005c82d6 | 3526 | case INTEL_FAM6_XEON_PHI_KNM: |
fb5d4327 DC |
3527 | return 1; |
3528 | } | |
3529 | return 0; | |
3530 | } | |
3531 | ||
b2b34dfe HC |
3532 | unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) |
3533 | { | |
3534 | if (is_knl(family, model)) | |
3535 | return 1024; | |
3536 | return 1; | |
3537 | } | |
3538 | ||
144b44b1 LB |
3539 | #define SLM_BCLK_FREQS 5 |
3540 | double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; | |
3541 | ||
3542 | double slm_bclk(void) | |
3543 | { | |
3544 | unsigned long long msr = 3; | |
3545 | unsigned int i; | |
3546 | double freq; | |
3547 | ||
7ce7d5de | 3548 | if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) |
b7d8c148 | 3549 | fprintf(outf, "SLM BCLK: unknown\n"); |
144b44b1 LB |
3550 | |
3551 | i = msr & 0xf; | |
3552 | if (i >= SLM_BCLK_FREQS) { | |
b7d8c148 | 3553 | fprintf(outf, "SLM BCLK[%d] invalid\n", i); |
0a91e551 | 3554 | i = 3; |
144b44b1 LB |
3555 | } |
3556 | freq = slm_freq_table[i]; | |
3557 | ||
96e47158 | 3558 | if (!quiet) |
8f6196c1 | 3559 | fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); |
144b44b1 LB |
3560 | |
3561 | return freq; | |
3562 | } | |
3563 | ||
103a8fea LB |
3564 | double discover_bclk(unsigned int family, unsigned int model) |
3565 | { | |
121b48bb | 3566 | if (has_snb_msrs(family, model) || is_knl(family, model)) |
103a8fea | 3567 | return 100.00; |
144b44b1 LB |
3568 | else if (is_slm(family, model)) |
3569 | return slm_bclk(); | |
103a8fea LB |
3570 | else |
3571 | return 133.33; | |
3572 | } | |
3573 | ||
889facbe LB |
3574 | /* |
3575 | * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where | |
3576 | * the Thermal Control Circuit (TCC) activates. | |
3577 | * This is usually equal to tjMax. | |
3578 | * | |
3579 | * Older processors do not have this MSR, so there we guess, | |
3580 | * but also allow cmdline over-ride with -T. | |
3581 | * | |
3582 | * Several MSR temperature values are in units of degrees-C | |
3583 | * below this value, including the Digital Thermal Sensor (DTS), | |
3584 | * Package Thermal Management Sensor (PTM), and thermal event thresholds. | |
3585 | */ | |
3586 | int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
3587 | { | |
3588 | unsigned long long msr; | |
3589 | unsigned int target_c_local; | |
3590 | int cpu; | |
3591 | ||
3592 | /* tcc_activation_temp is used only for dts or ptm */ | |
3593 | if (!(do_dts || do_ptm)) | |
3594 | return 0; | |
3595 | ||
3596 | /* this is a per-package concept */ | |
3597 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
3598 | return 0; | |
3599 | ||
3600 | cpu = t->cpu_id; | |
3601 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 3602 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
3603 | return -1; |
3604 | } | |
3605 | ||
3606 | if (tcc_activation_temp_override != 0) { | |
3607 | tcc_activation_temp = tcc_activation_temp_override; | |
b7d8c148 | 3608 | fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", |
889facbe LB |
3609 | cpu, tcc_activation_temp); |
3610 | return 0; | |
3611 | } | |
3612 | ||
3613 | /* Temperature Target MSR is Nehalem and newer only */ | |
d7899447 | 3614 | if (!do_nhm_platform_info) |
889facbe LB |
3615 | goto guess; |
3616 | ||
7ce7d5de | 3617 | if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) |
889facbe LB |
3618 | goto guess; |
3619 | ||
3482124a | 3620 | target_c_local = (msr >> 16) & 0xFF; |
889facbe | 3621 | |
96e47158 | 3622 | if (!quiet) |
b7d8c148 | 3623 | fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", |
889facbe LB |
3624 | cpu, msr, target_c_local); |
3625 | ||
3482124a | 3626 | if (!target_c_local) |
889facbe LB |
3627 | goto guess; |
3628 | ||
3629 | tcc_activation_temp = target_c_local; | |
3630 | ||
3631 | return 0; | |
3632 | ||
3633 | guess: | |
3634 | tcc_activation_temp = TJMAX_DEFAULT; | |
b7d8c148 | 3635 | fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", |
889facbe LB |
3636 | cpu, tcc_activation_temp); |
3637 | ||
3638 | return 0; | |
3639 | } | |
69807a63 | 3640 | |
aa8d8cc7 LB |
3641 | void decode_feature_control_msr(void) |
3642 | { | |
3643 | unsigned long long msr; | |
3644 | ||
3645 | if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) | |
3646 | fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", | |
3647 | base_cpu, msr, | |
3648 | msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", | |
3649 | msr & (1 << 18) ? "SGX" : ""); | |
3650 | } | |
3651 | ||
69807a63 LB |
3652 | void decode_misc_enable_msr(void) |
3653 | { | |
3654 | unsigned long long msr; | |
3655 | ||
3656 | if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) | |
e6512624 | 3657 | fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", |
69807a63 | 3658 | base_cpu, msr, |
e6512624 LB |
3659 | msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", |
3660 | msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", | |
3661 | msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "", | |
3662 | msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", | |
3663 | msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); | |
69807a63 LB |
3664 | } |
3665 | ||
33148d67 LB |
3666 | void decode_misc_feature_control(void) |
3667 | { | |
3668 | unsigned long long msr; | |
3669 | ||
3670 | if (!has_misc_feature_control) | |
3671 | return; | |
3672 | ||
3673 | if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) | |
3674 | fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", | |
3675 | base_cpu, msr, | |
3676 | msr & (0 << 0) ? "No-" : "", | |
3677 | msr & (1 << 0) ? "No-" : "", | |
3678 | msr & (2 << 0) ? "No-" : "", | |
3679 | msr & (3 << 0) ? "No-" : ""); | |
3680 | } | |
f0057310 LB |
3681 | /* |
3682 | * Decode MSR_MISC_PWR_MGMT | |
3683 | * | |
3684 | * Decode the bits according to the Nehalem documentation | |
3685 | * bit[0] seems to continue to have same meaning going forward | |
3686 | * bit[1] less so... | |
3687 | */ | |
3688 | void decode_misc_pwr_mgmt_msr(void) | |
3689 | { | |
3690 | unsigned long long msr; | |
3691 | ||
3692 | if (!do_nhm_platform_info) | |
3693 | return; | |
3694 | ||
cf4cbe53 LB |
3695 | if (no_MSR_MISC_PWR_MGMT) |
3696 | return; | |
3697 | ||
f0057310 | 3698 | if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) |
ddadb8ad | 3699 | fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", |
f0057310 LB |
3700 | base_cpu, msr, |
3701 | msr & (1 << 0) ? "DIS" : "EN", | |
ddadb8ad SP |
3702 | msr & (1 << 1) ? "EN" : "DIS", |
3703 | msr & (1 << 8) ? "EN" : "DIS"); | |
f0057310 | 3704 | } |
71616c8e LB |
3705 | /* |
3706 | * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG | |
3707 | * | |
3708 | * This MSRs are present on Silvermont processors, | |
3709 | * Intel Atom processor E3000 series (Baytrail), and friends. | |
3710 | */ | |
3711 | void decode_c6_demotion_policy_msr(void) | |
3712 | { | |
3713 | unsigned long long msr; | |
3714 | ||
3715 | if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) | |
3716 | fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", | |
3717 | base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); | |
3718 | ||
3719 | if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) | |
3720 | fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", | |
3721 | base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); | |
3722 | } | |
7f5c258e | 3723 | |
fcd17211 | 3724 | void process_cpuid() |
103a8fea | 3725 | { |
61a87ba7 | 3726 | unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; |
103a8fea | 3727 | unsigned int fms, family, model, stepping; |
b3a34e93 | 3728 | unsigned int has_turbo; |
103a8fea LB |
3729 | |
3730 | eax = ebx = ecx = edx = 0; | |
3731 | ||
5aea2f7f | 3732 | __cpuid(0, max_level, ebx, ecx, edx); |
103a8fea LB |
3733 | |
3734 | if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) | |
3735 | genuine_intel = 1; | |
3736 | ||
96e47158 | 3737 | if (!quiet) |
b7d8c148 | 3738 | fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", |
103a8fea LB |
3739 | (char *)&ebx, (char *)&edx, (char *)&ecx); |
3740 | ||
5aea2f7f | 3741 | __cpuid(1, fms, ebx, ecx, edx); |
103a8fea LB |
3742 | family = (fms >> 8) & 0xf; |
3743 | model = (fms >> 4) & 0xf; | |
3744 | stepping = fms & 0xf; | |
3745 | if (family == 6 || family == 0xf) | |
3746 | model += ((fms >> 16) & 0xf) << 4; | |
3747 | ||
96e47158 | 3748 | if (!quiet) { |
b7d8c148 | 3749 | fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", |
103a8fea | 3750 | max_level, family, model, stepping, family, model, stepping); |
aa8d8cc7 | 3751 | fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", |
69807a63 LB |
3752 | ecx & (1 << 0) ? "SSE3" : "-", |
3753 | ecx & (1 << 3) ? "MONITOR" : "-", | |
aa8d8cc7 | 3754 | ecx & (1 << 6) ? "SMX" : "-", |
69807a63 LB |
3755 | ecx & (1 << 7) ? "EIST" : "-", |
3756 | ecx & (1 << 8) ? "TM2" : "-", | |
3757 | edx & (1 << 4) ? "TSC" : "-", | |
3758 | edx & (1 << 5) ? "MSR" : "-", | |
3759 | edx & (1 << 22) ? "ACPI-TM" : "-", | |
3760 | edx & (1 << 29) ? "TM" : "-"); | |
3761 | } | |
103a8fea | 3762 | |
b2c95d90 JT |
3763 | if (!(edx & (1 << 5))) |
3764 | errx(1, "CPUID: no MSR"); | |
103a8fea LB |
3765 | |
3766 | /* | |
3767 | * check max extended function levels of CPUID. | |
3768 | * This is needed to check for invariant TSC. | |
3769 | * This check is valid for both Intel and AMD. | |
3770 | */ | |
3771 | ebx = ecx = edx = 0; | |
5aea2f7f | 3772 | __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); |
103a8fea | 3773 | |
61a87ba7 | 3774 | if (max_extended_level >= 0x80000007) { |
103a8fea | 3775 | |
d7899447 LB |
3776 | /* |
3777 | * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 | |
3778 | * this check is valid for both Intel and AMD | |
3779 | */ | |
5aea2f7f | 3780 | __cpuid(0x80000007, eax, ebx, ecx, edx); |
d7899447 LB |
3781 | has_invariant_tsc = edx & (1 << 8); |
3782 | } | |
103a8fea LB |
3783 | |
3784 | /* | |
3785 | * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 | |
3786 | * this check is valid for both Intel and AMD | |
3787 | */ | |
3788 | ||
5aea2f7f | 3789 | __cpuid(0x6, eax, ebx, ecx, edx); |
8209e054 | 3790 | has_aperf = ecx & (1 << 0); |
812db3f7 LB |
3791 | if (has_aperf) { |
3792 | BIC_PRESENT(BIC_Avg_MHz); | |
3793 | BIC_PRESENT(BIC_Busy); | |
3794 | BIC_PRESENT(BIC_Bzy_MHz); | |
3795 | } | |
889facbe | 3796 | do_dts = eax & (1 << 0); |
812db3f7 LB |
3797 | if (do_dts) |
3798 | BIC_PRESENT(BIC_CoreTmp); | |
b3a34e93 | 3799 | has_turbo = eax & (1 << 1); |
889facbe | 3800 | do_ptm = eax & (1 << 6); |
812db3f7 LB |
3801 | if (do_ptm) |
3802 | BIC_PRESENT(BIC_PkgTmp); | |
7f5c258e LB |
3803 | has_hwp = eax & (1 << 7); |
3804 | has_hwp_notify = eax & (1 << 8); | |
3805 | has_hwp_activity_window = eax & (1 << 9); | |
3806 | has_hwp_epp = eax & (1 << 10); | |
3807 | has_hwp_pkg = eax & (1 << 11); | |
889facbe LB |
3808 | has_epb = ecx & (1 << 3); |
3809 | ||
96e47158 | 3810 | if (!quiet) |
b3a34e93 | 3811 | fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " |
7f5c258e LB |
3812 | "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", |
3813 | has_aperf ? "" : "No-", | |
b3a34e93 | 3814 | has_turbo ? "" : "No-", |
7f5c258e LB |
3815 | do_dts ? "" : "No-", |
3816 | do_ptm ? "" : "No-", | |
3817 | has_hwp ? "" : "No-", | |
3818 | has_hwp_notify ? "" : "No-", | |
3819 | has_hwp_activity_window ? "" : "No-", | |
3820 | has_hwp_epp ? "" : "No-", | |
3821 | has_hwp_pkg ? "" : "No-", | |
3822 | has_epb ? "" : "No-"); | |
103a8fea | 3823 | |
96e47158 | 3824 | if (!quiet) |
69807a63 LB |
3825 | decode_misc_enable_msr(); |
3826 | ||
33148d67 | 3827 | |
96e47158 | 3828 | if (max_level >= 0x7 && !quiet) { |
aa8d8cc7 | 3829 | int has_sgx; |
103a8fea | 3830 | |
aa8d8cc7 LB |
3831 | ecx = 0; |
3832 | ||
3833 | __cpuid_count(0x7, 0, eax, ebx, ecx, edx); | |
3834 | ||
3835 | has_sgx = ebx & (1 << 2); | |
3836 | fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); | |
3837 | ||
3838 | if (has_sgx) | |
3839 | decode_feature_control_msr(); | |
3840 | } | |
3841 | ||
61a87ba7 | 3842 | if (max_level >= 0x15) { |
8a5bdf41 LB |
3843 | unsigned int eax_crystal; |
3844 | unsigned int ebx_tsc; | |
3845 | ||
3846 | /* | |
3847 | * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz | |
3848 | */ | |
3849 | eax_crystal = ebx_tsc = crystal_hz = edx = 0; | |
5aea2f7f | 3850 | __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); |
8a5bdf41 LB |
3851 | |
3852 | if (ebx_tsc != 0) { | |
3853 | ||
96e47158 | 3854 | if (!quiet && (ebx != 0)) |
b7d8c148 | 3855 | fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", |
8a5bdf41 LB |
3856 | eax_crystal, ebx_tsc, crystal_hz); |
3857 | ||
3858 | if (crystal_hz == 0) | |
3859 | switch(model) { | |
869ce69e LB |
3860 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ |
3861 | case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ | |
3862 | case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ | |
3863 | case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ | |
e8efbc80 LB |
3864 | crystal_hz = 24000000; /* 24.0 MHz */ |
3865 | break; | |
869ce69e | 3866 | case INTEL_FAM6_SKYLAKE_X: /* SKX */ |
7268d407 | 3867 | case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ |
ec53e594 LB |
3868 | crystal_hz = 25000000; /* 25.0 MHz */ |
3869 | break; | |
869ce69e | 3870 | case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ |
ac01ac13 | 3871 | case INTEL_FAM6_ATOM_GEMINI_LAKE: |
e8efbc80 | 3872 | crystal_hz = 19200000; /* 19.2 MHz */ |
8a5bdf41 LB |
3873 | break; |
3874 | default: | |
3875 | crystal_hz = 0; | |
3876 | } | |
3877 | ||
3878 | if (crystal_hz) { | |
3879 | tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; | |
96e47158 | 3880 | if (!quiet) |
b7d8c148 | 3881 | fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", |
8a5bdf41 LB |
3882 | tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); |
3883 | } | |
3884 | } | |
3885 | } | |
61a87ba7 LB |
3886 | if (max_level >= 0x16) { |
3887 | unsigned int base_mhz, max_mhz, bus_mhz, edx; | |
3888 | ||
3889 | /* | |
3890 | * CPUID 16H Base MHz, Max MHz, Bus MHz | |
3891 | */ | |
3892 | base_mhz = max_mhz = bus_mhz = edx = 0; | |
3893 | ||
5aea2f7f | 3894 | __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); |
96e47158 | 3895 | if (!quiet) |
b7d8c148 | 3896 | fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", |
61a87ba7 LB |
3897 | base_mhz, max_mhz, bus_mhz); |
3898 | } | |
8a5bdf41 | 3899 | |
b2b34dfe HC |
3900 | if (has_aperf) |
3901 | aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); | |
3902 | ||
812db3f7 LB |
3903 | BIC_PRESENT(BIC_IRQ); |
3904 | BIC_PRESENT(BIC_TSC_MHz); | |
3905 | ||
3906 | if (probe_nhm_msrs(family, model)) { | |
3907 | do_nhm_platform_info = 1; | |
3908 | BIC_PRESENT(BIC_CPU_c1); | |
3909 | BIC_PRESENT(BIC_CPU_c3); | |
3910 | BIC_PRESENT(BIC_CPU_c6); | |
3911 | BIC_PRESENT(BIC_SMI); | |
3912 | } | |
d7899447 | 3913 | do_snb_cstates = has_snb_msrs(family, model); |
812db3f7 LB |
3914 | |
3915 | if (do_snb_cstates) | |
3916 | BIC_PRESENT(BIC_CPU_c7); | |
3917 | ||
5a63426e | 3918 | do_irtl_snb = has_snb_msrs(family, model); |
0f47c08d LB |
3919 | if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) |
3920 | BIC_PRESENT(BIC_Pkgpc2); | |
3921 | if (pkg_cstate_limit >= PCL__3) | |
3922 | BIC_PRESENT(BIC_Pkgpc3); | |
3923 | if (pkg_cstate_limit >= PCL__6) | |
3924 | BIC_PRESENT(BIC_Pkgpc6); | |
3925 | if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) | |
3926 | BIC_PRESENT(BIC_Pkgpc7); | |
0539ba11 | 3927 | if (has_slv_msrs(family, model)) { |
0f47c08d LB |
3928 | BIC_NOT_PRESENT(BIC_Pkgpc2); |
3929 | BIC_NOT_PRESENT(BIC_Pkgpc3); | |
3930 | BIC_PRESENT(BIC_Pkgpc6); | |
3931 | BIC_NOT_PRESENT(BIC_Pkgpc7); | |
0539ba11 LB |
3932 | BIC_PRESENT(BIC_Mod_c6); |
3933 | use_c1_residency_msr = 1; | |
3934 | } | |
7170a374 LB |
3935 | if (is_dnv(family, model)) { |
3936 | BIC_PRESENT(BIC_CPU_c1); | |
3937 | BIC_NOT_PRESENT(BIC_CPU_c3); | |
3938 | BIC_NOT_PRESENT(BIC_Pkgpc3); | |
3939 | BIC_NOT_PRESENT(BIC_CPU_c7); | |
3940 | BIC_NOT_PRESENT(BIC_Pkgpc7); | |
3941 | use_c1_residency_msr = 1; | |
3942 | } | |
34c76197 LB |
3943 | if (is_skx(family, model)) { |
3944 | BIC_NOT_PRESENT(BIC_CPU_c3); | |
3945 | BIC_NOT_PRESENT(BIC_Pkgpc3); | |
3946 | BIC_NOT_PRESENT(BIC_CPU_c7); | |
3947 | BIC_NOT_PRESENT(BIC_Pkgpc7); | |
3948 | } | |
ade0ebac LB |
3949 | if (is_bdx(family, model)) { |
3950 | BIC_NOT_PRESENT(BIC_CPU_c7); | |
3951 | BIC_NOT_PRESENT(BIC_Pkgpc7); | |
3952 | } | |
0f47c08d LB |
3953 | if (has_hsw_msrs(family, model)) { |
3954 | BIC_PRESENT(BIC_Pkgpc8); | |
3955 | BIC_PRESENT(BIC_Pkgpc9); | |
3956 | BIC_PRESENT(BIC_Pkgpc10); | |
3957 | } | |
5a63426e | 3958 | do_irtl_hsw = has_hsw_msrs(family, model); |
0b2bb692 | 3959 | do_skl_residency = has_skl_msrs(family, model); |
144b44b1 | 3960 | do_slm_cstates = is_slm(family, model); |
fb5d4327 | 3961 | do_knl_cstates = is_knl(family, model); |
103a8fea | 3962 | |
96e47158 | 3963 | if (!quiet) |
f0057310 LB |
3964 | decode_misc_pwr_mgmt_msr(); |
3965 | ||
96e47158 | 3966 | if (!quiet && has_slv_msrs(family, model)) |
71616c8e LB |
3967 | decode_c6_demotion_policy_msr(); |
3968 | ||
889facbe | 3969 | rapl_probe(family, model); |
3a9a941d | 3970 | perf_limit_reasons_probe(family, model); |
889facbe | 3971 | |
96e47158 | 3972 | if (!quiet) |
1b69317d | 3973 | dump_cstate_pstate_config_info(family, model); |
fcd17211 | 3974 | |
a2b7b749 LB |
3975 | if (has_skl_msrs(family, model)) |
3976 | calculate_tsc_tweak(); | |
3977 | ||
812db3f7 LB |
3978 | if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) |
3979 | BIC_PRESENT(BIC_GFX_rc6); | |
fdf676e5 | 3980 | |
812db3f7 LB |
3981 | if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) |
3982 | BIC_PRESENT(BIC_GFXMHz); | |
27d47356 | 3983 | |
96e47158 | 3984 | if (!quiet) |
33148d67 LB |
3985 | decode_misc_feature_control(); |
3986 | ||
889facbe | 3987 | return; |
103a8fea LB |
3988 | } |
3989 | ||
d8af6f5f | 3990 | void help() |
103a8fea | 3991 | { |
b7d8c148 | 3992 | fprintf(outf, |
d8af6f5f LB |
3993 | "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" |
3994 | "\n" | |
3995 | "Turbostat forks the specified COMMAND and prints statistics\n" | |
3996 | "when COMMAND completes.\n" | |
3997 | "If no COMMAND is specified, turbostat wakes every 5-seconds\n" | |
3998 | "to print statistics, until interrupted.\n" | |
388e9c81 LB |
3999 | "--add add a counter\n" |
4000 | " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" | |
96e47158 | 4001 | "--quiet skip decoding system configuration header\n" |
d8af6f5f LB |
4002 | "--interval sec Override default 5-second measurement interval\n" |
4003 | "--help print this help message\n" | |
b7d8c148 | 4004 | "--out file create or truncate \"file\" for all output\n" |
d8af6f5f LB |
4005 | "--version print version information\n" |
4006 | "\n" | |
4007 | "For more help, run \"man turbostat\"\n"); | |
103a8fea LB |
4008 | } |
4009 | ||
4010 | ||
4011 | /* | |
4012 | * in /dev/cpu/ return success for names that are numbers | |
4013 | * ie. filter out ".", "..", "microcode". | |
4014 | */ | |
4015 | int dir_filter(const struct dirent *dirp) | |
4016 | { | |
4017 | if (isdigit(dirp->d_name[0])) | |
4018 | return 1; | |
4019 | else | |
4020 | return 0; | |
4021 | } | |
4022 | ||
4023 | int open_dev_cpu_msr(int dummy1) | |
4024 | { | |
4025 | return 0; | |
4026 | } | |
4027 | ||
c98d5d94 LB |
4028 | void topology_probe() |
4029 | { | |
4030 | int i; | |
4031 | int max_core_id = 0; | |
4032 | int max_package_id = 0; | |
4033 | int max_siblings = 0; | |
4034 | struct cpu_topology { | |
4035 | int core_id; | |
4036 | int physical_package_id; | |
4037 | } *cpus; | |
4038 | ||
4039 | /* Initialize num_cpus, max_cpu_num */ | |
4040 | topo.num_cpus = 0; | |
4041 | topo.max_cpu_num = 0; | |
4042 | for_all_proc_cpus(count_cpus); | |
4043 | if (!summary_only && topo.num_cpus > 1) | |
812db3f7 | 4044 | BIC_PRESENT(BIC_CPU); |
c98d5d94 | 4045 | |
d8af6f5f | 4046 | if (debug > 1) |
b7d8c148 | 4047 | fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); |
c98d5d94 LB |
4048 | |
4049 | cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); | |
b2c95d90 JT |
4050 | if (cpus == NULL) |
4051 | err(1, "calloc cpus"); | |
c98d5d94 LB |
4052 | |
4053 | /* | |
4054 | * Allocate and initialize cpu_present_set | |
4055 | */ | |
4056 | cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); | |
b2c95d90 JT |
4057 | if (cpu_present_set == NULL) |
4058 | err(3, "CPU_ALLOC"); | |
c98d5d94 LB |
4059 | cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); |
4060 | CPU_ZERO_S(cpu_present_setsize, cpu_present_set); | |
4061 | for_all_proc_cpus(mark_cpu_present); | |
4062 | ||
4063 | /* | |
4064 | * Allocate and initialize cpu_affinity_set | |
4065 | */ | |
4066 | cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); | |
b2c95d90 JT |
4067 | if (cpu_affinity_set == NULL) |
4068 | err(3, "CPU_ALLOC"); | |
c98d5d94 LB |
4069 | cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); |
4070 | CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); | |
4071 | ||
4072 | ||
4073 | /* | |
4074 | * For online cpus | |
4075 | * find max_core_id, max_package_id | |
4076 | */ | |
4077 | for (i = 0; i <= topo.max_cpu_num; ++i) { | |
4078 | int siblings; | |
4079 | ||
4080 | if (cpu_is_not_present(i)) { | |
d8af6f5f | 4081 | if (debug > 1) |
b7d8c148 | 4082 | fprintf(outf, "cpu%d NOT PRESENT\n", i); |
c98d5d94 LB |
4083 | continue; |
4084 | } | |
4085 | cpus[i].core_id = get_core_id(i); | |
4086 | if (cpus[i].core_id > max_core_id) | |
4087 | max_core_id = cpus[i].core_id; | |
4088 | ||
4089 | cpus[i].physical_package_id = get_physical_package_id(i); | |
4090 | if (cpus[i].physical_package_id > max_package_id) | |
4091 | max_package_id = cpus[i].physical_package_id; | |
4092 | ||
4093 | siblings = get_num_ht_siblings(i); | |
4094 | if (siblings > max_siblings) | |
4095 | max_siblings = siblings; | |
d8af6f5f | 4096 | if (debug > 1) |
b7d8c148 | 4097 | fprintf(outf, "cpu %d pkg %d core %d\n", |
c98d5d94 LB |
4098 | i, cpus[i].physical_package_id, cpus[i].core_id); |
4099 | } | |
4100 | topo.num_cores_per_pkg = max_core_id + 1; | |
d8af6f5f | 4101 | if (debug > 1) |
b7d8c148 | 4102 | fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", |
c98d5d94 | 4103 | max_core_id, topo.num_cores_per_pkg); |
0f47c08d | 4104 | if (!summary_only && topo.num_cores_per_pkg > 1) |
812db3f7 | 4105 | BIC_PRESENT(BIC_Core); |
c98d5d94 LB |
4106 | |
4107 | topo.num_packages = max_package_id + 1; | |
d8af6f5f | 4108 | if (debug > 1) |
b7d8c148 | 4109 | fprintf(outf, "max_package_id %d, sizing for %d packages\n", |
c98d5d94 | 4110 | max_package_id, topo.num_packages); |
1cc21f7b | 4111 | if (debug && !summary_only && topo.num_packages > 1) |
812db3f7 | 4112 | BIC_PRESENT(BIC_Package); |
c98d5d94 LB |
4113 | |
4114 | topo.num_threads_per_core = max_siblings; | |
d8af6f5f | 4115 | if (debug > 1) |
b7d8c148 | 4116 | fprintf(outf, "max_siblings %d\n", max_siblings); |
c98d5d94 LB |
4117 | |
4118 | free(cpus); | |
4119 | } | |
4120 | ||
4121 | void | |
4122 | allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) | |
4123 | { | |
4124 | int i; | |
4125 | ||
4126 | *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * | |
678a3bd1 | 4127 | topo.num_packages, sizeof(struct thread_data)); |
c98d5d94 LB |
4128 | if (*t == NULL) |
4129 | goto error; | |
4130 | ||
4131 | for (i = 0; i < topo.num_threads_per_core * | |
4132 | topo.num_cores_per_pkg * topo.num_packages; i++) | |
4133 | (*t)[i].cpu_id = -1; | |
4134 | ||
4135 | *c = calloc(topo.num_cores_per_pkg * topo.num_packages, | |
678a3bd1 | 4136 | sizeof(struct core_data)); |
c98d5d94 LB |
4137 | if (*c == NULL) |
4138 | goto error; | |
4139 | ||
4140 | for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) | |
4141 | (*c)[i].core_id = -1; | |
4142 | ||
678a3bd1 | 4143 | *p = calloc(topo.num_packages, sizeof(struct pkg_data)); |
c98d5d94 LB |
4144 | if (*p == NULL) |
4145 | goto error; | |
4146 | ||
4147 | for (i = 0; i < topo.num_packages; i++) | |
4148 | (*p)[i].package_id = i; | |
4149 | ||
4150 | return; | |
4151 | error: | |
b2c95d90 | 4152 | err(1, "calloc counters"); |
c98d5d94 LB |
4153 | } |
4154 | /* | |
4155 | * init_counter() | |
4156 | * | |
4157 | * set cpu_id, core_num, pkg_num | |
4158 | * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE | |
4159 | * | |
4160 | * increment topo.num_cores when 1st core in pkg seen | |
4161 | */ | |
4162 | void init_counter(struct thread_data *thread_base, struct core_data *core_base, | |
4163 | struct pkg_data *pkg_base, int thread_num, int core_num, | |
4164 | int pkg_num, int cpu_id) | |
4165 | { | |
4166 | struct thread_data *t; | |
4167 | struct core_data *c; | |
4168 | struct pkg_data *p; | |
4169 | ||
4170 | t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); | |
4171 | c = GET_CORE(core_base, core_num, pkg_num); | |
4172 | p = GET_PKG(pkg_base, pkg_num); | |
4173 | ||
4174 | t->cpu_id = cpu_id; | |
4175 | if (thread_num == 0) { | |
4176 | t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; | |
4177 | if (cpu_is_first_core_in_package(cpu_id)) | |
4178 | t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; | |
4179 | } | |
4180 | ||
4181 | c->core_id = core_num; | |
4182 | p->package_id = pkg_num; | |
4183 | } | |
4184 | ||
4185 | ||
4186 | int initialize_counters(int cpu_id) | |
4187 | { | |
4188 | int my_thread_id, my_core_id, my_package_id; | |
4189 | ||
4190 | my_package_id = get_physical_package_id(cpu_id); | |
4191 | my_core_id = get_core_id(cpu_id); | |
e275b388 DC |
4192 | my_thread_id = get_cpu_position_in_core(cpu_id); |
4193 | if (!my_thread_id) | |
c98d5d94 | 4194 | topo.num_cores++; |
c98d5d94 LB |
4195 | |
4196 | init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); | |
4197 | init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); | |
4198 | return 0; | |
4199 | } | |
4200 | ||
4201 | void allocate_output_buffer() | |
4202 | { | |
3b4d5c7f | 4203 | output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); |
c98d5d94 | 4204 | outp = output_buffer; |
b2c95d90 JT |
4205 | if (outp == NULL) |
4206 | err(-1, "calloc output buffer"); | |
c98d5d94 | 4207 | } |
36229897 LB |
4208 | void allocate_fd_percpu(void) |
4209 | { | |
01a67adf | 4210 | fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); |
36229897 LB |
4211 | if (fd_percpu == NULL) |
4212 | err(-1, "calloc fd_percpu"); | |
4213 | } | |
562a2d37 LB |
4214 | void allocate_irq_buffers(void) |
4215 | { | |
4216 | irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); | |
4217 | if (irq_column_2_cpu == NULL) | |
4218 | err(-1, "calloc %d", topo.num_cpus); | |
c98d5d94 | 4219 | |
01a67adf | 4220 | irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); |
562a2d37 | 4221 | if (irqs_per_cpu == NULL) |
01a67adf | 4222 | err(-1, "calloc %d", topo.max_cpu_num + 1); |
562a2d37 | 4223 | } |
c98d5d94 LB |
4224 | void setup_all_buffers(void) |
4225 | { | |
4226 | topology_probe(); | |
562a2d37 | 4227 | allocate_irq_buffers(); |
36229897 | 4228 | allocate_fd_percpu(); |
c98d5d94 LB |
4229 | allocate_counters(&thread_even, &core_even, &package_even); |
4230 | allocate_counters(&thread_odd, &core_odd, &package_odd); | |
4231 | allocate_output_buffer(); | |
4232 | for_all_proc_cpus(initialize_counters); | |
4233 | } | |
3b4d5c7f | 4234 | |
7ce7d5de PB |
4235 | void set_base_cpu(void) |
4236 | { | |
4237 | base_cpu = sched_getcpu(); | |
4238 | if (base_cpu < 0) | |
4239 | err(-ENODEV, "No valid cpus found"); | |
4240 | ||
4241 | if (debug > 1) | |
b7d8c148 | 4242 | fprintf(outf, "base_cpu = %d\n", base_cpu); |
7ce7d5de PB |
4243 | } |
4244 | ||
103a8fea LB |
4245 | void turbostat_init() |
4246 | { | |
7ce7d5de PB |
4247 | setup_all_buffers(); |
4248 | set_base_cpu(); | |
103a8fea | 4249 | check_dev_msr(); |
98481e79 | 4250 | check_permissions(); |
fcd17211 | 4251 | process_cpuid(); |
103a8fea | 4252 | |
103a8fea | 4253 | |
96e47158 | 4254 | if (!quiet) |
7f5c258e LB |
4255 | for_all_cpus(print_hwp, ODD_COUNTERS); |
4256 | ||
96e47158 | 4257 | if (!quiet) |
889facbe LB |
4258 | for_all_cpus(print_epb, ODD_COUNTERS); |
4259 | ||
96e47158 | 4260 | if (!quiet) |
3a9a941d LB |
4261 | for_all_cpus(print_perf_limit, ODD_COUNTERS); |
4262 | ||
96e47158 | 4263 | if (!quiet) |
889facbe LB |
4264 | for_all_cpus(print_rapl, ODD_COUNTERS); |
4265 | ||
4266 | for_all_cpus(set_temperature_target, ODD_COUNTERS); | |
4267 | ||
96e47158 | 4268 | if (!quiet) |
889facbe | 4269 | for_all_cpus(print_thermal, ODD_COUNTERS); |
5a63426e | 4270 | |
96e47158 | 4271 | if (!quiet && do_irtl_snb) |
5a63426e | 4272 | print_irtl(); |
103a8fea LB |
4273 | } |
4274 | ||
4275 | int fork_it(char **argv) | |
4276 | { | |
103a8fea | 4277 | pid_t child_pid; |
d91bb17c | 4278 | int status; |
d15cf7c1 | 4279 | |
d91bb17c LB |
4280 | status = for_all_cpus(get_counters, EVEN_COUNTERS); |
4281 | if (status) | |
4282 | exit(status); | |
c98d5d94 LB |
4283 | /* clear affinity side-effect of get_counters() */ |
4284 | sched_setaffinity(0, cpu_present_setsize, cpu_present_set); | |
103a8fea LB |
4285 | gettimeofday(&tv_even, (struct timezone *)NULL); |
4286 | ||
4287 | child_pid = fork(); | |
4288 | if (!child_pid) { | |
4289 | /* child */ | |
4290 | execvp(argv[0], argv); | |
4291 | } else { | |
103a8fea LB |
4292 | |
4293 | /* parent */ | |
b2c95d90 JT |
4294 | if (child_pid == -1) |
4295 | err(1, "fork"); | |
103a8fea LB |
4296 | |
4297 | signal(SIGINT, SIG_IGN); | |
4298 | signal(SIGQUIT, SIG_IGN); | |
b2c95d90 JT |
4299 | if (waitpid(child_pid, &status, 0) == -1) |
4300 | err(status, "waitpid"); | |
103a8fea | 4301 | } |
c98d5d94 LB |
4302 | /* |
4303 | * n.b. fork_it() does not check for errors from for_all_cpus() | |
4304 | * because re-starting is problematic when forking | |
4305 | */ | |
4306 | for_all_cpus(get_counters, ODD_COUNTERS); | |
103a8fea | 4307 | gettimeofday(&tv_odd, (struct timezone *)NULL); |
103a8fea | 4308 | timersub(&tv_odd, &tv_even, &tv_delta); |
ba3dec99 LB |
4309 | if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) |
4310 | fprintf(outf, "%s: Counter reset detected\n", progname); | |
4311 | else { | |
4312 | compute_average(EVEN_COUNTERS); | |
4313 | format_all_counters(EVEN_COUNTERS); | |
4314 | } | |
103a8fea | 4315 | |
b7d8c148 LB |
4316 | fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); |
4317 | ||
4318 | flush_output_stderr(); | |
103a8fea | 4319 | |
d91bb17c | 4320 | return status; |
103a8fea LB |
4321 | } |
4322 | ||
3b4d5c7f AS |
4323 | int get_and_dump_counters(void) |
4324 | { | |
4325 | int status; | |
4326 | ||
4327 | status = for_all_cpus(get_counters, ODD_COUNTERS); | |
4328 | if (status) | |
4329 | return status; | |
4330 | ||
4331 | status = for_all_cpus(dump_counters, ODD_COUNTERS); | |
4332 | if (status) | |
4333 | return status; | |
4334 | ||
b7d8c148 | 4335 | flush_output_stdout(); |
3b4d5c7f AS |
4336 | |
4337 | return status; | |
4338 | } | |
4339 | ||
d8af6f5f | 4340 | void print_version() { |
0539ba11 | 4341 | fprintf(outf, "turbostat version 4.17 10 Jan 2017" |
d8af6f5f LB |
4342 | " - Len Brown <lenb@kernel.org>\n"); |
4343 | } | |
4344 | ||
388e9c81 LB |
4345 | int add_counter(unsigned int msr_num, char *name, unsigned int width, |
4346 | enum counter_scope scope, enum counter_type type, | |
4347 | enum counter_format format) | |
4348 | { | |
4349 | struct msr_counter *msrp; | |
4350 | ||
4351 | msrp = calloc(1, sizeof(struct msr_counter)); | |
4352 | if (msrp == NULL) { | |
4353 | perror("calloc"); | |
4354 | exit(1); | |
4355 | } | |
4356 | ||
4357 | msrp->msr_num = msr_num; | |
4358 | strncpy(msrp->name, name, NAME_BYTES); | |
4359 | msrp->width = width; | |
4360 | msrp->type = type; | |
4361 | msrp->format = format; | |
4362 | ||
4363 | switch (scope) { | |
4364 | ||
4365 | case SCOPE_CPU: | |
388e9c81 LB |
4366 | msrp->next = sys.tp; |
4367 | sys.tp = msrp; | |
678a3bd1 LB |
4368 | sys.added_thread_counters++; |
4369 | if (sys.added_thread_counters > MAX_ADDED_COUNTERS) { | |
4370 | fprintf(stderr, "exceeded max %d added thread counters\n", | |
4371 | MAX_ADDED_COUNTERS); | |
4372 | exit(-1); | |
4373 | } | |
388e9c81 LB |
4374 | break; |
4375 | ||
4376 | case SCOPE_CORE: | |
388e9c81 LB |
4377 | msrp->next = sys.cp; |
4378 | sys.cp = msrp; | |
678a3bd1 LB |
4379 | sys.added_core_counters++; |
4380 | if (sys.added_core_counters > MAX_ADDED_COUNTERS) { | |
4381 | fprintf(stderr, "exceeded max %d added core counters\n", | |
4382 | MAX_ADDED_COUNTERS); | |
4383 | exit(-1); | |
4384 | } | |
388e9c81 LB |
4385 | break; |
4386 | ||
4387 | case SCOPE_PACKAGE: | |
388e9c81 LB |
4388 | msrp->next = sys.pp; |
4389 | sys.pp = msrp; | |
678a3bd1 LB |
4390 | sys.added_package_counters++; |
4391 | if (sys.added_package_counters > MAX_ADDED_COUNTERS) { | |
4392 | fprintf(stderr, "exceeded max %d added package counters\n", | |
4393 | MAX_ADDED_COUNTERS); | |
4394 | exit(-1); | |
4395 | } | |
388e9c81 LB |
4396 | break; |
4397 | } | |
4398 | ||
4399 | return 0; | |
4400 | } | |
4401 | ||
4402 | void parse_add_command(char *add_command) | |
4403 | { | |
4404 | int msr_num = 0; | |
0f47c08d | 4405 | char name_buffer[NAME_BYTES] = ""; |
388e9c81 LB |
4406 | int width = 64; |
4407 | int fail = 0; | |
4408 | enum counter_scope scope = SCOPE_CPU; | |
4409 | enum counter_type type = COUNTER_CYCLES; | |
4410 | enum counter_format format = FORMAT_DELTA; | |
4411 | ||
4412 | while (add_command) { | |
4413 | ||
4414 | if (sscanf(add_command, "msr0x%x", &msr_num) == 1) | |
4415 | goto next; | |
4416 | ||
4417 | if (sscanf(add_command, "msr%d", &msr_num) == 1) | |
4418 | goto next; | |
4419 | ||
4420 | if (sscanf(add_command, "u%d", &width) == 1) { | |
4421 | if ((width == 32) || (width == 64)) | |
4422 | goto next; | |
4423 | width = 64; | |
4424 | } | |
4425 | if (!strncmp(add_command, "cpu", strlen("cpu"))) { | |
4426 | scope = SCOPE_CPU; | |
4427 | goto next; | |
4428 | } | |
4429 | if (!strncmp(add_command, "core", strlen("core"))) { | |
4430 | scope = SCOPE_CORE; | |
4431 | goto next; | |
4432 | } | |
4433 | if (!strncmp(add_command, "package", strlen("package"))) { | |
4434 | scope = SCOPE_PACKAGE; | |
4435 | goto next; | |
4436 | } | |
4437 | if (!strncmp(add_command, "cycles", strlen("cycles"))) { | |
4438 | type = COUNTER_CYCLES; | |
4439 | goto next; | |
4440 | } | |
4441 | if (!strncmp(add_command, "seconds", strlen("seconds"))) { | |
4442 | type = COUNTER_SECONDS; | |
4443 | goto next; | |
4444 | } | |
4445 | if (!strncmp(add_command, "raw", strlen("raw"))) { | |
4446 | format = FORMAT_RAW; | |
4447 | goto next; | |
4448 | } | |
4449 | if (!strncmp(add_command, "delta", strlen("delta"))) { | |
4450 | format = FORMAT_DELTA; | |
4451 | goto next; | |
4452 | } | |
4453 | if (!strncmp(add_command, "percent", strlen("percent"))) { | |
4454 | format = FORMAT_PERCENT; | |
4455 | goto next; | |
4456 | } | |
4457 | ||
4458 | if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ | |
4459 | char *eos; | |
4460 | ||
4461 | eos = strchr(name_buffer, ','); | |
4462 | if (eos) | |
4463 | *eos = '\0'; | |
4464 | goto next; | |
4465 | } | |
4466 | ||
4467 | next: | |
4468 | add_command = strchr(add_command, ','); | |
4469 | if (add_command) | |
4470 | add_command++; | |
4471 | ||
4472 | } | |
4473 | if (msr_num == 0) { | |
4474 | fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n"); | |
4475 | fail++; | |
4476 | } | |
4477 | ||
4478 | /* generate default column header */ | |
4479 | if (*name_buffer == '\0') { | |
4480 | if (format == FORMAT_RAW) { | |
4481 | if (width == 32) | |
4482 | sprintf(name_buffer, "msr%d", msr_num); | |
4483 | else | |
4484 | sprintf(name_buffer, "MSR%d", msr_num); | |
4485 | } else if (format == FORMAT_DELTA) { | |
4486 | if (width == 32) | |
4487 | sprintf(name_buffer, "cnt%d", msr_num); | |
4488 | else | |
4489 | sprintf(name_buffer, "CNT%d", msr_num); | |
4490 | } else if (format == FORMAT_PERCENT) { | |
4491 | if (width == 32) | |
4492 | sprintf(name_buffer, "msr%d%%", msr_num); | |
4493 | else | |
4494 | sprintf(name_buffer, "MSR%d%%", msr_num); | |
4495 | } | |
4496 | } | |
4497 | ||
4498 | if (add_counter(msr_num, name_buffer, width, scope, type, format)) | |
4499 | fail++; | |
4500 | ||
4501 | if (fail) { | |
4502 | help(); | |
4503 | exit(1); | |
4504 | } | |
4505 | } | |
812db3f7 LB |
4506 | /* |
4507 | * HIDE_LIST - hide this list of counters, show the rest [default] | |
4508 | * SHOW_LIST - show this list of counters, hide the rest | |
4509 | */ | |
4510 | enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; | |
4511 | ||
4512 | int shown; | |
4513 | /* | |
4514 | * parse_show_hide() - process cmdline to set default counter action | |
4515 | */ | |
4516 | void parse_show_hide(char *optarg, enum show_hide_mode new_mode) | |
4517 | { | |
4518 | /* | |
4519 | * --show: show only those specified | |
4520 | * The 1st invocation will clear and replace the enabled mask | |
4521 | * subsequent invocations can add to it. | |
4522 | */ | |
4523 | if (new_mode == SHOW_LIST) { | |
4524 | if (shown == 0) | |
4525 | bic_enabled = bic_lookup(optarg); | |
4526 | else | |
4527 | bic_enabled |= bic_lookup(optarg); | |
4528 | shown = 1; | |
4529 | ||
4530 | return; | |
4531 | } | |
4532 | ||
4533 | /* | |
4534 | * --hide: do not show those specified | |
4535 | * multiple invocations simply clear more bits in enabled mask | |
4536 | */ | |
4537 | bic_enabled &= ~bic_lookup(optarg); | |
4538 | } | |
4539 | ||
103a8fea LB |
4540 | void cmdline(int argc, char **argv) |
4541 | { | |
4542 | int opt; | |
d8af6f5f LB |
4543 | int option_index = 0; |
4544 | static struct option long_options[] = { | |
388e9c81 | 4545 | {"add", required_argument, 0, 'a'}, |
d8af6f5f | 4546 | {"Dump", no_argument, 0, 'D'}, |
96e47158 | 4547 | {"debug", no_argument, 0, 'd'}, /* internal, not documented */ |
d8af6f5f LB |
4548 | {"interval", required_argument, 0, 'i'}, |
4549 | {"help", no_argument, 0, 'h'}, | |
812db3f7 | 4550 | {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help |
d8af6f5f | 4551 | {"Joules", no_argument, 0, 'J'}, |
b7d8c148 | 4552 | {"out", required_argument, 0, 'o'}, |
d8af6f5f LB |
4553 | {"Package", no_argument, 0, 'p'}, |
4554 | {"processor", no_argument, 0, 'p'}, | |
96e47158 | 4555 | {"quiet", no_argument, 0, 'q'}, |
812db3f7 | 4556 | {"show", required_argument, 0, 's'}, |
d8af6f5f LB |
4557 | {"Summary", no_argument, 0, 'S'}, |
4558 | {"TCC", required_argument, 0, 'T'}, | |
4559 | {"version", no_argument, 0, 'v' }, | |
4560 | {0, 0, 0, 0 } | |
4561 | }; | |
103a8fea LB |
4562 | |
4563 | progname = argv[0]; | |
4564 | ||
96e47158 | 4565 | while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpqST:v", |
d8af6f5f | 4566 | long_options, &option_index)) != -1) { |
103a8fea | 4567 | switch (opt) { |
388e9c81 LB |
4568 | case 'a': |
4569 | parse_add_command(optarg); | |
4570 | break; | |
d8af6f5f | 4571 | case 'D': |
3b4d5c7f AS |
4572 | dump_only++; |
4573 | break; | |
d8af6f5f LB |
4574 | case 'd': |
4575 | debug++; | |
103a8fea | 4576 | break; |
812db3f7 LB |
4577 | case 'H': |
4578 | parse_show_hide(optarg, HIDE_LIST); | |
4579 | break; | |
d8af6f5f LB |
4580 | case 'h': |
4581 | default: | |
4582 | help(); | |
4583 | exit(1); | |
103a8fea | 4584 | case 'i': |
2a0609c0 LB |
4585 | { |
4586 | double interval = strtod(optarg, NULL); | |
4587 | ||
4588 | if (interval < 0.001) { | |
b7d8c148 | 4589 | fprintf(outf, "interval %f seconds is too small\n", |
2a0609c0 LB |
4590 | interval); |
4591 | exit(2); | |
4592 | } | |
4593 | ||
4594 | interval_ts.tv_sec = interval; | |
4595 | interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; | |
4596 | } | |
103a8fea | 4597 | break; |
d8af6f5f LB |
4598 | case 'J': |
4599 | rapl_joules++; | |
8e180f3c | 4600 | break; |
b7d8c148 LB |
4601 | case 'o': |
4602 | outf = fopen_or_die(optarg, "w"); | |
4603 | break; | |
d8af6f5f LB |
4604 | case 'P': |
4605 | show_pkg_only++; | |
4606 | break; | |
4607 | case 'p': | |
4608 | show_core_only++; | |
103a8fea | 4609 | break; |
96e47158 LB |
4610 | case 'q': |
4611 | quiet = 1; | |
4612 | break; | |
812db3f7 LB |
4613 | case 's': |
4614 | parse_show_hide(optarg, SHOW_LIST); | |
4615 | break; | |
d8af6f5f LB |
4616 | case 'S': |
4617 | summary_only++; | |
889facbe LB |
4618 | break; |
4619 | case 'T': | |
4620 | tcc_activation_temp_override = atoi(optarg); | |
4621 | break; | |
d8af6f5f LB |
4622 | case 'v': |
4623 | print_version(); | |
4624 | exit(0); | |
5c56be9a | 4625 | break; |
103a8fea LB |
4626 | } |
4627 | } | |
4628 | } | |
4629 | ||
4630 | int main(int argc, char **argv) | |
4631 | { | |
b7d8c148 LB |
4632 | outf = stderr; |
4633 | ||
103a8fea LB |
4634 | cmdline(argc, argv); |
4635 | ||
96e47158 | 4636 | if (!quiet) |
d8af6f5f | 4637 | print_version(); |
103a8fea LB |
4638 | |
4639 | turbostat_init(); | |
4640 | ||
3b4d5c7f AS |
4641 | /* dump counters and exit */ |
4642 | if (dump_only) | |
4643 | return get_and_dump_counters(); | |
4644 | ||
103a8fea LB |
4645 | /* |
4646 | * if any params left, it must be a command to fork | |
4647 | */ | |
4648 | if (argc - optind) | |
4649 | return fork_it(argv + optind); | |
4650 | else | |
4651 | turbostat_loop(); | |
4652 | ||
4653 | return 0; | |
4654 | } |