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tools/power/turbostat: Rename some TRL functions
[linux-block.git] / tools / power / x86 / turbostat / turbostat.c
CommitLineData
a61127c2 1// SPDX-License-Identifier: GPL-2.0-only
103a8fea
LB		 2/*
3 * turbostat -- show CPU frequency and C-state residency
34041551 4 * on modern Intel and AMD processors.
103a8fea 5 *
de7839ee 6 * Copyright (c) 2023 Intel Corporation.
103a8fea 7 * Len Brown <len.brown@intel.com>
103a8fea
LB		 8 */
9
88c3281f 10#define _GNU_SOURCE
b731f311 11#include MSRHEADER
869ce69e 12#include INTEL_FAMILY_HEADER
95aebc44 13#include <stdarg.h>
103a8fea 14#include <stdio.h>
b2c95d90 15#include <err.h>
103a8fea
LB		 16#include <unistd.h>
17#include <sys/types.h>
18#include <sys/wait.h>
19#include <sys/stat.h>
b9ad8ee0 20#include <sys/select.h>
103a8fea
LB		 21#include <sys/resource.h>
22#include <fcntl.h>
23#include <signal.h>
24#include <sys/time.h>
25#include <stdlib.h>
d8af6f5f 26#include <getopt.h>
103a8fea
LB		 27#include <dirent.h>
28#include <string.h>
29#include <ctype.h>
88c3281f 30#include <sched.h>
2a0609c0 31#include <time.h>
2b92865e 32#include <cpuid.h>
fcaa681c 33#include <sys/capability.h>
98481e79 34#include <errno.h>
9392bd98 35#include <math.h>
2af4f9b8
LB		 36#include <linux/perf_event.h>
37#include <asm/unistd.h>
7ab5ff49 38#include <stdbool.h>
103a8fea 39
9878bf7a
LB		 40#define UNUSED(x) (void)(x)
41
164d7a96
LB		 42/*
43 * This list matches the column headers, except
44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
45 * 2. Core and CPU are moved to the end, we can't have strings that contain them
46 * matching on them for --show and --hide.
47 */
48
49/*
50 * buffer size used by sscanf() for added column names
51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
52 */
53#define NAME_BYTES 20
54#define PATH_BYTES 128
55
56enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE };
57enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC };
58enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT };
59
60struct msr_counter {
61 unsigned int msr_num;
62 char name[NAME_BYTES];
63 char path[PATH_BYTES];
64 unsigned int width;
65 enum counter_type type;
66 enum counter_format format;
67 struct msr_counter *next;
68 unsigned int flags;
69#define FLAGS_HIDE (1 << 0)
70#define FLAGS_SHOW (1 << 1)
71#define SYSFS_PERCPU (1 << 1)
72};
73
74struct msr_counter bic[] = {
9878bf7a
LB		 75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 },
76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 },
77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 },
78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 },
79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 },
80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 },
81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 },
82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 },
83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 },
84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 },
85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 },
86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 },
87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 },
88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 },
89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 },
90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 },
91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 },
92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 },
93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 },
94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 },
95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 },
96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 },
97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 },
98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 },
99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 },
100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 },
101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 },
102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 },
103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 },
104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 },
105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 },
106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 },
107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 },
108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 },
109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 },
110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 },
111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 },
112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 },
113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 },
114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 },
115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 },
116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 },
117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 },
118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 },
119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 },
120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 },
121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 },
122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 },
123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 },
124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 },
125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 },
126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 },
127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 },
128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 },
a5c6d65d 129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 },
164d7a96
LB		 130};
131
132#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
133#define BIC_USEC (1ULL << 0)
134#define BIC_TOD (1ULL << 1)
135#define BIC_Package (1ULL << 2)
136#define BIC_Node (1ULL << 3)
137#define BIC_Avg_MHz (1ULL << 4)
138#define BIC_Busy (1ULL << 5)
139#define BIC_Bzy_MHz (1ULL << 6)
140#define BIC_TSC_MHz (1ULL << 7)
141#define BIC_IRQ (1ULL << 8)
142#define BIC_SMI (1ULL << 9)
143#define BIC_sysfs (1ULL << 10)
144#define BIC_CPU_c1 (1ULL << 11)
145#define BIC_CPU_c3 (1ULL << 12)
146#define BIC_CPU_c6 (1ULL << 13)
147#define BIC_CPU_c7 (1ULL << 14)
148#define BIC_ThreadC (1ULL << 15)
149#define BIC_CoreTmp (1ULL << 16)
150#define BIC_CoreCnt (1ULL << 17)
151#define BIC_PkgTmp (1ULL << 18)
152#define BIC_GFX_rc6 (1ULL << 19)
153#define BIC_GFXMHz (1ULL << 20)
154#define BIC_Pkgpc2 (1ULL << 21)
155#define BIC_Pkgpc3 (1ULL << 22)
156#define BIC_Pkgpc6 (1ULL << 23)
157#define BIC_Pkgpc7 (1ULL << 24)
158#define BIC_Pkgpc8 (1ULL << 25)
159#define BIC_Pkgpc9 (1ULL << 26)
160#define BIC_Pkgpc10 (1ULL << 27)
161#define BIC_CPU_LPI (1ULL << 28)
162#define BIC_SYS_LPI (1ULL << 29)
163#define BIC_PkgWatt (1ULL << 30)
164#define BIC_CorWatt (1ULL << 31)
165#define BIC_GFXWatt (1ULL << 32)
166#define BIC_PkgCnt (1ULL << 33)
167#define BIC_RAMWatt (1ULL << 34)
168#define BIC_PKG__ (1ULL << 35)
169#define BIC_RAM__ (1ULL << 36)
170#define BIC_Pkg_J (1ULL << 37)
171#define BIC_Cor_J (1ULL << 38)
172#define BIC_GFX_J (1ULL << 39)
173#define BIC_RAM_J (1ULL << 40)
174#define BIC_Mod_c6 (1ULL << 41)
175#define BIC_Totl_c0 (1ULL << 42)
176#define BIC_Any_c0 (1ULL << 43)
177#define BIC_GFX_c0 (1ULL << 44)
178#define BIC_CPUGFX (1ULL << 45)
179#define BIC_Core (1ULL << 46)
180#define BIC_CPU (1ULL << 47)
181#define BIC_APIC (1ULL << 48)
182#define BIC_X2APIC (1ULL << 49)
183#define BIC_Die (1ULL << 50)
184#define BIC_GFXACTMHz (1ULL << 51)
185#define BIC_IPC (1ULL << 52)
186#define BIC_CORE_THROT_CNT (1ULL << 53)
a5c6d65d 187#define BIC_UNCORE_MHZ (1ULL << 54)
164d7a96
LB		 188
189#define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die )
190#define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__)
a5c6d65d 191#define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ)
164d7a96
LB		 192#define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX)
193#define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC)
194
195#define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
196
197unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
198unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
199
200#define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
201#define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
202#define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
203#define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
204#define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
205#define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT)
206
103a8fea 207char *proc_stat = "/proc/stat";
b7d8c148 208FILE *outf;
36229897 209int *fd_percpu;
2af4f9b8 210int *fd_instr_count_percpu;
1b439f01
LB		 211struct timeval interval_tv = { 5, 0 };
212struct timespec interval_ts = { 5, 0 };
e9d3092f 213
023fe0ac 214unsigned int num_iterations;
c7e399f8 215unsigned int header_iterations;
d8af6f5f 216unsigned int debug;
96e47158 217unsigned int quiet;
3f44a5c6 218unsigned int shown;
0de6c0df 219unsigned int sums_need_wide_columns;
d8af6f5f
LB		 220unsigned int rapl_joules;
221unsigned int summary_only;
c8ade361 222unsigned int list_header_only;
d8af6f5f 223unsigned int dump_only;
103a8fea 224unsigned int do_snb_cstates;
fb5d4327 225unsigned int do_knl_cstates;
144b44b1
LB		 226unsigned int do_slm_cstates;
227unsigned int use_c1_residency_msr;
103a8fea 228unsigned int has_aperf;
889facbe 229unsigned int has_epb;
3ea8e52e 230unsigned int has_turbo;
774627c5 231unsigned int is_hybrid;
5a63426e
LB		 232unsigned int do_irtl_snb;
233unsigned int do_irtl_hsw;
fc04cc67 234unsigned int units = 1000000; /* MHz etc */
103a8fea 235unsigned int genuine_intel;
34041551 236unsigned int authentic_amd;
c1c10cc7 237unsigned int hygon_genuine;
34041551 238unsigned int max_level, max_extended_level;
103a8fea 239unsigned int has_invariant_tsc;
b2b34dfe 240unsigned int aperf_mperf_multiplier = 1;
103a8fea 241double bclk;
a2b7b749 242double base_hz;
21ed5574 243unsigned int has_base_hz;
a2b7b749 244double tsc_tweak = 1.0;
c98d5d94
LB		 245unsigned int show_pkg_only;
246unsigned int show_core_only;
247char *output_buffer, *outp;
889facbe
LB		 248unsigned int do_rapl;
249unsigned int do_dts;
250unsigned int do_ptm;
2af4f9b8 251unsigned int do_ipc;
1b439f01 252unsigned long long gfx_cur_rc6_ms;
be0e54c4
LB		 253unsigned long long cpuidle_cur_cpu_lpi_us;
254unsigned long long cpuidle_cur_sys_lpi_us;
27d47356 255unsigned int gfx_cur_mhz;
b4b91569 256unsigned int gfx_act_mhz;
55279aef
ZR		 257unsigned int tj_max;
258unsigned int tj_max_override;
0b9a0b9b 259int tcc_offset_bits;
40ee8e3b
AS		 260double rapl_power_units, rapl_time_units;
261double rapl_dram_energy_units, rapl_energy_units;
889facbe 262double rapl_joule_counter_range;
3a9a941d 263unsigned int do_core_perf_limit_reasons;
ac980e13 264unsigned int has_automatic_cstate_conversion;
aeb01e6d 265unsigned int dis_cstate_prewake;
3a9a941d
LB		 266unsigned int do_gfx_perf_limit_reasons;
267unsigned int do_ring_perf_limit_reasons;
8a5bdf41
LB		 268unsigned int crystal_hz;
269unsigned long long tsc_hz;
7ce7d5de 270int base_cpu;
1b439f01 271unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
7f5c258e 272 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
1b439f01 273unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
7f5c258e 274unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
1b439f01
LB		 275unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
276unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
4c2122d4 277unsigned int first_counter_read = 1;
c026c236 278int ignore_stdin;
889facbe 279
71e84129
ZR		 280int get_msr(int cpu, off_t offset, unsigned long long *msr);
281
45232ab1
ZR		 282/* Model specific support Start */
283
284/* List of features that may diverge among different platforms */
285struct platform_features {
778fc34a 286 bool has_msr_misc_feature_control; /* MSR_MISC_FEATURE_CONTROL */
3dd0e754 287 bool has_msr_misc_pwr_mgmt; /* MSR_MISC_PWR_MGMT */
fcfa1ce0 288 bool has_nhm_msrs; /* MSR_PLATFORM_INFO, MSR_IA32_TEMPERATURE_TARGET, MSR_SMI_COUNT, MSR_PKG_CST_CONFIG_CONTROL, TRL MSRs */
71e84129 289 int bclk_freq; /* CPU base clock */
3989fc89 290 int cst_limit; /* MSR_PKG_CST_CONFIG_CONTROL */
10d85d85 291 int trl_msrs; /* MSR_TURBO_RATIO_LIMIT/LIMIT1/LIMIT2/SECONDARY, Atom TRL MSRs */
45232ab1
ZR		 292};
293
294struct platform_data {
295 unsigned int model;
296 const struct platform_features *features;
297};
298
71e84129
ZR		 299/* For BCLK */
300enum bclk_freq {
301 BCLK_100MHZ = 1,
302 BCLK_133MHZ,
303 BCLK_SLV,
304};
305
306#define SLM_BCLK_FREQS 5
307double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 };
308
309double slm_bclk(void)
310{
311 unsigned long long msr = 3;
312 unsigned int i;
313 double freq;
314
315 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
316 fprintf(outf, "SLM BCLK: unknown\n");
317
318 i = msr & 0xf;
319 if (i >= SLM_BCLK_FREQS) {
320 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
321 i = 3;
322 }
323 freq = slm_freq_table[i];
324
325 if (!quiet)
326 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
327
328 return freq;
329}
330
3989fc89
ZR		 331/* For Package cstate limit */
332enum package_cstate_limit {
333 CST_LIMIT_NHM = 1,
334 CST_LIMIT_SNB,
335 CST_LIMIT_HSW,
336 CST_LIMIT_SKX,
337 CST_LIMIT_ICX,
338 CST_LIMIT_SLV,
339 CST_LIMIT_AMT,
340 CST_LIMIT_KNL,
341 CST_LIMIT_GMT,
342};
343
10d85d85
ZR		 344/* For Turbo Ratio Limit MSRs */
345enum turbo_ratio_limit_msrs {
346 TRL_BASE = BIT(0),
347 TRL_LIMIT1 = BIT(1),
348 TRL_LIMIT2 = BIT(2),
349 TRL_ATOM = BIT(3),
350 TRL_KNL = BIT(4),
351 TRL_CORECOUNT = BIT(5),
352};
353
45232ab1 354static const struct platform_features nhm_features = {
3dd0e754 355 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 356 .has_nhm_msrs = 1,
71e84129 357 .bclk_freq = BCLK_133MHZ,
3989fc89 358 .cst_limit = CST_LIMIT_NHM,
10d85d85 359 .trl_msrs = TRL_BASE,
45232ab1
ZR		 360};
361
362static const struct platform_features nhx_features = {
3dd0e754 363 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 364 .has_nhm_msrs = 1,
71e84129 365 .bclk_freq = BCLK_133MHZ,
3989fc89 366 .cst_limit = CST_LIMIT_NHM,
45232ab1
ZR		 367};
368
369static const struct platform_features snb_features = {
778fc34a 370 .has_msr_misc_feature_control = 1,
3dd0e754 371 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 372 .has_nhm_msrs = 1,
71e84129 373 .bclk_freq = BCLK_100MHZ,
3989fc89 374 .cst_limit = CST_LIMIT_SNB,
10d85d85 375 .trl_msrs = TRL_BASE,
45232ab1
ZR		 376};
377
378static const struct platform_features snx_features = {
778fc34a 379 .has_msr_misc_feature_control = 1,
3dd0e754 380 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 381 .has_nhm_msrs = 1,
71e84129 382 .bclk_freq = BCLK_100MHZ,
3989fc89 383 .cst_limit = CST_LIMIT_SNB,
10d85d85 384 .trl_msrs = TRL_BASE,
45232ab1
ZR		 385};
386
387static const struct platform_features ivb_features = {
778fc34a 388 .has_msr_misc_feature_control = 1,
3dd0e754 389 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 390 .has_nhm_msrs = 1,
71e84129 391 .bclk_freq = BCLK_100MHZ,
3989fc89 392 .cst_limit = CST_LIMIT_SNB,
10d85d85 393 .trl_msrs = TRL_BASE,
45232ab1
ZR		 394};
395
396static const struct platform_features ivx_features = {
778fc34a 397 .has_msr_misc_feature_control = 1,
3dd0e754 398 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 399 .has_nhm_msrs = 1,
71e84129 400 .bclk_freq = BCLK_100MHZ,
3989fc89 401 .cst_limit = CST_LIMIT_SNB,
10d85d85 402 .trl_msrs = TRL_BASE | TRL_LIMIT1,
45232ab1
ZR		 403};
404
405static const struct platform_features hsw_features = {
778fc34a 406 .has_msr_misc_feature_control = 1,
3dd0e754 407 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 408 .has_nhm_msrs = 1,
71e84129 409 .bclk_freq = BCLK_100MHZ,
3989fc89 410 .cst_limit = CST_LIMIT_HSW,
10d85d85 411 .trl_msrs = TRL_BASE,
45232ab1
ZR		 412};
413
414static const struct platform_features hsx_features = {
778fc34a 415 .has_msr_misc_feature_control = 1,
3dd0e754 416 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 417 .has_nhm_msrs = 1,
71e84129 418 .bclk_freq = BCLK_100MHZ,
3989fc89 419 .cst_limit = CST_LIMIT_HSW,
10d85d85 420 .trl_msrs = TRL_BASE | TRL_LIMIT1 | TRL_LIMIT2,
45232ab1
ZR		 421};
422
423static const struct platform_features hswl_features = {
778fc34a 424 .has_msr_misc_feature_control = 1,
3dd0e754 425 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 426 .has_nhm_msrs = 1,
71e84129 427 .bclk_freq = BCLK_100MHZ,
3989fc89 428 .cst_limit = CST_LIMIT_HSW,
10d85d85 429 .trl_msrs = TRL_BASE,
45232ab1
ZR		 430};
431
432static const struct platform_features hswg_features = {
778fc34a 433 .has_msr_misc_feature_control = 1,
3dd0e754 434 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 435 .has_nhm_msrs = 1,
71e84129 436 .bclk_freq = BCLK_100MHZ,
3989fc89 437 .cst_limit = CST_LIMIT_HSW,
10d85d85 438 .trl_msrs = TRL_BASE,
45232ab1
ZR		 439};
440
441static const struct platform_features bdw_features = {
778fc34a 442 .has_msr_misc_feature_control = 1,
3dd0e754 443 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 444 .has_nhm_msrs = 1,
71e84129 445 .bclk_freq = BCLK_100MHZ,
3989fc89 446 .cst_limit = CST_LIMIT_HSW,
10d85d85 447 .trl_msrs = TRL_BASE,
45232ab1
ZR		 448};
449
450static const struct platform_features bdwg_features = {
778fc34a 451 .has_msr_misc_feature_control = 1,
3dd0e754 452 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 453 .has_nhm_msrs = 1,
71e84129 454 .bclk_freq = BCLK_100MHZ,
3989fc89 455 .cst_limit = CST_LIMIT_HSW,
10d85d85 456 .trl_msrs = TRL_BASE,
45232ab1
ZR		 457};
458
459static const struct platform_features bdx_features = {
778fc34a 460 .has_msr_misc_feature_control = 1,
3dd0e754 461 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 462 .has_nhm_msrs = 1,
71e84129 463 .bclk_freq = BCLK_100MHZ,
3989fc89 464 .cst_limit = CST_LIMIT_HSW,
10d85d85 465 .trl_msrs = TRL_BASE,
45232ab1
ZR		 466};
467
468static const struct platform_features skl_features = {
778fc34a 469 .has_msr_misc_feature_control = 1,
3dd0e754 470 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 471 .has_nhm_msrs = 1,
71e84129 472 .bclk_freq = BCLK_100MHZ,
3989fc89 473 .cst_limit = CST_LIMIT_HSW,
10d85d85 474 .trl_msrs = TRL_BASE,
45232ab1
ZR		 475};
476
477static const struct platform_features cnl_features = {
778fc34a 478 .has_msr_misc_feature_control = 1,
3dd0e754 479 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 480 .has_nhm_msrs = 1,
71e84129 481 .bclk_freq = BCLK_100MHZ,
3989fc89 482 .cst_limit = CST_LIMIT_HSW,
10d85d85 483 .trl_msrs = TRL_BASE,
45232ab1
ZR		 484};
485
486static const struct platform_features skx_features = {
778fc34a 487 .has_msr_misc_feature_control = 1,
3dd0e754 488 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 489 .has_nhm_msrs = 1,
71e84129 490 .bclk_freq = BCLK_100MHZ,
3989fc89 491 .cst_limit = CST_LIMIT_SKX,
10d85d85 492 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
45232ab1
ZR		 493};
494
495static const struct platform_features icx_features = {
778fc34a 496 .has_msr_misc_feature_control = 1,
3dd0e754 497 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 498 .has_nhm_msrs = 1,
71e84129 499 .bclk_freq = BCLK_100MHZ,
3989fc89 500 .cst_limit = CST_LIMIT_ICX,
10d85d85 501 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
45232ab1
ZR		 502};
503
504static const struct platform_features spr_features = {
778fc34a 505 .has_msr_misc_feature_control = 1,
3dd0e754 506 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 507 .has_nhm_msrs = 1,
71e84129 508 .bclk_freq = BCLK_100MHZ,
3989fc89 509 .cst_limit = CST_LIMIT_SKX,
10d85d85 510 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
45232ab1
ZR		 511};
512
513static const struct platform_features slv_features = {
fcfa1ce0 514 .has_nhm_msrs = 1,
71e84129 515 .bclk_freq = BCLK_SLV,
3989fc89 516 .cst_limit = CST_LIMIT_SLV,
10d85d85 517 .trl_msrs = TRL_ATOM,
45232ab1
ZR		 518};
519
520static const struct platform_features slvd_features = {
3dd0e754 521 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 522 .has_nhm_msrs = 1,
71e84129 523 .bclk_freq = BCLK_SLV,
3989fc89 524 .cst_limit = CST_LIMIT_SLV,
10d85d85 525 .trl_msrs = TRL_BASE,
45232ab1
ZR		 526};
527
528static const struct platform_features amt_features = {
fcfa1ce0 529 .has_nhm_msrs = 1,
71e84129 530 .bclk_freq = BCLK_133MHZ,
3989fc89 531 .cst_limit = CST_LIMIT_AMT,
10d85d85 532 .trl_msrs = TRL_BASE,
45232ab1
ZR		 533};
534
535static const struct platform_features gmt_features = {
3dd0e754 536 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 537 .has_nhm_msrs = 1,
71e84129 538 .bclk_freq = BCLK_100MHZ,
3989fc89 539 .cst_limit = CST_LIMIT_GMT,
10d85d85 540 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
45232ab1
ZR		 541};
542
543static const struct platform_features gmtd_features = {
3dd0e754 544 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 545 .has_nhm_msrs = 1,
71e84129 546 .bclk_freq = BCLK_100MHZ,
3989fc89 547 .cst_limit = CST_LIMIT_GMT,
10d85d85 548 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
45232ab1
ZR		 549};
550
551static const struct platform_features gmtp_features = {
3dd0e754 552 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 553 .has_nhm_msrs = 1,
71e84129 554 .bclk_freq = BCLK_100MHZ,
3989fc89 555 .cst_limit = CST_LIMIT_GMT,
10d85d85 556 .trl_msrs = TRL_BASE,
45232ab1
ZR		 557};
558
559static const struct platform_features tmt_features = {
3dd0e754 560 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 561 .has_nhm_msrs = 1,
71e84129 562 .bclk_freq = BCLK_100MHZ,
3989fc89 563 .cst_limit = CST_LIMIT_GMT,
10d85d85 564 .trl_msrs = TRL_BASE,
45232ab1
ZR		 565};
566
567static const struct platform_features tmtd_features = {
3dd0e754 568 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 569 .has_nhm_msrs = 1,
71e84129 570 .bclk_freq = BCLK_100MHZ,
3989fc89 571 .cst_limit = CST_LIMIT_GMT,
10d85d85 572 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
45232ab1
ZR		 573};
574
575static const struct platform_features knl_features = {
3dd0e754 576 .has_msr_misc_pwr_mgmt = 1,
fcfa1ce0 577 .has_nhm_msrs = 1,
71e84129 578 .bclk_freq = BCLK_100MHZ,
3989fc89 579 .cst_limit = CST_LIMIT_KNL,
10d85d85 580 .trl_msrs = TRL_KNL,
45232ab1
ZR		 581};
582
583static const struct platform_features default_features = {
584};
585
586static const struct platform_features amd_features = {
587};
588
589static const struct platform_data turbostat_pdata[] = {
590 { INTEL_FAM6_NEHALEM, &nhm_features },
591 { INTEL_FAM6_NEHALEM_G, &nhm_features },
592 { INTEL_FAM6_NEHALEM_EP, &nhm_features },
593 { INTEL_FAM6_NEHALEM_EX, &nhx_features },
594 { INTEL_FAM6_WESTMERE, &nhm_features },
595 { INTEL_FAM6_WESTMERE_EP, &nhm_features },
596 { INTEL_FAM6_WESTMERE_EX, &nhx_features },
597 { INTEL_FAM6_SANDYBRIDGE, &snb_features },
598 { INTEL_FAM6_SANDYBRIDGE_X, &snx_features },
599 { INTEL_FAM6_IVYBRIDGE, &ivb_features },
600 { INTEL_FAM6_IVYBRIDGE_X, &ivx_features },
601 { INTEL_FAM6_HASWELL, &hsw_features },
602 { INTEL_FAM6_HASWELL_X, &hsx_features },
603 { INTEL_FAM6_HASWELL_L, &hswl_features },
604 { INTEL_FAM6_HASWELL_G, &hswg_features },
605 { INTEL_FAM6_BROADWELL, &bdw_features },
606 { INTEL_FAM6_BROADWELL_G, &bdwg_features },
607 { INTEL_FAM6_BROADWELL_X, &bdx_features },
608 { INTEL_FAM6_BROADWELL_D, &bdx_features },
609 { INTEL_FAM6_SKYLAKE_L, &skl_features },
610 { INTEL_FAM6_SKYLAKE, &skl_features },
611 { INTEL_FAM6_SKYLAKE_X, &skx_features },
612 { INTEL_FAM6_KABYLAKE_L, &skl_features },
613 { INTEL_FAM6_KABYLAKE, &skl_features },
614 { INTEL_FAM6_COMETLAKE, &skl_features },
615 { INTEL_FAM6_COMETLAKE_L, &skl_features },
616 { INTEL_FAM6_CANNONLAKE_L, &cnl_features },
617 { INTEL_FAM6_ICELAKE_X, &icx_features },
618 { INTEL_FAM6_ICELAKE_D, &icx_features },
619 { INTEL_FAM6_ICELAKE_L, &cnl_features },
620 { INTEL_FAM6_ICELAKE_NNPI, &cnl_features },
621 { INTEL_FAM6_ROCKETLAKE, &cnl_features },
622 { INTEL_FAM6_TIGERLAKE_L, &cnl_features },
623 { INTEL_FAM6_TIGERLAKE, &cnl_features },
624 { INTEL_FAM6_SAPPHIRERAPIDS_X, &spr_features },
625 { INTEL_FAM6_EMERALDRAPIDS_X, &spr_features },
626 { INTEL_FAM6_LAKEFIELD, &cnl_features },
627 { INTEL_FAM6_ALDERLAKE, &cnl_features },
628 { INTEL_FAM6_ALDERLAKE_L, &cnl_features },
629 { INTEL_FAM6_RAPTORLAKE, &cnl_features },
630 { INTEL_FAM6_RAPTORLAKE_P, &cnl_features },
631 { INTEL_FAM6_RAPTORLAKE_S, &cnl_features },
632 { INTEL_FAM6_METEORLAKE, &cnl_features },
633 { INTEL_FAM6_METEORLAKE_L, &cnl_features },
634 { INTEL_FAM6_ATOM_SILVERMONT, &slv_features },
635 { INTEL_FAM6_ATOM_SILVERMONT_D, &slvd_features },
636 { INTEL_FAM6_ATOM_AIRMONT, &amt_features },
637 { INTEL_FAM6_ATOM_GOLDMONT, &gmt_features },
638 { INTEL_FAM6_ATOM_GOLDMONT_D, &gmtd_features },
639 { INTEL_FAM6_ATOM_GOLDMONT_PLUS, &gmtp_features },
640 { INTEL_FAM6_ATOM_TREMONT_D, &tmtd_features },
641 { INTEL_FAM6_ATOM_TREMONT, &tmt_features },
642 { INTEL_FAM6_ATOM_TREMONT_L, &tmt_features },
643 { INTEL_FAM6_ATOM_GRACEMONT, &cnl_features },
644 { INTEL_FAM6_XEON_PHI_KNL, &knl_features },
645 { INTEL_FAM6_XEON_PHI_KNM, &knl_features },
646 /*
647 * Missing support for
648 * INTEL_FAM6_ICELAKE
649 * INTEL_FAM6_ATOM_SILVERMONT_MID
650 * INTEL_FAM6_ATOM_AIRMONT_MID
651 * INTEL_FAM6_ATOM_AIRMONT_NP
652 */
653 { 0, NULL },
654};
655
656static const struct platform_features *platform;
657
658void probe_platform_features(unsigned int family, unsigned int model)
659{
660 int i;
661
662 if (authentic_amd || hygon_genuine) {
663 platform = &amd_features;
664 return;
665 }
666
667 platform = &default_features;
668
669 if (!genuine_intel || family != 6)
670 return;
671
672 for (i = 0; turbostat_pdata[i].features; i++) {
673 if (turbostat_pdata[i].model == model) {
674 platform = turbostat_pdata[i].features;
675 return;
676 }
677 }
678}
679
680/* Model specific support End */
681
e6f9bb3c
LB		 682#define RAPL_PKG (1 << 0)
683 /* 0x610 MSR_PKG_POWER_LIMIT */
684 /* 0x611 MSR_PKG_ENERGY_STATUS */
685#define RAPL_PKG_PERF_STATUS (1 << 1)
686 /* 0x613 MSR_PKG_PERF_STATUS */
687#define RAPL_PKG_POWER_INFO (1 << 2)
688 /* 0x614 MSR_PKG_POWER_INFO */
689
690#define RAPL_DRAM (1 << 3)
691 /* 0x618 MSR_DRAM_POWER_LIMIT */
692 /* 0x619 MSR_DRAM_ENERGY_STATUS */
e6f9bb3c
LB		 693#define RAPL_DRAM_PERF_STATUS (1 << 4)
694 /* 0x61b MSR_DRAM_PERF_STATUS */
0b2bb692
LB		 695#define RAPL_DRAM_POWER_INFO (1 << 5)
696 /* 0x61c MSR_DRAM_POWER_INFO */
e6f9bb3c 697
9148494c 698#define RAPL_CORES_POWER_LIMIT (1 << 6)
e6f9bb3c 699 /* 0x638 MSR_PP0_POWER_LIMIT */
0b2bb692 700#define RAPL_CORE_POLICY (1 << 7)
e6f9bb3c
LB		 701 /* 0x63a MSR_PP0_POLICY */
702
0b2bb692 703#define RAPL_GFX (1 << 8)
e6f9bb3c
LB		 704 /* 0x640 MSR_PP1_POWER_LIMIT */
705 /* 0x641 MSR_PP1_ENERGY_STATUS */
706 /* 0x642 MSR_PP1_POLICY */
9148494c
JP		 707
708#define RAPL_CORES_ENERGY_STATUS (1 << 9)
709 /* 0x639 MSR_PP0_ENERGY_STATUS */
9392bd98
CW		 710#define RAPL_PER_CORE_ENERGY (1 << 10)
711 /* Indicates cores energy collection is per-core,
712 * not per-package. */
713#define RAPL_AMD_F17H (1 << 11)
714 /* 0xc0010299 MSR_RAPL_PWR_UNIT */
715 /* 0xc001029a MSR_CORE_ENERGY_STAT */
716 /* 0xc001029b MSR_PKG_ENERGY_STAT */
9148494c 717#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
889facbe
LB		 718#define TJMAX_DEFAULT 100
719
9392bd98
CW		 720/* MSRs that are not yet in the kernel-provided header. */
721#define MSR_RAPL_PWR_UNIT 0xc0010299
722#define MSR_CORE_ENERGY_STAT 0xc001029a
723#define MSR_PKG_ENERGY_STAT 0xc001029b
724
889facbe 725#define MAX(a, b) ((a) > (b) ? (a) : (b))
103a8fea 726
103a8fea
LB		 727int backwards_count;
728char *progname;
103a8fea 729
1ef7d21a
LB		 730#define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
731cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
732size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
0748eaf0
LB		 733#define MAX_ADDED_COUNTERS 8
734#define MAX_ADDED_THREAD_COUNTERS 24
0e2d8f05 735#define BITMASK_SIZE 32
c98d5d94
LB		 736
737struct thread_data {
f4fdf2b4
LB		 738 struct timeval tv_begin;
739 struct timeval tv_end;
d4794f25 740 struct timeval tv_delta;
c98d5d94
LB		 741 unsigned long long tsc;
742 unsigned long long aperf;
743 unsigned long long mperf;
144b44b1 744 unsigned long long c1;
2af4f9b8 745 unsigned long long instr_count;
1b439f01 746 unsigned long long irq_count;
1ed51011 747 unsigned int smi_count;
c98d5d94 748 unsigned int cpu_id;
4c2122d4
LB		 749 unsigned int apic_id;
750 unsigned int x2apic_id;
c98d5d94 751 unsigned int flags;
7ab5ff49 752 bool is_atom;
c98d5d94
LB		 753#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
754#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
0748eaf0 755 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
c98d5d94
LB		 756} *thread_even, *thread_odd;
757
758struct core_data {
759 unsigned long long c3;
760 unsigned long long c6;
761 unsigned long long c7;
0539ba11 762 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
889facbe 763 unsigned int core_temp_c;
9392bd98 764 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
c98d5d94 765 unsigned int core_id;
eae97e05 766 unsigned long long core_throt_cnt;
678a3bd1 767 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 768} *core_even, *core_odd;
769
770struct pkg_data {
771 unsigned long long pc2;
772 unsigned long long pc3;
773 unsigned long long pc6;
774 unsigned long long pc7;
ca58710f
KCA		 775 unsigned long long pc8;
776 unsigned long long pc9;
777 unsigned long long pc10;
be0e54c4
LB		 778 unsigned long long cpu_lpi;
779 unsigned long long sys_lpi;
0b2bb692
LB		 780 unsigned long long pkg_wtd_core_c0;
781 unsigned long long pkg_any_core_c0;
782 unsigned long long pkg_any_gfxe_c0;
783 unsigned long long pkg_both_core_gfxe_c0;
9185e988 784 long long gfx_rc6_ms;
27d47356 785 unsigned int gfx_mhz;
b4b91569 786 unsigned int gfx_act_mhz;
c98d5d94 787 unsigned int package_id;
7c2ccc50
CY		 788 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */
789 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */
790 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */
791 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */
792 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
793 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
889facbe 794 unsigned int pkg_temp_c;
a5c6d65d 795 unsigned int uncore_mhz;
678a3bd1 796 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 797} *package_even, *package_odd;
798
799#define ODD_COUNTERS thread_odd, core_odd, package_odd
800#define EVEN_COUNTERS thread_even, core_even, package_even
801
40f5cfe7
PB		 802#define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
803 ((thread_base) + \
804 ((pkg_no) * \
805 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
806 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
807 ((core_no) * topo.threads_per_core) + \
808 (thread_no))
809
810#define GET_CORE(core_base, core_no, node_no, pkg_no) \
811 ((core_base) + \
812 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
813 ((node_no) * topo.cores_per_node) + \
814 (core_no))
815
c98d5d94
LB		 816#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
817
87e15da9
CY		 818/*
819 * The accumulated sum of MSR is defined as a monotonic
820 * increasing MSR, it will be accumulated periodically,
821 * despite its register's bit width.
822 */
823enum {
824 IDX_PKG_ENERGY,
825 IDX_DRAM_ENERGY,
826 IDX_PP0_ENERGY,
827 IDX_PP1_ENERGY,
828 IDX_PKG_PERF,
829 IDX_DRAM_PERF,
830 IDX_COUNT,
831};
832
833int get_msr_sum(int cpu, off_t offset, unsigned long long *msr);
834
835struct msr_sum_array {
836 /* get_msr_sum() = sum + (get_msr() - last) */
837 struct {
1b439f01 838 /*The accumulated MSR value is updated by the timer */
87e15da9 839 unsigned long long sum;
1b439f01 840 /*The MSR footprint recorded in last timer */
87e15da9
CY		 841 unsigned long long last;
842 } entries[IDX_COUNT];
843};
844
845/* The percpu MSR sum array.*/
846struct msr_sum_array *per_cpu_msr_sum;
847
13a779de 848off_t idx_to_offset(int idx)
87e15da9 849{
13a779de 850 off_t offset;
87e15da9
CY		 851
852 switch (idx) {
853 case IDX_PKG_ENERGY:
301b1d3a
BN		 854 if (do_rapl & RAPL_AMD_F17H)
855 offset = MSR_PKG_ENERGY_STAT;
856 else
857 offset = MSR_PKG_ENERGY_STATUS;
87e15da9
CY		 858 break;
859 case IDX_DRAM_ENERGY:
860 offset = MSR_DRAM_ENERGY_STATUS;
861 break;
862 case IDX_PP0_ENERGY:
863 offset = MSR_PP0_ENERGY_STATUS;
864 break;
865 case IDX_PP1_ENERGY:
866 offset = MSR_PP1_ENERGY_STATUS;
867 break;
868 case IDX_PKG_PERF:
869 offset = MSR_PKG_PERF_STATUS;
870 break;
871 case IDX_DRAM_PERF:
872 offset = MSR_DRAM_PERF_STATUS;
873 break;
874 default:
875 offset = -1;
876 }
877 return offset;
878}
879
13a779de 880int offset_to_idx(off_t offset)
87e15da9
CY		 881{
882 int idx;
883
884 switch (offset) {
885 case MSR_PKG_ENERGY_STATUS:
301b1d3a 886 case MSR_PKG_ENERGY_STAT:
87e15da9
CY		 887 idx = IDX_PKG_ENERGY;
888 break;
889 case MSR_DRAM_ENERGY_STATUS:
890 idx = IDX_DRAM_ENERGY;
891 break;
892 case MSR_PP0_ENERGY_STATUS:
893 idx = IDX_PP0_ENERGY;
894 break;
895 case MSR_PP1_ENERGY_STATUS:
896 idx = IDX_PP1_ENERGY;
897 break;
898 case MSR_PKG_PERF_STATUS:
899 idx = IDX_PKG_PERF;
900 break;
901 case MSR_DRAM_PERF_STATUS:
902 idx = IDX_DRAM_PERF;
903 break;
904 default:
905 idx = -1;
906 }
907 return idx;
908}
909
910int idx_valid(int idx)
911{
912 switch (idx) {
913 case IDX_PKG_ENERGY:
301b1d3a 914 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H);
87e15da9
CY		 915 case IDX_DRAM_ENERGY:
916 return do_rapl & RAPL_DRAM;
917 case IDX_PP0_ENERGY:
918 return do_rapl & RAPL_CORES_ENERGY_STATUS;
919 case IDX_PP1_ENERGY:
920 return do_rapl & RAPL_GFX;
921 case IDX_PKG_PERF:
922 return do_rapl & RAPL_PKG_PERF_STATUS;
923 case IDX_DRAM_PERF:
924 return do_rapl & RAPL_DRAM_PERF_STATUS;
925 default:
926 return 0;
927 }
928}
1b439f01 929
388e9c81 930struct sys_counters {
678a3bd1
LB		 931 unsigned int added_thread_counters;
932 unsigned int added_core_counters;
933 unsigned int added_package_counters;
388e9c81
LB		 934 struct msr_counter *tp;
935 struct msr_counter *cp;
936 struct msr_counter *pp;
937} sys;
938
c98d5d94
LB		 939struct system_summary {
940 struct thread_data threads;
941 struct core_data cores;
942 struct pkg_data packages;
388e9c81 943} average;
c98d5d94 944
0e2d8f05
LB		 945struct cpu_topology {
946 int physical_package_id;
6de68fe1 947 int die_id;
0e2d8f05 948 int logical_cpu_id;
ef605741
PB		 949 int physical_node_id;
950 int logical_node_id; /* 0-based count within the package */
0e2d8f05 951 int physical_core_id;
8cb48b32 952 int thread_id;
1b439f01 953 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
0e2d8f05 954} *cpus;
c98d5d94
LB		 955
956struct topo_params {
957 int num_packages;
6de68fe1 958 int num_die;
c98d5d94
LB		 959 int num_cpus;
960 int num_cores;
961 int max_cpu_num;
ef605741 962 int max_node_num;
70a9c6e8
PB		 963 int nodes_per_pkg;
964 int cores_per_node;
965 int threads_per_core;
c98d5d94
LB		 966} topo;
967
968struct timeval tv_even, tv_odd, tv_delta;
969
1b439f01 970int *irq_column_2_cpu; /* /proc/interrupts column numbers */
562a2d37
LB		 971int *irqs_per_cpu; /* indexed by cpu_num */
972
c98d5d94
LB		 973void setup_all_buffers(void);
974
1f81c5ef
LB		 975char *sys_lpi_file;
976char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
977char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
978
c98d5d94 979int cpu_is_not_present(int cpu)
d15cf7c1 980{
c98d5d94 981 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
d15cf7c1 982}
1b439f01 983
88c3281f 984/*
c98d5d94
LB		 985 * run func(thread, core, package) in topology order
986 * skip non-present cpus
88c3281f 987 */
c98d5d94 988
1b439f01
LB		 989int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *),
990 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
88c3281f 991{
40f5cfe7 992 int retval, pkg_no, core_no, thread_no, node_no;
d15cf7c1 993
c98d5d94 994 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
df2f677d
LB		 995 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
996 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
1b439f01 997 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
40f5cfe7
PB		 998 struct thread_data *t;
999 struct core_data *c;
1000 struct pkg_data *p;
1001
1b439f01 1002 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
40f5cfe7
PB		 1003
1004 if (cpu_is_not_present(t->cpu_id))
1005 continue;
1006
1b439f01 1007 c = GET_CORE(core_base, core_no, node_no, pkg_no);
40f5cfe7
PB		 1008 p = GET_PKG(pkg_base, pkg_no);
1009
1010 retval = func(t, c, p);
1011 if (retval)
1012 return retval;
1013 }
c98d5d94
LB		 1014 }
1015 }
1016 }
1017 return 0;
88c3281f
LB		 1018}
1019
1020int cpu_migrate(int cpu)
1021{
c98d5d94
LB		 1022 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
1023 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
1024 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
88c3281f
LB		 1025 return -1;
1026 else
1027 return 0;
1028}
1b439f01 1029
36229897 1030int get_msr_fd(int cpu)
103a8fea 1031{
103a8fea
LB		 1032 char pathname[32];
1033 int fd;
1034
36229897
LB		 1035 fd = fd_percpu[cpu];
1036
1037 if (fd)
1038 return fd;
1039
103a8fea
LB		 1040 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
1041 fd = open(pathname, O_RDONLY);
15aaa346 1042 if (fd < 0)
98481e79 1043 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
103a8fea 1044
36229897
LB		 1045 fd_percpu[cpu] = fd;
1046
1047 return fd;
1048}
1049
2af4f9b8
LB		 1050static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
1051{
1052 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags);
1053}
1054
1055static int perf_instr_count_open(int cpu_num)
1056{
1057 struct perf_event_attr pea;
1058 int fd;
1059
1060 memset(&pea, 0, sizeof(struct perf_event_attr));
1061 pea.type = PERF_TYPE_HARDWARE;
1062 pea.size = sizeof(struct perf_event_attr);
1063 pea.config = PERF_COUNT_HW_INSTRUCTIONS;
1064
1065 /* counter for cpu_num, including user + kernel and all processes */
1066 fd = perf_event_open(&pea, -1, cpu_num, -1, 0);
164d7a96 1067 if (fd == -1) {
de7839ee 1068 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
164d7a96
LB		 1069 BIC_NOT_PRESENT(BIC_IPC);
1070 }
2af4f9b8
LB		 1071
1072 return fd;
1073}
1074
1075int get_instr_count_fd(int cpu)
1076{
1077 if (fd_instr_count_percpu[cpu])
1078 return fd_instr_count_percpu[cpu];
1079
1080 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu);
1081
1082 return fd_instr_count_percpu[cpu];
1083}
1084
36229897
LB		 1085int get_msr(int cpu, off_t offset, unsigned long long *msr)
1086{
1087 ssize_t retval;
1088
1089 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
15aaa346 1090
98481e79 1091 if (retval != sizeof *msr)
cf4cbe53 1092 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
15aaa346
LB		 1093
1094 return 0;
103a8fea
LB		 1095}
1096
dd778a5e 1097#define MAX_DEFERRED 16
0fc521bc 1098char *deferred_add_names[MAX_DEFERRED];
dd778a5e 1099char *deferred_skip_names[MAX_DEFERRED];
0fc521bc 1100int deferred_add_index;
dd778a5e
LB		 1101int deferred_skip_index;
1102
1103/*
1104 * HIDE_LIST - hide this list of counters, show the rest [default]
1105 * SHOW_LIST - show this list of counters, hide the rest
1106 */
1107enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
1108
1109void help(void)
1110{
1111 fprintf(outf,
1b439f01
LB		 1112 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
1113 "\n"
1114 "Turbostat forks the specified COMMAND and prints statistics\n"
1115 "when COMMAND completes.\n"
1116 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
1117 "to print statistics, until interrupted.\n"
1118 " -a, --add add a counter\n"
1119 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
1120 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
1121 " {core | package | j,k,l..m,n-p }\n"
1122 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
1123 " -D, --Dump displays the raw counter values\n"
1124 " -e, --enable [all | column]\n"
1125 " shows all or the specified disabled column\n"
1126 " -H, --hide [column|column,column,...]\n"
1127 " hide the specified column(s)\n"
1128 " -i, --interval sec.subsec\n"
1129 " Override default 5-second measurement interval\n"
1130 " -J, --Joules displays energy in Joules instead of Watts\n"
1131 " -l, --list list column headers only\n"
1132 " -n, --num_iterations num\n"
1133 " number of the measurement iterations\n"
c7e399f8
ZLCH		 1134 " -N, --header_iterations num\n"
1135 " print header every num iterations\n"
1b439f01
LB		 1136 " -o, --out file\n"
1137 " create or truncate \"file\" for all output\n"
1138 " -q, --quiet skip decoding system configuration header\n"
1139 " -s, --show [column|column,column,...]\n"
1140 " show only the specified column(s)\n"
1141 " -S, --Summary\n"
1142 " limits output to 1-line system summary per interval\n"
1143 " -T, --TCC temperature\n"
1144 " sets the Thermal Control Circuit temperature in\n"
1145 " degrees Celsius\n"
1146 " -h, --help print this help message\n"
1147 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n");
dd778a5e
LB		 1148}
1149
812db3f7
LB		 1150/*
1151 * bic_lookup
1152 * for all the strings in comma separate name_list,
1153 * set the approprate bit in return value.
1154 */
dd778a5e 1155unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
812db3f7 1156{
9878bf7a 1157 unsigned int i;
812db3f7
LB		 1158 unsigned long long retval = 0;
1159
1160 while (name_list) {
1161 char *comma;
1162
1163 comma = strchr(name_list, ',');
1164
1165 if (comma)
1166 *comma = '\0';
1167
1168 for (i = 0; i < MAX_BIC; ++i) {
1169 if (!strcmp(name_list, bic[i].name)) {
1170 retval |= (1ULL << i);
1171 break;
1172 }
5dc241f2
LB		 1173 if (!strcmp(name_list, "all")) {
1174 retval |= ~0;
1175 break;
1176 } else if (!strcmp(name_list, "topology")) {
1177 retval |= BIC_TOPOLOGY;
1178 break;
1179 } else if (!strcmp(name_list, "power")) {
1180 retval |= BIC_THERMAL_PWR;
1181 break;
1182 } else if (!strcmp(name_list, "idle")) {
1183 retval |= BIC_IDLE;
1184 break;
1185 } else if (!strcmp(name_list, "frequency")) {
1186 retval |= BIC_FREQUENCY;
1187 break;
1188 } else if (!strcmp(name_list, "other")) {
1189 retval |= BIC_OTHER;
1190 break;
1191 }
1192
812db3f7
LB		 1193 }
1194 if (i == MAX_BIC) {
dd778a5e 1195 if (mode == SHOW_LIST) {
0fc521bc
ZLCH		 1196 deferred_add_names[deferred_add_index++] = name_list;
1197 if (deferred_add_index >= MAX_DEFERRED) {
1198 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n",
164d7a96 1199 MAX_DEFERRED, name_list);
0fc521bc
ZLCH		 1200 help();
1201 exit(1);
1202 }
1203 } else {
1204 deferred_skip_names[deferred_skip_index++] = name_list;
1205 if (debug)
1206 fprintf(stderr, "deferred \"%s\"\n", name_list);
1207 if (deferred_skip_index >= MAX_DEFERRED) {
1208 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
164d7a96 1209 MAX_DEFERRED, name_list);
0fc521bc
ZLCH		 1210 help();
1211 exit(1);
1212 }
dd778a5e 1213 }
812db3f7
LB		 1214 }
1215
1216 name_list = comma;
1217 if (name_list)
1218 name_list++;
1219
1220 }
1221 return retval;
1222}
fc04cc67 1223
c8ade361 1224void print_header(char *delim)
103a8fea 1225{
388e9c81 1226 struct msr_counter *mp;
6168c2e0 1227 int printed = 0;
388e9c81 1228
3f44a5c6
LB		 1229 if (DO_BIC(BIC_USEC))
1230 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
1231 if (DO_BIC(BIC_TOD))
1232 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
812db3f7 1233 if (DO_BIC(BIC_Package))
6168c2e0 1234 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
6de68fe1
LB		 1235 if (DO_BIC(BIC_Die))
1236 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
01235041
PB		 1237 if (DO_BIC(BIC_Node))
1238 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
812db3f7 1239 if (DO_BIC(BIC_Core))
6168c2e0 1240 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
812db3f7 1241 if (DO_BIC(BIC_CPU))
6168c2e0 1242 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
4c2122d4
LB		 1243 if (DO_BIC(BIC_APIC))
1244 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
1245 if (DO_BIC(BIC_X2APIC))
1246 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
812db3f7 1247 if (DO_BIC(BIC_Avg_MHz))
6168c2e0 1248 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
812db3f7 1249 if (DO_BIC(BIC_Busy))
6168c2e0 1250 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
812db3f7 1251 if (DO_BIC(BIC_Bzy_MHz))
6168c2e0 1252 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
812db3f7 1253 if (DO_BIC(BIC_TSC_MHz))
6168c2e0 1254 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
1cc21f7b 1255
2af4f9b8
LB		 1256 if (DO_BIC(BIC_IPC))
1257 outp += sprintf(outp, "%sIPC", (printed++ ? delim : ""));
1258
0de6c0df
LB		 1259 if (DO_BIC(BIC_IRQ)) {
1260 if (sums_need_wide_columns)
6168c2e0 1261 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
0de6c0df 1262 else
6168c2e0 1263 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
0de6c0df
LB		 1264 }
1265
812db3f7 1266 if (DO_BIC(BIC_SMI))
6168c2e0 1267 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
1cc21f7b 1268
388e9c81 1269 for (mp = sys.tp; mp; mp = mp->next) {
dd778a5e 1270
388e9c81
LB		 1271 if (mp->format == FORMAT_RAW) {
1272 if (mp->width == 64)
dd778a5e 1273 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
388e9c81 1274 else
dd778a5e 1275 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
388e9c81 1276 } else {
0de6c0df 1277 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
dd778a5e 1278 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
0de6c0df 1279 else
dd778a5e 1280 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
388e9c81
LB		 1281 }
1282 }
1283
41618e63 1284 if (DO_BIC(BIC_CPU_c1))
6168c2e0 1285 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
562855ee 1286 if (DO_BIC(BIC_CPU_c3))
6168c2e0 1287 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
812db3f7 1288 if (DO_BIC(BIC_CPU_c6))
6168c2e0 1289 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
812db3f7 1290 if (DO_BIC(BIC_CPU_c7))
6168c2e0 1291 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
678a3bd1 1292
0539ba11 1293 if (DO_BIC(BIC_Mod_c6))
6168c2e0 1294 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
678a3bd1 1295
812db3f7 1296 if (DO_BIC(BIC_CoreTmp))
6168c2e0 1297 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
388e9c81 1298
eae97e05
CY		 1299 if (DO_BIC(BIC_CORE_THROT_CNT))
1300 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : ""));
1301
9392bd98
CW		 1302 if (do_rapl && !rapl_joules) {
1303 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1304 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
1305 } else if (do_rapl && rapl_joules) {
1306 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1307 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
1308 }
1309
388e9c81
LB		 1310 for (mp = sys.cp; mp; mp = mp->next) {
1311 if (mp->format == FORMAT_RAW) {
1312 if (mp->width == 64)
c8ade361 1313 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
388e9c81 1314 else
c8ade361 1315 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
388e9c81 1316 } else {
0de6c0df
LB		 1317 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1318 outp += sprintf(outp, "%s%8s", delim, mp->name);
1319 else
1320 outp += sprintf(outp, "%s%s", delim, mp->name);
388e9c81
LB		 1321 }
1322 }
1323
812db3f7 1324 if (DO_BIC(BIC_PkgTmp))
6168c2e0 1325 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
889facbe 1326
812db3f7 1327 if (DO_BIC(BIC_GFX_rc6))
6168c2e0 1328 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
fdf676e5 1329
812db3f7 1330 if (DO_BIC(BIC_GFXMHz))
6168c2e0 1331 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
27d47356 1332
b4b91569
RA		 1333 if (DO_BIC(BIC_GFXACTMHz))
1334 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : ""));
1335
a99d8730 1336 if (DO_BIC(BIC_Totl_c0))
6168c2e0 1337 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
a99d8730 1338 if (DO_BIC(BIC_Any_c0))
6168c2e0 1339 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
a99d8730 1340 if (DO_BIC(BIC_GFX_c0))
6168c2e0 1341 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
a99d8730 1342 if (DO_BIC(BIC_CPUGFX))
6168c2e0 1343 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
0b2bb692 1344
0f47c08d 1345 if (DO_BIC(BIC_Pkgpc2))
6168c2e0 1346 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
0f47c08d 1347 if (DO_BIC(BIC_Pkgpc3))
6168c2e0 1348 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
0f47c08d 1349 if (DO_BIC(BIC_Pkgpc6))
6168c2e0 1350 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
0f47c08d 1351 if (DO_BIC(BIC_Pkgpc7))
6168c2e0 1352 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
0f47c08d 1353 if (DO_BIC(BIC_Pkgpc8))
6168c2e0 1354 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
0f47c08d 1355 if (DO_BIC(BIC_Pkgpc9))
6168c2e0 1356 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
0f47c08d 1357 if (DO_BIC(BIC_Pkgpc10))
6168c2e0 1358 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
be0e54c4
LB		 1359 if (DO_BIC(BIC_CPU_LPI))
1360 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
1361 if (DO_BIC(BIC_SYS_LPI))
1362 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
103a8fea 1363
5c56be9a 1364 if (do_rapl && !rapl_joules) {
812db3f7 1365 if (DO_BIC(BIC_PkgWatt))
6168c2e0 1366 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
9392bd98 1367 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 1368 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
812db3f7 1369 if (DO_BIC(BIC_GFXWatt))
6168c2e0 1370 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
812db3f7 1371 if (DO_BIC(BIC_RAMWatt))
6168c2e0 1372 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
812db3f7 1373 if (DO_BIC(BIC_PKG__))
6168c2e0 1374 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
812db3f7 1375 if (DO_BIC(BIC_RAM__))
6168c2e0 1376 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
d7899447 1377 } else if (do_rapl && rapl_joules) {
812db3f7 1378 if (DO_BIC(BIC_Pkg_J))
6168c2e0 1379 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
9392bd98 1380 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 1381 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
812db3f7 1382 if (DO_BIC(BIC_GFX_J))
6168c2e0 1383 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
812db3f7 1384 if (DO_BIC(BIC_RAM_J))
6168c2e0 1385 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
812db3f7 1386 if (DO_BIC(BIC_PKG__))
6168c2e0 1387 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
812db3f7 1388 if (DO_BIC(BIC_RAM__))
6168c2e0 1389 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
5c56be9a 1390 }
a5c6d65d
LB		 1391 if (DO_BIC(BIC_UNCORE_MHZ))
1392 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : ""));
1393
388e9c81
LB		 1394 for (mp = sys.pp; mp; mp = mp->next) {
1395 if (mp->format == FORMAT_RAW) {
1396 if (mp->width == 64)
c8ade361 1397 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
388e9c81 1398 else
c8ade361 1399 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
388e9c81 1400 } else {
0de6c0df
LB		 1401 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1402 outp += sprintf(outp, "%s%8s", delim, mp->name);
1403 else
1404 outp += sprintf(outp, "%s%s", delim, mp->name);
388e9c81
LB		 1405 }
1406 }
1407
c98d5d94 1408 outp += sprintf(outp, "\n");
103a8fea
LB		 1409}
1410
1b439f01 1411int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1412{
388e9c81
LB		 1413 int i;
1414 struct msr_counter *mp;
1415
3b4d5c7f 1416 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
c98d5d94
LB		 1417
1418 if (t) {
1b439f01 1419 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags);
3b4d5c7f
AS		 1420 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
1421 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
1422 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
1423 outp += sprintf(outp, "c1: %016llX\n", t->c1);
6886fee4 1424
2af4f9b8
LB		 1425 if (DO_BIC(BIC_IPC))
1426 outp += sprintf(outp, "IPC: %lld\n", t->instr_count);
1427
812db3f7 1428 if (DO_BIC(BIC_IRQ))
0de6c0df 1429 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
812db3f7 1430 if (DO_BIC(BIC_SMI))
218f0e8d 1431 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
388e9c81
LB		 1432
1433 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1b439f01 1434 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]);
388e9c81 1435 }
c98d5d94 1436 }
103a8fea 1437
c98d5d94 1438 if (c) {
3b4d5c7f
AS		 1439 outp += sprintf(outp, "core: %d\n", c->core_id);
1440 outp += sprintf(outp, "c3: %016llX\n", c->c3);
1441 outp += sprintf(outp, "c6: %016llX\n", c->c6);
1442 outp += sprintf(outp, "c7: %016llX\n", c->c7);
1443 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
eae97e05 1444 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt);
9392bd98 1445 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
388e9c81
LB		 1446
1447 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1b439f01 1448 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]);
388e9c81 1449 }
0539ba11 1450 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
c98d5d94 1451 }
103a8fea 1452
c98d5d94 1453 if (p) {
3b4d5c7f 1454 outp += sprintf(outp, "package: %d\n", p->package_id);
0b2bb692
LB		 1455
1456 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
1457 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
1458 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
1459 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
1460
3b4d5c7f 1461 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
0f47c08d 1462 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1463 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
0f47c08d 1464 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1465 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
0f47c08d 1466 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1467 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
3b4d5c7f
AS		 1468 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
1469 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
1470 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
be0e54c4
LB		 1471 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
1472 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
7c2ccc50
CY		 1473 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg);
1474 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores);
1475 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx);
1476 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram);
1b439f01
LB		 1477 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status);
1478 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status);
3b4d5c7f 1479 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
388e9c81
LB		 1480
1481 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1b439f01 1482 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]);
388e9c81 1483 }
c98d5d94 1484 }
3b4d5c7f
AS		 1485
1486 outp += sprintf(outp, "\n");
1487
c98d5d94 1488 return 0;
103a8fea
LB		 1489}
1490
e23da037
LB		 1491/*
1492 * column formatting convention & formats
e23da037 1493 */
1b439f01 1494int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1495{
008d396e 1496 double interval_float, tsc;
fc04cc67 1497 char *fmt8;
388e9c81
LB		 1498 int i;
1499 struct msr_counter *mp;
6168c2e0
LB		 1500 char *delim = "\t";
1501 int printed = 0;
103a8fea 1502
1b439f01 1503 /* if showing only 1st thread in core and this isn't one, bail out */
c98d5d94
LB		 1504 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1505 return 0;
1506
1b439f01 1507 /* if showing only 1st thread in pkg and this isn't one, bail out */
c98d5d94
LB		 1508 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1509 return 0;
1510
1ef7d21a 1511 /*if not summary line and --cpu is used */
1b439f01 1512 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
1ef7d21a
LB		 1513 return 0;
1514
3f44a5c6 1515 if (DO_BIC(BIC_USEC)) {
f4fdf2b4
LB		 1516 /* on each row, print how many usec each timestamp took to gather */
1517 struct timeval tv;
1518
1519 timersub(&t->tv_end, &t->tv_begin, &tv);
1520 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
1521 }
1522
3f44a5c6
LB		 1523 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
1524 if (DO_BIC(BIC_TOD))
1525 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
1526
1b439f01 1527 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0;
103a8fea 1528
008d396e
LB		 1529 tsc = t->tsc * tsc_tweak;
1530
c98d5d94
LB		 1531 /* topo columns, print blanks on 1st (average) line */
1532 if (t == &average.threads) {
812db3f7 1533 if (DO_BIC(BIC_Package))
6168c2e0 1534 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
6de68fe1
LB		 1535 if (DO_BIC(BIC_Die))
1536 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
01235041
PB		 1537 if (DO_BIC(BIC_Node))
1538 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
812db3f7 1539 if (DO_BIC(BIC_Core))
6168c2e0 1540 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
812db3f7 1541 if (DO_BIC(BIC_CPU))
6168c2e0 1542 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
4c2122d4
LB		 1543 if (DO_BIC(BIC_APIC))
1544 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1545 if (DO_BIC(BIC_X2APIC))
1546 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
103a8fea 1547 } else {
812db3f7 1548 if (DO_BIC(BIC_Package)) {
c98d5d94 1549 if (p)
6168c2e0 1550 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
c98d5d94 1551 else
6168c2e0 1552 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
c98d5d94 1553 }
6de68fe1
LB		 1554 if (DO_BIC(BIC_Die)) {
1555 if (c)
1556 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
1557 else
1558 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1559 }
01235041
PB		 1560 if (DO_BIC(BIC_Node)) {
1561 if (t)
1562 outp += sprintf(outp, "%s%d",
1b439f01 1563 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id);
01235041 1564 else
1b439f01 1565 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
01235041 1566 }
812db3f7 1567 if (DO_BIC(BIC_Core)) {
c98d5d94 1568 if (c)
6168c2e0 1569 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
c98d5d94 1570 else
6168c2e0 1571 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
c98d5d94 1572 }
812db3f7 1573 if (DO_BIC(BIC_CPU))
6168c2e0 1574 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
4c2122d4
LB		 1575 if (DO_BIC(BIC_APIC))
1576 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
1577 if (DO_BIC(BIC_X2APIC))
1578 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
103a8fea 1579 }
fc04cc67 1580
812db3f7 1581 if (DO_BIC(BIC_Avg_MHz))
1b439f01 1582 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float);
fc04cc67 1583
812db3f7 1584 if (DO_BIC(BIC_Busy))
1b439f01 1585 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc);
103a8fea 1586
812db3f7 1587 if (DO_BIC(BIC_Bzy_MHz)) {
21ed5574 1588 if (has_base_hz)
1b439f01
LB		 1589 outp +=
1590 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
21ed5574 1591 else
6168c2e0 1592 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
1b439f01 1593 tsc / units * t->aperf / t->mperf / interval_float);
21ed5574 1594 }
103a8fea 1595
812db3f7 1596 if (DO_BIC(BIC_TSC_MHz))
1b439f01 1597 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float);
103a8fea 1598
2af4f9b8
LB		 1599 if (DO_BIC(BIC_IPC))
1600 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf);
1601
562a2d37 1602 /* IRQ */
0de6c0df
LB		 1603 if (DO_BIC(BIC_IRQ)) {
1604 if (sums_need_wide_columns)
6168c2e0 1605 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
0de6c0df 1606 else
6168c2e0 1607 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
0de6c0df 1608 }
562a2d37 1609
1cc21f7b 1610 /* SMI */
812db3f7 1611 if (DO_BIC(BIC_SMI))
6168c2e0 1612 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1cc21f7b 1613
678a3bd1 1614 /* Added counters */
388e9c81
LB		 1615 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1616 if (mp->format == FORMAT_RAW) {
1617 if (mp->width == 32)
1b439f01
LB		 1618 outp +=
1619 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]);
388e9c81 1620 else
6168c2e0 1621 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
388e9c81 1622 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1623 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1624 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
0de6c0df 1625 else
6168c2e0 1626 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
388e9c81 1627 } else if (mp->format == FORMAT_PERCENT) {
41618e63 1628 if (mp->type == COUNTER_USEC)
1b439f01
LB		 1629 outp +=
1630 sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1631 t->counter[i] / interval_float / 10000);
41618e63 1632 else
1b439f01 1633 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc);
388e9c81
LB		 1634 }
1635 }
1636
41618e63
LB		 1637 /* C1 */
1638 if (DO_BIC(BIC_CPU_c1))
1b439f01 1639 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc);
41618e63 1640
678a3bd1
LB		 1641 /* print per-core data only for 1st thread in core */
1642 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1643 goto done;
1644
562855ee 1645 if (DO_BIC(BIC_CPU_c3))
1b439f01 1646 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc);
812db3f7 1647 if (DO_BIC(BIC_CPU_c6))
1b439f01 1648 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc);
812db3f7 1649 if (DO_BIC(BIC_CPU_c7))
1b439f01 1650 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc);
678a3bd1 1651
0539ba11
LB		 1652 /* Mod%c6 */
1653 if (DO_BIC(BIC_Mod_c6))
6168c2e0 1654 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
0539ba11 1655
812db3f7 1656 if (DO_BIC(BIC_CoreTmp))
6168c2e0 1657 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
889facbe 1658
eae97e05
CY		 1659 /* Core throttle count */
1660 if (DO_BIC(BIC_CORE_THROT_CNT))
1661 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt);
1662
388e9c81
LB		 1663 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1664 if (mp->format == FORMAT_RAW) {
1665 if (mp->width == 32)
1b439f01
LB		 1666 outp +=
1667 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]);
388e9c81 1668 else
6168c2e0 1669 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
388e9c81 1670 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1671 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1672 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
0de6c0df 1673 else
6168c2e0 1674 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
388e9c81 1675 } else if (mp->format == FORMAT_PERCENT) {
1b439f01 1676 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc);
388e9c81
LB		 1677 }
1678 }
1679
9972d5d8 1680 fmt8 = "%s%.2f";
9392bd98
CW		 1681
1682 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1b439f01
LB		 1683 outp +=
1684 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
9392bd98
CW		 1685 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1686 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1687
c98d5d94
LB		 1688 /* print per-package data only for 1st core in package */
1689 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1690 goto done;
1691
0b2bb692 1692 /* PkgTmp */
812db3f7 1693 if (DO_BIC(BIC_PkgTmp))
6168c2e0 1694 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
889facbe 1695
fdf676e5 1696 /* GFXrc6 */
812db3f7 1697 if (DO_BIC(BIC_GFX_rc6)) {
ba3dec99 1698 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
6168c2e0 1699 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
9185e988 1700 } else {
6168c2e0 1701 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1b439f01 1702 p->gfx_rc6_ms / 10.0 / interval_float);
9185e988
LB		 1703 }
1704 }
fdf676e5 1705
27d47356 1706 /* GFXMHz */
812db3f7 1707 if (DO_BIC(BIC_GFXMHz))
6168c2e0 1708 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
27d47356 1709
b4b91569
RA		 1710 /* GFXACTMHz */
1711 if (DO_BIC(BIC_GFXACTMHz))
1712 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz);
1713
0b2bb692 1714 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
a99d8730 1715 if (DO_BIC(BIC_Totl_c0))
1b439f01 1716 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc);
a99d8730 1717 if (DO_BIC(BIC_Any_c0))
1b439f01 1718 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc);
a99d8730 1719 if (DO_BIC(BIC_GFX_c0))
1b439f01 1720 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc);
a99d8730 1721 if (DO_BIC(BIC_CPUGFX))
1b439f01 1722 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc);
0b2bb692 1723
0f47c08d 1724 if (DO_BIC(BIC_Pkgpc2))
1b439f01 1725 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc);
0f47c08d 1726 if (DO_BIC(BIC_Pkgpc3))
1b439f01 1727 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc);
0f47c08d 1728 if (DO_BIC(BIC_Pkgpc6))
1b439f01 1729 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc);
0f47c08d 1730 if (DO_BIC(BIC_Pkgpc7))
1b439f01 1731 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc);
0f47c08d 1732 if (DO_BIC(BIC_Pkgpc8))
1b439f01 1733 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc);
0f47c08d 1734 if (DO_BIC(BIC_Pkgpc9))
1b439f01 1735 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc);
0f47c08d 1736 if (DO_BIC(BIC_Pkgpc10))
1b439f01 1737 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc);
889facbe 1738
be0e54c4 1739 if (DO_BIC(BIC_CPU_LPI))
1b439f01
LB		 1740 outp +=
1741 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
be0e54c4 1742 if (DO_BIC(BIC_SYS_LPI))
1b439f01
LB		 1743 outp +=
1744 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
be0e54c4 1745
812db3f7 1746 if (DO_BIC(BIC_PkgWatt))
1b439f01
LB		 1747 outp +=
1748 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
eae97e05 1749
9392bd98 1750 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1b439f01
LB		 1751 outp +=
1752 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
812db3f7 1753 if (DO_BIC(BIC_GFXWatt))
1b439f01
LB		 1754 outp +=
1755 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
812db3f7 1756 if (DO_BIC(BIC_RAMWatt))
1b439f01
LB		 1757 outp +=
1758 sprintf(outp, fmt8, (printed++ ? delim : ""),
1759 p->energy_dram * rapl_dram_energy_units / interval_float);
812db3f7 1760 if (DO_BIC(BIC_Pkg_J))
6168c2e0 1761 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
9392bd98 1762 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 1763 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
812db3f7 1764 if (DO_BIC(BIC_GFX_J))
6168c2e0 1765 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
812db3f7 1766 if (DO_BIC(BIC_RAM_J))
6168c2e0 1767 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
812db3f7 1768 if (DO_BIC(BIC_PKG__))
1b439f01
LB		 1769 outp +=
1770 sprintf(outp, fmt8, (printed++ ? delim : ""),
1771 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
812db3f7 1772 if (DO_BIC(BIC_RAM__))
1b439f01
LB		 1773 outp +=
1774 sprintf(outp, fmt8, (printed++ ? delim : ""),
1775 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
a5c6d65d
LB		 1776 /* UncMHz */
1777 if (DO_BIC(BIC_UNCORE_MHZ))
1778 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz);
812db3f7 1779
388e9c81
LB		 1780 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1781 if (mp->format == FORMAT_RAW) {
1782 if (mp->width == 32)
1b439f01
LB		 1783 outp +=
1784 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]);
388e9c81 1785 else
6168c2e0 1786 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
388e9c81 1787 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1788 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1789 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
0de6c0df 1790 else
6168c2e0 1791 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
388e9c81 1792 } else if (mp->format == FORMAT_PERCENT) {
1b439f01 1793 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc);
388e9c81
LB		 1794 }
1795 }
1796
c98d5d94 1797done:
94d6ab4b
LB		 1798 if (*(outp - 1) != '\n')
1799 outp += sprintf(outp, "\n");
c98d5d94
LB		 1800
1801 return 0;
103a8fea
LB		 1802}
1803
b7d8c148 1804void flush_output_stdout(void)
c98d5d94 1805{
b7d8c148
LB		 1806 FILE *filep;
1807
1808 if (outf == stderr)
1809 filep = stdout;
1810 else
1811 filep = outf;
1812
1813 fputs(output_buffer, filep);
1814 fflush(filep);
1815
c98d5d94
LB		 1816 outp = output_buffer;
1817}
1b439f01 1818
b7d8c148 1819void flush_output_stderr(void)
c98d5d94 1820{
b7d8c148
LB		 1821 fputs(output_buffer, outf);
1822 fflush(outf);
c98d5d94
LB		 1823 outp = output_buffer;
1824}
1b439f01 1825
c98d5d94 1826void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1827{
c7e399f8 1828 static int count;
103a8fea 1829
c7e399f8 1830 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only)
c8ade361 1831 print_header("\t");
103a8fea 1832
9d83601a 1833 format_counters(&average.threads, &average.cores, &average.packages);
103a8fea 1834
c7e399f8 1835 count++;
e23da037
LB		 1836
1837 if (summary_only)
1838 return;
1839
c98d5d94 1840 for_all_cpus(format_counters, t, c, p);
103a8fea
LB		 1841}
1842
889facbe 1843#define DELTA_WRAP32(new, old) \
7c2ccc50 1844 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32);
889facbe 1845
1b439f01 1846int delta_package(struct pkg_data *new, struct pkg_data *old)
c98d5d94 1847{
388e9c81
LB		 1848 int i;
1849 struct msr_counter *mp;
0b2bb692 1850
a99d8730 1851 if (DO_BIC(BIC_Totl_c0))
0b2bb692 1852 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
a99d8730 1853 if (DO_BIC(BIC_Any_c0))
0b2bb692 1854 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
a99d8730 1855 if (DO_BIC(BIC_GFX_c0))
0b2bb692 1856 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
a99d8730 1857 if (DO_BIC(BIC_CPUGFX))
0b2bb692 1858 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
a99d8730 1859
c98d5d94 1860 old->pc2 = new->pc2 - old->pc2;
0f47c08d 1861 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1862 old->pc3 = new->pc3 - old->pc3;
0f47c08d 1863 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1864 old->pc6 = new->pc6 - old->pc6;
0f47c08d 1865 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1866 old->pc7 = new->pc7 - old->pc7;
ca58710f
KCA		 1867 old->pc8 = new->pc8 - old->pc8;
1868 old->pc9 = new->pc9 - old->pc9;
1869 old->pc10 = new->pc10 - old->pc10;
be0e54c4
LB		 1870 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
1871 old->sys_lpi = new->sys_lpi - old->sys_lpi;
889facbe
LB		 1872 old->pkg_temp_c = new->pkg_temp_c;
1873
9185e988 1874 /* flag an error when rc6 counter resets/wraps */
1b439f01 1875 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
9185e988
LB		 1876 old->gfx_rc6_ms = -1;
1877 else
1878 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1879
a5c6d65d 1880 old->uncore_mhz = new->uncore_mhz;
27d47356 1881 old->gfx_mhz = new->gfx_mhz;
b4b91569 1882 old->gfx_act_mhz = new->gfx_act_mhz;
27d47356 1883
87e15da9
CY		 1884 old->energy_pkg = new->energy_pkg - old->energy_pkg;
1885 old->energy_cores = new->energy_cores - old->energy_cores;
1886 old->energy_gfx = new->energy_gfx - old->energy_gfx;
1887 old->energy_dram = new->energy_dram - old->energy_dram;
1888 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status;
1889 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status;
ba3dec99 1890
388e9c81
LB		 1891 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1892 if (mp->format == FORMAT_RAW)
1893 old->counter[i] = new->counter[i];
1894 else
1895 old->counter[i] = new->counter[i] - old->counter[i];
1896 }
1897
ba3dec99 1898 return 0;
c98d5d94 1899}
103a8fea 1900
1b439f01 1901void delta_core(struct core_data *new, struct core_data *old)
103a8fea 1902{
388e9c81
LB		 1903 int i;
1904 struct msr_counter *mp;
1905
c98d5d94
LB		 1906 old->c3 = new->c3 - old->c3;
1907 old->c6 = new->c6 - old->c6;
1908 old->c7 = new->c7 - old->c7;
889facbe 1909 old->core_temp_c = new->core_temp_c;
eae97e05 1910 old->core_throt_cnt = new->core_throt_cnt;
0539ba11 1911 old->mc6_us = new->mc6_us - old->mc6_us;
388e9c81 1912
9392bd98
CW		 1913 DELTA_WRAP32(new->core_energy, old->core_energy);
1914
388e9c81
LB		 1915 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1916 if (mp->format == FORMAT_RAW)
1917 old->counter[i] = new->counter[i];
1918 else
1919 old->counter[i] = new->counter[i] - old->counter[i];
1920 }
c98d5d94 1921}
103a8fea 1922
1e9042b9
SP		 1923int soft_c1_residency_display(int bic)
1924{
1925 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr)
1926 return 0;
1927
1928 return DO_BIC_READ(bic);
1929}
1930
c3ae331d
LB		 1931/*
1932 * old = new - old
1933 */
1b439f01 1934int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta)
c98d5d94 1935{
388e9c81
LB		 1936 int i;
1937 struct msr_counter *mp;
1938
4c2122d4
LB		 1939 /* we run cpuid just the 1st time, copy the results */
1940 if (DO_BIC(BIC_APIC))
1941 new->apic_id = old->apic_id;
1942 if (DO_BIC(BIC_X2APIC))
1943 new->x2apic_id = old->x2apic_id;
1944
3f44a5c6
LB		 1945 /*
1946 * the timestamps from start of measurement interval are in "old"
1947 * the timestamp from end of measurement interval are in "new"
1948 * over-write old w/ new so we can print end of interval values
1949 */
1950
d4794f25 1951 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
3f44a5c6
LB		 1952 old->tv_begin = new->tv_begin;
1953 old->tv_end = new->tv_end;
1954
c98d5d94
LB		 1955 old->tsc = new->tsc - old->tsc;
1956
1957 /* check for TSC < 1 Mcycles over interval */
b2c95d90
JT		 1958 if (old->tsc < (1000 * 1000))
1959 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1960 "You can disable all c-states by booting with \"idle=poll\"\n"
1961 "or just the deep ones with \"processor.max_cstate=1\"");
103a8fea 1962
c98d5d94 1963 old->c1 = new->c1 - old->c1;
103a8fea 1964
1b439f01 1965 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
a729617c
LB		 1966 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1967 old->aperf = new->aperf - old->aperf;
1968 old->mperf = new->mperf - old->mperf;
1969 } else {
ba3dec99 1970 return -1;
103a8fea 1971 }
c98d5d94 1972 }
103a8fea 1973
144b44b1
LB		 1974 if (use_c1_residency_msr) {
1975 /*
1976 * Some models have a dedicated C1 residency MSR,
1977 * which should be more accurate than the derivation below.
1978 */
1979 } else {
1980 /*
1981 * As counter collection is not atomic,
1982 * it is possible for mperf's non-halted cycles + idle states
1983 * to exceed TSC's all cycles: show c1 = 0% in that case.
1984 */
95149369 1985 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
144b44b1
LB		 1986 old->c1 = 0;
1987 else {
1988 /* normal case, derive c1 */
008d396e 1989 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1b439f01 1990 - core_delta->c6 - core_delta->c7;
144b44b1 1991 }
c98d5d94 1992 }
c3ae331d 1993
c98d5d94 1994 if (old->mperf == 0) {
b7d8c148
LB		 1995 if (debug > 1)
1996 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
c98d5d94 1997 old->mperf = 1; /* divide by 0 protection */
103a8fea 1998 }
c98d5d94 1999
2af4f9b8
LB		 2000 if (DO_BIC(BIC_IPC))
2001 old->instr_count = new->instr_count - old->instr_count;
2002
812db3f7 2003 if (DO_BIC(BIC_IRQ))
562a2d37
LB		 2004 old->irq_count = new->irq_count - old->irq_count;
2005
812db3f7 2006 if (DO_BIC(BIC_SMI))
1ed51011 2007 old->smi_count = new->smi_count - old->smi_count;
ba3dec99 2008
388e9c81
LB		 2009 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2010 if (mp->format == FORMAT_RAW)
2011 old->counter[i] = new->counter[i];
2012 else
2013 old->counter[i] = new->counter[i] - old->counter[i];
2014 }
ba3dec99 2015 return 0;
c98d5d94
LB		 2016}
2017
2018int delta_cpu(struct thread_data *t, struct core_data *c,
1b439f01 2019 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2)
c98d5d94 2020{
ba3dec99
LB		 2021 int retval = 0;
2022
c98d5d94
LB		 2023 /* calculate core delta only for 1st thread in core */
2024 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
2025 delta_core(c, c2);
2026
2027 /* always calculate thread delta */
ba3dec99
LB		 2028 retval = delta_thread(t, t2, c2); /* c2 is core delta */
2029 if (retval)
2030 return retval;
c98d5d94
LB		 2031
2032 /* calculate package delta only for 1st core in package */
2033 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
ba3dec99 2034 retval = delta_package(p, p2);
c98d5d94 2035
ba3dec99 2036 return retval;
103a8fea
LB		 2037}
2038
c98d5d94
LB		 2039void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2040{
388e9c81 2041 int i;
1b439f01 2042 struct msr_counter *mp;
388e9c81 2043
3f44a5c6
LB		 2044 t->tv_begin.tv_sec = 0;
2045 t->tv_begin.tv_usec = 0;
2046 t->tv_end.tv_sec = 0;
2047 t->tv_end.tv_usec = 0;
d4794f25
YG		 2048 t->tv_delta.tv_sec = 0;
2049 t->tv_delta.tv_usec = 0;
3f44a5c6 2050
c98d5d94
LB		 2051 t->tsc = 0;
2052 t->aperf = 0;
2053 t->mperf = 0;
2054 t->c1 = 0;
2055
2af4f9b8
LB		 2056 t->instr_count = 0;
2057
562a2d37
LB		 2058 t->irq_count = 0;
2059 t->smi_count = 0;
2060
c98d5d94
LB		 2061 /* tells format_counters to dump all fields from this set */
2062 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
2063
2064 c->c3 = 0;
2065 c->c6 = 0;
2066 c->c7 = 0;
0539ba11 2067 c->mc6_us = 0;
889facbe 2068 c->core_temp_c = 0;
9392bd98 2069 c->core_energy = 0;
eae97e05 2070 c->core_throt_cnt = 0;
c98d5d94 2071
0b2bb692
LB		 2072 p->pkg_wtd_core_c0 = 0;
2073 p->pkg_any_core_c0 = 0;
2074 p->pkg_any_gfxe_c0 = 0;
2075 p->pkg_both_core_gfxe_c0 = 0;
2076
c98d5d94 2077 p->pc2 = 0;
0f47c08d 2078 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 2079 p->pc3 = 0;
0f47c08d 2080 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 2081 p->pc6 = 0;
0f47c08d 2082 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 2083 p->pc7 = 0;
ca58710f
KCA		 2084 p->pc8 = 0;
2085 p->pc9 = 0;
2086 p->pc10 = 0;
be0e54c4
LB		 2087 p->cpu_lpi = 0;
2088 p->sys_lpi = 0;
889facbe
LB		 2089
2090 p->energy_pkg = 0;
2091 p->energy_dram = 0;
2092 p->energy_cores = 0;
2093 p->energy_gfx = 0;
2094 p->rapl_pkg_perf_status = 0;
2095 p->rapl_dram_perf_status = 0;
2096 p->pkg_temp_c = 0;
27d47356 2097
fdf676e5 2098 p->gfx_rc6_ms = 0;
a5c6d65d 2099 p->uncore_mhz = 0;
27d47356 2100 p->gfx_mhz = 0;
b4b91569 2101 p->gfx_act_mhz = 0;
388e9c81
LB		 2102 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
2103 t->counter[i] = 0;
2104
2105 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
2106 c->counter[i] = 0;
2107
2108 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
2109 p->counter[i] = 0;
c98d5d94 2110}
1b439f01
LB		 2111
2112int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 2113{
388e9c81
LB		 2114 int i;
2115 struct msr_counter *mp;
2116
4c2122d4
LB		 2117 /* copy un-changing apic_id's */
2118 if (DO_BIC(BIC_APIC))
2119 average.threads.apic_id = t->apic_id;
2120 if (DO_BIC(BIC_X2APIC))
2121 average.threads.x2apic_id = t->x2apic_id;
2122
3f44a5c6
LB		 2123 /* remember first tv_begin */
2124 if (average.threads.tv_begin.tv_sec == 0)
2125 average.threads.tv_begin = t->tv_begin;
2126
2127 /* remember last tv_end */
2128 average.threads.tv_end = t->tv_end;
2129
c98d5d94
LB		 2130 average.threads.tsc += t->tsc;
2131 average.threads.aperf += t->aperf;
2132 average.threads.mperf += t->mperf;
2133 average.threads.c1 += t->c1;
103a8fea 2134
2af4f9b8
LB		 2135 average.threads.instr_count += t->instr_count;
2136
562a2d37
LB		 2137 average.threads.irq_count += t->irq_count;
2138 average.threads.smi_count += t->smi_count;
2139
388e9c81
LB		 2140 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2141 if (mp->format == FORMAT_RAW)
2142 continue;
2143 average.threads.counter[i] += t->counter[i];
2144 }
2145
c98d5d94
LB		 2146 /* sum per-core values only for 1st thread in core */
2147 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2148 return 0;
103a8fea 2149
c98d5d94
LB		 2150 average.cores.c3 += c->c3;
2151 average.cores.c6 += c->c6;
2152 average.cores.c7 += c->c7;
0539ba11 2153 average.cores.mc6_us += c->mc6_us;
c98d5d94 2154
889facbe 2155 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
eae97e05 2156 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt);
889facbe 2157
9392bd98
CW		 2158 average.cores.core_energy += c->core_energy;
2159
388e9c81
LB		 2160 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2161 if (mp->format == FORMAT_RAW)
2162 continue;
2163 average.cores.counter[i] += c->counter[i];
2164 }
2165
c98d5d94
LB		 2166 /* sum per-pkg values only for 1st core in pkg */
2167 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2168 return 0;
2169
a99d8730 2170 if (DO_BIC(BIC_Totl_c0))
0b2bb692 2171 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
a99d8730 2172 if (DO_BIC(BIC_Any_c0))
0b2bb692 2173 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
a99d8730 2174 if (DO_BIC(BIC_GFX_c0))
0b2bb692 2175 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
a99d8730 2176 if (DO_BIC(BIC_CPUGFX))
0b2bb692 2177 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
0b2bb692 2178
c98d5d94 2179 average.packages.pc2 += p->pc2;
0f47c08d 2180 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 2181 average.packages.pc3 += p->pc3;
0f47c08d 2182 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 2183 average.packages.pc6 += p->pc6;
0f47c08d 2184 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 2185 average.packages.pc7 += p->pc7;
ca58710f
KCA		 2186 average.packages.pc8 += p->pc8;
2187 average.packages.pc9 += p->pc9;
2188 average.packages.pc10 += p->pc10;
c98d5d94 2189
be0e54c4
LB		 2190 average.packages.cpu_lpi = p->cpu_lpi;
2191 average.packages.sys_lpi = p->sys_lpi;
2192
889facbe
LB		 2193 average.packages.energy_pkg += p->energy_pkg;
2194 average.packages.energy_dram += p->energy_dram;
2195 average.packages.energy_cores += p->energy_cores;
2196 average.packages.energy_gfx += p->energy_gfx;
2197
fdf676e5 2198 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
a5c6d65d 2199 average.packages.uncore_mhz = p->uncore_mhz;
27d47356 2200 average.packages.gfx_mhz = p->gfx_mhz;
b4b91569 2201 average.packages.gfx_act_mhz = p->gfx_act_mhz;
27d47356 2202
889facbe
LB		 2203 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
2204
2205 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
2206 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
388e9c81
LB		 2207
2208 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2209 if (mp->format == FORMAT_RAW)
2210 continue;
2211 average.packages.counter[i] += p->counter[i];
2212 }
c98d5d94
LB		 2213 return 0;
2214}
1b439f01 2215
c98d5d94
LB		 2216/*
2217 * sum the counters for all cpus in the system
2218 * compute the weighted average
2219 */
1b439f01 2220void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p)
c98d5d94 2221{
388e9c81
LB		 2222 int i;
2223 struct msr_counter *mp;
2224
c98d5d94
LB		 2225 clear_counters(&average.threads, &average.cores, &average.packages);
2226
2227 for_all_cpus(sum_counters, t, c, p);
2228
d4794f25
YG		 2229 /* Use the global time delta for the average. */
2230 average.threads.tv_delta = tv_delta;
2231
c98d5d94
LB		 2232 average.threads.tsc /= topo.num_cpus;
2233 average.threads.aperf /= topo.num_cpus;
2234 average.threads.mperf /= topo.num_cpus;
2af4f9b8 2235 average.threads.instr_count /= topo.num_cpus;
c98d5d94
LB		 2236 average.threads.c1 /= topo.num_cpus;
2237
0de6c0df
LB		 2238 if (average.threads.irq_count > 9999999)
2239 sums_need_wide_columns = 1;
2240
c98d5d94
LB		 2241 average.cores.c3 /= topo.num_cores;
2242 average.cores.c6 /= topo.num_cores;
2243 average.cores.c7 /= topo.num_cores;
0539ba11 2244 average.cores.mc6_us /= topo.num_cores;
c98d5d94 2245
a99d8730 2246 if (DO_BIC(BIC_Totl_c0))
0b2bb692 2247 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
a99d8730 2248 if (DO_BIC(BIC_Any_c0))
0b2bb692 2249 average.packages.pkg_any_core_c0 /= topo.num_packages;
a99d8730 2250 if (DO_BIC(BIC_GFX_c0))
0b2bb692 2251 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
a99d8730 2252 if (DO_BIC(BIC_CPUGFX))
0b2bb692 2253 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
0b2bb692 2254
c98d5d94 2255 average.packages.pc2 /= topo.num_packages;
0f47c08d 2256 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 2257 average.packages.pc3 /= topo.num_packages;
0f47c08d 2258 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 2259 average.packages.pc6 /= topo.num_packages;
0f47c08d 2260 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 2261 average.packages.pc7 /= topo.num_packages;
ca58710f
KCA		 2262
2263 average.packages.pc8 /= topo.num_packages;
2264 average.packages.pc9 /= topo.num_packages;
2265 average.packages.pc10 /= topo.num_packages;
388e9c81
LB		 2266
2267 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2268 if (mp->format == FORMAT_RAW)
2269 continue;
0de6c0df
LB		 2270 if (mp->type == COUNTER_ITEMS) {
2271 if (average.threads.counter[i] > 9999999)
2272 sums_need_wide_columns = 1;
41618e63 2273 continue;
0de6c0df 2274 }
388e9c81
LB		 2275 average.threads.counter[i] /= topo.num_cpus;
2276 }
2277 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2278 if (mp->format == FORMAT_RAW)
2279 continue;
0de6c0df
LB		 2280 if (mp->type == COUNTER_ITEMS) {
2281 if (average.cores.counter[i] > 9999999)
2282 sums_need_wide_columns = 1;
2283 }
388e9c81
LB		 2284 average.cores.counter[i] /= topo.num_cores;
2285 }
2286 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2287 if (mp->format == FORMAT_RAW)
2288 continue;
0de6c0df
LB		 2289 if (mp->type == COUNTER_ITEMS) {
2290 if (average.packages.counter[i] > 9999999)
2291 sums_need_wide_columns = 1;
2292 }
388e9c81
LB		 2293 average.packages.counter[i] /= topo.num_packages;
2294 }
103a8fea
LB		 2295}
2296
c98d5d94 2297static unsigned long long rdtsc(void)
103a8fea 2298{
c98d5d94 2299 unsigned int low, high;
15aaa346 2300
1b439f01 2301 asm volatile ("rdtsc":"=a" (low), "=d"(high));
15aaa346 2302
c98d5d94
LB		 2303 return low | ((unsigned long long)high) << 32;
2304}
15aaa346 2305
495c7654
LB		 2306/*
2307 * Open a file, and exit on failure
2308 */
2309FILE *fopen_or_die(const char *path, const char *mode)
2310{
2311 FILE *filep = fopen(path, mode);
2312
2313 if (!filep)
2314 err(1, "%s: open failed", path);
2315 return filep;
2316}
1b439f01 2317
495c7654
LB		 2318/*
2319 * snapshot_sysfs_counter()
2320 *
2321 * return snapshot of given counter
2322 */
2323unsigned long long snapshot_sysfs_counter(char *path)
2324{
2325 FILE *fp;
2326 int retval;
2327 unsigned long long counter;
2328
2329 fp = fopen_or_die(path, "r");
2330
2331 retval = fscanf(fp, "%lld", &counter);
2332 if (retval != 1)
2333 err(1, "snapshot_sysfs_counter(%s)", path);
2334
2335 fclose(fp);
2336
2337 return counter;
2338}
2339
2340int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
2341{
2342 if (mp->msr_num != 0) {
2343 if (get_msr(cpu, mp->msr_num, counterp))
2344 return -1;
2345 } else {
46c27978 2346 char path[128 + PATH_BYTES];
41618e63
LB		 2347
2348 if (mp->flags & SYSFS_PERCPU) {
1b439f01 2349 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path);
41618e63
LB		 2350
2351 *counterp = snapshot_sysfs_counter(path);
2352 } else {
2353 *counterp = snapshot_sysfs_counter(mp->path);
2354 }
495c7654
LB		 2355 }
2356
2357 return 0;
2358}
2359
a5c6d65d
LB		 2360unsigned long long get_uncore_mhz(int package, int die)
2361{
2362 char path[128];
2363
2364 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package,
2365 die);
2366
2367 return (snapshot_sysfs_counter(path) / 1000);
2368}
2369
6d6501d9
BP		 2370int get_epb(int cpu)
2371{
2372 char path[128 + PATH_BYTES];
7f1b11ba 2373 unsigned long long msr;
6d6501d9
BP		 2374 int ret, epb = -1;
2375 FILE *fp;
2376
2377 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu);
2378
7f1b11ba
BP		 2379 fp = fopen(path, "r");
2380 if (!fp)
2381 goto msr_fallback;
6d6501d9
BP		 2382
2383 ret = fscanf(fp, "%d", &epb);
2384 if (ret != 1)
2385 err(1, "%s(%s)", __func__, path);
2386
2387 fclose(fp);
2388
2389 return epb;
7f1b11ba
BP		 2390
2391msr_fallback:
2392 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
2393
2394 return msr & 0xf;
6d6501d9
BP		 2395}
2396
4c2122d4
LB		 2397void get_apic_id(struct thread_data *t)
2398{
34041551 2399 unsigned int eax, ebx, ecx, edx;
4c2122d4 2400
34041551
LB		 2401 if (DO_BIC(BIC_APIC)) {
2402 eax = ebx = ecx = edx = 0;
2403 __cpuid(1, eax, ebx, ecx, edx);
4c2122d4 2404
34041551
LB		 2405 t->apic_id = (ebx >> 24) & 0xff;
2406 }
2407
2408 if (!DO_BIC(BIC_X2APIC))
4c2122d4
LB		 2409 return;
2410
c1c10cc7 2411 if (authentic_amd || hygon_genuine) {
34041551 2412 unsigned int topology_extensions;
4c2122d4 2413
34041551
LB		 2414 if (max_extended_level < 0x8000001e)
2415 return;
4c2122d4 2416
34041551
LB		 2417 eax = ebx = ecx = edx = 0;
2418 __cpuid(0x80000001, eax, ebx, ecx, edx);
1b439f01 2419 topology_extensions = ecx & (1 << 22);
34041551
LB		 2420
2421 if (topology_extensions == 0)
2422 return;
2423
2424 eax = ebx = ecx = edx = 0;
2425 __cpuid(0x8000001e, eax, ebx, ecx, edx);
2426
2427 t->x2apic_id = eax;
4c2122d4 2428 return;
34041551 2429 }
4c2122d4 2430
34041551
LB		 2431 if (!genuine_intel)
2432 return;
2433
2434 if (max_level < 0xb)
4c2122d4
LB		 2435 return;
2436
2437 ecx = 0;
2438 __cpuid(0xb, eax, ebx, ecx, edx);
2439 t->x2apic_id = edx;
2440
34041551 2441 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
1b439f01 2442 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id);
4c2122d4
LB		 2443}
2444
eae97e05
CY		 2445int get_core_throt_cnt(int cpu, unsigned long long *cnt)
2446{
2447 char path[128 + PATH_BYTES];
2448 unsigned long long tmp;
2449 FILE *fp;
2450 int ret;
2451
2452 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu);
2453 fp = fopen(path, "r");
2454 if (!fp)
2455 return -1;
2456 ret = fscanf(fp, "%lld", &tmp);
5e5fd36c 2457 fclose(fp);
eae97e05
CY		 2458 if (ret != 1)
2459 return -1;
eae97e05
CY		 2460 *cnt = tmp;
2461
2462 return 0;
2463}
2464
c98d5d94
LB		 2465/*
2466 * get_counters(...)
2467 * migrate to cpu
2468 * acquire and record local counters for that cpu
2469 */
2470int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2471{
2472 int cpu = t->cpu_id;
889facbe 2473 unsigned long long msr;
0102b067 2474 int aperf_mperf_retry_count = 0;
388e9c81
LB		 2475 struct msr_counter *mp;
2476 int i;
88c3281f 2477
e52966c0 2478 if (cpu_migrate(cpu)) {
3d7772ea 2479 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu);
c98d5d94 2480 return -1;
e52966c0 2481 }
15aaa346 2482
d4794f25
YG		 2483 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
2484
4c2122d4
LB		 2485 if (first_counter_read)
2486 get_apic_id(t);
0102b067 2487retry:
c98d5d94
LB		 2488 t->tsc = rdtsc(); /* we are running on local CPU of interest */
2489
1b439f01 2490 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
0102b067
LB		 2491 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
2492
2493 /*
2494 * The TSC, APERF and MPERF must be read together for
2495 * APERF/MPERF and MPERF/TSC to give accurate results.
2496 *
2497 * Unfortunately, APERF and MPERF are read by
2498 * individual system call, so delays may occur
2499 * between them. If the time to read them
2500 * varies by a large amount, we re-read them.
2501 */
2502
2503 /*
2504 * This initial dummy APERF read has been seen to
2505 * reduce jitter in the subsequent reads.
2506 */
2507
2508 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2509 return -3;
2510
2511 t->tsc = rdtsc(); /* re-read close to APERF */
2512
2513 tsc_before = t->tsc;
2514
9c63a650 2515 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
c98d5d94 2516 return -3;
0102b067
LB		 2517
2518 tsc_between = rdtsc();
2519
9c63a650 2520 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
c98d5d94 2521 return -4;
0102b067
LB		 2522
2523 tsc_after = rdtsc();
2524
2525 aperf_time = tsc_between - tsc_before;
2526 mperf_time = tsc_after - tsc_between;
2527
2528 /*
2529 * If the system call latency to read APERF and MPERF
2530 * differ by more than 2x, then try again.
2531 */
2532 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
2533 aperf_mperf_retry_count++;
2534 if (aperf_mperf_retry_count < 5)
2535 goto retry;
2536 else
1b439f01 2537 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time);
0102b067
LB		 2538 }
2539 aperf_mperf_retry_count = 0;
2540
b2b34dfe
HC		 2541 t->aperf = t->aperf * aperf_mperf_multiplier;
2542 t->mperf = t->mperf * aperf_mperf_multiplier;
c98d5d94
LB		 2543 }
2544
2af4f9b8
LB		 2545 if (DO_BIC(BIC_IPC))
2546 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long))
2547 return -4;
2548
812db3f7 2549 if (DO_BIC(BIC_IRQ))
562a2d37 2550 t->irq_count = irqs_per_cpu[cpu];
812db3f7 2551 if (DO_BIC(BIC_SMI)) {
1ed51011
LB		 2552 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
2553 return -5;
2554 t->smi_count = msr & 0xFFFFFFFF;
2555 }
0539ba11 2556 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
144b44b1
LB		 2557 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
2558 return -6;
2559 }
2560
388e9c81 2561 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
495c7654 2562 if (get_mp(cpu, mp, &t->counter[i]))
388e9c81
LB		 2563 return -10;
2564 }
2565
c98d5d94
LB		 2566 /* collect core counters only for 1st thread in core */
2567 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
f4fdf2b4 2568 goto done;
c98d5d94 2569
1e9042b9 2570 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
c98d5d94
LB		 2571 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
2572 return -6;
144b44b1
LB		 2573 }
2574
1e9042b9 2575 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) {
c98d5d94
LB		 2576 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
2577 return -7;
137f01b3 2578 } else if (do_knl_cstates && soft_c1_residency_display(BIC_CPU_c6)) {
fb5d4327
DC		 2579 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
2580 return -7;
c98d5d94
LB		 2581 }
2582
7ab5ff49 2583 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) {
c98d5d94
LB		 2584 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
2585 return -8;
7ab5ff49
ZR		 2586 else if (t->is_atom) {
2587 /*
2588 * For Atom CPUs that has core cstate deeper than c6,
2589 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper.
2590 * Minus CC7 (and deeper cstates) residency to get
2591 * accturate cc6 residency.
2592 */
2593 c->c6 -= c->c7;
2594 }
2595 }
c98d5d94 2596
0539ba11
LB		 2597 if (DO_BIC(BIC_Mod_c6))
2598 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
2599 return -8;
2600
812db3f7 2601 if (DO_BIC(BIC_CoreTmp)) {
889facbe
LB		 2602 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2603 return -9;
55279aef 2604 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F);
889facbe
LB		 2605 }
2606
eae97e05
CY		 2607 if (DO_BIC(BIC_CORE_THROT_CNT))
2608 get_core_throt_cnt(cpu, &c->core_throt_cnt);
2609
9392bd98
CW		 2610 if (do_rapl & RAPL_AMD_F17H) {
2611 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
2612 return -14;
2613 c->core_energy = msr & 0xFFFFFFFF;
2614 }
2615
388e9c81 2616 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
495c7654 2617 if (get_mp(cpu, mp, &c->counter[i]))
388e9c81
LB		 2618 return -10;
2619 }
889facbe 2620
c98d5d94
LB		 2621 /* collect package counters only for 1st core in package */
2622 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
f4fdf2b4 2623 goto done;
c98d5d94 2624
a99d8730 2625 if (DO_BIC(BIC_Totl_c0)) {
0b2bb692
LB		 2626 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
2627 return -10;
a99d8730
LB		 2628 }
2629 if (DO_BIC(BIC_Any_c0)) {
0b2bb692
LB		 2630 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
2631 return -11;
a99d8730
LB		 2632 }
2633 if (DO_BIC(BIC_GFX_c0)) {
0b2bb692
LB		 2634 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
2635 return -12;
a99d8730
LB		 2636 }
2637 if (DO_BIC(BIC_CPUGFX)) {
0b2bb692
LB		 2638 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
2639 return -13;
2640 }
0f47c08d 2641 if (DO_BIC(BIC_Pkgpc3))
c98d5d94
LB		 2642 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
2643 return -9;
0f47c08d 2644 if (DO_BIC(BIC_Pkgpc6)) {
0539ba11
LB		 2645 if (do_slm_cstates) {
2646 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
2647 return -10;
2648 } else {
2649 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
2650 return -10;
2651 }
2652 }
2653
0f47c08d 2654 if (DO_BIC(BIC_Pkgpc2))
c98d5d94
LB		 2655 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
2656 return -11;
0f47c08d 2657 if (DO_BIC(BIC_Pkgpc7))
c98d5d94
LB		 2658 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
2659 return -12;
0f47c08d 2660 if (DO_BIC(BIC_Pkgpc8))
ca58710f
KCA		 2661 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
2662 return -13;
0f47c08d 2663 if (DO_BIC(BIC_Pkgpc9))
ca58710f
KCA		 2664 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
2665 return -13;
0f47c08d 2666 if (DO_BIC(BIC_Pkgpc10))
ca58710f
KCA		 2667 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
2668 return -13;
0f47c08d 2669
be0e54c4
LB		 2670 if (DO_BIC(BIC_CPU_LPI))
2671 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
2672 if (DO_BIC(BIC_SYS_LPI))
2673 p->sys_lpi = cpuidle_cur_sys_lpi_us;
2674
889facbe 2675 if (do_rapl & RAPL_PKG) {
9972d5d8 2676 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr))
889facbe 2677 return -13;
9972d5d8 2678 p->energy_pkg = msr;
889facbe 2679 }
9148494c 2680 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
9972d5d8 2681 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr))
889facbe 2682 return -14;
9972d5d8 2683 p->energy_cores = msr;
889facbe
LB		 2684 }
2685 if (do_rapl & RAPL_DRAM) {
9972d5d8 2686 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
889facbe 2687 return -15;
9972d5d8 2688 p->energy_dram = msr;
889facbe
LB		 2689 }
2690 if (do_rapl & RAPL_GFX) {
9972d5d8 2691 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr))
889facbe 2692 return -16;
9972d5d8 2693 p->energy_gfx = msr;
889facbe
LB		 2694 }
2695 if (do_rapl & RAPL_PKG_PERF_STATUS) {
9972d5d8 2696 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr))
889facbe 2697 return -16;
9972d5d8 2698 p->rapl_pkg_perf_status = msr;
889facbe
LB		 2699 }
2700 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
9972d5d8 2701 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr))
889facbe 2702 return -16;
9972d5d8 2703 p->rapl_dram_perf_status = msr;
889facbe 2704 }
3316f99a 2705 if (do_rapl & RAPL_AMD_F17H) {
9972d5d8 2706 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr))
3316f99a 2707 return -13;
9972d5d8 2708 p->energy_pkg = msr;
3316f99a 2709 }
812db3f7 2710 if (DO_BIC(BIC_PkgTmp)) {
889facbe
LB		 2711 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2712 return -17;
55279aef 2713 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F);
889facbe 2714 }
fdf676e5 2715
812db3f7 2716 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 2717 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2718
a5c6d65d
LB		 2719 /* n.b. assume die0 uncore frequency applies to whole package */
2720 if (DO_BIC(BIC_UNCORE_MHZ))
2721 p->uncore_mhz = get_uncore_mhz(p->package_id, 0);
2722
812db3f7 2723 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 2724 p->gfx_mhz = gfx_cur_mhz;
2725
b4b91569
RA		 2726 if (DO_BIC(BIC_GFXACTMHz))
2727 p->gfx_act_mhz = gfx_act_mhz;
2728
388e9c81 2729 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
495c7654 2730 if (get_mp(cpu, mp, &p->counter[i]))
388e9c81
LB		 2731 return -10;
2732 }
f4fdf2b4
LB		 2733done:
2734 gettimeofday(&t->tv_end, (struct timezone *)NULL);
388e9c81 2735
15aaa346 2736 return 0;
103a8fea
LB		 2737}
2738
ee7e38e3
LB		 2739/*
2740 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2741 * If you change the values, note they are used both in comparisons
2742 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2743 */
2744
1b439f01
LB		 2745#define PCLUKN 0 /* Unknown */
2746#define PCLRSV 1 /* Reserved */
2747#define PCL__0 2 /* PC0 */
2748#define PCL__1 3 /* PC1 */
2749#define PCL__2 4 /* PC2 */
2750#define PCL__3 5 /* PC3 */
2751#define PCL__4 6 /* PC4 */
2752#define PCL__6 7 /* PC6 */
2753#define PCL_6N 8 /* PC6 No Retention */
2754#define PCL_6R 9 /* PC6 Retention */
2755#define PCL__7 10 /* PC7 */
2756#define PCL_7S 11 /* PC7 Shrink */
2757#define PCL__8 12 /* PC8 */
2758#define PCL__9 13 /* PC9 */
2759#define PCL_10 14 /* PC10 */
2760#define PCLUNL 15 /* Unlimited */
ee7e38e3
LB		 2761
2762int pkg_cstate_limit = PCLUKN;
2763char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1b439f01
LB		 2764 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"
2765};
a2b7b749 2766
1b439f01
LB		 2767int nhm_pkg_cstate_limits[16] =
2768 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2769 PCLRSV, PCLRSV
2770};
2771
1b439f01
LB		 2772int snb_pkg_cstate_limits[16] =
2773 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2774 PCLRSV, PCLRSV
2775};
2776
1b439f01
LB		 2777int hsw_pkg_cstate_limits[16] =
2778 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2779 PCLRSV, PCLRSV
2780};
2781
1b439f01
LB		 2782int slv_pkg_cstate_limits[16] =
2783 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2784 PCL__6, PCL__7
2785};
2786
1b439f01
LB		 2787int amt_pkg_cstate_limits[16] =
2788 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2789 PCLRSV, PCLRSV
2790};
2791
1b439f01
LB		 2792int phi_pkg_cstate_limits[16] =
2793 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2794 PCLRSV, PCLRSV
2795};
2796
1b439f01
LB		 2797int glm_pkg_cstate_limits[16] =
2798 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2799 PCLRSV, PCLRSV
2800};
2801
1b439f01
LB		 2802int skx_pkg_cstate_limits[16] =
2803 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2804 PCLRSV, PCLRSV
2805};
2806
1b439f01 2807int icx_pkg_cstate_limits[16] =
a1b6f487 2808 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2809 PCLRSV, PCLRSV
2810};
1b439f01 2811
3989fc89
ZR		 2812void probe_cst_limit(void)
2813{
2814 unsigned long long msr;
2815 int *pkg_cstate_limits;
2816
fcfa1ce0 2817 if (!platform->has_nhm_msrs)
3989fc89
ZR		 2818 return;
2819
2820 switch (platform->cst_limit) {
2821 case CST_LIMIT_NHM:
2822 pkg_cstate_limits = nhm_pkg_cstate_limits;
2823 break;
2824 case CST_LIMIT_SNB:
2825 pkg_cstate_limits = snb_pkg_cstate_limits;
2826 break;
2827 case CST_LIMIT_HSW:
2828 pkg_cstate_limits = hsw_pkg_cstate_limits;
2829 break;
2830 case CST_LIMIT_SKX:
2831 pkg_cstate_limits = skx_pkg_cstate_limits;
2832 break;
2833 case CST_LIMIT_ICX:
2834 pkg_cstate_limits = icx_pkg_cstate_limits;
2835 break;
2836 case CST_LIMIT_SLV:
2837 pkg_cstate_limits = slv_pkg_cstate_limits;
2838 break;
2839 case CST_LIMIT_AMT:
2840 pkg_cstate_limits = amt_pkg_cstate_limits;
2841 break;
2842 case CST_LIMIT_KNL:
2843 pkg_cstate_limits = phi_pkg_cstate_limits;
2844 break;
2845 case CST_LIMIT_GMT:
2846 pkg_cstate_limits = glm_pkg_cstate_limits;
2847 break;
2848 default:
2849 return;
2850 }
2851
2852 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2853 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2854}
2855
1b439f01 2856static void calculate_tsc_tweak()
a2b7b749 2857{
a2b7b749
LB		 2858 tsc_tweak = base_hz / tsc_hz;
2859}
2860
aeb01e6d
CY		 2861void prewake_cstate_probe(unsigned int family, unsigned int model);
2862
8b7199c0 2863static void dump_platform_info(void)
103a8fea
LB		 2864{
2865 unsigned long long msr;
2866 unsigned int ratio;
2867
ec0adc53 2868 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
103a8fea 2869
b7d8c148 2870 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
6574a5d5 2871
103a8fea 2872 ratio = (msr >> 40) & 0xFF;
1b439f01 2873 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk);
103a8fea
LB		 2874
2875 ratio = (msr >> 8) & 0xFF;
1b439f01 2876 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
103a8fea 2877
7ce7d5de 2878 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
b7d8c148 2879 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
bfae2052 2880 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
67920418 2881
aeb01e6d
CY		 2882 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
2883 if (dis_cstate_prewake)
1b439f01 2884 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN");
aeb01e6d 2885
fcd17211
LB		 2886 return;
2887}
2888
a3943dea 2889static void dump_turbo_ratio_limit2(void)
fcd17211
LB		 2890{
2891 unsigned long long msr;
2892 unsigned int ratio;
2893
7ce7d5de 2894 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
fcd17211 2895
b7d8c148 2896 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
fcd17211
LB		 2897
2898 ratio = (msr >> 8) & 0xFF;
2899 if (ratio)
1b439f01 2900 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2901
2902 ratio = (msr >> 0) & 0xFF;
2903 if (ratio)
1b439f01 2904 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2905 return;
2906}
2907
a3943dea 2908static void dump_turbo_ratio_limit1(void)
fcd17211
LB		 2909{
2910 unsigned long long msr;
2911 unsigned int ratio;
6574a5d5 2912
7ce7d5de 2913 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
6574a5d5 2914
b7d8c148 2915 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 2916
2917 ratio = (msr >> 56) & 0xFF;
2918 if (ratio)
1b439f01 2919 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2920
2921 ratio = (msr >> 48) & 0xFF;
2922 if (ratio)
1b439f01 2923 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2924
2925 ratio = (msr >> 40) & 0xFF;
2926 if (ratio)
1b439f01 2927 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2928
2929 ratio = (msr >> 32) & 0xFF;
2930 if (ratio)
1b439f01 2931 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2932
2933 ratio = (msr >> 24) & 0xFF;
2934 if (ratio)
1b439f01 2935 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2936
2937 ratio = (msr >> 16) & 0xFF;
2938 if (ratio)
1b439f01 2939 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2940
2941 ratio = (msr >> 8) & 0xFF;
2942 if (ratio)
1b439f01 2943 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2944
2945 ratio = (msr >> 0) & 0xFF;
2946 if (ratio)
1b439f01 2947 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2948 return;
2949}
1b439f01 2950
10d85d85 2951static void dump_turbo_ratio_limits(int trl_msr_offset)
fcd17211 2952{
31e07522 2953 unsigned long long msr, core_counts;
5d622845 2954 int shift;
103a8fea 2955
4af184ee
LB		 2956 get_msr(base_cpu, trl_msr_offset, &msr);
2957 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n",
884a1f95 2958 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr);
6574a5d5 2959
10d85d85 2960 if (platform->trl_msrs & TRL_CORECOUNT) {
31e07522
LB		 2961 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
2962 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
2963 } else {
2964 core_counts = 0x0807060504030201;
2965 }
2966
5d622845
LB		 2967 for (shift = 56; shift >= 0; shift -= 8) {
2968 unsigned int ratio, group_size;
6574a5d5 2969
5d622845
LB		 2970 ratio = (msr >> shift) & 0xFF;
2971 group_size = (core_counts >> shift) & 0xFF;
2972 if (ratio)
2973 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2974 ratio, bclk, ratio * bclk, group_size);
2975 }
103a8fea 2976
fcd17211
LB		 2977 return;
2978}
3a9a941d 2979
1b439f01 2980static void dump_atom_turbo_ratio_limits(void)
0f7887c4
LB		 2981{
2982 unsigned long long msr;
2983 unsigned int ratio;
2984
2985 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
2986 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2987
2988 ratio = (msr >> 0) & 0x3F;
2989 if (ratio)
1b439f01 2990 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2991
2992 ratio = (msr >> 8) & 0x3F;
2993 if (ratio)
1b439f01 2994 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2995
2996 ratio = (msr >> 16) & 0x3F;
2997 if (ratio)
1b439f01 2998 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2999
3000 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
3001 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
3002
3003 ratio = (msr >> 24) & 0x3F;
3004 if (ratio)
1b439f01 3005 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 3006
3007 ratio = (msr >> 16) & 0x3F;
3008 if (ratio)
1b439f01 3009 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 3010
3011 ratio = (msr >> 8) & 0x3F;
3012 if (ratio)
1b439f01 3013 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 3014
3015 ratio = (msr >> 0) & 0x3F;
3016 if (ratio)
1b439f01 3017 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 3018}
3019
1b439f01 3020static void dump_knl_turbo_ratio_limits(void)
fb5d4327 3021{
cbf97aba
HC		 3022 const unsigned int buckets_no = 7;
3023
fb5d4327 3024 unsigned long long msr;
cbf97aba
HC		 3025 int delta_cores, delta_ratio;
3026 int i, b_nr;
3027 unsigned int cores[buckets_no];
3028 unsigned int ratio[buckets_no];
fb5d4327 3029
ebf5926a 3030 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
fb5d4327 3031
1b439f01 3032 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
fb5d4327 3033
1e3ec5cd 3034 /*
fb5d4327 3035 * Turbo encoding in KNL is as follows:
cbf97aba
HC		 3036 * [0] -- Reserved
3037 * [7:1] -- Base value of number of active cores of bucket 1.
fb5d4327
DC		 3038 * [15:8] -- Base value of freq ratio of bucket 1.
3039 * [20:16] -- +ve delta of number of active cores of bucket 2.
3040 * i.e. active cores of bucket 2 =
3041 * active cores of bucket 1 + delta
3042 * [23:21] -- Negative delta of freq ratio of bucket 2.
3043 * i.e. freq ratio of bucket 2 =
3044 * freq ratio of bucket 1 - delta
3045 * [28:24]-- +ve delta of number of active cores of bucket 3.
3046 * [31:29]-- -ve delta of freq ratio of bucket 3.
3047 * [36:32]-- +ve delta of number of active cores of bucket 4.
3048 * [39:37]-- -ve delta of freq ratio of bucket 4.
3049 * [44:40]-- +ve delta of number of active cores of bucket 5.
3050 * [47:45]-- -ve delta of freq ratio of bucket 5.
3051 * [52:48]-- +ve delta of number of active cores of bucket 6.
3052 * [55:53]-- -ve delta of freq ratio of bucket 6.
3053 * [60:56]-- +ve delta of number of active cores of bucket 7.
3054 * [63:61]-- -ve delta of freq ratio of bucket 7.
3055 */
cbf97aba
HC		 3056
3057 b_nr = 0;
3058 cores[b_nr] = (msr & 0xFF) >> 1;
3059 ratio[b_nr] = (msr >> 8) & 0xFF;
3060
3061 for (i = 16; i < 64; i += 8) {
fb5d4327 3062 delta_cores = (msr >> i) & 0x1F;
cbf97aba
HC		 3063 delta_ratio = (msr >> (i + 5)) & 0x7;
3064
3065 cores[b_nr + 1] = cores[b_nr] + delta_cores;
3066 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
3067 b_nr++;
fb5d4327 3068 }
cbf97aba
HC		 3069
3070 for (i = buckets_no - 1; i >= 0; i--)
3071 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
b7d8c148 3072 fprintf(outf,
710f273b 3073 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
cbf97aba 3074 ratio[i], bclk, ratio[i] * bclk, cores[i]);
fb5d4327
DC		 3075}
3076
8b7199c0 3077static void dump_cst_cfg(void)
fcd17211
LB		 3078{
3079 unsigned long long msr;
3080
1df2e55a 3081 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
fcd17211 3082
1df2e55a 3083 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
fcd17211 3084
3e8b62bf 3085 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
fcd17211
LB		 3086 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
3087 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
3088 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
3089 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1b439f01 3090 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);
ac980e13
AB		 3091
3092#define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
3093 if (has_automatic_cstate_conversion) {
1b439f01 3094 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
ac980e13
AB		 3095 }
3096
3097 fprintf(outf, ")\n");
3098
fcd17211 3099 return;
103a8fea
LB		 3100}
3101
1b439f01 3102static void dump_config_tdp(void)
6fb3143b
LB		 3103{
3104 unsigned long long msr;
3105
3106 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
b7d8c148 3107 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
685b535b 3108 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
6fb3143b
LB		 3109
3110 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
b7d8c148 3111 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
6fb3143b 3112 if (msr) {
685b535b
CY		 3113 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
3114 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
3115 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
3116 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 3117 }
b7d8c148 3118 fprintf(outf, ")\n");
6fb3143b
LB		 3119
3120 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
b7d8c148 3121 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
6fb3143b 3122 if (msr) {
685b535b
CY		 3123 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
3124 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
3125 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
3126 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 3127 }
b7d8c148 3128 fprintf(outf, ")\n");
6fb3143b
LB		 3129
3130 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
b7d8c148 3131 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
6fb3143b 3132 if ((msr) & 0x3)
b7d8c148
LB		 3133 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
3134 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
3135 fprintf(outf, ")\n");
36229897 3136
6fb3143b 3137 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
b7d8c148 3138 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
685b535b 3139 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
b7d8c148
LB		 3140 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
3141 fprintf(outf, ")\n");
6fb3143b 3142}
5a63426e 3143
1b439f01 3144unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
5a63426e
LB		 3145
3146void print_irtl(void)
3147{
3148 unsigned long long msr;
3149
3150 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
3151 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
3152 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3153 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3154
3155 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
3156 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
3157 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3158 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3159
3160 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
3161 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
3162 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3163 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3164
3165 if (!do_irtl_hsw)
3166 return;
3167
3168 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
3169 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
3170 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3171 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3172
3173 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
3174 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
3175 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3176 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3177
3178 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
3179 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
3180 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3181 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3182
3183}
1b439f01 3184
36229897
LB		 3185void free_fd_percpu(void)
3186{
3187 int i;
3188
01a67adf 3189 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
36229897
LB		 3190 if (fd_percpu[i] != 0)
3191 close(fd_percpu[i]);
3192 }
3193
3194 free(fd_percpu);
6fb3143b
LB		 3195}
3196
c98d5d94 3197void free_all_buffers(void)
103a8fea 3198{
0e2d8f05
LB		 3199 int i;
3200
c98d5d94
LB		 3201 CPU_FREE(cpu_present_set);
3202 cpu_present_set = NULL;
36229897 3203 cpu_present_setsize = 0;
103a8fea 3204
c98d5d94
LB		 3205 CPU_FREE(cpu_affinity_set);
3206 cpu_affinity_set = NULL;
3207 cpu_affinity_setsize = 0;
103a8fea 3208
c98d5d94
LB		 3209 free(thread_even);
3210 free(core_even);
3211 free(package_even);
103a8fea 3212
c98d5d94
LB		 3213 thread_even = NULL;
3214 core_even = NULL;
3215 package_even = NULL;
103a8fea 3216
c98d5d94
LB		 3217 free(thread_odd);
3218 free(core_odd);
3219 free(package_odd);
103a8fea 3220
c98d5d94
LB		 3221 thread_odd = NULL;
3222 core_odd = NULL;
3223 package_odd = NULL;
103a8fea 3224
c98d5d94
LB		 3225 free(output_buffer);
3226 output_buffer = NULL;
3227 outp = NULL;
36229897
LB		 3228
3229 free_fd_percpu();
562a2d37
LB		 3230
3231 free(irq_column_2_cpu);
3232 free(irqs_per_cpu);
0e2d8f05
LB		 3233
3234 for (i = 0; i <= topo.max_cpu_num; ++i) {
3235 if (cpus[i].put_ids)
3236 CPU_FREE(cpus[i].put_ids);
3237 }
3238 free(cpus);
103a8fea
LB		 3239}
3240
c98d5d94 3241/*
95aebc44 3242 * Parse a file containing a single int.
6de68fe1
LB		 3243 * Return 0 if file can not be opened
3244 * Exit if file can be opened, but can not be parsed
c98d5d94 3245 */
95aebc44 3246int parse_int_file(const char *fmt, ...)
103a8fea 3247{
95aebc44
JT		 3248 va_list args;
3249 char path[PATH_MAX];
c98d5d94 3250 FILE *filep;
95aebc44 3251 int value;
103a8fea 3252
95aebc44
JT		 3253 va_start(args, fmt);
3254 vsnprintf(path, sizeof(path), fmt, args);
3255 va_end(args);
6de68fe1
LB		 3256 filep = fopen(path, "r");
3257 if (!filep)
3258 return 0;
b2c95d90
JT		 3259 if (fscanf(filep, "%d", &value) != 1)
3260 err(1, "%s: failed to parse number from file", path);
c98d5d94 3261 fclose(filep);
95aebc44
JT		 3262 return value;
3263}
3264
c98d5d94
LB		 3265/*
3266 * cpu_is_first_core_in_package(cpu)
3267 * return 1 if given CPU is 1st core in package
3268 */
3269int cpu_is_first_core_in_package(int cpu)
103a8fea 3270{
95aebc44 3271 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
103a8fea
LB		 3272}
3273
3274int get_physical_package_id(int cpu)
3275{
95aebc44 3276 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
103a8fea
LB		 3277}
3278
6de68fe1
LB		 3279int get_die_id(int cpu)
3280{
3281 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
3282}
3283
103a8fea
LB		 3284int get_core_id(int cpu)
3285{
95aebc44 3286 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
103a8fea
LB		 3287}
3288
ef605741
PB		 3289void set_node_data(void)
3290{
2ffbb224
PB		 3291 int pkg, node, lnode, cpu, cpux;
3292 int cpu_count;
3293
3294 /* initialize logical_node_id */
3295 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
3296 cpus[cpu].logical_node_id = -1;
3297
3298 cpu_count = 0;
3299 for (pkg = 0; pkg < topo.num_packages; pkg++) {
3300 lnode = 0;
3301 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
3302 if (cpus[cpu].physical_package_id != pkg)
3303 continue;
3304 /* find a cpu with an unset logical_node_id */
3305 if (cpus[cpu].logical_node_id != -1)
3306 continue;
3307 cpus[cpu].logical_node_id = lnode;
3308 node = cpus[cpu].physical_node_id;
3309 cpu_count++;
3310 /*
3311 * find all matching cpus on this pkg and set
3312 * the logical_node_id
3313 */
3314 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
1b439f01 3315 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) {
2ffbb224
PB		 3316 cpus[cpux].logical_node_id = lnode;
3317 cpu_count++;
3318 }
3319 }
3320 lnode++;
3321 if (lnode > topo.nodes_per_pkg)
3322 topo.nodes_per_pkg = lnode;
3323 }
3324 if (cpu_count >= topo.max_cpu_num)
3325 break;
ef605741 3326 }
ef605741
PB		 3327}
3328
3329int get_physical_node_id(struct cpu_topology *thiscpu)
c98d5d94
LB		 3330{
3331 char path[80];
3332 FILE *filep;
0e2d8f05
LB		 3333 int i;
3334 int cpu = thiscpu->logical_cpu_id;
e275b388 3335
0e2d8f05 3336 for (i = 0; i <= topo.max_cpu_num; i++) {
1b439f01 3337 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i);
0e2d8f05
LB		 3338 filep = fopen(path, "r");
3339 if (!filep)
3340 continue;
3341 fclose(filep);
3342 return i;
e275b388 3343 }
0e2d8f05
LB		 3344 return -1;
3345}
c98d5d94 3346
0e2d8f05
LB		 3347int get_thread_siblings(struct cpu_topology *thiscpu)
3348{
3349 char path[80], character;
3350 FILE *filep;
3351 unsigned long map;
8cb48b32 3352 int so, shift, sib_core;
0e2d8f05
LB		 3353 int cpu = thiscpu->logical_cpu_id;
3354 int offset = topo.max_cpu_num + 1;
3355 size_t size;
8cb48b32 3356 int thread_id = 0;
0e2d8f05
LB		 3357
3358 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
8cb48b32
PB		 3359 if (thiscpu->thread_id < 0)
3360 thiscpu->thread_id = thread_id++;
0e2d8f05
LB		 3361 if (!thiscpu->put_ids)
3362 return -1;
3363
3364 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3365 CPU_ZERO_S(size, thiscpu->put_ids);
3366
1b439f01 3367 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
3d7772ea
LB		 3368 filep = fopen(path, "r");
3369
3370 if (!filep) {
3371 warnx("%s: open failed", path);
3372 return -1;
3373 }
0e2d8f05
LB		 3374 do {
3375 offset -= BITMASK_SIZE;
8173c336
BH		 3376 if (fscanf(filep, "%lx%c", &map, &character) != 2)
3377 err(1, "%s: failed to parse file", path);
0e2d8f05
LB		 3378 for (shift = 0; shift < BITMASK_SIZE; shift++) {
3379 if ((map >> shift) & 0x1) {
8cb48b32
PB		 3380 so = shift + offset;
3381 sib_core = get_core_id(so);
3382 if (sib_core == thiscpu->physical_core_id) {
3383 CPU_SET_S(so, size, thiscpu->put_ids);
1b439f01
LB		 3384 if ((so != cpu) && (cpus[so].thread_id < 0))
3385 cpus[so].thread_id = thread_id++;
8cb48b32 3386 }
0e2d8f05
LB		 3387 }
3388 }
e13da9a1 3389 } while (character == ',');
c98d5d94 3390 fclose(filep);
0e2d8f05
LB		 3391
3392 return CPU_COUNT_S(size, thiscpu->put_ids);
c98d5d94
LB		 3393}
3394
103a8fea 3395/*
c98d5d94
LB		 3396 * run func(thread, core, package) in topology order
3397 * skip non-present cpus
103a8fea
LB		 3398 */
3399
1b439f01
LB		 3400int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *,
3401 struct pkg_data *, struct thread_data *, struct core_data *,
3402 struct pkg_data *), struct thread_data *thread_base,
3403 struct core_data *core_base, struct pkg_data *pkg_base,
3404 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2)
c98d5d94 3405{
40f5cfe7 3406 int retval, pkg_no, node_no, core_no, thread_no;
c98d5d94
LB		 3407
3408 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
40f5cfe7 3409 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
1b439f01
LB		 3410 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
3411 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
40f5cfe7
PB		 3412 struct thread_data *t, *t2;
3413 struct core_data *c, *c2;
3414 struct pkg_data *p, *p2;
3415
1b439f01 3416 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
40f5cfe7
PB		 3417
3418 if (cpu_is_not_present(t->cpu_id))
3419 continue;
3420
1b439f01 3421 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no);
40f5cfe7 3422
1b439f01
LB		 3423 c = GET_CORE(core_base, core_no, node_no, pkg_no);
3424 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no);
40f5cfe7
PB		 3425
3426 p = GET_PKG(pkg_base, pkg_no);
3427 p2 = GET_PKG(pkg_base2, pkg_no);
3428
3429 retval = func(t, c, p, t2, c2, p2);
3430 if (retval)
3431 return retval;
3432 }
c98d5d94
LB		 3433 }
3434 }
3435 }
3436 return 0;
3437}
3438
3439/*
3440 * run func(cpu) on every cpu in /proc/stat
3441 * return max_cpu number
3442 */
1b439f01 3443int for_all_proc_cpus(int (func) (int))
103a8fea
LB		 3444{
3445 FILE *fp;
c98d5d94 3446 int cpu_num;
103a8fea
LB		 3447 int retval;
3448
57a42a34 3449 fp = fopen_or_die(proc_stat, "r");
103a8fea
LB		 3450
3451 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
b2c95d90
JT		 3452 if (retval != 0)
3453 err(1, "%s: failed to parse format", proc_stat);
103a8fea 3454
c98d5d94
LB		 3455 while (1) {
3456 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
103a8fea
LB		 3457 if (retval != 1)
3458 break;
3459
c98d5d94
LB		 3460 retval = func(cpu_num);
3461 if (retval) {
3462 fclose(fp);
1b439f01 3463 return (retval);
c98d5d94 3464 }
103a8fea
LB		 3465 }
3466 fclose(fp);
c98d5d94 3467 return 0;
103a8fea
LB		 3468}
3469
3470void re_initialize(void)
3471{
c98d5d94
LB		 3472 free_all_buffers();
3473 setup_all_buffers();
3d7772ea 3474 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
103a8fea
LB		 3475}
3476
843c5791
PB		 3477void set_max_cpu_num(void)
3478{
3479 FILE *filep;
8201a028 3480 int base_cpu;
843c5791 3481 unsigned long dummy;
8201a028 3482 char pathname[64];
843c5791 3483
8201a028
PB		 3484 base_cpu = sched_getcpu();
3485 if (base_cpu < 0)
3486 err(1, "cannot find calling cpu ID");
1b439f01 3487 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu);
8201a028
PB		 3488
3489 filep = fopen_or_die(pathname, "r");
843c5791 3490 topo.max_cpu_num = 0;
843c5791 3491 while (fscanf(filep, "%lx,", &dummy) == 1)
0e2d8f05 3492 topo.max_cpu_num += BITMASK_SIZE;
843c5791 3493 fclose(filep);
1b439f01 3494 topo.max_cpu_num--; /* 0 based */
843c5791 3495}
c98d5d94 3496
103a8fea 3497/*
c98d5d94
LB		 3498 * count_cpus()
3499 * remember the last one seen, it will be the max
103a8fea 3500 */
c98d5d94 3501int count_cpus(int cpu)
103a8fea 3502{
9878bf7a
LB		 3503 UNUSED(cpu);
3504
843c5791 3505 topo.num_cpus++;
c98d5d94
LB		 3506 return 0;
3507}
1b439f01 3508
c98d5d94
LB		 3509int mark_cpu_present(int cpu)
3510{
3511 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
15aaa346 3512 return 0;
103a8fea
LB		 3513}
3514
8cb48b32
PB		 3515int init_thread_id(int cpu)
3516{
3517 cpus[cpu].thread_id = -1;
3518 return 0;
3519}
3520
562a2d37
LB		 3521/*
3522 * snapshot_proc_interrupts()
3523 *
3524 * read and record summary of /proc/interrupts
3525 *
3526 * return 1 if config change requires a restart, else return 0
3527 */
3528int snapshot_proc_interrupts(void)
3529{
3530 static FILE *fp;
3531 int column, retval;
3532
3533 if (fp == NULL)
3534 fp = fopen_or_die("/proc/interrupts", "r");
3535 else
3536 rewind(fp);
3537
3538 /* read 1st line of /proc/interrupts to get cpu* name for each column */
3539 for (column = 0; column < topo.num_cpus; ++column) {
3540 int cpu_number;
3541
3542 retval = fscanf(fp, " CPU%d", &cpu_number);
3543 if (retval != 1)
3544 break;
3545
3546 if (cpu_number > topo.max_cpu_num) {
3547 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
3548 return 1;
3549 }
3550
3551 irq_column_2_cpu[column] = cpu_number;
3552 irqs_per_cpu[cpu_number] = 0;
3553 }
3554
3555 /* read /proc/interrupt count lines and sum up irqs per cpu */
3556 while (1) {
3557 int column;
3558 char buf[64];
3559
3560 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
3561 if (retval != 1)
3562 break;
3563
3564 /* read the count per cpu */
3565 for (column = 0; column < topo.num_cpus; ++column) {
3566
3567 int cpu_number, irq_count;
3568
3569 retval = fscanf(fp, " %d", &irq_count);
3570 if (retval != 1)
3571 break;
3572
3573 cpu_number = irq_column_2_cpu[column];
3574 irqs_per_cpu[cpu_number] += irq_count;
3575
3576 }
3577
1b439f01 3578 while (getc(fp) != '\n') ; /* flush interrupt description */
562a2d37
LB		 3579
3580 }
3581 return 0;
3582}
1b439f01 3583
fdf676e5
LB		 3584/*
3585 * snapshot_gfx_rc6_ms()
3586 *
3587 * record snapshot of
3588 * /sys/class/drm/card0/power/rc6_residency_ms
3589 *
3590 * return 1 if config change requires a restart, else return 0
3591 */
3592int snapshot_gfx_rc6_ms(void)
3593{
3594 FILE *fp;
3595 int retval;
3596
3597 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
3598
3599 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
3600 if (retval != 1)
3601 err(1, "GFX rc6");
3602
3603 fclose(fp);
3604
3605 return 0;
3606}
1b439f01 3607
27d47356
LB		 3608/*
3609 * snapshot_gfx_mhz()
3610 *
2c019d65
ZR		 3611 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
3612 * when /sys/class/drm/card0/gt_cur_freq_mhz is not available.
27d47356
LB		 3613 *
3614 * return 1 if config change requires a restart, else return 0
3615 */
3616int snapshot_gfx_mhz(void)
3617{
3618 static FILE *fp;
3619 int retval;
3620
2c019d65
ZR		 3621 if (fp == NULL) {
3622 fp = fopen("/sys/class/drm/card0/gt_cur_freq_mhz", "r");
3623 if (!fp)
3624 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
3625 } else {
27d47356 3626 rewind(fp);
22048c54
LB		 3627 fflush(fp);
3628 }
27d47356
LB		 3629
3630 retval = fscanf(fp, "%d", &gfx_cur_mhz);
3631 if (retval != 1)
3632 err(1, "GFX MHz");
3633
3634 return 0;
3635}
562a2d37 3636
b4b91569
RA		 3637/*
3638 * snapshot_gfx_cur_mhz()
3639 *
2c019d65
ZR		 3640 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz
3641 * when /sys/class/drm/card0/gt_act_freq_mhz is not available.
b4b91569
RA		 3642 *
3643 * return 1 if config change requires a restart, else return 0
3644 */
3645int snapshot_gfx_act_mhz(void)
3646{
3647 static FILE *fp;
3648 int retval;
3649
2c019d65
ZR		 3650 if (fp == NULL) {
3651 fp = fopen("/sys/class/drm/card0/gt_act_freq_mhz", "r");
3652 if (!fp)
3653 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r");
3654 } else {
b4b91569
RA		 3655 rewind(fp);
3656 fflush(fp);
3657 }
3658
3659 retval = fscanf(fp, "%d", &gfx_act_mhz);
3660 if (retval != 1)
3661 err(1, "GFX ACT MHz");
3662
3663 return 0;
3664}
3665
be0e54c4
LB		 3666/*
3667 * snapshot_cpu_lpi()
3668 *
3669 * record snapshot of
3670 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
be0e54c4
LB		 3671 */
3672int snapshot_cpu_lpi_us(void)
3673{
3674 FILE *fp;
3675 int retval;
3676
3677 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
3678
3679 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
5ea7647b
PB		 3680 if (retval != 1) {
3681 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
3682 BIC_NOT_PRESENT(BIC_CPU_LPI);
605736c6 3683 fclose(fp);
5ea7647b
PB		 3684 return -1;
3685 }
be0e54c4
LB		 3686
3687 fclose(fp);
3688
3689 return 0;
3690}
1b439f01 3691
be0e54c4
LB		 3692/*
3693 * snapshot_sys_lpi()
3694 *
1f81c5ef 3695 * record snapshot of sys_lpi_file
be0e54c4
LB		 3696 */
3697int snapshot_sys_lpi_us(void)
3698{
3699 FILE *fp;
3700 int retval;
3701
1f81c5ef 3702 fp = fopen_or_die(sys_lpi_file, "r");
be0e54c4
LB		 3703
3704 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
5ea7647b
PB		 3705 if (retval != 1) {
3706 fprintf(stderr, "Disabling Low Power Idle System output\n");
3707 BIC_NOT_PRESENT(BIC_SYS_LPI);
15423b95 3708 fclose(fp);
5ea7647b
PB		 3709 return -1;
3710 }
be0e54c4
LB		 3711 fclose(fp);
3712
3713 return 0;
3714}
1b439f01 3715
562a2d37
LB		 3716/*
3717 * snapshot /proc and /sys files
3718 *
3719 * return 1 if configuration restart needed, else return 0
3720 */
3721int snapshot_proc_sysfs_files(void)
3722{
218f0e8d
LB		 3723 if (DO_BIC(BIC_IRQ))
3724 if (snapshot_proc_interrupts())
3725 return 1;
562a2d37 3726
812db3f7 3727 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 3728 snapshot_gfx_rc6_ms();
3729
812db3f7 3730 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 3731 snapshot_gfx_mhz();
3732
b4b91569
RA		 3733 if (DO_BIC(BIC_GFXACTMHz))
3734 snapshot_gfx_act_mhz();
3735
be0e54c4
LB		 3736 if (DO_BIC(BIC_CPU_LPI))
3737 snapshot_cpu_lpi_us();
3738
3739 if (DO_BIC(BIC_SYS_LPI))
3740 snapshot_sys_lpi_us();
3741
562a2d37
LB		 3742 return 0;
3743}
3744
8aa2ed0b
LB		 3745int exit_requested;
3746
1b439f01 3747static void signal_handler(int signal)
8aa2ed0b
LB		 3748{
3749 switch (signal) {
3750 case SIGINT:
3751 exit_requested = 1;
3752 if (debug)
3753 fprintf(stderr, " SIGINT\n");
3754 break;
07211960
LB		 3755 case SIGUSR1:
3756 if (debug > 1)
3757 fprintf(stderr, "SIGUSR1\n");
3758 break;
8aa2ed0b
LB		 3759 }
3760}
3761
3762void setup_signal_handler(void)
3763{
3764 struct sigaction sa;
3765
3766 memset(&sa, 0, sizeof(sa));
3767
3768 sa.sa_handler = &signal_handler;
3769
3770 if (sigaction(SIGINT, &sa, NULL) < 0)
3771 err(1, "sigaction SIGINT");
07211960
LB		 3772 if (sigaction(SIGUSR1, &sa, NULL) < 0)
3773 err(1, "sigaction SIGUSR1");
8aa2ed0b 3774}
b9ad8ee0 3775
47936f94 3776void do_sleep(void)
b9ad8ee0 3777{
c026c236
AB		 3778 struct timeval tout;
3779 struct timespec rest;
b9ad8ee0
LB		 3780 fd_set readfds;
3781 int retval;
3782
3783 FD_ZERO(&readfds);
3784 FD_SET(0, &readfds);
3785
c026c236 3786 if (ignore_stdin) {
47936f94
AB		 3787 nanosleep(&interval_ts, NULL);
3788 return;
3789 }
b9ad8ee0 3790
c026c236
AB		 3791 tout = interval_tv;
3792 retval = select(1, &readfds, NULL, NULL, &tout);
b9ad8ee0
LB		 3793
3794 if (retval == 1) {
b9ad8ee0
LB		 3795 switch (getc(stdin)) {
3796 case 'q':
3797 exit_requested = 1;
3798 break;
c026c236
AB		 3799 case EOF:
3800 /*
3801 * 'stdin' is a pipe closed on the other end. There
3802 * won't be any further input.
3803 */
3804 ignore_stdin = 1;
3805 /* Sleep the rest of the time */
3806 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
3807 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
3808 nanosleep(&rest, NULL);
b9ad8ee0 3809 }
b9ad8ee0 3810 }
b9ad8ee0 3811}
47936f94 3812
87e15da9
CY		 3813int get_msr_sum(int cpu, off_t offset, unsigned long long *msr)
3814{
3815 int ret, idx;
3816 unsigned long long msr_cur, msr_last;
3817
3818 if (!per_cpu_msr_sum)
3819 return 1;
3820
3821 idx = offset_to_idx(offset);
3822 if (idx < 0)
3823 return idx;
3824 /* get_msr_sum() = sum + (get_msr() - last) */
3825 ret = get_msr(cpu, offset, &msr_cur);
3826 if (ret)
3827 return ret;
3828 msr_last = per_cpu_msr_sum[cpu].entries[idx].last;
3829 DELTA_WRAP32(msr_cur, msr_last);
3830 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum;
3831
3832 return 0;
3833}
3834
3835timer_t timerid;
3836
3837/* Timer callback, update the sum of MSRs periodically. */
3838static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3839{
3840 int i, ret;
3841 int cpu = t->cpu_id;
3842
9878bf7a
LB		 3843 UNUSED(c);
3844 UNUSED(p);
3845
87e15da9
CY		 3846 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) {
3847 unsigned long long msr_cur, msr_last;
13a779de 3848 off_t offset;
87e15da9
CY		 3849
3850 if (!idx_valid(i))
3851 continue;
3852 offset = idx_to_offset(i);
3853 if (offset < 0)
3854 continue;
3855 ret = get_msr(cpu, offset, &msr_cur);
3856 if (ret) {
1b439f01 3857 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset);
87e15da9
CY		 3858 continue;
3859 }
3860
3861 msr_last = per_cpu_msr_sum[cpu].entries[i].last;
3862 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff;
3863
3864 DELTA_WRAP32(msr_cur, msr_last);
3865 per_cpu_msr_sum[cpu].entries[i].sum += msr_last;
3866 }
3867 return 0;
3868}
3869
1b439f01 3870static void msr_record_handler(union sigval v)
87e15da9 3871{
9878bf7a
LB		 3872 UNUSED(v);
3873
87e15da9
CY		 3874 for_all_cpus(update_msr_sum, EVEN_COUNTERS);
3875}
3876
3877void msr_sum_record(void)
3878{
3879 struct itimerspec its;
3880 struct sigevent sev;
3881
3882 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array));
3883 if (!per_cpu_msr_sum) {
3884 fprintf(outf, "Can not allocate memory for long time MSR.\n");
3885 return;
3886 }
3887 /*
3888 * Signal handler might be restricted, so use thread notifier instead.
3889 */
3890 memset(&sev, 0, sizeof(struct sigevent));
3891 sev.sigev_notify = SIGEV_THREAD;
3892 sev.sigev_notify_function = msr_record_handler;
3893
3894 sev.sigev_value.sival_ptr = &timerid;
3895 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) {
3896 fprintf(outf, "Can not create timer.\n");
3897 goto release_msr;
3898 }
3899
3900 its.it_value.tv_sec = 0;
3901 its.it_value.tv_nsec = 1;
3902 /*
3903 * A wraparound time has been calculated early.
3904 * Some sources state that the peak power for a
3905 * microprocessor is usually 1.5 times the TDP rating,
3906 * use 2 * TDP for safety.
3907 */
3908 its.it_interval.tv_sec = rapl_joule_counter_range / 2;
3909 its.it_interval.tv_nsec = 0;
3910
3911 if (timer_settime(timerid, 0, &its, NULL) == -1) {
3912 fprintf(outf, "Can not set timer.\n");
3913 goto release_timer;
3914 }
3915 return;
3916
1b439f01 3917release_timer:
87e15da9 3918 timer_delete(timerid);
1b439f01 3919release_msr:
87e15da9
CY		 3920 free(per_cpu_msr_sum);
3921}
4c2122d4 3922
38c6663a
LB		 3923/*
3924 * set_my_sched_priority(pri)
3925 * return previous
3926 */
3927int set_my_sched_priority(int priority)
3928{
3929 int retval;
3930 int original_priority;
3931
3932 errno = 0;
3933 original_priority = getpriority(PRIO_PROCESS, 0);
3934 if (errno && (original_priority == -1))
3935 err(errno, "getpriority");
3936
3937 retval = setpriority(PRIO_PROCESS, 0, priority);
3938 if (retval)
de7839ee 3939 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname);
38c6663a
LB		 3940
3941 errno = 0;
3942 retval = getpriority(PRIO_PROCESS, 0);
3943 if (retval != priority)
164d7a96 3944 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority);
38c6663a
LB		 3945
3946 return original_priority;
3947}
3948
103a8fea
LB		 3949void turbostat_loop()
3950{
c98d5d94 3951 int retval;
e52966c0 3952 int restarted = 0;
9878bf7a 3953 unsigned int done_iters = 0;
c98d5d94 3954
8aa2ed0b
LB		 3955 setup_signal_handler();
3956
38c6663a
LB		 3957 /*
3958 * elevate own priority for interval mode
3959 */
3960 set_my_sched_priority(-20);
3961
103a8fea 3962restart:
e52966c0
LB		 3963 restarted++;
3964
562a2d37 3965 snapshot_proc_sysfs_files();
c98d5d94 3966 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
4c2122d4 3967 first_counter_read = 0;
d91bb17c
LB		 3968 if (retval < -1) {
3969 exit(retval);
3970 } else if (retval == -1) {
3d7772ea 3971 if (restarted > 10) {
e52966c0
LB		 3972 exit(retval);
3973 }
c98d5d94
LB		 3974 re_initialize();
3975 goto restart;
3976 }
e52966c0 3977 restarted = 0;
023fe0ac 3978 done_iters = 0;
103a8fea
LB		 3979 gettimeofday(&tv_even, (struct timezone *)NULL);
3980
3981 while (1) {
c98d5d94 3982 if (for_all_proc_cpus(cpu_is_not_present)) {
103a8fea
LB		 3983 re_initialize();
3984 goto restart;
3985 }
b9ad8ee0 3986 do_sleep();
562a2d37
LB		 3987 if (snapshot_proc_sysfs_files())
3988 goto restart;
c98d5d94 3989 retval = for_all_cpus(get_counters, ODD_COUNTERS);
d91bb17c
LB		 3990 if (retval < -1) {
3991 exit(retval);
3992 } else if (retval == -1) {
15aaa346
LB		 3993 re_initialize();
3994 goto restart;
3995 }
103a8fea 3996 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 3997 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 3998 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
3999 re_initialize();
4000 goto restart;
4001 }
c98d5d94
LB		 4002 compute_average(EVEN_COUNTERS);
4003 format_all_counters(EVEN_COUNTERS);
b7d8c148 4004 flush_output_stdout();
8aa2ed0b
LB		 4005 if (exit_requested)
4006 break;
023fe0ac
CY		 4007 if (num_iterations && ++done_iters >= num_iterations)
4008 break;
b9ad8ee0 4009 do_sleep();
562a2d37
LB		 4010 if (snapshot_proc_sysfs_files())
4011 goto restart;
c98d5d94 4012 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 4013 if (retval < -1) {
4014 exit(retval);
4015 } else if (retval == -1) {
103a8fea
LB		 4016 re_initialize();
4017 goto restart;
4018 }
103a8fea 4019 gettimeofday(&tv_even, (struct timezone *)NULL);
103a8fea 4020 timersub(&tv_even, &tv_odd, &tv_delta);
ba3dec99
LB		 4021 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
4022 re_initialize();
4023 goto restart;
4024 }
c98d5d94
LB		 4025 compute_average(ODD_COUNTERS);
4026 format_all_counters(ODD_COUNTERS);
b7d8c148 4027 flush_output_stdout();
8aa2ed0b
LB		 4028 if (exit_requested)
4029 break;
023fe0ac
CY		 4030 if (num_iterations && ++done_iters >= num_iterations)
4031 break;
103a8fea
LB		 4032 }
4033}
4034
4035void check_dev_msr()
4036{
4037 struct stat sb;
7ce7d5de 4038 char pathname[32];
103a8fea 4039
7ce7d5de
PB		 4040 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
4041 if (stat(pathname, &sb))
1b439f01 4042 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
a21d38c8 4043 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
103a8fea
LB		 4044}
4045
fcaa681c
LB		 4046/*
4047 * check for CAP_SYS_RAWIO
4048 * return 0 on success
4049 * return 1 on fail
4050 */
4051int check_for_cap_sys_rawio(void)
103a8fea 4052{
fcaa681c
LB		 4053 cap_t caps;
4054 cap_flag_value_t cap_flag_value;
98481e79 4055
fcaa681c
LB		 4056 caps = cap_get_proc();
4057 if (caps == NULL)
4058 err(-6, "cap_get_proc\n");
98481e79 4059
fcaa681c
LB		 4060 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
4061 err(-6, "cap_get\n");
4062
4063 if (cap_flag_value != CAP_SET) {
1b439f01 4064 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname);
fcaa681c 4065 return 1;
98481e79
LB		 4066 }
4067
fcaa681c
LB		 4068 if (cap_free(caps) == -1)
4069 err(-6, "cap_free\n");
4070
4071 return 0;
4072}
1b439f01 4073
fcaa681c
LB		 4074void check_permissions(void)
4075{
4076 int do_exit = 0;
4077 char pathname[32];
4078
4079 /* check for CAP_SYS_RAWIO */
4080 do_exit += check_for_cap_sys_rawio();
4081
98481e79 4082 /* test file permissions */
7ce7d5de
PB		 4083 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
4084 if (euidaccess(pathname, R_OK)) {
98481e79
LB		 4085 do_exit++;
4086 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
4087 }
4088
4089 /* if all else fails, thell them to be root */
4090 if (do_exit)
4091 if (getuid() != 0)
d7899447 4092 warnx("... or simply run as root");
98481e79
LB		 4093
4094 if (do_exit)
4095 exit(-6);
103a8fea
LB		 4096}
4097
71e84129
ZR		 4098void probe_bclk(void)
4099{
4100 unsigned long long msr;
4101 unsigned int base_ratio;
4102
fcfa1ce0 4103 if (!platform->has_nhm_msrs)
71e84129
ZR		 4104 return;
4105
4106 if (platform->bclk_freq == BCLK_100MHZ)
4107 bclk = 100.00;
4108 else if (platform->bclk_freq == BCLK_133MHZ)
4109 bclk = 133.33;
4110 else if (platform->bclk_freq == BCLK_SLV)
4111 bclk = slm_bclk();
4112 else
4113 return;
4114
4115 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
4116 base_ratio = (msr >> 8) & 0xFF;
4117
4118 base_hz = base_ratio * bclk * 1000000;
4119 has_base_hz = 1;
4120}
4121
0f7887c4 4122/*
495c7654 4123 * SLV client has support for unique MSRs:
0f7887c4
LB		 4124 *
4125 * MSR_CC6_DEMOTION_POLICY_CONFIG
4126 * MSR_MC6_DEMOTION_POLICY_CONFIG
4127 */
4128
4129int has_slv_msrs(unsigned int family, unsigned int model)
4130{
4131 if (!genuine_intel)
4132 return 0;
4133
9878bf7a
LB		 4134 if (family != 6)
4135 return 0;
4136
0f7887c4 4137 switch (model) {
f2c4db1b 4138 case INTEL_FAM6_ATOM_SILVERMONT:
0f7887c4
LB		 4139 return 1;
4140 }
4141 return 0;
4142}
1b439f01 4143
7170a374
LB		 4144int is_dnv(unsigned int family, unsigned int model)
4145{
4146
4147 if (!genuine_intel)
4148 return 0;
4149
9878bf7a
LB		 4150 if (family != 6)
4151 return 0;
4152
7170a374 4153 switch (model) {
5ebb34ed 4154 case INTEL_FAM6_ATOM_GOLDMONT_D:
7170a374
LB		 4155 return 1;
4156 }
4157 return 0;
4158}
1b439f01 4159
ade0ebac
LB		 4160int is_bdx(unsigned int family, unsigned int model)
4161{
4162
4163 if (!genuine_intel)
4164 return 0;
4165
9878bf7a
LB		 4166 if (family != 6)
4167 return 0;
4168
ade0ebac
LB		 4169 switch (model) {
4170 case INTEL_FAM6_BROADWELL_X:
ade0ebac
LB		 4171 return 1;
4172 }
4173 return 0;
4174}
1b439f01 4175
34c76197
LB		 4176int is_skx(unsigned int family, unsigned int model)
4177{
4178
4179 if (!genuine_intel)
4180 return 0;
4181
9878bf7a
LB		 4182 if (family != 6)
4183 return 0;
4184
34c76197
LB		 4185 switch (model) {
4186 case INTEL_FAM6_SKYLAKE_X:
4187 return 1;
4188 }
4189 return 0;
4190}
25368d7c
CY		 4191
4192int is_icx(unsigned int family, unsigned int model)
4193{
4194
4195 if (!genuine_intel)
4196 return 0;
4197
9878bf7a
LB		 4198 if (family != 6)
4199 return 0;
4200
25368d7c
CY		 4201 switch (model) {
4202 case INTEL_FAM6_ICELAKE_X:
4203 return 1;
4204 }
4205 return 0;
4206}
4207
684e40e9
AB		 4208int is_spr(unsigned int family, unsigned int model)
4209{
4210
4211 if (!genuine_intel)
4212 return 0;
4213
4214 if (family != 6)
4215 return 0;
4216
4217 switch (model) {
4218 case INTEL_FAM6_SAPPHIRERAPIDS_X:
4219 return 1;
4220 }
4221 return 0;
4222}
4223
f6708400
CY		 4224int is_ehl(unsigned int family, unsigned int model)
4225{
4226 if (!genuine_intel)
4227 return 0;
4228
9878bf7a
LB		 4229 if (family != 6)
4230 return 0;
4231
f6708400
CY		 4232 switch (model) {
4233 case INTEL_FAM6_ATOM_TREMONT:
4234 return 1;
4235 }
4236 return 0;
4237}
1b439f01 4238
20de0dab
AL		 4239int is_jvl(unsigned int family, unsigned int model)
4240{
4241 if (!genuine_intel)
4242 return 0;
4243
9878bf7a
LB		 4244 if (family != 6)
4245 return 0;
4246
20de0dab
AL		 4247 switch (model) {
4248 case INTEL_FAM6_ATOM_TREMONT_D:
4249 return 1;
4250 }
4251 return 0;
4252}
0f7887c4 4253
6fb3143b
LB		 4254int has_config_tdp(unsigned int family, unsigned int model)
4255{
4256 if (!genuine_intel)
4257 return 0;
4258
4259 if (family != 6)
4260 return 0;
4261
4262 switch (model) {
869ce69e 4263 case INTEL_FAM6_IVYBRIDGE: /* IVB */
c66f78a6 4264 case INTEL_FAM6_HASWELL: /* HSW */
869ce69e 4265 case INTEL_FAM6_HASWELL_X: /* HSX */
77e5517c 4266 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 4267 case INTEL_FAM6_HASWELL_G: /* HSW */
c66f78a6 4268 case INTEL_FAM6_BROADWELL: /* BDW */
5e741407 4269 case INTEL_FAM6_BROADWELL_G: /* BDW */
869ce69e 4270 case INTEL_FAM6_BROADWELL_X: /* BDX */
af239c44
PZ		 4271 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4272 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
869ce69e 4273 case INTEL_FAM6_SKYLAKE_X: /* SKX */
25368d7c 4274 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 4275 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
869ce69e 4276 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
6fb3143b
LB		 4277 return 1;
4278 default:
4279 return 0;
4280 }
4281}
4282
0b9a0b9b
ZR		 4283/*
4284 * tcc_offset_bits:
4285 * 0: Tcc Offset not supported (Default)
4286 * 6: Bit 29:24 of MSR_PLATFORM_INFO
4287 * 4: Bit 27:24 of MSR_PLATFORM_INFO
4288 */
4289void check_tcc_offset(int model)
4290{
4291 unsigned long long msr;
4292
4293 if (!genuine_intel)
4294 return;
4295
4296 switch (model) {
4297 case INTEL_FAM6_SKYLAKE_L:
b98a6d78 4298 case INTEL_FAM6_CANNONLAKE_L:
0b9a0b9b
ZR		 4299 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) {
4300 msr = (msr >> 30) & 1;
4301 if (msr)
4302 tcc_offset_bits = 6;
4303 }
4304 return;
4305 default:
4306 return;
4307 }
4308}
4309
1b439f01 4310static void remove_underbar(char *s)
fecb3bc8
DA		 4311{
4312 char *to = s;
4313
4314 while (*s) {
4315 if (*s != '_')
4316 *to++ = *s;
4317 s++;
4318 }
4319
4320 *to = 0;
4321}
4322
3ea8e52e 4323static void dump_turbo_ratio_info(unsigned int family, unsigned int model)
fcd17211 4324{
3ea8e52e 4325 if (!has_turbo)
fcd17211
LB		 4326 return;
4327
10d85d85 4328 if (platform->trl_msrs & TRL_LIMIT2)
a3943dea 4329 dump_turbo_ratio_limit2();
fcd17211 4330
10d85d85 4331 if (platform->trl_msrs & TRL_LIMIT1)
a3943dea 4332 dump_turbo_ratio_limit1();
fcd17211 4333
10d85d85
ZR		 4334 if (platform->trl_msrs & TRL_BASE) {
4335 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT);
4af184ee
LB		 4336
4337 if (is_hybrid)
10d85d85 4338 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT);
4af184ee 4339 }
fcd17211 4340
10d85d85 4341 if (platform->trl_msrs & TRL_ATOM)
0f7887c4
LB		 4342 dump_atom_turbo_ratio_limits();
4343
10d85d85 4344 if (platform->trl_msrs & TRL_KNL)
fb5d4327
DC		 4345 dump_knl_turbo_ratio_limits();
4346
6fb3143b
LB		 4347 if (has_config_tdp(family, model))
4348 dump_config_tdp();
3ea8e52e 4349}
6fb3143b 4350
3ea8e52e
AB		 4351static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
4352{
fcfa1ce0 4353 if (!platform->has_nhm_msrs)
3ea8e52e
AB		 4354 return;
4355
8b7199c0 4356 dump_platform_info();
3ea8e52e 4357 dump_turbo_ratio_info(family, model);
8b7199c0 4358 dump_cst_cfg();
fcd17211
LB		 4359}
4360
a5c6d65d
LB		 4361static int read_sysfs_int(char *path)
4362{
4363 FILE *input;
4364 int retval = -1;
4365
4366 input = fopen(path, "r");
4367 if (input == NULL) {
4368 if (debug)
4369 fprintf(outf, "NSFOD %s\n", path);
4370 return (-1);
4371 }
4372 if (fscanf(input, "%d", &retval) != 1)
4373 err(1, "%s: failed to read int from file", path);
4374 fclose(input);
4375
4376 return (retval);
4377}
4378
abdcbdb2
LB		 4379static void dump_sysfs_file(char *path)
4380{
4381 FILE *input;
4382 char cpuidle_buf[64];
4383
4384 input = fopen(path, "r");
4385 if (input == NULL) {
4386 if (debug)
4387 fprintf(outf, "NSFOD %s\n", path);
4388 return;
4389 }
4390 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input))
4391 err(1, "%s: failed to read file", path);
4392 fclose(input);
4393
4394 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf);
4395}
1b439f01 4396
a5c6d65d
LB		 4397static void intel_uncore_frequency_probe(void)
4398{
4399 int i, j;
4400 char path[128];
4401
4402 if (!genuine_intel)
4403 return;
4404
4405 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK))
4406 return;
4407
4d182748
ZR		 4408 /* Cluster level sysfs not supported yet. */
4409 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/uncore00", R_OK))
4410 return;
4411
a5c6d65d
LB		 4412 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK))
4413 BIC_PRESENT(BIC_UNCORE_MHZ);
4414
4415 if (quiet)
4416 return;
4417
4418 for (i = 0; i < topo.num_packages; ++i) {
4419 for (j = 0; j < topo.num_die; ++j) {
4420 int k, l;
4421
4422 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz",
4423 i, j);
4424 k = read_sysfs_int(path);
4425 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz",
4426 i, j);
4427 l = read_sysfs_int(path);
4428 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000);
4429
4430 sprintf(path,
4431 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz",
4432 i, j);
4433 k = read_sysfs_int(path);
4434 sprintf(path,
4435 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz",
4436 i, j);
4437 l = read_sysfs_int(path);
4438 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000);
4439 }
4440 }
4441}
4442
1b439f01 4443static void dump_sysfs_cstate_config(void)
41618e63
LB		 4444{
4445 char path[64];
4446 char name_buf[16];
4447 char desc[64];
4448 FILE *input;
4449 int state;
4450 char *sp;
4451
abdcbdb2
LB		 4452 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) {
4453 fprintf(outf, "cpuidle not loaded\n");
4454 return;
4455 }
4456
4457 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver");
4458 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor");
4459 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro");
4460
41618e63
LB		 4461 for (state = 0; state < 10; ++state) {
4462
1b439f01 4463 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 4464 input = fopen(path, "r");
4465 if (input == NULL)
4466 continue;
8173c336
BH		 4467 if (!fgets(name_buf, sizeof(name_buf), input))
4468 err(1, "%s: failed to read file", path);
41618e63 4469
1b439f01 4470 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 4471 sp = strchr(name_buf, '-');
4472 if (!sp)
4473 sp = strchrnul(name_buf, '\n');
4474 *sp = '\0';
41618e63
LB		 4475 fclose(input);
4476
fecb3bc8
DA		 4477 remove_underbar(name_buf);
4478
1b439f01 4479 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state);
41618e63
LB		 4480 input = fopen(path, "r");
4481 if (input == NULL)
4482 continue;
8173c336
BH		 4483 if (!fgets(desc, sizeof(desc), input))
4484 err(1, "%s: failed to read file", path);
41618e63
LB		 4485
4486 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
4487 fclose(input);
4488 }
4489}
1b439f01
LB		 4490
4491static void dump_sysfs_pstate_config(void)
7293fccd
LB		 4492{
4493 char path[64];
4494 char driver_buf[64];
4495 char governor_buf[64];
4496 FILE *input;
4497 int turbo;
4498
1b439f01 4499 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu);
7293fccd
LB		 4500 input = fopen(path, "r");
4501 if (input == NULL) {
0a42d235 4502 fprintf(outf, "NSFOD %s\n", path);
7293fccd
LB		 4503 return;
4504 }
8173c336
BH		 4505 if (!fgets(driver_buf, sizeof(driver_buf), input))
4506 err(1, "%s: failed to read file", path);
7293fccd
LB		 4507 fclose(input);
4508
1b439f01 4509 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu);
7293fccd
LB		 4510 input = fopen(path, "r");
4511 if (input == NULL) {
0a42d235 4512 fprintf(outf, "NSFOD %s\n", path);
7293fccd
LB		 4513 return;
4514 }
8173c336
BH		 4515 if (!fgets(governor_buf, sizeof(governor_buf), input))
4516 err(1, "%s: failed to read file", path);
7293fccd
LB		 4517 fclose(input);
4518
4519 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
4520 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
4521
4522 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
4523 input = fopen(path, "r");
4524 if (input != NULL) {
8173c336
BH		 4525 if (fscanf(input, "%d", &turbo) != 1)
4526 err(1, "%s: failed to parse number from file", path);
7293fccd
LB		 4527 fprintf(outf, "cpufreq boost: %d\n", turbo);
4528 fclose(input);
4529 }
4530
4531 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
4532 input = fopen(path, "r");
4533 if (input != NULL) {
8173c336
BH		 4534 if (fscanf(input, "%d", &turbo) != 1)
4535 err(1, "%s: failed to parse number from file", path);
7293fccd
LB		 4536 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
4537 fclose(input);
4538 }
4539}
41618e63 4540
889facbe
LB		 4541/*
4542 * print_epb()
4543 * Decode the ENERGY_PERF_BIAS MSR
4544 */
4545int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4546{
889facbe 4547 char *epb_string;
6d6501d9 4548 int cpu, epb;
889facbe 4549
9878bf7a
LB		 4550 UNUSED(c);
4551 UNUSED(p);
4552
889facbe
LB		 4553 if (!has_epb)
4554 return 0;
4555
4556 cpu = t->cpu_id;
4557
4558 /* EPB is per-package */
4559 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4560 return 0;
4561
4562 if (cpu_migrate(cpu)) {
3d7772ea 4563 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 4564 return -1;
4565 }
4566
6d6501d9
BP		 4567 epb = get_epb(cpu);
4568 if (epb < 0)
889facbe
LB		 4569 return 0;
4570
6d6501d9 4571 switch (epb) {
889facbe
LB		 4572 case ENERGY_PERF_BIAS_PERFORMANCE:
4573 epb_string = "performance";
4574 break;
4575 case ENERGY_PERF_BIAS_NORMAL:
4576 epb_string = "balanced";
4577 break;
4578 case ENERGY_PERF_BIAS_POWERSAVE:
4579 epb_string = "powersave";
4580 break;
4581 default:
4582 epb_string = "custom";
4583 break;
4584 }
6d6501d9 4585 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string);
889facbe
LB		 4586
4587 return 0;
4588}
1b439f01 4589
7f5c258e
LB		 4590/*
4591 * print_hwp()
4592 * Decode the MSR_HWP_CAPABILITIES
4593 */
4594int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4595{
4596 unsigned long long msr;
4597 int cpu;
4598
9878bf7a
LB		 4599 UNUSED(c);
4600 UNUSED(p);
4601
7f5c258e
LB		 4602 if (!has_hwp)
4603 return 0;
4604
4605 cpu = t->cpu_id;
4606
4607 /* MSR_HWP_CAPABILITIES is per-package */
4608 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4609 return 0;
4610
4611 if (cpu_migrate(cpu)) {
3d7772ea 4612 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu);
7f5c258e
LB		 4613 return -1;
4614 }
4615
4616 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
4617 return 0;
4618
1b439f01 4619 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-");
7f5c258e
LB		 4620
4621 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
4622 if ((msr & (1 << 0)) == 0)
4623 return 0;
4624
4625 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
4626 return 0;
4627
b7d8c148 4628 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
1b439f01
LB		 4629 "(high %d guar %d eff %d low %d)\n",
4630 cpu, msr,
4631 (unsigned int)HWP_HIGHEST_PERF(msr),
4632 (unsigned int)HWP_GUARANTEED_PERF(msr),
4633 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr));
7f5c258e
LB		 4634
4635 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
4636 return 0;
4637
b7d8c148 4638 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
1b439f01
LB		 4639 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
4640 cpu, msr,
4641 (unsigned int)(((msr) >> 0) & 0xff),
4642 (unsigned int)(((msr) >> 8) & 0xff),
4643 (unsigned int)(((msr) >> 16) & 0xff),
4644 (unsigned int)(((msr) >> 24) & 0xff),
4645 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1));
7f5c258e
LB		 4646
4647 if (has_hwp_pkg) {
4648 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
4649 return 0;
4650
b7d8c148 4651 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
6dbd25a2 4652 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
7f5c258e
LB		 4653 cpu, msr,
4654 (unsigned int)(((msr) >> 0) & 0xff),
4655 (unsigned int)(((msr) >> 8) & 0xff),
4656 (unsigned int)(((msr) >> 16) & 0xff),
1b439f01 4657 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3));
7f5c258e
LB		 4658 }
4659 if (has_hwp_notify) {
4660 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
4661 return 0;
4662
b7d8c148 4663 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
7f5c258e 4664 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
1b439f01 4665 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis");
7f5c258e
LB		 4666 }
4667 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
4668 return 0;
4669
b7d8c148 4670 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
1b439f01 4671 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
92c25393 4672 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-");
889facbe
LB		 4673
4674 return 0;
4675}
4676
3a9a941d
LB		 4677/*
4678 * print_perf_limit()
4679 */
4680int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4681{
4682 unsigned long long msr;
4683 int cpu;
4684
9878bf7a
LB		 4685 UNUSED(c);
4686 UNUSED(p);
4687
3a9a941d
LB		 4688 cpu = t->cpu_id;
4689
4690 /* per-package */
4691 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4692 return 0;
4693
4694 if (cpu_migrate(cpu)) {
3d7772ea 4695 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu);
3a9a941d
LB		 4696 return -1;
4697 }
4698
4699 if (do_core_perf_limit_reasons) {
4700 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4701 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4702 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
e33cbe85 4703 (msr & 1 << 15) ? "bit15, " : "",
3a9a941d 4704 (msr & 1 << 14) ? "bit14, " : "",
e33cbe85
LB		 4705 (msr & 1 << 13) ? "Transitions, " : "",
4706 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
4707 (msr & 1 << 11) ? "PkgPwrL2, " : "",
4708 (msr & 1 << 10) ? "PkgPwrL1, " : "",
4709 (msr & 1 << 9) ? "CorePwr, " : "",
4710 (msr & 1 << 8) ? "Amps, " : "",
4711 (msr & 1 << 6) ? "VR-Therm, " : "",
4712 (msr & 1 << 5) ? "Auto-HWP, " : "",
4713 (msr & 1 << 4) ? "Graphics, " : "",
4714 (msr & 1 << 2) ? "bit2, " : "",
1b439f01 4715 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : "");
b7d8c148 4716 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
e33cbe85 4717 (msr & 1 << 31) ? "bit31, " : "",
3a9a941d 4718 (msr & 1 << 30) ? "bit30, " : "",
e33cbe85
LB		 4719 (msr & 1 << 29) ? "Transitions, " : "",
4720 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
4721 (msr & 1 << 27) ? "PkgPwrL2, " : "",
4722 (msr & 1 << 26) ? "PkgPwrL1, " : "",
4723 (msr & 1 << 25) ? "CorePwr, " : "",
4724 (msr & 1 << 24) ? "Amps, " : "",
4725 (msr & 1 << 22) ? "VR-Therm, " : "",
4726 (msr & 1 << 21) ? "Auto-HWP, " : "",
4727 (msr & 1 << 20) ? "Graphics, " : "",
4728 (msr & 1 << 18) ? "bit18, " : "",
1b439f01 4729 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : "");
3a9a941d
LB		 4730
4731 }
4732 if (do_gfx_perf_limit_reasons) {
4733 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4734 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4735 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3a9a941d
LB		 4736 (msr & 1 << 0) ? "PROCHOT, " : "",
4737 (msr & 1 << 1) ? "ThermStatus, " : "",
4738 (msr & 1 << 4) ? "Graphics, " : "",
4739 (msr & 1 << 6) ? "VR-Therm, " : "",
4740 (msr & 1 << 8) ? "Amps, " : "",
4741 (msr & 1 << 9) ? "GFXPwr, " : "",
1b439f01 4742 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 4743 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3a9a941d
LB		 4744 (msr & 1 << 16) ? "PROCHOT, " : "",
4745 (msr & 1 << 17) ? "ThermStatus, " : "",
4746 (msr & 1 << 20) ? "Graphics, " : "",
4747 (msr & 1 << 22) ? "VR-Therm, " : "",
4748 (msr & 1 << 24) ? "Amps, " : "",
4749 (msr & 1 << 25) ? "GFXPwr, " : "",
1b439f01 4750 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
3a9a941d
LB		 4751 }
4752 if (do_ring_perf_limit_reasons) {
4753 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4754 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4755 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3a9a941d
LB		 4756 (msr & 1 << 0) ? "PROCHOT, " : "",
4757 (msr & 1 << 1) ? "ThermStatus, " : "",
4758 (msr & 1 << 6) ? "VR-Therm, " : "",
4759 (msr & 1 << 8) ? "Amps, " : "",
1b439f01 4760 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 4761 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3a9a941d
LB		 4762 (msr & 1 << 16) ? "PROCHOT, " : "",
4763 (msr & 1 << 17) ? "ThermStatus, " : "",
4764 (msr & 1 << 22) ? "VR-Therm, " : "",
4765 (msr & 1 << 24) ? "Amps, " : "",
1b439f01 4766 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
3a9a941d
LB		 4767 }
4768 return 0;
4769}
4770
889facbe 4771#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
1b439f01 4772#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
889facbe 4773
9392bd98 4774double get_tdp_intel(unsigned int model)
144b44b1
LB		 4775{
4776 unsigned long long msr;
4777
4778 if (do_rapl & RAPL_PKG_POWER_INFO)
7ce7d5de 4779 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
144b44b1
LB		 4780 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
4781
4782 switch (model) {
f2c4db1b 4783 case INTEL_FAM6_ATOM_SILVERMONT:
5ebb34ed 4784 case INTEL_FAM6_ATOM_SILVERMONT_D:
144b44b1
LB		 4785 return 30.0;
4786 default:
4787 return 135.0;
4788 }
4789}
4790
9392bd98
CW		 4791double get_tdp_amd(unsigned int family)
4792{
9878bf7a
LB		 4793 UNUSED(family);
4794
33eb8225
KP		 4795 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */
4796 return 280.0;
9392bd98
CW		 4797}
4798
40ee8e3b
AS		 4799/*
4800 * rapl_dram_energy_units_probe()
4801 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
4802 */
1b439f01 4803static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
40ee8e3b
AS		 4804{
4805 /* only called for genuine_intel, family 6 */
4806
4807 switch (model) {
869ce69e
LB		 4808 case INTEL_FAM6_HASWELL_X: /* HSX */
4809 case INTEL_FAM6_BROADWELL_X: /* BDX */
abdc75ab 4810 case INTEL_FAM6_SKYLAKE_X: /* SKX */
869ce69e 4811 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
6397b641 4812 case INTEL_FAM6_ICELAKE_X: /* ICX */
40ee8e3b
AS		 4813 return (rapl_dram_energy_units = 15.3 / 1000000);
4814 default:
4815 return (rapl_energy_units);
4816 }
4817}
4818
9392bd98 4819void rapl_probe_intel(unsigned int family, unsigned int model)
889facbe
LB		 4820{
4821 unsigned long long msr;
144b44b1 4822 unsigned int time_unit;
889facbe
LB		 4823 double tdp;
4824
889facbe
LB		 4825 if (family != 6)
4826 return;
4827
4828 switch (model) {
869ce69e
LB		 4829 case INTEL_FAM6_SANDYBRIDGE:
4830 case INTEL_FAM6_IVYBRIDGE:
c66f78a6 4831 case INTEL_FAM6_HASWELL: /* HSW */
77e5517c 4832 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 4833 case INTEL_FAM6_HASWELL_G: /* HSW */
c66f78a6 4834 case INTEL_FAM6_BROADWELL: /* BDW */
5e741407 4835 case INTEL_FAM6_BROADWELL_G: /* BDW */
144b44b1 4836 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4837 if (rapl_joules) {
4838 BIC_PRESENT(BIC_Pkg_J);
4839 BIC_PRESENT(BIC_Cor_J);
4840 BIC_PRESENT(BIC_GFX_J);
4841 } else {
4842 BIC_PRESENT(BIC_PkgWatt);
4843 BIC_PRESENT(BIC_CorWatt);
4844 BIC_PRESENT(BIC_GFXWatt);
4845 }
889facbe 4846 break;
869ce69e 4847 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 4848 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
e4085d54 4849 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4850 if (rapl_joules)
4851 BIC_PRESENT(BIC_Pkg_J);
4852 else
4853 BIC_PRESENT(BIC_PkgWatt);
e4085d54 4854 break;
f6708400 4855 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
1b439f01
LB		 4856 do_rapl =
4857 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4858 | RAPL_GFX | RAPL_PKG_POWER_INFO;
f6708400
CY		 4859 if (rapl_joules) {
4860 BIC_PRESENT(BIC_Pkg_J);
4861 BIC_PRESENT(BIC_Cor_J);
4862 BIC_PRESENT(BIC_RAM_J);
4863 BIC_PRESENT(BIC_GFX_J);
4864 } else {
4865 BIC_PRESENT(BIC_PkgWatt);
4866 BIC_PRESENT(BIC_CorWatt);
4867 BIC_PRESENT(BIC_RAMWatt);
4868 BIC_PRESENT(BIC_GFXWatt);
4869 }
4870 break;
20de0dab
AL		 4871 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
4872 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
4873 BIC_PRESENT(BIC_PKG__);
4874 if (rapl_joules)
4875 BIC_PRESENT(BIC_Pkg_J);
4876 else
4877 BIC_PRESENT(BIC_PkgWatt);
4878 break;
af239c44
PZ		 4879 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4880 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
1b439f01
LB		 4881 do_rapl =
4882 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4883 | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4884 BIC_PRESENT(BIC_PKG__);
4885 BIC_PRESENT(BIC_RAM__);
4886 if (rapl_joules) {
4887 BIC_PRESENT(BIC_Pkg_J);
4888 BIC_PRESENT(BIC_Cor_J);
4889 BIC_PRESENT(BIC_RAM_J);
81824921 4890 BIC_PRESENT(BIC_GFX_J);
812db3f7
LB		 4891 } else {
4892 BIC_PRESENT(BIC_PkgWatt);
4893 BIC_PRESENT(BIC_CorWatt);
4894 BIC_PRESENT(BIC_RAMWatt);
81824921 4895 BIC_PRESENT(BIC_GFXWatt);
812db3f7 4896 }
0b2bb692 4897 break;
869ce69e
LB		 4898 case INTEL_FAM6_HASWELL_X: /* HSX */
4899 case INTEL_FAM6_BROADWELL_X: /* BDX */
869ce69e 4900 case INTEL_FAM6_SKYLAKE_X: /* SKX */
25368d7c 4901 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 4902 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
869ce69e 4903 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
1b439f01
LB		 4904 do_rapl =
4905 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4906 RAPL_PKG_POWER_INFO;
812db3f7
LB		 4907 BIC_PRESENT(BIC_PKG__);
4908 BIC_PRESENT(BIC_RAM__);
4909 if (rapl_joules) {
4910 BIC_PRESENT(BIC_Pkg_J);
4911 BIC_PRESENT(BIC_RAM_J);
4912 } else {
4913 BIC_PRESENT(BIC_PkgWatt);
4914 BIC_PRESENT(BIC_RAMWatt);
4915 }
e6f9bb3c 4916 break;
869ce69e
LB		 4917 case INTEL_FAM6_SANDYBRIDGE_X:
4918 case INTEL_FAM6_IVYBRIDGE_X:
1b439f01
LB		 4919 do_rapl =
4920 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS |
4921 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4922 BIC_PRESENT(BIC_PKG__);
4923 BIC_PRESENT(BIC_RAM__);
4924 if (rapl_joules) {
4925 BIC_PRESENT(BIC_Pkg_J);
4926 BIC_PRESENT(BIC_Cor_J);
4927 BIC_PRESENT(BIC_RAM_J);
4928 } else {
4929 BIC_PRESENT(BIC_PkgWatt);
4930 BIC_PRESENT(BIC_CorWatt);
4931 BIC_PRESENT(BIC_RAMWatt);
4932 }
144b44b1 4933 break;
f2c4db1b 4934 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5ebb34ed 4935 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
9148494c 4936 do_rapl = RAPL_PKG | RAPL_CORES;
812db3f7
LB		 4937 if (rapl_joules) {
4938 BIC_PRESENT(BIC_Pkg_J);
4939 BIC_PRESENT(BIC_Cor_J);
4940 } else {
4941 BIC_PRESENT(BIC_PkgWatt);
4942 BIC_PRESENT(BIC_CorWatt);
4943 }
889facbe 4944 break;
5ebb34ed 4945 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
1b439f01
LB		 4946 do_rapl =
4947 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4948 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
812db3f7
LB		 4949 BIC_PRESENT(BIC_PKG__);
4950 BIC_PRESENT(BIC_RAM__);
4951 if (rapl_joules) {
4952 BIC_PRESENT(BIC_Pkg_J);
4953 BIC_PRESENT(BIC_Cor_J);
4954 BIC_PRESENT(BIC_RAM_J);
4955 } else {
4956 BIC_PRESENT(BIC_PkgWatt);
4957 BIC_PRESENT(BIC_CorWatt);
4958 BIC_PRESENT(BIC_RAMWatt);
4959 }
0f644909 4960 break;
889facbe
LB		 4961 default:
4962 return;
4963 }
4964
4965 /* units on package 0, verify later other packages match */
7ce7d5de 4966 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
889facbe
LB		 4967 return;
4968
4969 rapl_power_units = 1.0 / (1 << (msr & 0xF));
f2c4db1b 4970 if (model == INTEL_FAM6_ATOM_SILVERMONT)
144b44b1
LB		 4971 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
4972 else
4973 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
889facbe 4974
40ee8e3b
AS		 4975 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
4976
144b44b1
LB		 4977 time_unit = msr >> 16 & 0xF;
4978 if (time_unit == 0)
4979 time_unit = 0xA;
889facbe 4980
144b44b1 4981 rapl_time_units = 1.0 / (1 << (time_unit));
889facbe 4982
9392bd98 4983 tdp = get_tdp_intel(model);
889facbe 4984
144b44b1 4985 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
96e47158 4986 if (!quiet)
b7d8c148 4987 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
9392bd98 4988}
889facbe 4989
9392bd98
CW		 4990void rapl_probe_amd(unsigned int family, unsigned int model)
4991{
4992 unsigned long long msr;
4993 unsigned int eax, ebx, ecx, edx;
4994 unsigned int has_rapl = 0;
4995 double tdp;
4996
9878bf7a
LB		 4997 UNUSED(model);
4998
9392bd98
CW		 4999 if (max_extended_level >= 0x80000007) {
5000 __cpuid(0x80000007, eax, ebx, ecx, edx);
33eb8225 5001 /* RAPL (Fam 17h+) */
9392bd98
CW		 5002 has_rapl = edx & (1 << 14);
5003 }
5004
33eb8225 5005 if (!has_rapl || family < 0x17)
9392bd98
CW		 5006 return;
5007
33eb8225
KP		 5008 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY;
5009 if (rapl_joules) {
5010 BIC_PRESENT(BIC_Pkg_J);
5011 BIC_PRESENT(BIC_Cor_J);
5012 } else {
5013 BIC_PRESENT(BIC_PkgWatt);
5014 BIC_PRESENT(BIC_CorWatt);
9392bd98
CW		 5015 }
5016
5017 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
5018 return;
5019
5020 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
5021 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
5022 rapl_power_units = ldexp(1.0, -(msr & 0xf));
5023
9cfa8e04 5024 tdp = get_tdp_amd(family);
9392bd98
CW		 5025
5026 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
5027 if (!quiet)
5028 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
5029}
5030
5031/*
5032 * rapl_probe()
5033 *
5034 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
5035 */
5036void rapl_probe(unsigned int family, unsigned int model)
5037{
5038 if (genuine_intel)
5039 rapl_probe_intel(family, model);
c1c10cc7 5040 if (authentic_amd || hygon_genuine)
9392bd98 5041 rapl_probe_amd(family, model);
889facbe
LB		 5042}
5043
1b69317d 5044void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3a9a941d
LB		 5045{
5046 if (!genuine_intel)
5047 return;
5048
5049 if (family != 6)
5050 return;
5051
5052 switch (model) {
c66f78a6 5053 case INTEL_FAM6_HASWELL: /* HSW */
77e5517c 5054 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 5055 case INTEL_FAM6_HASWELL_G: /* HSW */
3a9a941d 5056 do_gfx_perf_limit_reasons = 1;
9878bf7a 5057 /* FALLTHRU */
869ce69e 5058 case INTEL_FAM6_HASWELL_X: /* HSX */
3a9a941d
LB		 5059 do_core_perf_limit_reasons = 1;
5060 do_ring_perf_limit_reasons = 1;
5061 default:
5062 return;
5063 }
5064}
5065
ac980e13
AB		 5066void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
5067{
eade39b2
AB		 5068 if (family != 6)
5069 return;
5070
5071 switch (model) {
5072 case INTEL_FAM6_BROADWELL_X:
5073 case INTEL_FAM6_SKYLAKE_X:
ac980e13 5074 has_automatic_cstate_conversion = 1;
eade39b2 5075 }
ac980e13
AB		 5076}
5077
aeb01e6d
CY		 5078void prewake_cstate_probe(unsigned int family, unsigned int model)
5079{
684e40e9 5080 if (is_icx(family, model) || is_spr(family, model))
aeb01e6d
CY		 5081 dis_cstate_prewake = 1;
5082}
5083
889facbe
LB		 5084int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5085{
5086 unsigned long long msr;
f4896fa5 5087 unsigned int dts, dts2;
889facbe
LB		 5088 int cpu;
5089
9878bf7a
LB		 5090 UNUSED(c);
5091 UNUSED(p);
5092
889facbe
LB		 5093 if (!(do_dts || do_ptm))
5094 return 0;
5095
5096 cpu = t->cpu_id;
5097
5098 /* DTS is per-core, no need to print for each thread */
388e9c81 5099 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
889facbe
LB		 5100 return 0;
5101
5102 if (cpu_migrate(cpu)) {
3d7772ea 5103 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 5104 return -1;
5105 }
5106
5107 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
5108 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
5109 return 0;
5110
5111 dts = (msr >> 16) & 0x7F;
1b439f01 5112 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts);
889facbe 5113
889facbe
LB		 5114 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
5115 return 0;
5116
5117 dts = (msr >> 16) & 0x7F;
5118 dts2 = (msr >> 8) & 0x7F;
b7d8c148 5119 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
55279aef 5120 cpu, msr, tj_max - dts, tj_max - dts2);
889facbe
LB		 5121 }
5122
f4896fa5 5123 if (do_dts && debug) {
889facbe
LB		 5124 unsigned int resolution;
5125
5126 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
5127 return 0;
5128
5129 dts = (msr >> 16) & 0x7F;
5130 resolution = (msr >> 27) & 0xF;
b7d8c148 5131 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
55279aef 5132 cpu, msr, tj_max - dts, resolution);
889facbe 5133
889facbe
LB		 5134 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
5135 return 0;
5136
5137 dts = (msr >> 16) & 0x7F;
5138 dts2 = (msr >> 8) & 0x7F;
b7d8c148 5139 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
55279aef 5140 cpu, msr, tj_max - dts, tj_max - dts2);
889facbe
LB		 5141 }
5142
5143 return 0;
5144}
36229897 5145
889facbe
LB		 5146void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
5147{
6b398625 5148 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n",
889facbe
LB		 5149 cpu, label,
5150 ((msr >> 15) & 1) ? "EN" : "DIS",
5151 ((msr >> 0) & 0x7FFF) * rapl_power_units,
1b439f01 5152 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
889facbe
LB		 5153 (((msr >> 16) & 1) ? "EN" : "DIS"));
5154
5155 return;
5156}
5157
5158int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5159{
5160 unsigned long long msr;
9392bd98 5161 const char *msr_name;
889facbe 5162 int cpu;
889facbe 5163
9878bf7a
LB		 5164 UNUSED(c);
5165 UNUSED(p);
5166
889facbe
LB		 5167 if (!do_rapl)
5168 return 0;
5169
5170 /* RAPL counters are per package, so print only for 1st thread/package */
5171 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
5172 return 0;
5173
5174 cpu = t->cpu_id;
5175 if (cpu_migrate(cpu)) {
3d7772ea 5176 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 5177 return -1;
5178 }
5179
9392bd98
CW		 5180 if (do_rapl & RAPL_AMD_F17H) {
5181 msr_name = "MSR_RAPL_PWR_UNIT";
5182 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
5183 return -1;
5184 } else {
5185 msr_name = "MSR_RAPL_POWER_UNIT";
5186 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
5187 return -1;
5188 }
889facbe 5189
9392bd98 5190 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
96e47158
LB		 5191 rapl_power_units, rapl_energy_units, rapl_time_units);
5192
144b44b1
LB		 5193 if (do_rapl & RAPL_PKG_POWER_INFO) {
5194
889facbe 5195 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
1b439f01 5196 return -5;
889facbe 5197
b7d8c148 5198 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe 5199 cpu, msr,
1b439f01 5200 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
889facbe
LB		 5201 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5202 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5203 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
5204
144b44b1
LB		 5205 }
5206 if (do_rapl & RAPL_PKG) {
5207
889facbe
LB		 5208 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
5209 return -9;
5210
b7d8c148 5211 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
96e47158 5212 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
889facbe
LB		 5213
5214 print_power_limit_msr(cpu, msr, "PKG Limit #1");
6b398625 5215 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n",
889facbe
LB		 5216 cpu,
5217 ((msr >> 47) & 1) ? "EN" : "DIS",
5218 ((msr >> 32) & 0x7FFF) * rapl_power_units,
1b439f01 5219 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
889facbe 5220 ((msr >> 48) & 1) ? "EN" : "DIS");
f52ba931
SP		 5221
5222 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
5223 return -9;
5224
5225 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr);
5226 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n",
164d7a96 5227 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN");
889facbe
LB		 5228 }
5229
0b2bb692 5230 if (do_rapl & RAPL_DRAM_POWER_INFO) {
889facbe 5231 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
1b439f01 5232 return -6;
889facbe 5233
b7d8c148 5234 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe 5235 cpu, msr,
1b439f01 5236 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
889facbe
LB		 5237 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5238 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5239 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
0b2bb692
LB		 5240 }
5241 if (do_rapl & RAPL_DRAM) {
889facbe
LB		 5242 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
5243 return -9;
b7d8c148 5244 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5245 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
889facbe
LB		 5246
5247 print_power_limit_msr(cpu, msr, "DRAM Limit");
5248 }
144b44b1 5249 if (do_rapl & RAPL_CORE_POLICY) {
96e47158
LB		 5250 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
5251 return -7;
889facbe 5252
96e47158 5253 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
144b44b1 5254 }
9148494c 5255 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
96e47158
LB		 5256 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
5257 return -9;
5258 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5259 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
96e47158 5260 print_power_limit_msr(cpu, msr, "Cores Limit");
889facbe
LB		 5261 }
5262 if (do_rapl & RAPL_GFX) {
96e47158
LB		 5263 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
5264 return -8;
889facbe 5265
96e47158 5266 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
889facbe 5267
96e47158
LB		 5268 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
5269 return -9;
5270 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5271 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
96e47158 5272 print_power_limit_msr(cpu, msr, "GFX Limit");
889facbe
LB		 5273 }
5274 return 0;
5275}
5276
d7899447
LB		 5277/*
5278 * SNB adds support for additional MSRs:
5279 *
5280 * MSR_PKG_C7_RESIDENCY 0x000003fa
5281 * MSR_CORE_C7_RESIDENCY 0x000003fe
5282 * MSR_PKG_C2_RESIDENCY 0x0000060d
5283 */
103a8fea 5284
d7899447 5285int has_snb_msrs(unsigned int family, unsigned int model)
103a8fea
LB		 5286{
5287 if (!genuine_intel)
5288 return 0;
5289
9878bf7a
LB		 5290 if (family != 6)
5291 return 0;
5292
103a8fea 5293 switch (model) {
869ce69e
LB		 5294 case INTEL_FAM6_SANDYBRIDGE:
5295 case INTEL_FAM6_SANDYBRIDGE_X:
1b439f01
LB		 5296 case INTEL_FAM6_IVYBRIDGE: /* IVB */
5297 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
5298 case INTEL_FAM6_HASWELL: /* HSW */
5299 case INTEL_FAM6_HASWELL_X: /* HSW */
5300 case INTEL_FAM6_HASWELL_L: /* HSW */
5301 case INTEL_FAM6_HASWELL_G: /* HSW */
5302 case INTEL_FAM6_BROADWELL: /* BDW */
5303 case INTEL_FAM6_BROADWELL_G: /* BDW */
5304 case INTEL_FAM6_BROADWELL_X: /* BDX */
5305 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5306 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5307 case INTEL_FAM6_SKYLAKE_X: /* SKX */
5308 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 5309 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
1b439f01 5310 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5311 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5ebb34ed 5312 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
1b439f01
LB		 5313 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
5314 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
103a8fea
LB		 5315 return 1;
5316 }
5317 return 0;
5318}
5319
d7899447 5320/*
570992fc 5321 * HSW ULT added support for C8/C9/C10 MSRs:
d7899447 5322 *
5a63426e
LB		 5323 * MSR_PKG_C8_RESIDENCY 0x00000630
5324 * MSR_PKG_C9_RESIDENCY 0x00000631
5325 * MSR_PKG_C10_RESIDENCY 0x00000632
5326 *
5327 * MSR_PKGC8_IRTL 0x00000633
5328 * MSR_PKGC9_IRTL 0x00000634
5329 * MSR_PKGC10_IRTL 0x00000635
5330 *
d7899447 5331 */
570992fc 5332int has_c8910_msrs(unsigned int family, unsigned int model)
ca58710f
KCA		 5333{
5334 if (!genuine_intel)
5335 return 0;
5336
9878bf7a
LB		 5337 if (family != 6)
5338 return 0;
5339
ca58710f 5340 switch (model) {
77e5517c 5341 case INTEL_FAM6_HASWELL_L: /* HSW */
c66f78a6 5342 case INTEL_FAM6_BROADWELL: /* BDW */
af239c44
PZ		 5343 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5344 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
869ce69e 5345 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5346 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
f6708400 5347 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
0b2bb692
LB		 5348 return 1;
5349 }
5350 return 0;
5351}
5352
5353/*
5354 * SKL adds support for additional MSRS:
5355 *
5356 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
5357 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
5358 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
5359 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
5360 */
5361int has_skl_msrs(unsigned int family, unsigned int model)
5362{
5363 if (!genuine_intel)
5364 return 0;
5365
9878bf7a
LB		 5366 if (family != 6)
5367 return 0;
5368
0b2bb692 5369 switch (model) {
af239c44
PZ		 5370 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5371 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
ca58710f
KCA		 5372 return 1;
5373 }
5374 return 0;
5375}
5376
144b44b1
LB		 5377int is_slm(unsigned int family, unsigned int model)
5378{
5379 if (!genuine_intel)
5380 return 0;
9878bf7a
LB		 5381
5382 if (family != 6)
5383 return 0;
5384
144b44b1 5385 switch (model) {
f2c4db1b 5386 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5ebb34ed 5387 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
144b44b1
LB		 5388 return 1;
5389 }
5390 return 0;
5391}
5392
fb5d4327
DC		 5393int is_knl(unsigned int family, unsigned int model)
5394{
5395 if (!genuine_intel)
5396 return 0;
9878bf7a
LB		 5397
5398 if (family != 6)
5399 return 0;
5400
fb5d4327 5401 switch (model) {
869ce69e 5402 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
fb5d4327
DC		 5403 return 1;
5404 }
5405 return 0;
5406}
5407
997e5395
SP		 5408int is_cnl(unsigned int family, unsigned int model)
5409{
5410 if (!genuine_intel)
5411 return 0;
5412
9878bf7a
LB		 5413 if (family != 6)
5414 return 0;
5415
997e5395 5416 switch (model) {
1b439f01 5417 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
997e5395
SP		 5418 return 1;
5419 }
5420
5421 return 0;
5422}
5423
b2b34dfe
HC		 5424unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
5425{
5426 if (is_knl(family, model))
5427 return 1024;
5428 return 1;
5429}
5430
7ab5ff49
ZR		 5431int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5432{
5433 unsigned int eax, ebx, ecx, edx;
5434
9878bf7a
LB		 5435 UNUSED(c);
5436 UNUSED(p);
5437
7ab5ff49
ZR		 5438 if (!genuine_intel)
5439 return 0;
5440
5441 if (cpu_migrate(t->cpu_id)) {
5442 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id);
5443 return -1;
5444 }
5445
5446 if (max_level < 0x1a)
5447 return 0;
5448
5449 __cpuid(0x1a, eax, ebx, ecx, edx);
5450 eax = (eax >> 24) & 0xFF;
1b439f01 5451 if (eax == 0x20)
7ab5ff49
ZR		 5452 t->is_atom = true;
5453 return 0;
5454}
5455
889facbe
LB		 5456/*
5457 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
5458 * the Thermal Control Circuit (TCC) activates.
5459 * This is usually equal to tjMax.
5460 *
5461 * Older processors do not have this MSR, so there we guess,
5462 * but also allow cmdline over-ride with -T.
5463 *
5464 * Several MSR temperature values are in units of degrees-C
5465 * below this value, including the Digital Thermal Sensor (DTS),
5466 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
5467 */
b2b94be7 5468int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
889facbe
LB		 5469{
5470 unsigned long long msr;
55279aef 5471 unsigned int tcc_default, tcc_offset;
b2b94be7 5472 int cpu;
6ff7cb37 5473
9878bf7a
LB		 5474 UNUSED(c);
5475 UNUSED(p);
5476
55279aef 5477 /* tj_max is used only for dts or ptm */
889facbe
LB		 5478 if (!(do_dts || do_ptm))
5479 return 0;
5480
5481 /* this is a per-package concept */
5482 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
5483 return 0;
5484
b2b94be7
LB		 5485 cpu = t->cpu_id;
5486 if (cpu_migrate(cpu)) {
5487 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
5488 return -1;
5489 }
5490
55279aef
ZR		 5491 if (tj_max_override != 0) {
5492 tj_max = tj_max_override;
1b439f01 5493 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max);
889facbe
LB		 5494 return 0;
5495 }
5496
b2b94be7 5497 /* Temperature Target MSR is Nehalem and newer only */
fcfa1ce0 5498 if (!platform->has_nhm_msrs)
b2b94be7
LB		 5499 goto guess;
5500
5501 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
5502 goto guess;
5503
55279aef 5504 tcc_default = (msr >> 16) & 0xFF;
b2b94be7 5505
0b9a0b9b
ZR		 5506 if (!quiet) {
5507 switch (tcc_offset_bits) {
5508 case 4:
5509 tcc_offset = (msr >> 24) & 0xF;
5510 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
1b439f01 5511 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
0b9a0b9b
ZR		 5512 break;
5513 case 6:
5514 tcc_offset = (msr >> 24) & 0x3F;
5515 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
1b439f01 5516 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
0b9a0b9b
ZR		 5517 break;
5518 default:
1b439f01 5519 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default);
0b9a0b9b
ZR		 5520 break;
5521 }
5522 }
b2b94be7 5523
55279aef 5524 if (!tcc_default)
b2b94be7
LB		 5525 goto guess;
5526
55279aef 5527 tj_max = tcc_default;
b2b94be7
LB		 5528
5529 return 0;
889facbe 5530
b2b94be7 5531guess:
55279aef 5532 tj_max = TJMAX_DEFAULT;
1b439f01 5533 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max);
889facbe
LB		 5534
5535 return 0;
5536}
69807a63 5537
aa8d8cc7
LB		 5538void decode_feature_control_msr(void)
5539{
5540 unsigned long long msr;
5541
f6505c88 5542 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
aa8d8cc7 5543 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
1b439f01 5544 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");
aa8d8cc7
LB		 5545}
5546
69807a63
LB		 5547void decode_misc_enable_msr(void)
5548{
5549 unsigned long long msr;
5550
f26b1519
LB		 5551 if (!genuine_intel)
5552 return;
5553
69807a63 5554 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
e6512624 5555 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
69807a63 5556 base_cpu, msr,
e6512624
LB		 5557 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
5558 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
fd3933ca 5559 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
e6512624
LB		 5560 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
5561 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
69807a63
LB		 5562}
5563
33148d67
LB		 5564void decode_misc_feature_control(void)
5565{
5566 unsigned long long msr;
5567
778fc34a 5568 if (!platform->has_msr_misc_feature_control)
33148d67
LB		 5569 return;
5570
5571 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
1b439f01
LB		 5572 fprintf(outf,
5573 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
5574 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "",
5575 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");
33148d67 5576}
1b439f01 5577
f0057310
LB		 5578/*
5579 * Decode MSR_MISC_PWR_MGMT
5580 *
5581 * Decode the bits according to the Nehalem documentation
5582 * bit[0] seems to continue to have same meaning going forward
5583 * bit[1] less so...
5584 */
5585void decode_misc_pwr_mgmt_msr(void)
5586{
5587 unsigned long long msr;
5588
3dd0e754 5589 if (!platform->has_msr_misc_pwr_mgmt)
cf4cbe53
LB		 5590 return;
5591
f0057310 5592 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
ddadb8ad 5593 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
f0057310 5594 base_cpu, msr,
1b439f01 5595 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");
f0057310 5596}
1b439f01 5597
71616c8e
LB		 5598/*
5599 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
5600 *
5601 * This MSRs are present on Silvermont processors,
5602 * Intel Atom processor E3000 series (Baytrail), and friends.
5603 */
5604void decode_c6_demotion_policy_msr(void)
5605{
5606 unsigned long long msr;
5607
5608 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
5609 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
5610 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5611
5612 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
5613 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
5614 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5615}
7f5c258e 5616
f5a4c76a
LB		 5617/*
5618 * When models are the same, for the purpose of turbostat, reuse
5619 */
5620unsigned int intel_model_duplicates(unsigned int model)
5621{
5622
1b439f01 5623 switch (model) {
f5a4c76a 5624 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
6d306d6e 5625 case INTEL_FAM6_NEHALEM_G: /* Core i7 and i5 Processor - Nehalem */
f5a4c76a
LB		 5626 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
5627 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
5628 return INTEL_FAM6_NEHALEM;
5629
f5a4c76a
LB		 5630 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
5631 return INTEL_FAM6_NEHALEM_EX;
5632
5633 case INTEL_FAM6_XEON_PHI_KNM:
5634 return INTEL_FAM6_XEON_PHI_KNL;
5635
5ebb34ed 5636 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
f5a4c76a
LB		 5637 return INTEL_FAM6_BROADWELL_X;
5638
c66f78a6 5639 case INTEL_FAM6_SKYLAKE:
af239c44 5640 case INTEL_FAM6_KABYLAKE_L:
c66f78a6 5641 case INTEL_FAM6_KABYLAKE:
081c5432
CY		 5642 case INTEL_FAM6_COMETLAKE_L:
5643 case INTEL_FAM6_COMETLAKE:
af239c44 5644 return INTEL_FAM6_SKYLAKE_L;
937807d3 5645
af239c44 5646 case INTEL_FAM6_ICELAKE_L:
d93ea567 5647 case INTEL_FAM6_ICELAKE_NNPI:
4bf7132a
CY		 5648 case INTEL_FAM6_TIGERLAKE_L:
5649 case INTEL_FAM6_TIGERLAKE:
e7af1ed3
LB		 5650 case INTEL_FAM6_ROCKETLAKE:
5651 case INTEL_FAM6_LAKEFIELD:
5652 case INTEL_FAM6_ALDERLAKE:
5683460b 5653 case INTEL_FAM6_ALDERLAKE_L:
882cdb06 5654 case INTEL_FAM6_ATOM_GRACEMONT:
fb5e29df 5655 case INTEL_FAM6_RAPTORLAKE:
6f9cf553 5656 case INTEL_FAM6_RAPTORLAKE_P:
9b1c2ecf 5657 case INTEL_FAM6_RAPTORLAKE_S:
8e45a9bf
ZR		 5658 case INTEL_FAM6_METEORLAKE:
5659 case INTEL_FAM6_METEORLAKE_L:
af239c44 5660 return INTEL_FAM6_CANNONLAKE_L;
b62b3184 5661
d7814c30
CY		 5662 case INTEL_FAM6_ATOM_TREMONT_L:
5663 return INTEL_FAM6_ATOM_TREMONT;
5664
6c5c6560 5665 case INTEL_FAM6_ICELAKE_D:
25368d7c 5666 return INTEL_FAM6_ICELAKE_X;
93cac415
ZR		 5667
5668 case INTEL_FAM6_EMERALDRAPIDS_X:
5669 return INTEL_FAM6_SAPPHIRERAPIDS_X;
f5a4c76a
LB		 5670 }
5671 return model;
5672}
d76bb7a0
LB		 5673
5674void print_dev_latency(void)
5675{
5676 char *path = "/dev/cpu_dma_latency";
5677 int fd;
5678 int value;
5679 int retval;
5680
5681 fd = open(path, O_RDONLY);
5682 if (fd < 0) {
de7839ee 5683 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
d76bb7a0
LB		 5684 return;
5685 }
5686
5687 retval = read(fd, (void *)&value, sizeof(int));
5688 if (retval != sizeof(int)) {
6cbfedc7 5689 warn("read failed %s", path);
d76bb7a0
LB		 5690 close(fd);
5691 return;
5692 }
1b439f01 5693 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained");
d76bb7a0
LB		 5694
5695 close(fd);
5696}
5697
2af4f9b8 5698/*
2db0e5eb 5699 * Linux-perf manages the HW instructions-retired counter
2af4f9b8
LB		 5700 * by enabling when requested, and hiding rollover
5701 */
5702void linux_perf_init(void)
5703{
5704 if (!BIC_IS_ENABLED(BIC_IPC))
5705 return;
5706
5707 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK))
5708 return;
5709
5710 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5711 if (fd_instr_count_percpu == NULL)
5712 err(-1, "calloc fd_instr_count_percpu");
5713
5714 BIC_PRESENT(BIC_IPC);
5715}
5716
fcd17211 5717void process_cpuid()
103a8fea 5718{
34041551
LB		 5719 unsigned int eax, ebx, ecx, edx;
5720 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
ed0757b8 5721 unsigned long long ucode_patch = 0;
103a8fea
LB		 5722
5723 eax = ebx = ecx = edx = 0;
5724
5aea2f7f 5725 __cpuid(0, max_level, ebx, ecx, edx);
103a8fea 5726
34041551 5727 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
103a8fea 5728 genuine_intel = 1;
34041551
LB		 5729 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
5730 authentic_amd = 1;
c1c10cc7
PW		 5731 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
5732 hygon_genuine = 1;
103a8fea 5733
96e47158 5734 if (!quiet)
ed0757b8
LB		 5735 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n",
5736 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level);
103a8fea 5737
5aea2f7f 5738 __cpuid(1, fms, ebx, ecx, edx);
103a8fea
LB		 5739 family = (fms >> 8) & 0xf;
5740 model = (fms >> 4) & 0xf;
5741 stepping = fms & 0xf;
5aa3d1a2
CW		 5742 if (family == 0xf)
5743 family += (fms >> 20) & 0xff;
5744 if (family >= 6)
103a8fea 5745 model += ((fms >> 16) & 0xf) << 4;
34041551
LB		 5746 ecx_flags = ecx;
5747 edx_flags = edx;
103a8fea 5748
ed0757b8 5749 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
6cbfedc7 5750 warnx("get_msr(UCODE)");
ed0757b8 5751
103a8fea
LB		 5752 /*
5753 * check max extended function levels of CPUID.
5754 * This is needed to check for invariant TSC.
5755 * This check is valid for both Intel and AMD.
5756 */
5757 ebx = ecx = edx = 0;
5aea2f7f 5758 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
103a8fea 5759
34041551 5760 if (!quiet) {
ed0757b8 5761 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n",
1b439f01
LB		 5762 family, model, stepping, family, model, stepping,
5763 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));
ed0757b8 5764 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);
34041551
LB		 5765 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
5766 ecx_flags & (1 << 0) ? "SSE3" : "-",
5767 ecx_flags & (1 << 3) ? "MONITOR" : "-",
5768 ecx_flags & (1 << 6) ? "SMX" : "-",
5769 ecx_flags & (1 << 7) ? "EIST" : "-",
5770 ecx_flags & (1 << 8) ? "TM2" : "-",
5771 edx_flags & (1 << 4) ? "TSC" : "-",
5772 edx_flags & (1 << 5) ? "MSR" : "-",
5773 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
1b439f01 5774 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-");
34041551 5775 }
b98a6d78 5776
45232ab1 5777 probe_platform_features(family, model);
b98a6d78 5778 if (genuine_intel)
f5a4c76a 5779 model = intel_model_duplicates(model);
34041551
LB		 5780
5781 if (!(edx_flags & (1 << 5)))
5782 errx(1, "CPUID: no MSR");
5783
61a87ba7 5784 if (max_extended_level >= 0x80000007) {
103a8fea 5785
d7899447
LB		 5786 /*
5787 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
5788 * this check is valid for both Intel and AMD
5789 */
5aea2f7f 5790 __cpuid(0x80000007, eax, ebx, ecx, edx);
d7899447
LB		 5791 has_invariant_tsc = edx & (1 << 8);
5792 }
103a8fea
LB		 5793
5794 /*
5795 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
5796 * this check is valid for both Intel and AMD
5797 */
5798
5aea2f7f 5799 __cpuid(0x6, eax, ebx, ecx, edx);
8209e054 5800 has_aperf = ecx & (1 << 0);
812db3f7
LB		 5801 if (has_aperf) {
5802 BIC_PRESENT(BIC_Avg_MHz);
5803 BIC_PRESENT(BIC_Busy);
5804 BIC_PRESENT(BIC_Bzy_MHz);
5805 }
889facbe 5806 do_dts = eax & (1 << 0);
812db3f7
LB		 5807 if (do_dts)
5808 BIC_PRESENT(BIC_CoreTmp);
b3a34e93 5809 has_turbo = eax & (1 << 1);
889facbe 5810 do_ptm = eax & (1 << 6);
812db3f7
LB		 5811 if (do_ptm)
5812 BIC_PRESENT(BIC_PkgTmp);
7f5c258e
LB		 5813 has_hwp = eax & (1 << 7);
5814 has_hwp_notify = eax & (1 << 8);
5815 has_hwp_activity_window = eax & (1 << 9);
5816 has_hwp_epp = eax & (1 << 10);
5817 has_hwp_pkg = eax & (1 << 11);
889facbe
LB		 5818 has_epb = ecx & (1 << 3);
5819
96e47158 5820 if (!quiet)
b3a34e93 5821 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
7f5c258e
LB		 5822 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
5823 has_aperf ? "" : "No-",
b3a34e93 5824 has_turbo ? "" : "No-",
7f5c258e
LB		 5825 do_dts ? "" : "No-",
5826 do_ptm ? "" : "No-",
5827 has_hwp ? "" : "No-",
5828 has_hwp_notify ? "" : "No-",
5829 has_hwp_activity_window ? "" : "No-",
1b439f01 5830 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-");
103a8fea 5831
96e47158 5832 if (!quiet)
69807a63
LB		 5833 decode_misc_enable_msr();
5834
96e47158 5835 if (max_level >= 0x7 && !quiet) {
aa8d8cc7 5836 int has_sgx;
103a8fea 5837
aa8d8cc7
LB		 5838 ecx = 0;
5839
5840 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
5841
5842 has_sgx = ebx & (1 << 2);
774627c5
LB		 5843
5844 is_hybrid = edx & (1 << 15);
5845
5846 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-");
aa8d8cc7
LB		 5847
5848 if (has_sgx)
5849 decode_feature_control_msr();
5850 }
5851
61a87ba7 5852 if (max_level >= 0x15) {
8a5bdf41
LB		 5853 unsigned int eax_crystal;
5854 unsigned int ebx_tsc;
5855
5856 /*
5857 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
5858 */
5859 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5aea2f7f 5860 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
8a5bdf41
LB		 5861
5862 if (ebx_tsc != 0) {
5863
96e47158 5864 if (!quiet && (ebx != 0))
b7d8c148 5865 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
8a5bdf41
LB		 5866 eax_crystal, ebx_tsc, crystal_hz);
5867
5868 if (crystal_hz == 0)
1b439f01 5869 switch (model) {
af239c44 5870 case INTEL_FAM6_SKYLAKE_L: /* SKL */
e8efbc80
LB		 5871 crystal_hz = 24000000; /* 24.0 MHz */
5872 break;
5ebb34ed 5873 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
ec53e594
LB		 5874 crystal_hz = 25000000; /* 25.0 MHz */
5875 break;
869ce69e 5876 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5877 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
e8efbc80 5878 crystal_hz = 19200000; /* 19.2 MHz */
8a5bdf41
LB		 5879 break;
5880 default:
5881 crystal_hz = 0;
1b439f01 5882 }
8a5bdf41
LB		 5883
5884 if (crystal_hz) {
1b439f01 5885 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal;
96e47158 5886 if (!quiet)
b7d8c148 5887 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
1b439f01 5888 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
8a5bdf41
LB		 5889 }
5890 }
5891 }
61a87ba7
LB		 5892 if (max_level >= 0x16) {
5893 unsigned int base_mhz, max_mhz, bus_mhz, edx;
5894
5895 /*
5896 * CPUID 16H Base MHz, Max MHz, Bus MHz
5897 */
5898 base_mhz = max_mhz = bus_mhz = edx = 0;
5899
5aea2f7f 5900 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
96e47158 5901 if (!quiet)
b7d8c148 5902 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
61a87ba7
LB		 5903 base_mhz, max_mhz, bus_mhz);
5904 }
8a5bdf41 5905
b2b34dfe
HC		 5906 if (has_aperf)
5907 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
5908
812db3f7
LB		 5909 BIC_PRESENT(BIC_IRQ);
5910 BIC_PRESENT(BIC_TSC_MHz);
5911
3989fc89 5912 probe_cst_limit();
fcfa1ce0 5913 if (platform->has_nhm_msrs) {
812db3f7
LB		 5914 BIC_PRESENT(BIC_CPU_c1);
5915 BIC_PRESENT(BIC_CPU_c3);
5916 BIC_PRESENT(BIC_CPU_c6);
5917 BIC_PRESENT(BIC_SMI);
5918 }
71e84129 5919 probe_bclk();
d7899447 5920 do_snb_cstates = has_snb_msrs(family, model);
812db3f7
LB		 5921
5922 if (do_snb_cstates)
5923 BIC_PRESENT(BIC_CPU_c7);
5924
5a63426e 5925 do_irtl_snb = has_snb_msrs(family, model);
0f47c08d
LB		 5926 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
5927 BIC_PRESENT(BIC_Pkgpc2);
5928 if (pkg_cstate_limit >= PCL__3)
5929 BIC_PRESENT(BIC_Pkgpc3);
5930 if (pkg_cstate_limit >= PCL__6)
5931 BIC_PRESENT(BIC_Pkgpc6);
5932 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
5933 BIC_PRESENT(BIC_Pkgpc7);
0539ba11 5934 if (has_slv_msrs(family, model)) {
0f47c08d
LB		 5935 BIC_NOT_PRESENT(BIC_Pkgpc2);
5936 BIC_NOT_PRESENT(BIC_Pkgpc3);
5937 BIC_PRESENT(BIC_Pkgpc6);
5938 BIC_NOT_PRESENT(BIC_Pkgpc7);
0539ba11
LB		 5939 BIC_PRESENT(BIC_Mod_c6);
5940 use_c1_residency_msr = 1;
5941 }
20de0dab
AL		 5942 if (is_jvl(family, model)) {
5943 BIC_NOT_PRESENT(BIC_CPU_c3);
5944 BIC_NOT_PRESENT(BIC_CPU_c7);
5945 BIC_NOT_PRESENT(BIC_Pkgpc2);
5946 BIC_NOT_PRESENT(BIC_Pkgpc3);
5947 BIC_NOT_PRESENT(BIC_Pkgpc6);
5948 BIC_NOT_PRESENT(BIC_Pkgpc7);
5949 }
7170a374
LB		 5950 if (is_dnv(family, model)) {
5951 BIC_PRESENT(BIC_CPU_c1);
5952 BIC_NOT_PRESENT(BIC_CPU_c3);
5953 BIC_NOT_PRESENT(BIC_Pkgpc3);
5954 BIC_NOT_PRESENT(BIC_CPU_c7);
5955 BIC_NOT_PRESENT(BIC_Pkgpc7);
5956 use_c1_residency_msr = 1;
5957 }
684e40e9 5958 if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) {
34c76197
LB		 5959 BIC_NOT_PRESENT(BIC_CPU_c3);
5960 BIC_NOT_PRESENT(BIC_Pkgpc3);
5961 BIC_NOT_PRESENT(BIC_CPU_c7);
5962 BIC_NOT_PRESENT(BIC_Pkgpc7);
5963 }
ade0ebac
LB		 5964 if (is_bdx(family, model)) {
5965 BIC_NOT_PRESENT(BIC_CPU_c7);
5966 BIC_NOT_PRESENT(BIC_Pkgpc7);
5967 }
570992fc 5968 if (has_c8910_msrs(family, model)) {
c315a09b
LB		 5969 if (pkg_cstate_limit >= PCL__8)
5970 BIC_PRESENT(BIC_Pkgpc8);
5971 if (pkg_cstate_limit >= PCL__9)
5972 BIC_PRESENT(BIC_Pkgpc9);
5973 if (pkg_cstate_limit >= PCL_10)
5974 BIC_PRESENT(BIC_Pkgpc10);
0f47c08d 5975 }
570992fc 5976 do_irtl_hsw = has_c8910_msrs(family, model);
a99d8730
LB		 5977 if (has_skl_msrs(family, model)) {
5978 BIC_PRESENT(BIC_Totl_c0);
5979 BIC_PRESENT(BIC_Any_c0);
5980 BIC_PRESENT(BIC_GFX_c0);
5981 BIC_PRESENT(BIC_CPUGFX);
5982 }
144b44b1 5983 do_slm_cstates = is_slm(family, model);
1b439f01 5984 do_knl_cstates = is_knl(family, model);
103a8fea 5985
1b439f01 5986 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model))
562855ee 5987 BIC_NOT_PRESENT(BIC_CPU_c3);
103a8fea 5988
96e47158 5989 if (!quiet)
f0057310
LB		 5990 decode_misc_pwr_mgmt_msr();
5991
96e47158 5992 if (!quiet && has_slv_msrs(family, model))
71616c8e
LB		 5993 decode_c6_demotion_policy_msr();
5994
889facbe 5995 rapl_probe(family, model);
3a9a941d 5996 perf_limit_reasons_probe(family, model);
ac980e13 5997 automatic_cstate_conversion_probe(family, model);
b61b7d8c 5998 prewake_cstate_probe(family, model);
889facbe 5999
b98a6d78 6000 check_tcc_offset(model);
0b9a0b9b 6001
96e47158 6002 if (!quiet)
1b69317d 6003 dump_cstate_pstate_config_info(family, model);
a5c6d65d 6004 intel_uncore_frequency_probe();
fcd17211 6005
d76bb7a0
LB		 6006 if (!quiet)
6007 print_dev_latency();
41618e63
LB		 6008 if (!quiet)
6009 dump_sysfs_cstate_config();
7293fccd
LB		 6010 if (!quiet)
6011 dump_sysfs_pstate_config();
41618e63 6012
8c69da29 6013 if (has_skl_msrs(family, model) || is_ehl(family, model))
a2b7b749
LB		 6014 calculate_tsc_tweak();
6015
812db3f7
LB		 6016 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
6017 BIC_PRESENT(BIC_GFX_rc6);
fdf676e5 6018
2c019d65
ZR		 6019 if (!access("/sys/class/drm/card0/gt_cur_freq_mhz", R_OK) ||
6020 !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
812db3f7 6021 BIC_PRESENT(BIC_GFXMHz);
27d47356 6022
2c019d65
ZR		 6023 if (!access("/sys/class/drm/card0/gt_act_freq_mhz", R_OK) ||
6024 !access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK))
b4b91569
RA		 6025 BIC_PRESENT(BIC_GFXACTMHz);
6026
be0e54c4
LB		 6027 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
6028 BIC_PRESENT(BIC_CPU_LPI);
6029 else
6030 BIC_NOT_PRESENT(BIC_CPU_LPI);
6031
eae97e05
CY		 6032 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK))
6033 BIC_PRESENT(BIC_CORE_THROT_CNT);
6034 else
6035 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT);
6036
1f81c5ef
LB		 6037 if (!access(sys_lpi_file_sysfs, R_OK)) {
6038 sys_lpi_file = sys_lpi_file_sysfs;
be0e54c4 6039 BIC_PRESENT(BIC_SYS_LPI);
1f81c5ef
LB		 6040 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
6041 sys_lpi_file = sys_lpi_file_debugfs;
6042 BIC_PRESENT(BIC_SYS_LPI);
6043 } else {
6044 sys_lpi_file_sysfs = NULL;
be0e54c4 6045 BIC_NOT_PRESENT(BIC_SYS_LPI);
1f81c5ef 6046 }
be0e54c4 6047
96e47158 6048 if (!quiet)
33148d67
LB		 6049 decode_misc_feature_control();
6050
889facbe 6051 return;
103a8fea
LB		 6052}
6053
103a8fea
LB		 6054/*
6055 * in /dev/cpu/ return success for names that are numbers
6056 * ie. filter out ".", "..", "microcode".
6057 */
6058int dir_filter(const struct dirent *dirp)
6059{
6060 if (isdigit(dirp->d_name[0]))
6061 return 1;
6062 else
6063 return 0;
6064}
6065
c98d5d94
LB		 6066void topology_probe()
6067{
6068 int i;
6069 int max_core_id = 0;
6070 int max_package_id = 0;
6de68fe1 6071 int max_die_id = 0;
c98d5d94 6072 int max_siblings = 0;
c98d5d94
LB		 6073
6074 /* Initialize num_cpus, max_cpu_num */
843c5791 6075 set_max_cpu_num();
c98d5d94 6076 topo.num_cpus = 0;
c98d5d94
LB		 6077 for_all_proc_cpus(count_cpus);
6078 if (!summary_only && topo.num_cpus > 1)
812db3f7 6079 BIC_PRESENT(BIC_CPU);
c98d5d94 6080
d8af6f5f 6081 if (debug > 1)
b7d8c148 6082 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
c98d5d94 6083
1b439f01 6084 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
b2c95d90
JT		 6085 if (cpus == NULL)
6086 err(1, "calloc cpus");
c98d5d94
LB		 6087
6088 /*
6089 * Allocate and initialize cpu_present_set
6090 */
6091 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 6092 if (cpu_present_set == NULL)
6093 err(3, "CPU_ALLOC");
c98d5d94
LB		 6094 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
6095 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
6096 for_all_proc_cpus(mark_cpu_present);
6097
1ef7d21a
LB		 6098 /*
6099 * Validate that all cpus in cpu_subset are also in cpu_present_set
6100 */
6101 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
6102 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
6103 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
6104 err(1, "cpu%d not present", i);
6105 }
6106
c98d5d94
LB		 6107 /*
6108 * Allocate and initialize cpu_affinity_set
6109 */
6110 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 6111 if (cpu_affinity_set == NULL)
6112 err(3, "CPU_ALLOC");
c98d5d94
LB		 6113 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
6114 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
6115
8cb48b32 6116 for_all_proc_cpus(init_thread_id);
c98d5d94
LB		 6117
6118 /*
6119 * For online cpus
6120 * find max_core_id, max_package_id
6121 */
6122 for (i = 0; i <= topo.max_cpu_num; ++i) {
6123 int siblings;
6124
6125 if (cpu_is_not_present(i)) {
d8af6f5f 6126 if (debug > 1)
b7d8c148 6127 fprintf(outf, "cpu%d NOT PRESENT\n", i);
c98d5d94
LB		 6128 continue;
6129 }
c98d5d94 6130
0e2d8f05
LB		 6131 cpus[i].logical_cpu_id = i;
6132
6133 /* get package information */
c98d5d94
LB		 6134 cpus[i].physical_package_id = get_physical_package_id(i);
6135 if (cpus[i].physical_package_id > max_package_id)
6136 max_package_id = cpus[i].physical_package_id;
6137
6de68fe1
LB		 6138 /* get die information */
6139 cpus[i].die_id = get_die_id(i);
6140 if (cpus[i].die_id > max_die_id)
6141 max_die_id = cpus[i].die_id;
6142
0e2d8f05 6143 /* get numa node information */
ef605741
PB		 6144 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
6145 if (cpus[i].physical_node_id > topo.max_node_num)
6146 topo.max_node_num = cpus[i].physical_node_id;
0e2d8f05
LB		 6147
6148 /* get core information */
6149 cpus[i].physical_core_id = get_core_id(i);
6150 if (cpus[i].physical_core_id > max_core_id)
6151 max_core_id = cpus[i].physical_core_id;
6152
6153 /* get thread information */
6154 siblings = get_thread_siblings(&cpus[i]);
c98d5d94
LB		 6155 if (siblings > max_siblings)
6156 max_siblings = siblings;
4f206a0f 6157 if (cpus[i].thread_id == 0)
8cb48b32 6158 topo.num_cores++;
c98d5d94 6159 }
ef605741 6160
70a9c6e8 6161 topo.cores_per_node = max_core_id + 1;
d8af6f5f 6162 if (debug > 1)
1b439f01 6163 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node);
70a9c6e8 6164 if (!summary_only && topo.cores_per_node > 1)
812db3f7 6165 BIC_PRESENT(BIC_Core);
c98d5d94 6166
6de68fe1
LB		 6167 topo.num_die = max_die_id + 1;
6168 if (debug > 1)
1b439f01 6169 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die);
6de68fe1
LB		 6170 if (!summary_only && topo.num_die > 1)
6171 BIC_PRESENT(BIC_Die);
6172
c98d5d94 6173 topo.num_packages = max_package_id + 1;
d8af6f5f 6174 if (debug > 1)
1b439f01 6175 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages);
7da6e3e2 6176 if (!summary_only && topo.num_packages > 1)
812db3f7 6177 BIC_PRESENT(BIC_Package);
c98d5d94 6178
ef605741
PB		 6179 set_node_data();
6180 if (debug > 1)
70a9c6e8 6181 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
01235041
PB		 6182 if (!summary_only && topo.nodes_per_pkg > 1)
6183 BIC_PRESENT(BIC_Node);
ef605741 6184
70a9c6e8 6185 topo.threads_per_core = max_siblings;
d8af6f5f 6186 if (debug > 1)
b7d8c148 6187 fprintf(outf, "max_siblings %d\n", max_siblings);
2ffbb224
PB		 6188
6189 if (debug < 1)
6190 return;
6191
6192 for (i = 0; i <= topo.max_cpu_num; ++i) {
0ec712e3
LB		 6193 if (cpu_is_not_present(i))
6194 continue;
2ffbb224 6195 fprintf(outf,
6de68fe1
LB		 6196 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
6197 i, cpus[i].physical_package_id, cpus[i].die_id,
1b439f01 6198 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id);
2ffbb224
PB		 6199 }
6200
c98d5d94
LB		 6201}
6202
1b439f01 6203void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
c98d5d94
LB		 6204{
6205 int i;
1b439f01 6206 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages;
40f5cfe7 6207 int num_threads = topo.threads_per_core * num_cores;
c98d5d94 6208
40f5cfe7 6209 *t = calloc(num_threads, sizeof(struct thread_data));
c98d5d94
LB		 6210 if (*t == NULL)
6211 goto error;
6212
40f5cfe7 6213 for (i = 0; i < num_threads; i++)
c98d5d94
LB		 6214 (*t)[i].cpu_id = -1;
6215
40f5cfe7 6216 *c = calloc(num_cores, sizeof(struct core_data));
c98d5d94
LB		 6217 if (*c == NULL)
6218 goto error;
6219
40f5cfe7 6220 for (i = 0; i < num_cores; i++)
c98d5d94
LB		 6221 (*c)[i].core_id = -1;
6222
678a3bd1 6223 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
c98d5d94
LB		 6224 if (*p == NULL)
6225 goto error;
6226
6227 for (i = 0; i < topo.num_packages; i++)
6228 (*p)[i].package_id = i;
6229
6230 return;
6231error:
b2c95d90 6232 err(1, "calloc counters");
c98d5d94 6233}
1b439f01 6234
c98d5d94
LB		 6235/*
6236 * init_counter()
6237 *
c98d5d94 6238 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
c98d5d94 6239 */
1b439f01 6240void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id)
c98d5d94 6241{
8cb48b32 6242 int pkg_id = cpus[cpu_id].physical_package_id;
40f5cfe7 6243 int node_id = cpus[cpu_id].logical_node_id;
8cb48b32
PB		 6244 int core_id = cpus[cpu_id].physical_core_id;
6245 int thread_id = cpus[cpu_id].thread_id;
c98d5d94
LB		 6246 struct thread_data *t;
6247 struct core_data *c;
6248 struct pkg_data *p;
6249
42dd4520
NC		 6250 /* Workaround for systems where physical_node_id==-1
6251 * and logical_node_id==(-1 - topo.num_cpus)
6252 */
6253 if (node_id < 0)
6254 node_id = 0;
6255
40f5cfe7
PB		 6256 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
6257 c = GET_CORE(core_base, core_id, node_id, pkg_id);
8cb48b32 6258 p = GET_PKG(pkg_base, pkg_id);
c98d5d94
LB		 6259
6260 t->cpu_id = cpu_id;
8cb48b32 6261 if (thread_id == 0) {
c98d5d94
LB		 6262 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
6263 if (cpu_is_first_core_in_package(cpu_id))
6264 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
6265 }
6266
8cb48b32
PB		 6267 c->core_id = core_id;
6268 p->package_id = pkg_id;
c98d5d94
LB		 6269}
6270
c98d5d94
LB		 6271int initialize_counters(int cpu_id)
6272{
8cb48b32
PB		 6273 init_counter(EVEN_COUNTERS, cpu_id);
6274 init_counter(ODD_COUNTERS, cpu_id);
c98d5d94
LB		 6275 return 0;
6276}
6277
6278void allocate_output_buffer()
6279{
eeb71c95 6280 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
c98d5d94 6281 outp = output_buffer;
b2c95d90
JT		 6282 if (outp == NULL)
6283 err(-1, "calloc output buffer");
c98d5d94 6284}
1b439f01 6285
36229897
LB		 6286void allocate_fd_percpu(void)
6287{
01a67adf 6288 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
36229897
LB		 6289 if (fd_percpu == NULL)
6290 err(-1, "calloc fd_percpu");
6291}
1b439f01 6292
562a2d37
LB		 6293void allocate_irq_buffers(void)
6294{
6295 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
6296 if (irq_column_2_cpu == NULL)
6297 err(-1, "calloc %d", topo.num_cpus);
c98d5d94 6298
01a67adf 6299 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
562a2d37 6300 if (irqs_per_cpu == NULL)
01a67adf 6301 err(-1, "calloc %d", topo.max_cpu_num + 1);
562a2d37 6302}
1b439f01 6303
c98d5d94
LB		 6304void setup_all_buffers(void)
6305{
6306 topology_probe();
562a2d37 6307 allocate_irq_buffers();
36229897 6308 allocate_fd_percpu();
c98d5d94
LB		 6309 allocate_counters(&thread_even, &core_even, &package_even);
6310 allocate_counters(&thread_odd, &core_odd, &package_odd);
6311 allocate_output_buffer();
6312 for_all_proc_cpus(initialize_counters);
6313}
3b4d5c7f 6314
7ce7d5de
PB		 6315void set_base_cpu(void)
6316{
6317 base_cpu = sched_getcpu();
6318 if (base_cpu < 0)
6319 err(-ENODEV, "No valid cpus found");
6320
6321 if (debug > 1)
b7d8c148 6322 fprintf(outf, "base_cpu = %d\n", base_cpu);
7ce7d5de
PB		 6323}
6324
103a8fea
LB		 6325void turbostat_init()
6326{
7ce7d5de
PB		 6327 setup_all_buffers();
6328 set_base_cpu();
103a8fea 6329 check_dev_msr();
98481e79 6330 check_permissions();
fcd17211 6331 process_cpuid();
2af4f9b8 6332 linux_perf_init();
103a8fea 6333
96e47158 6334 if (!quiet)
7f5c258e
LB		 6335 for_all_cpus(print_hwp, ODD_COUNTERS);
6336
96e47158 6337 if (!quiet)
889facbe
LB		 6338 for_all_cpus(print_epb, ODD_COUNTERS);
6339
96e47158 6340 if (!quiet)
3a9a941d
LB		 6341 for_all_cpus(print_perf_limit, ODD_COUNTERS);
6342
96e47158 6343 if (!quiet)
889facbe
LB		 6344 for_all_cpus(print_rapl, ODD_COUNTERS);
6345
6346 for_all_cpus(set_temperature_target, ODD_COUNTERS);
6347
7ab5ff49
ZR		 6348 for_all_cpus(get_cpu_type, ODD_COUNTERS);
6349 for_all_cpus(get_cpu_type, EVEN_COUNTERS);
6350
96e47158 6351 if (!quiet)
889facbe 6352 for_all_cpus(print_thermal, ODD_COUNTERS);
5a63426e 6353
96e47158 6354 if (!quiet && do_irtl_snb)
5a63426e 6355 print_irtl();
164d7a96
LB		 6356
6357 if (DO_BIC(BIC_IPC))
6358 (void)get_instr_count_fd(base_cpu);
103a8fea
LB		 6359}
6360
6361int fork_it(char **argv)
6362{
103a8fea 6363 pid_t child_pid;
d91bb17c 6364 int status;
d15cf7c1 6365
218f0e8d 6366 snapshot_proc_sysfs_files();
d91bb17c 6367 status = for_all_cpus(get_counters, EVEN_COUNTERS);
4c2122d4 6368 first_counter_read = 0;
d91bb17c
LB		 6369 if (status)
6370 exit(status);
c98d5d94
LB		 6371 /* clear affinity side-effect of get_counters() */
6372 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
103a8fea
LB		 6373 gettimeofday(&tv_even, (struct timezone *)NULL);
6374
6375 child_pid = fork();
6376 if (!child_pid) {
6377 /* child */
6378 execvp(argv[0], argv);
0815a3d0 6379 err(errno, "exec %s", argv[0]);
103a8fea 6380 } else {
103a8fea
LB		 6381
6382 /* parent */
b2c95d90
JT		 6383 if (child_pid == -1)
6384 err(1, "fork");
103a8fea
LB		 6385
6386 signal(SIGINT, SIG_IGN);
6387 signal(SIGQUIT, SIG_IGN);
b2c95d90
JT		 6388 if (waitpid(child_pid, &status, 0) == -1)
6389 err(status, "waitpid");
2a954966
DA		 6390
6391 if (WIFEXITED(status))
6392 status = WEXITSTATUS(status);
103a8fea 6393 }
c98d5d94
LB		 6394 /*
6395 * n.b. fork_it() does not check for errors from for_all_cpus()
6396 * because re-starting is problematic when forking
6397 */
218f0e8d 6398 snapshot_proc_sysfs_files();
c98d5d94 6399 for_all_cpus(get_counters, ODD_COUNTERS);
103a8fea 6400 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 6401 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 6402 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
6403 fprintf(outf, "%s: Counter reset detected\n", progname);
6404 else {
6405 compute_average(EVEN_COUNTERS);
6406 format_all_counters(EVEN_COUNTERS);
6407 }
103a8fea 6408
1b439f01 6409 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0);
b7d8c148
LB		 6410
6411 flush_output_stderr();
103a8fea 6412
d91bb17c 6413 return status;
103a8fea
LB		 6414}
6415
3b4d5c7f
AS		 6416int get_and_dump_counters(void)
6417{
6418 int status;
6419
218f0e8d 6420 snapshot_proc_sysfs_files();
3b4d5c7f
AS		 6421 status = for_all_cpus(get_counters, ODD_COUNTERS);
6422 if (status)
6423 return status;
6424
6425 status = for_all_cpus(dump_counters, ODD_COUNTERS);
6426 if (status)
6427 return status;
6428
b7d8c148 6429 flush_output_stdout();
3b4d5c7f
AS		 6430
6431 return status;
6432}
6433
1b439f01
LB		 6434void print_version()
6435{
de7839ee 6436 fprintf(outf, "turbostat version 2023.03.17 - Len Brown <lenb@kernel.org>\n");
d8af6f5f
LB		 6437}
6438
03331233
CY		 6439#define COMMAND_LINE_SIZE 2048
6440
6441void print_bootcmd(void)
6442{
6443 char bootcmd[COMMAND_LINE_SIZE];
6444 FILE *fp;
6445 int ret;
6446
6447 memset(bootcmd, 0, COMMAND_LINE_SIZE);
6448 fp = fopen("/proc/cmdline", "r");
6449 if (!fp)
6450 return;
6451
6452 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp);
6453 if (ret) {
6454 bootcmd[ret] = '\0';
6455 /* the last character is already '\n' */
6456 fprintf(outf, "Kernel command line: %s", bootcmd);
6457 }
6458
6459 fclose(fp);
6460}
6461
495c7654 6462int add_counter(unsigned int msr_num, char *path, char *name,
1b439f01
LB		 6463 unsigned int width, enum counter_scope scope,
6464 enum counter_type type, enum counter_format format, int flags)
388e9c81
LB		 6465{
6466 struct msr_counter *msrp;
6467
6468 msrp = calloc(1, sizeof(struct msr_counter));
6469 if (msrp == NULL) {
6470 perror("calloc");
6471 exit(1);
6472 }
6473
6474 msrp->msr_num = msr_num;
d8d005ba 6475 strncpy(msrp->name, name, NAME_BYTES - 1);
495c7654 6476 if (path)
d8d005ba 6477 strncpy(msrp->path, path, PATH_BYTES - 1);
388e9c81
LB		 6478 msrp->width = width;
6479 msrp->type = type;
6480 msrp->format = format;
41618e63 6481 msrp->flags = flags;
388e9c81
LB		 6482
6483 switch (scope) {
6484
6485 case SCOPE_CPU:
388e9c81
LB		 6486 msrp->next = sys.tp;
6487 sys.tp = msrp;
678a3bd1 6488 sys.added_thread_counters++;
0748eaf0 6489 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
1b439f01 6490 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6491 exit(-1);
6492 }
388e9c81
LB		 6493 break;
6494
6495 case SCOPE_CORE:
388e9c81
LB		 6496 msrp->next = sys.cp;
6497 sys.cp = msrp;
678a3bd1
LB		 6498 sys.added_core_counters++;
6499 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
1b439f01 6500 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6501 exit(-1);
6502 }
388e9c81
LB		 6503 break;
6504
6505 case SCOPE_PACKAGE:
388e9c81
LB		 6506 msrp->next = sys.pp;
6507 sys.pp = msrp;
678a3bd1
LB		 6508 sys.added_package_counters++;
6509 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
1b439f01 6510 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6511 exit(-1);
6512 }
388e9c81
LB		 6513 break;
6514 }
6515
6516 return 0;
6517}
6518
6519void parse_add_command(char *add_command)
6520{
6521 int msr_num = 0;
495c7654 6522 char *path = NULL;
0f47c08d 6523 char name_buffer[NAME_BYTES] = "";
388e9c81
LB		 6524 int width = 64;
6525 int fail = 0;
6526 enum counter_scope scope = SCOPE_CPU;
6527 enum counter_type type = COUNTER_CYCLES;
6528 enum counter_format format = FORMAT_DELTA;
6529
6530 while (add_command) {
6531
6532 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
6533 goto next;
6534
6535 if (sscanf(add_command, "msr%d", &msr_num) == 1)
6536 goto next;
6537
495c7654
LB		 6538 if (*add_command == '/') {
6539 path = add_command;
6540 goto next;
6541 }
6542
388e9c81
LB		 6543 if (sscanf(add_command, "u%d", &width) == 1) {
6544 if ((width == 32) || (width == 64))
6545 goto next;
6546 width = 64;
6547 }
6548 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
6549 scope = SCOPE_CPU;
6550 goto next;
6551 }
6552 if (!strncmp(add_command, "core", strlen("core"))) {
6553 scope = SCOPE_CORE;
6554 goto next;
6555 }
6556 if (!strncmp(add_command, "package", strlen("package"))) {
6557 scope = SCOPE_PACKAGE;
6558 goto next;
6559 }
6560 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
6561 type = COUNTER_CYCLES;
6562 goto next;
6563 }
6564 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
6565 type = COUNTER_SECONDS;
6566 goto next;
6567 }
41618e63
LB		 6568 if (!strncmp(add_command, "usec", strlen("usec"))) {
6569 type = COUNTER_USEC;
6570 goto next;
6571 }
388e9c81
LB		 6572 if (!strncmp(add_command, "raw", strlen("raw"))) {
6573 format = FORMAT_RAW;
6574 goto next;
6575 }
6576 if (!strncmp(add_command, "delta", strlen("delta"))) {
6577 format = FORMAT_DELTA;
6578 goto next;
6579 }
6580 if (!strncmp(add_command, "percent", strlen("percent"))) {
6581 format = FORMAT_PERCENT;
6582 goto next;
6583 }
6584
6585 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
6586 char *eos;
6587
6588 eos = strchr(name_buffer, ',');
6589 if (eos)
6590 *eos = '\0';
6591 goto next;
6592 }
6593
6594next:
6595 add_command = strchr(add_command, ',');
495c7654
LB		 6596 if (add_command) {
6597 *add_command = '\0';
388e9c81 6598 add_command++;
495c7654 6599 }
388e9c81
LB		 6600
6601 }
495c7654
LB		 6602 if ((msr_num == 0) && (path == NULL)) {
6603 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
388e9c81
LB		 6604 fail++;
6605 }
6606
6607 /* generate default column header */
6608 if (*name_buffer == '\0') {
5f3aea57
LB		 6609 if (width == 32)
6610 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6611 else
6612 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
388e9c81
LB		 6613 }
6614
41618e63 6615 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
388e9c81
LB		 6616 fail++;
6617
6618 if (fail) {
6619 help();
6620 exit(1);
6621 }
6622}
41618e63 6623
0fc521bc
ZLCH		 6624int is_deferred_add(char *name)
6625{
6626 int i;
6627
6628 for (i = 0; i < deferred_add_index; ++i)
6629 if (!strcmp(name, deferred_add_names[i]))
6630 return 1;
6631 return 0;
6632}
6633
dd778a5e
LB		 6634int is_deferred_skip(char *name)
6635{
6636 int i;
6637
6638 for (i = 0; i < deferred_skip_index; ++i)
6639 if (!strcmp(name, deferred_skip_names[i]))
6640 return 1;
6641 return 0;
6642}
6643
41618e63
LB		 6644void probe_sysfs(void)
6645{
6646 char path[64];
6647 char name_buf[16];
6648 FILE *input;
6649 int state;
6650 char *sp;
6651
0748eaf0 6652 for (state = 10; state >= 0; --state) {
41618e63 6653
1b439f01 6654 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 6655 input = fopen(path, "r");
6656 if (input == NULL)
6657 continue;
8173c336
BH		 6658 if (!fgets(name_buf, sizeof(name_buf), input))
6659 err(1, "%s: failed to read file", path);
41618e63 6660
1b439f01 6661 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 6662 sp = strchr(name_buf, '-');
6663 if (!sp)
6664 sp = strchrnul(name_buf, '\n');
6665 *sp = '%';
6666 *(sp + 1) = '\0';
6667
fecb3bc8
DA		 6668 remove_underbar(name_buf);
6669
41618e63
LB		 6670 fclose(input);
6671
6672 sprintf(path, "cpuidle/state%d/time", state);
6673
0fc521bc
ZLCH		 6674 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6675 continue;
6676
dd778a5e
LB		 6677 if (is_deferred_skip(name_buf))
6678 continue;
6679
1b439f01 6680 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU);
41618e63
LB		 6681 }
6682
0748eaf0 6683 for (state = 10; state >= 0; --state) {
41618e63 6684
1b439f01 6685 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 6686 input = fopen(path, "r");
6687 if (input == NULL)
6688 continue;
8173c336
BH		 6689 if (!fgets(name_buf, sizeof(name_buf), input))
6690 err(1, "%s: failed to read file", path);
1b439f01 6691 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 6692 sp = strchr(name_buf, '-');
6693 if (!sp)
6694 sp = strchrnul(name_buf, '\n');
6695 *sp = '\0';
6696 fclose(input);
fecb3bc8
DA		 6697
6698 remove_underbar(name_buf);
41618e63
LB		 6699
6700 sprintf(path, "cpuidle/state%d/usage", state);
6701
0fc521bc
ZLCH		 6702 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6703 continue;
6704
dd778a5e
LB		 6705 if (is_deferred_skip(name_buf))
6706 continue;
6707
1b439f01 6708 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU);
41618e63
LB		 6709 }
6710
6711}
6712
1ef7d21a
LB		 6713/*
6714 * parse cpuset with following syntax
6715 * 1,2,4..6,8-10 and set bits in cpu_subset
6716 */
6717void parse_cpu_command(char *optarg)
6718{
6719 unsigned int start, end;
6720 char *next;
6721
4e4e1e7c
LB		 6722 if (!strcmp(optarg, "core")) {
6723 if (cpu_subset)
6724 goto error;
6725 show_core_only++;
6726 return;
6727 }
6728 if (!strcmp(optarg, "package")) {
6729 if (cpu_subset)
6730 goto error;
6731 show_pkg_only++;
6732 return;
6733 }
6734 if (show_core_only || show_pkg_only)
6735 goto error;
6736
1ef7d21a
LB		 6737 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
6738 if (cpu_subset == NULL)
6739 err(3, "CPU_ALLOC");
6740 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
6741
6742 CPU_ZERO_S(cpu_subset_size, cpu_subset);
6743
6744 next = optarg;
6745
6746 while (next && *next) {
6747
6748 if (*next == '-') /* no negative cpu numbers */
6749 goto error;
6750
6751 start = strtoul(next, &next, 10);
6752
6753 if (start >= CPU_SUBSET_MAXCPUS)
6754 goto error;
6755 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6756
6757 if (*next == '\0')
6758 break;
6759
6760 if (*next == ',') {
6761 next += 1;
6762 continue;
6763 }
6764
6765 if (*next == '-') {
6766 next += 1; /* start range */
6767 } else if (*next == '.') {
6768 next += 1;
6769 if (*next == '.')
6770 next += 1; /* start range */
6771 else
6772 goto error;
6773 }
6774
6775 end = strtoul(next, &next, 10);
6776 if (end <= start)
6777 goto error;
6778
6779 while (++start <= end) {
6780 if (start >= CPU_SUBSET_MAXCPUS)
6781 goto error;
6782 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6783 }
6784
6785 if (*next == ',')
6786 next += 1;
6787 else if (*next != '\0')
6788 goto error;
6789 }
6790
6791 return;
6792
6793error:
4e4e1e7c
LB		 6794 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
6795 help();
1ef7d21a
LB		 6796 exit(-1);
6797}
6798
103a8fea
LB		 6799void cmdline(int argc, char **argv)
6800{
6801 int opt;
d8af6f5f
LB		 6802 int option_index = 0;
6803 static struct option long_options[] = {
1b439f01
LB		 6804 { "add", required_argument, 0, 'a' },
6805 { "cpu", required_argument, 0, 'c' },
6806 { "Dump", no_argument, 0, 'D' },
6807 { "debug", no_argument, 0, 'd' }, /* internal, not documented */
6808 { "enable", required_argument, 0, 'e' },
6809 { "interval", required_argument, 0, 'i' },
6810 { "IPC", no_argument, 0, 'I' },
6811 { "num_iterations", required_argument, 0, 'n' },
c7e399f8 6812 { "header_iterations", required_argument, 0, 'N' },
1b439f01
LB		 6813 { "help", no_argument, 0, 'h' },
6814 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help
6815 { "Joules", no_argument, 0, 'J' },
6816 { "list", no_argument, 0, 'l' },
6817 { "out", required_argument, 0, 'o' },
6818 { "quiet", no_argument, 0, 'q' },
6819 { "show", required_argument, 0, 's' },
6820 { "Summary", no_argument, 0, 'S' },
6821 { "TCC", required_argument, 0, 'T' },
6822 { "version", no_argument, 0, 'v' },
6823 { 0, 0, 0, 0 }
d8af6f5f 6824 };
103a8fea
LB		 6825
6826 progname = argv[0];
6827
1b439f01 6828 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) {
103a8fea 6829 switch (opt) {
388e9c81
LB		 6830 case 'a':
6831 parse_add_command(optarg);
6832 break;
1ef7d21a
LB		 6833 case 'c':
6834 parse_cpu_command(optarg);
6835 break;
d8af6f5f 6836 case 'D':
3b4d5c7f
AS		 6837 dump_only++;
6838 break;
3f44a5c6
LB		 6839 case 'e':
6840 /* --enable specified counter */
4c2122d4 6841 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
3f44a5c6 6842 break;
d8af6f5f
LB		 6843 case 'd':
6844 debug++;
3f44a5c6 6845 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
103a8fea 6846 break;
812db3f7 6847 case 'H':
3f44a5c6
LB		 6848 /*
6849 * --hide: do not show those specified
6850 * multiple invocations simply clear more bits in enabled mask
6851 */
6852 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
812db3f7 6853 break;
d8af6f5f
LB		 6854 case 'h':
6855 default:
6856 help();
6857 exit(1);
103a8fea 6858 case 'i':
2a0609c0
LB		 6859 {
6860 double interval = strtod(optarg, NULL);
6861
6862 if (interval < 0.001) {
1b439f01 6863 fprintf(outf, "interval %f seconds is too small\n", interval);
2a0609c0
LB		 6864 exit(2);
6865 }
6866
47936f94 6867 interval_tv.tv_sec = interval_ts.tv_sec = interval;
b9ad8ee0 6868 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
47936f94 6869 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
2a0609c0 6870 }
103a8fea 6871 break;
d8af6f5f
LB		 6872 case 'J':
6873 rapl_joules++;
8e180f3c 6874 break;
c8ade361 6875 case 'l':
3f44a5c6 6876 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
c8ade361
LB		 6877 list_header_only++;
6878 quiet++;
6879 break;
b7d8c148
LB		 6880 case 'o':
6881 outf = fopen_or_die(optarg, "w");
6882 break;
96e47158
LB		 6883 case 'q':
6884 quiet = 1;
6885 break;
023fe0ac
CY		 6886 case 'n':
6887 num_iterations = strtod(optarg, NULL);
6888
6889 if (num_iterations <= 0) {
1b439f01 6890 fprintf(outf, "iterations %d should be positive number\n", num_iterations);
023fe0ac
CY		 6891 exit(2);
6892 }
6893 break;
c7e399f8
ZLCH		 6894 case 'N':
6895 header_iterations = strtod(optarg, NULL);
6896
6897 if (header_iterations <= 0) {
164d7a96 6898 fprintf(outf, "iterations %d should be positive number\n", header_iterations);
c7e399f8 6899 exit(2);
023fe0ac
CY		 6900 }
6901 break;
812db3f7 6902 case 's':
3f44a5c6
LB		 6903 /*
6904 * --show: show only those specified
6905 * The 1st invocation will clear and replace the enabled mask
6906 * subsequent invocations can add to it.
6907 */
6908 if (shown == 0)
6909 bic_enabled = bic_lookup(optarg, SHOW_LIST);
6910 else
6911 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
6912 shown = 1;
812db3f7 6913 break;
d8af6f5f
LB		 6914 case 'S':
6915 summary_only++;
889facbe
LB		 6916 break;
6917 case 'T':
55279aef 6918 tj_max_override = atoi(optarg);
889facbe 6919 break;
d8af6f5f
LB		 6920 case 'v':
6921 print_version();
6922 exit(0);
5c56be9a 6923 break;
103a8fea
LB		 6924 }
6925 }
6926}
6927
6928int main(int argc, char **argv)
6929{
b7d8c148 6930 outf = stderr;
103a8fea
LB		 6931 cmdline(argc, argv);
6932
03331233 6933 if (!quiet) {
d8af6f5f 6934 print_version();
03331233
CY		 6935 print_bootcmd();
6936 }
103a8fea 6937
41618e63
LB		 6938 probe_sysfs();
6939
103a8fea
LB		 6940 turbostat_init();
6941
6799ba84
DM		 6942 msr_sum_record();
6943
3b4d5c7f
AS		 6944 /* dump counters and exit */
6945 if (dump_only)
6946 return get_and_dump_counters();
6947
c8ade361
LB		 6948 /* list header and exit */
6949 if (list_header_only) {
6950 print_header(",");
6951 flush_output_stdout();
6952 return 0;
6953 }
6954
103a8fea
LB		 6955 /*
6956 * if any params left, it must be a command to fork
6957 */
6958 if (argc - optind)
6959 return fork_it(argv + optind);
6960 else
6961 turbostat_loop();
6962
6963 return 0;
6964}
Linux 6.x block layer and io_uring tree(s)