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tools/power turbostat: fix decoding of HWP_STATUS
[linux-block.git] / tools / power / x86 / turbostat / turbostat.c
CommitLineData
a61127c2 1// SPDX-License-Identifier: GPL-2.0-only
103a8fea
LB		 2/*
3 * turbostat -- show CPU frequency and C-state residency
34041551 4 * on modern Intel and AMD processors.
103a8fea 5 *
58990892 6 * Copyright (c) 2022 Intel Corporation.
103a8fea 7 * Len Brown <len.brown@intel.com>
103a8fea
LB		 8 */
9
88c3281f 10#define _GNU_SOURCE
b731f311 11#include MSRHEADER
869ce69e 12#include INTEL_FAMILY_HEADER
95aebc44 13#include <stdarg.h>
103a8fea 14#include <stdio.h>
b2c95d90 15#include <err.h>
103a8fea
LB		 16#include <unistd.h>
17#include <sys/types.h>
18#include <sys/wait.h>
19#include <sys/stat.h>
b9ad8ee0 20#include <sys/select.h>
103a8fea
LB		 21#include <sys/resource.h>
22#include <fcntl.h>
23#include <signal.h>
24#include <sys/time.h>
25#include <stdlib.h>
d8af6f5f 26#include <getopt.h>
103a8fea
LB		 27#include <dirent.h>
28#include <string.h>
29#include <ctype.h>
88c3281f 30#include <sched.h>
2a0609c0 31#include <time.h>
2b92865e 32#include <cpuid.h>
fcaa681c 33#include <sys/capability.h>
98481e79 34#include <errno.h>
9392bd98 35#include <math.h>
2af4f9b8
LB		 36#include <linux/perf_event.h>
37#include <asm/unistd.h>
7ab5ff49 38#include <stdbool.h>
103a8fea 39
9878bf7a
LB		 40#define UNUSED(x) (void)(x)
41
164d7a96
LB		 42/*
43 * This list matches the column headers, except
44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
45 * 2. Core and CPU are moved to the end, we can't have strings that contain them
46 * matching on them for --show and --hide.
47 */
48
49/*
50 * buffer size used by sscanf() for added column names
51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
52 */
53#define NAME_BYTES 20
54#define PATH_BYTES 128
55
56enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE };
57enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC };
58enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT };
59
60struct msr_counter {
61 unsigned int msr_num;
62 char name[NAME_BYTES];
63 char path[PATH_BYTES];
64 unsigned int width;
65 enum counter_type type;
66 enum counter_format format;
67 struct msr_counter *next;
68 unsigned int flags;
69#define FLAGS_HIDE (1 << 0)
70#define FLAGS_SHOW (1 << 1)
71#define SYSFS_PERCPU (1 << 1)
72};
73
74struct msr_counter bic[] = {
9878bf7a
LB		 75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 },
76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 },
77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 },
78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 },
79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 },
80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 },
81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 },
82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 },
83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 },
84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 },
85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 },
86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 },
87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 },
88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 },
89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 },
90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 },
91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 },
92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 },
93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 },
94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 },
95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 },
96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 },
97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 },
98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 },
99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 },
100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 },
101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 },
102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 },
103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 },
104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 },
105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 },
106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 },
107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 },
108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 },
109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 },
110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 },
111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 },
112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 },
113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 },
114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 },
115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 },
116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 },
117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 },
118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 },
119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 },
120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 },
121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 },
122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 },
123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 },
124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 },
125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 },
126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 },
127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 },
128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 },
a5c6d65d 129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 },
164d7a96
LB		 130};
131
132#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
133#define BIC_USEC (1ULL << 0)
134#define BIC_TOD (1ULL << 1)
135#define BIC_Package (1ULL << 2)
136#define BIC_Node (1ULL << 3)
137#define BIC_Avg_MHz (1ULL << 4)
138#define BIC_Busy (1ULL << 5)
139#define BIC_Bzy_MHz (1ULL << 6)
140#define BIC_TSC_MHz (1ULL << 7)
141#define BIC_IRQ (1ULL << 8)
142#define BIC_SMI (1ULL << 9)
143#define BIC_sysfs (1ULL << 10)
144#define BIC_CPU_c1 (1ULL << 11)
145#define BIC_CPU_c3 (1ULL << 12)
146#define BIC_CPU_c6 (1ULL << 13)
147#define BIC_CPU_c7 (1ULL << 14)
148#define BIC_ThreadC (1ULL << 15)
149#define BIC_CoreTmp (1ULL << 16)
150#define BIC_CoreCnt (1ULL << 17)
151#define BIC_PkgTmp (1ULL << 18)
152#define BIC_GFX_rc6 (1ULL << 19)
153#define BIC_GFXMHz (1ULL << 20)
154#define BIC_Pkgpc2 (1ULL << 21)
155#define BIC_Pkgpc3 (1ULL << 22)
156#define BIC_Pkgpc6 (1ULL << 23)
157#define BIC_Pkgpc7 (1ULL << 24)
158#define BIC_Pkgpc8 (1ULL << 25)
159#define BIC_Pkgpc9 (1ULL << 26)
160#define BIC_Pkgpc10 (1ULL << 27)
161#define BIC_CPU_LPI (1ULL << 28)
162#define BIC_SYS_LPI (1ULL << 29)
163#define BIC_PkgWatt (1ULL << 30)
164#define BIC_CorWatt (1ULL << 31)
165#define BIC_GFXWatt (1ULL << 32)
166#define BIC_PkgCnt (1ULL << 33)
167#define BIC_RAMWatt (1ULL << 34)
168#define BIC_PKG__ (1ULL << 35)
169#define BIC_RAM__ (1ULL << 36)
170#define BIC_Pkg_J (1ULL << 37)
171#define BIC_Cor_J (1ULL << 38)
172#define BIC_GFX_J (1ULL << 39)
173#define BIC_RAM_J (1ULL << 40)
174#define BIC_Mod_c6 (1ULL << 41)
175#define BIC_Totl_c0 (1ULL << 42)
176#define BIC_Any_c0 (1ULL << 43)
177#define BIC_GFX_c0 (1ULL << 44)
178#define BIC_CPUGFX (1ULL << 45)
179#define BIC_Core (1ULL << 46)
180#define BIC_CPU (1ULL << 47)
181#define BIC_APIC (1ULL << 48)
182#define BIC_X2APIC (1ULL << 49)
183#define BIC_Die (1ULL << 50)
184#define BIC_GFXACTMHz (1ULL << 51)
185#define BIC_IPC (1ULL << 52)
186#define BIC_CORE_THROT_CNT (1ULL << 53)
a5c6d65d 187#define BIC_UNCORE_MHZ (1ULL << 54)
164d7a96
LB		 188
189#define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die )
190#define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__)
a5c6d65d 191#define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ)
164d7a96
LB		 192#define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX)
193#define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC)
194
195#define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
196
197unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
198unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
199
200#define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
201#define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
202#define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
203#define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
204#define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
205#define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT)
206
103a8fea 207char *proc_stat = "/proc/stat";
b7d8c148 208FILE *outf;
36229897 209int *fd_percpu;
2af4f9b8 210int *fd_instr_count_percpu;
1b439f01
LB		 211struct timeval interval_tv = { 5, 0 };
212struct timespec interval_ts = { 5, 0 };
e9d3092f
ZR		 213
214/* Save original CPU model */
215unsigned int model_orig;
216
023fe0ac 217unsigned int num_iterations;
c7e399f8 218unsigned int header_iterations;
d8af6f5f 219unsigned int debug;
96e47158 220unsigned int quiet;
3f44a5c6 221unsigned int shown;
0de6c0df 222unsigned int sums_need_wide_columns;
d8af6f5f
LB		 223unsigned int rapl_joules;
224unsigned int summary_only;
c8ade361 225unsigned int list_header_only;
d8af6f5f 226unsigned int dump_only;
103a8fea 227unsigned int do_snb_cstates;
fb5d4327 228unsigned int do_knl_cstates;
144b44b1
LB		 229unsigned int do_slm_cstates;
230unsigned int use_c1_residency_msr;
103a8fea 231unsigned int has_aperf;
889facbe 232unsigned int has_epb;
3ea8e52e 233unsigned int has_turbo;
774627c5 234unsigned int is_hybrid;
5a63426e
LB		 235unsigned int do_irtl_snb;
236unsigned int do_irtl_hsw;
fc04cc67 237unsigned int units = 1000000; /* MHz etc */
103a8fea 238unsigned int genuine_intel;
34041551 239unsigned int authentic_amd;
c1c10cc7 240unsigned int hygon_genuine;
34041551 241unsigned int max_level, max_extended_level;
103a8fea 242unsigned int has_invariant_tsc;
d7899447 243unsigned int do_nhm_platform_info;
cf4cbe53 244unsigned int no_MSR_MISC_PWR_MGMT;
b2b34dfe 245unsigned int aperf_mperf_multiplier = 1;
103a8fea 246double bclk;
a2b7b749 247double base_hz;
21ed5574 248unsigned int has_base_hz;
a2b7b749 249double tsc_tweak = 1.0;
c98d5d94
LB		 250unsigned int show_pkg_only;
251unsigned int show_core_only;
252char *output_buffer, *outp;
889facbe
LB		 253unsigned int do_rapl;
254unsigned int do_dts;
255unsigned int do_ptm;
2af4f9b8 256unsigned int do_ipc;
1b439f01 257unsigned long long gfx_cur_rc6_ms;
be0e54c4
LB		 258unsigned long long cpuidle_cur_cpu_lpi_us;
259unsigned long long cpuidle_cur_sys_lpi_us;
27d47356 260unsigned int gfx_cur_mhz;
b4b91569 261unsigned int gfx_act_mhz;
55279aef
ZR		 262unsigned int tj_max;
263unsigned int tj_max_override;
0b9a0b9b 264int tcc_offset_bits;
40ee8e3b
AS		 265double rapl_power_units, rapl_time_units;
266double rapl_dram_energy_units, rapl_energy_units;
889facbe 267double rapl_joule_counter_range;
3a9a941d 268unsigned int do_core_perf_limit_reasons;
ac980e13 269unsigned int has_automatic_cstate_conversion;
aeb01e6d 270unsigned int dis_cstate_prewake;
3a9a941d
LB		 271unsigned int do_gfx_perf_limit_reasons;
272unsigned int do_ring_perf_limit_reasons;
8a5bdf41
LB		 273unsigned int crystal_hz;
274unsigned long long tsc_hz;
7ce7d5de 275int base_cpu;
21ed5574 276double discover_bclk(unsigned int family, unsigned int model);
1b439f01 277unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
7f5c258e 278 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
1b439f01 279unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
7f5c258e 280unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
1b439f01
LB		 281unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
282unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
33148d67 283unsigned int has_misc_feature_control;
4c2122d4 284unsigned int first_counter_read = 1;
c026c236 285int ignore_stdin;
889facbe 286
e6f9bb3c
LB		 287#define RAPL_PKG (1 << 0)
288 /* 0x610 MSR_PKG_POWER_LIMIT */
289 /* 0x611 MSR_PKG_ENERGY_STATUS */
290#define RAPL_PKG_PERF_STATUS (1 << 1)
291 /* 0x613 MSR_PKG_PERF_STATUS */
292#define RAPL_PKG_POWER_INFO (1 << 2)
293 /* 0x614 MSR_PKG_POWER_INFO */
294
295#define RAPL_DRAM (1 << 3)
296 /* 0x618 MSR_DRAM_POWER_LIMIT */
297 /* 0x619 MSR_DRAM_ENERGY_STATUS */
e6f9bb3c
LB		 298#define RAPL_DRAM_PERF_STATUS (1 << 4)
299 /* 0x61b MSR_DRAM_PERF_STATUS */
0b2bb692
LB		 300#define RAPL_DRAM_POWER_INFO (1 << 5)
301 /* 0x61c MSR_DRAM_POWER_INFO */
e6f9bb3c 302
9148494c 303#define RAPL_CORES_POWER_LIMIT (1 << 6)
e6f9bb3c 304 /* 0x638 MSR_PP0_POWER_LIMIT */
0b2bb692 305#define RAPL_CORE_POLICY (1 << 7)
e6f9bb3c
LB		 306 /* 0x63a MSR_PP0_POLICY */
307
0b2bb692 308#define RAPL_GFX (1 << 8)
e6f9bb3c
LB		 309 /* 0x640 MSR_PP1_POWER_LIMIT */
310 /* 0x641 MSR_PP1_ENERGY_STATUS */
311 /* 0x642 MSR_PP1_POLICY */
9148494c
JP		 312
313#define RAPL_CORES_ENERGY_STATUS (1 << 9)
314 /* 0x639 MSR_PP0_ENERGY_STATUS */
9392bd98
CW		 315#define RAPL_PER_CORE_ENERGY (1 << 10)
316 /* Indicates cores energy collection is per-core,
317 * not per-package. */
318#define RAPL_AMD_F17H (1 << 11)
319 /* 0xc0010299 MSR_RAPL_PWR_UNIT */
320 /* 0xc001029a MSR_CORE_ENERGY_STAT */
321 /* 0xc001029b MSR_PKG_ENERGY_STAT */
9148494c 322#define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
889facbe
LB		 323#define TJMAX_DEFAULT 100
324
9392bd98
CW		 325/* MSRs that are not yet in the kernel-provided header. */
326#define MSR_RAPL_PWR_UNIT 0xc0010299
327#define MSR_CORE_ENERGY_STAT 0xc001029a
328#define MSR_PKG_ENERGY_STAT 0xc001029b
329
889facbe 330#define MAX(a, b) ((a) > (b) ? (a) : (b))
103a8fea 331
103a8fea
LB		 332int backwards_count;
333char *progname;
103a8fea 334
1ef7d21a
LB		 335#define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
336cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
337size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
0748eaf0
LB		 338#define MAX_ADDED_COUNTERS 8
339#define MAX_ADDED_THREAD_COUNTERS 24
0e2d8f05 340#define BITMASK_SIZE 32
c98d5d94
LB		 341
342struct thread_data {
f4fdf2b4
LB		 343 struct timeval tv_begin;
344 struct timeval tv_end;
d4794f25 345 struct timeval tv_delta;
c98d5d94
LB		 346 unsigned long long tsc;
347 unsigned long long aperf;
348 unsigned long long mperf;
144b44b1 349 unsigned long long c1;
2af4f9b8 350 unsigned long long instr_count;
1b439f01 351 unsigned long long irq_count;
1ed51011 352 unsigned int smi_count;
c98d5d94 353 unsigned int cpu_id;
4c2122d4
LB		 354 unsigned int apic_id;
355 unsigned int x2apic_id;
c98d5d94 356 unsigned int flags;
7ab5ff49 357 bool is_atom;
c98d5d94
LB		 358#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
359#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
0748eaf0 360 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
c98d5d94
LB		 361} *thread_even, *thread_odd;
362
363struct core_data {
364 unsigned long long c3;
365 unsigned long long c6;
366 unsigned long long c7;
0539ba11 367 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
889facbe 368 unsigned int core_temp_c;
9392bd98 369 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
c98d5d94 370 unsigned int core_id;
eae97e05 371 unsigned long long core_throt_cnt;
678a3bd1 372 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 373} *core_even, *core_odd;
374
375struct pkg_data {
376 unsigned long long pc2;
377 unsigned long long pc3;
378 unsigned long long pc6;
379 unsigned long long pc7;
ca58710f
KCA		 380 unsigned long long pc8;
381 unsigned long long pc9;
382 unsigned long long pc10;
be0e54c4
LB		 383 unsigned long long cpu_lpi;
384 unsigned long long sys_lpi;
0b2bb692
LB		 385 unsigned long long pkg_wtd_core_c0;
386 unsigned long long pkg_any_core_c0;
387 unsigned long long pkg_any_gfxe_c0;
388 unsigned long long pkg_both_core_gfxe_c0;
9185e988 389 long long gfx_rc6_ms;
27d47356 390 unsigned int gfx_mhz;
b4b91569 391 unsigned int gfx_act_mhz;
c98d5d94 392 unsigned int package_id;
7c2ccc50
CY		 393 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */
394 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */
395 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */
396 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */
397 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
398 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
889facbe 399 unsigned int pkg_temp_c;
a5c6d65d 400 unsigned int uncore_mhz;
678a3bd1 401 unsigned long long counter[MAX_ADDED_COUNTERS];
c98d5d94
LB		 402} *package_even, *package_odd;
403
404#define ODD_COUNTERS thread_odd, core_odd, package_odd
405#define EVEN_COUNTERS thread_even, core_even, package_even
406
40f5cfe7
PB		 407#define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
408 ((thread_base) + \
409 ((pkg_no) * \
410 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
411 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
412 ((core_no) * topo.threads_per_core) + \
413 (thread_no))
414
415#define GET_CORE(core_base, core_no, node_no, pkg_no) \
416 ((core_base) + \
417 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
418 ((node_no) * topo.cores_per_node) + \
419 (core_no))
420
c98d5d94
LB		 421#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
422
87e15da9
CY		 423/*
424 * The accumulated sum of MSR is defined as a monotonic
425 * increasing MSR, it will be accumulated periodically,
426 * despite its register's bit width.
427 */
428enum {
429 IDX_PKG_ENERGY,
430 IDX_DRAM_ENERGY,
431 IDX_PP0_ENERGY,
432 IDX_PP1_ENERGY,
433 IDX_PKG_PERF,
434 IDX_DRAM_PERF,
435 IDX_COUNT,
436};
437
438int get_msr_sum(int cpu, off_t offset, unsigned long long *msr);
439
440struct msr_sum_array {
441 /* get_msr_sum() = sum + (get_msr() - last) */
442 struct {
1b439f01 443 /*The accumulated MSR value is updated by the timer */
87e15da9 444 unsigned long long sum;
1b439f01 445 /*The MSR footprint recorded in last timer */
87e15da9
CY		 446 unsigned long long last;
447 } entries[IDX_COUNT];
448};
449
450/* The percpu MSR sum array.*/
451struct msr_sum_array *per_cpu_msr_sum;
452
13a779de 453off_t idx_to_offset(int idx)
87e15da9 454{
13a779de 455 off_t offset;
87e15da9
CY		 456
457 switch (idx) {
458 case IDX_PKG_ENERGY:
301b1d3a
BN		 459 if (do_rapl & RAPL_AMD_F17H)
460 offset = MSR_PKG_ENERGY_STAT;
461 else
462 offset = MSR_PKG_ENERGY_STATUS;
87e15da9
CY		 463 break;
464 case IDX_DRAM_ENERGY:
465 offset = MSR_DRAM_ENERGY_STATUS;
466 break;
467 case IDX_PP0_ENERGY:
468 offset = MSR_PP0_ENERGY_STATUS;
469 break;
470 case IDX_PP1_ENERGY:
471 offset = MSR_PP1_ENERGY_STATUS;
472 break;
473 case IDX_PKG_PERF:
474 offset = MSR_PKG_PERF_STATUS;
475 break;
476 case IDX_DRAM_PERF:
477 offset = MSR_DRAM_PERF_STATUS;
478 break;
479 default:
480 offset = -1;
481 }
482 return offset;
483}
484
13a779de 485int offset_to_idx(off_t offset)
87e15da9
CY		 486{
487 int idx;
488
489 switch (offset) {
490 case MSR_PKG_ENERGY_STATUS:
301b1d3a 491 case MSR_PKG_ENERGY_STAT:
87e15da9
CY		 492 idx = IDX_PKG_ENERGY;
493 break;
494 case MSR_DRAM_ENERGY_STATUS:
495 idx = IDX_DRAM_ENERGY;
496 break;
497 case MSR_PP0_ENERGY_STATUS:
498 idx = IDX_PP0_ENERGY;
499 break;
500 case MSR_PP1_ENERGY_STATUS:
501 idx = IDX_PP1_ENERGY;
502 break;
503 case MSR_PKG_PERF_STATUS:
504 idx = IDX_PKG_PERF;
505 break;
506 case MSR_DRAM_PERF_STATUS:
507 idx = IDX_DRAM_PERF;
508 break;
509 default:
510 idx = -1;
511 }
512 return idx;
513}
514
515int idx_valid(int idx)
516{
517 switch (idx) {
518 case IDX_PKG_ENERGY:
301b1d3a 519 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H);
87e15da9
CY		 520 case IDX_DRAM_ENERGY:
521 return do_rapl & RAPL_DRAM;
522 case IDX_PP0_ENERGY:
523 return do_rapl & RAPL_CORES_ENERGY_STATUS;
524 case IDX_PP1_ENERGY:
525 return do_rapl & RAPL_GFX;
526 case IDX_PKG_PERF:
527 return do_rapl & RAPL_PKG_PERF_STATUS;
528 case IDX_DRAM_PERF:
529 return do_rapl & RAPL_DRAM_PERF_STATUS;
530 default:
531 return 0;
532 }
533}
1b439f01 534
388e9c81 535struct sys_counters {
678a3bd1
LB		 536 unsigned int added_thread_counters;
537 unsigned int added_core_counters;
538 unsigned int added_package_counters;
388e9c81
LB		 539 struct msr_counter *tp;
540 struct msr_counter *cp;
541 struct msr_counter *pp;
542} sys;
543
c98d5d94
LB		 544struct system_summary {
545 struct thread_data threads;
546 struct core_data cores;
547 struct pkg_data packages;
388e9c81 548} average;
c98d5d94 549
0e2d8f05
LB		 550struct cpu_topology {
551 int physical_package_id;
6de68fe1 552 int die_id;
0e2d8f05 553 int logical_cpu_id;
ef605741
PB		 554 int physical_node_id;
555 int logical_node_id; /* 0-based count within the package */
0e2d8f05 556 int physical_core_id;
8cb48b32 557 int thread_id;
1b439f01 558 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
0e2d8f05 559} *cpus;
c98d5d94
LB		 560
561struct topo_params {
562 int num_packages;
6de68fe1 563 int num_die;
c98d5d94
LB		 564 int num_cpus;
565 int num_cores;
566 int max_cpu_num;
ef605741 567 int max_node_num;
70a9c6e8
PB		 568 int nodes_per_pkg;
569 int cores_per_node;
570 int threads_per_core;
c98d5d94
LB		 571} topo;
572
573struct timeval tv_even, tv_odd, tv_delta;
574
1b439f01 575int *irq_column_2_cpu; /* /proc/interrupts column numbers */
562a2d37
LB		 576int *irqs_per_cpu; /* indexed by cpu_num */
577
c98d5d94
LB		 578void setup_all_buffers(void);
579
1f81c5ef
LB		 580char *sys_lpi_file;
581char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
582char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
583
c98d5d94 584int cpu_is_not_present(int cpu)
d15cf7c1 585{
c98d5d94 586 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
d15cf7c1 587}
1b439f01 588
88c3281f 589/*
c98d5d94
LB		 590 * run func(thread, core, package) in topology order
591 * skip non-present cpus
88c3281f 592 */
c98d5d94 593
1b439f01
LB		 594int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *),
595 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
88c3281f 596{
40f5cfe7 597 int retval, pkg_no, core_no, thread_no, node_no;
d15cf7c1 598
c98d5d94 599 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
df2f677d
LB		 600 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
601 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
1b439f01 602 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
40f5cfe7
PB		 603 struct thread_data *t;
604 struct core_data *c;
605 struct pkg_data *p;
606
1b439f01 607 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
40f5cfe7
PB		 608
609 if (cpu_is_not_present(t->cpu_id))
610 continue;
611
1b439f01 612 c = GET_CORE(core_base, core_no, node_no, pkg_no);
40f5cfe7
PB		 613 p = GET_PKG(pkg_base, pkg_no);
614
615 retval = func(t, c, p);
616 if (retval)
617 return retval;
618 }
c98d5d94
LB		 619 }
620 }
621 }
622 return 0;
88c3281f
LB		 623}
624
625int cpu_migrate(int cpu)
626{
c98d5d94
LB		 627 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
628 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
629 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
88c3281f
LB		 630 return -1;
631 else
632 return 0;
633}
1b439f01 634
36229897 635int get_msr_fd(int cpu)
103a8fea 636{
103a8fea
LB		 637 char pathname[32];
638 int fd;
639
36229897
LB		 640 fd = fd_percpu[cpu];
641
642 if (fd)
643 return fd;
644
103a8fea
LB		 645 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
646 fd = open(pathname, O_RDONLY);
15aaa346 647 if (fd < 0)
98481e79 648 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
103a8fea 649
36229897
LB		 650 fd_percpu[cpu] = fd;
651
652 return fd;
653}
654
2af4f9b8
LB		 655static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
656{
657 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags);
658}
659
660static int perf_instr_count_open(int cpu_num)
661{
662 struct perf_event_attr pea;
663 int fd;
664
665 memset(&pea, 0, sizeof(struct perf_event_attr));
666 pea.type = PERF_TYPE_HARDWARE;
667 pea.size = sizeof(struct perf_event_attr);
668 pea.config = PERF_COUNT_HW_INSTRUCTIONS;
669
670 /* counter for cpu_num, including user + kernel and all processes */
671 fd = perf_event_open(&pea, -1, cpu_num, -1, 0);
164d7a96 672 if (fd == -1) {
9c085817
PB		 673 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"",
674 progname);
164d7a96
LB		 675 BIC_NOT_PRESENT(BIC_IPC);
676 }
2af4f9b8
LB		 677
678 return fd;
679}
680
681int get_instr_count_fd(int cpu)
682{
683 if (fd_instr_count_percpu[cpu])
684 return fd_instr_count_percpu[cpu];
685
686 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu);
687
688 return fd_instr_count_percpu[cpu];
689}
690
36229897
LB		 691int get_msr(int cpu, off_t offset, unsigned long long *msr)
692{
693 ssize_t retval;
694
695 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
15aaa346 696
98481e79 697 if (retval != sizeof *msr)
cf4cbe53 698 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
15aaa346
LB		 699
700 return 0;
103a8fea
LB		 701}
702
dd778a5e 703#define MAX_DEFERRED 16
0fc521bc 704char *deferred_add_names[MAX_DEFERRED];
dd778a5e 705char *deferred_skip_names[MAX_DEFERRED];
0fc521bc 706int deferred_add_index;
dd778a5e
LB		 707int deferred_skip_index;
708
709/*
710 * HIDE_LIST - hide this list of counters, show the rest [default]
711 * SHOW_LIST - show this list of counters, hide the rest
712 */
713enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
714
715void help(void)
716{
717 fprintf(outf,
1b439f01
LB		 718 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
719 "\n"
720 "Turbostat forks the specified COMMAND and prints statistics\n"
721 "when COMMAND completes.\n"
722 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
723 "to print statistics, until interrupted.\n"
724 " -a, --add add a counter\n"
725 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
726 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
727 " {core | package | j,k,l..m,n-p }\n"
728 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
729 " -D, --Dump displays the raw counter values\n"
730 " -e, --enable [all | column]\n"
731 " shows all or the specified disabled column\n"
732 " -H, --hide [column|column,column,...]\n"
733 " hide the specified column(s)\n"
734 " -i, --interval sec.subsec\n"
735 " Override default 5-second measurement interval\n"
736 " -J, --Joules displays energy in Joules instead of Watts\n"
737 " -l, --list list column headers only\n"
738 " -n, --num_iterations num\n"
739 " number of the measurement iterations\n"
c7e399f8
ZLCH		 740 " -N, --header_iterations num\n"
741 " print header every num iterations\n"
1b439f01
LB		 742 " -o, --out file\n"
743 " create or truncate \"file\" for all output\n"
744 " -q, --quiet skip decoding system configuration header\n"
745 " -s, --show [column|column,column,...]\n"
746 " show only the specified column(s)\n"
747 " -S, --Summary\n"
748 " limits output to 1-line system summary per interval\n"
749 " -T, --TCC temperature\n"
750 " sets the Thermal Control Circuit temperature in\n"
751 " degrees Celsius\n"
752 " -h, --help print this help message\n"
753 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n");
dd778a5e
LB		 754}
755
812db3f7
LB		 756/*
757 * bic_lookup
758 * for all the strings in comma separate name_list,
759 * set the approprate bit in return value.
760 */
dd778a5e 761unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
812db3f7 762{
9878bf7a 763 unsigned int i;
812db3f7
LB		 764 unsigned long long retval = 0;
765
766 while (name_list) {
767 char *comma;
768
769 comma = strchr(name_list, ',');
770
771 if (comma)
772 *comma = '\0';
773
774 for (i = 0; i < MAX_BIC; ++i) {
775 if (!strcmp(name_list, bic[i].name)) {
776 retval |= (1ULL << i);
777 break;
778 }
5dc241f2
LB		 779 if (!strcmp(name_list, "all")) {
780 retval |= ~0;
781 break;
782 } else if (!strcmp(name_list, "topology")) {
783 retval |= BIC_TOPOLOGY;
784 break;
785 } else if (!strcmp(name_list, "power")) {
786 retval |= BIC_THERMAL_PWR;
787 break;
788 } else if (!strcmp(name_list, "idle")) {
789 retval |= BIC_IDLE;
790 break;
791 } else if (!strcmp(name_list, "frequency")) {
792 retval |= BIC_FREQUENCY;
793 break;
794 } else if (!strcmp(name_list, "other")) {
795 retval |= BIC_OTHER;
796 break;
797 }
798
812db3f7
LB		 799 }
800 if (i == MAX_BIC) {
dd778a5e 801 if (mode == SHOW_LIST) {
0fc521bc
ZLCH		 802 deferred_add_names[deferred_add_index++] = name_list;
803 if (deferred_add_index >= MAX_DEFERRED) {
804 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n",
164d7a96 805 MAX_DEFERRED, name_list);
0fc521bc
ZLCH		 806 help();
807 exit(1);
808 }
809 } else {
810 deferred_skip_names[deferred_skip_index++] = name_list;
811 if (debug)
812 fprintf(stderr, "deferred \"%s\"\n", name_list);
813 if (deferred_skip_index >= MAX_DEFERRED) {
814 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
164d7a96 815 MAX_DEFERRED, name_list);
0fc521bc
ZLCH		 816 help();
817 exit(1);
818 }
dd778a5e 819 }
812db3f7
LB		 820 }
821
822 name_list = comma;
823 if (name_list)
824 name_list++;
825
826 }
827 return retval;
828}
fc04cc67 829
c8ade361 830void print_header(char *delim)
103a8fea 831{
388e9c81 832 struct msr_counter *mp;
6168c2e0 833 int printed = 0;
388e9c81 834
3f44a5c6
LB		 835 if (DO_BIC(BIC_USEC))
836 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
837 if (DO_BIC(BIC_TOD))
838 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
812db3f7 839 if (DO_BIC(BIC_Package))
6168c2e0 840 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
6de68fe1
LB		 841 if (DO_BIC(BIC_Die))
842 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
01235041
PB		 843 if (DO_BIC(BIC_Node))
844 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
812db3f7 845 if (DO_BIC(BIC_Core))
6168c2e0 846 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
812db3f7 847 if (DO_BIC(BIC_CPU))
6168c2e0 848 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
4c2122d4
LB		 849 if (DO_BIC(BIC_APIC))
850 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
851 if (DO_BIC(BIC_X2APIC))
852 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
812db3f7 853 if (DO_BIC(BIC_Avg_MHz))
6168c2e0 854 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
812db3f7 855 if (DO_BIC(BIC_Busy))
6168c2e0 856 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
812db3f7 857 if (DO_BIC(BIC_Bzy_MHz))
6168c2e0 858 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
812db3f7 859 if (DO_BIC(BIC_TSC_MHz))
6168c2e0 860 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
1cc21f7b 861
2af4f9b8
LB		 862 if (DO_BIC(BIC_IPC))
863 outp += sprintf(outp, "%sIPC", (printed++ ? delim : ""));
864
0de6c0df
LB		 865 if (DO_BIC(BIC_IRQ)) {
866 if (sums_need_wide_columns)
6168c2e0 867 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
0de6c0df 868 else
6168c2e0 869 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
0de6c0df
LB		 870 }
871
812db3f7 872 if (DO_BIC(BIC_SMI))
6168c2e0 873 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
1cc21f7b 874
388e9c81 875 for (mp = sys.tp; mp; mp = mp->next) {
dd778a5e 876
388e9c81
LB		 877 if (mp->format == FORMAT_RAW) {
878 if (mp->width == 64)
dd778a5e 879 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
388e9c81 880 else
dd778a5e 881 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
388e9c81 882 } else {
0de6c0df 883 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
dd778a5e 884 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
0de6c0df 885 else
dd778a5e 886 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
388e9c81
LB		 887 }
888 }
889
41618e63 890 if (DO_BIC(BIC_CPU_c1))
6168c2e0 891 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
562855ee 892 if (DO_BIC(BIC_CPU_c3))
6168c2e0 893 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
812db3f7 894 if (DO_BIC(BIC_CPU_c6))
6168c2e0 895 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
812db3f7 896 if (DO_BIC(BIC_CPU_c7))
6168c2e0 897 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
678a3bd1 898
0539ba11 899 if (DO_BIC(BIC_Mod_c6))
6168c2e0 900 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
678a3bd1 901
812db3f7 902 if (DO_BIC(BIC_CoreTmp))
6168c2e0 903 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
388e9c81 904
eae97e05
CY		 905 if (DO_BIC(BIC_CORE_THROT_CNT))
906 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : ""));
907
9392bd98
CW		 908 if (do_rapl && !rapl_joules) {
909 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
910 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
911 } else if (do_rapl && rapl_joules) {
912 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
913 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
914 }
915
388e9c81
LB		 916 for (mp = sys.cp; mp; mp = mp->next) {
917 if (mp->format == FORMAT_RAW) {
918 if (mp->width == 64)
c8ade361 919 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
388e9c81 920 else
c8ade361 921 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
388e9c81 922 } else {
0de6c0df
LB		 923 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
924 outp += sprintf(outp, "%s%8s", delim, mp->name);
925 else
926 outp += sprintf(outp, "%s%s", delim, mp->name);
388e9c81
LB		 927 }
928 }
929
812db3f7 930 if (DO_BIC(BIC_PkgTmp))
6168c2e0 931 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
889facbe 932
812db3f7 933 if (DO_BIC(BIC_GFX_rc6))
6168c2e0 934 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
fdf676e5 935
812db3f7 936 if (DO_BIC(BIC_GFXMHz))
6168c2e0 937 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
27d47356 938
b4b91569
RA		 939 if (DO_BIC(BIC_GFXACTMHz))
940 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : ""));
941
a99d8730 942 if (DO_BIC(BIC_Totl_c0))
6168c2e0 943 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
a99d8730 944 if (DO_BIC(BIC_Any_c0))
6168c2e0 945 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
a99d8730 946 if (DO_BIC(BIC_GFX_c0))
6168c2e0 947 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
a99d8730 948 if (DO_BIC(BIC_CPUGFX))
6168c2e0 949 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
0b2bb692 950
0f47c08d 951 if (DO_BIC(BIC_Pkgpc2))
6168c2e0 952 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
0f47c08d 953 if (DO_BIC(BIC_Pkgpc3))
6168c2e0 954 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
0f47c08d 955 if (DO_BIC(BIC_Pkgpc6))
6168c2e0 956 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
0f47c08d 957 if (DO_BIC(BIC_Pkgpc7))
6168c2e0 958 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
0f47c08d 959 if (DO_BIC(BIC_Pkgpc8))
6168c2e0 960 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
0f47c08d 961 if (DO_BIC(BIC_Pkgpc9))
6168c2e0 962 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
0f47c08d 963 if (DO_BIC(BIC_Pkgpc10))
6168c2e0 964 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
be0e54c4
LB		 965 if (DO_BIC(BIC_CPU_LPI))
966 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
967 if (DO_BIC(BIC_SYS_LPI))
968 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
103a8fea 969
5c56be9a 970 if (do_rapl && !rapl_joules) {
812db3f7 971 if (DO_BIC(BIC_PkgWatt))
6168c2e0 972 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
9392bd98 973 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 974 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
812db3f7 975 if (DO_BIC(BIC_GFXWatt))
6168c2e0 976 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
812db3f7 977 if (DO_BIC(BIC_RAMWatt))
6168c2e0 978 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
812db3f7 979 if (DO_BIC(BIC_PKG__))
6168c2e0 980 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
812db3f7 981 if (DO_BIC(BIC_RAM__))
6168c2e0 982 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
d7899447 983 } else if (do_rapl && rapl_joules) {
812db3f7 984 if (DO_BIC(BIC_Pkg_J))
6168c2e0 985 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
9392bd98 986 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 987 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
812db3f7 988 if (DO_BIC(BIC_GFX_J))
6168c2e0 989 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
812db3f7 990 if (DO_BIC(BIC_RAM_J))
6168c2e0 991 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
812db3f7 992 if (DO_BIC(BIC_PKG__))
6168c2e0 993 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
812db3f7 994 if (DO_BIC(BIC_RAM__))
6168c2e0 995 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
5c56be9a 996 }
a5c6d65d
LB		 997 if (DO_BIC(BIC_UNCORE_MHZ))
998 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : ""));
999
388e9c81
LB		 1000 for (mp = sys.pp; mp; mp = mp->next) {
1001 if (mp->format == FORMAT_RAW) {
1002 if (mp->width == 64)
c8ade361 1003 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
388e9c81 1004 else
c8ade361 1005 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
388e9c81 1006 } else {
0de6c0df
LB		 1007 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1008 outp += sprintf(outp, "%s%8s", delim, mp->name);
1009 else
1010 outp += sprintf(outp, "%s%s", delim, mp->name);
388e9c81
LB		 1011 }
1012 }
1013
c98d5d94 1014 outp += sprintf(outp, "\n");
103a8fea
LB		 1015}
1016
1b439f01 1017int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1018{
388e9c81
LB		 1019 int i;
1020 struct msr_counter *mp;
1021
3b4d5c7f 1022 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
c98d5d94
LB		 1023
1024 if (t) {
1b439f01 1025 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags);
3b4d5c7f
AS		 1026 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
1027 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
1028 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
1029 outp += sprintf(outp, "c1: %016llX\n", t->c1);
6886fee4 1030
2af4f9b8
LB		 1031 if (DO_BIC(BIC_IPC))
1032 outp += sprintf(outp, "IPC: %lld\n", t->instr_count);
1033
812db3f7 1034 if (DO_BIC(BIC_IRQ))
0de6c0df 1035 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
812db3f7 1036 if (DO_BIC(BIC_SMI))
218f0e8d 1037 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
388e9c81
LB		 1038
1039 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1b439f01 1040 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]);
388e9c81 1041 }
c98d5d94 1042 }
103a8fea 1043
c98d5d94 1044 if (c) {
3b4d5c7f
AS		 1045 outp += sprintf(outp, "core: %d\n", c->core_id);
1046 outp += sprintf(outp, "c3: %016llX\n", c->c3);
1047 outp += sprintf(outp, "c6: %016llX\n", c->c6);
1048 outp += sprintf(outp, "c7: %016llX\n", c->c7);
1049 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
eae97e05 1050 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt);
9392bd98 1051 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
388e9c81
LB		 1052
1053 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1b439f01 1054 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]);
388e9c81 1055 }
0539ba11 1056 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
c98d5d94 1057 }
103a8fea 1058
c98d5d94 1059 if (p) {
3b4d5c7f 1060 outp += sprintf(outp, "package: %d\n", p->package_id);
0b2bb692
LB		 1061
1062 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
1063 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
1064 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
1065 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
1066
3b4d5c7f 1067 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
0f47c08d 1068 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1069 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
0f47c08d 1070 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1071 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
0f47c08d 1072 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1073 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
3b4d5c7f
AS		 1074 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
1075 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
1076 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
be0e54c4
LB		 1077 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
1078 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
7c2ccc50
CY		 1079 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg);
1080 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores);
1081 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx);
1082 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram);
1b439f01
LB		 1083 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status);
1084 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status);
3b4d5c7f 1085 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
388e9c81
LB		 1086
1087 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1b439f01 1088 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]);
388e9c81 1089 }
c98d5d94 1090 }
3b4d5c7f
AS		 1091
1092 outp += sprintf(outp, "\n");
1093
c98d5d94 1094 return 0;
103a8fea
LB		 1095}
1096
e23da037
LB		 1097/*
1098 * column formatting convention & formats
e23da037 1099 */
1b439f01 1100int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1101{
008d396e 1102 double interval_float, tsc;
fc04cc67 1103 char *fmt8;
388e9c81
LB		 1104 int i;
1105 struct msr_counter *mp;
6168c2e0
LB		 1106 char *delim = "\t";
1107 int printed = 0;
103a8fea 1108
1b439f01 1109 /* if showing only 1st thread in core and this isn't one, bail out */
c98d5d94
LB		 1110 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1111 return 0;
1112
1b439f01 1113 /* if showing only 1st thread in pkg and this isn't one, bail out */
c98d5d94
LB		 1114 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1115 return 0;
1116
1ef7d21a 1117 /*if not summary line and --cpu is used */
1b439f01 1118 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
1ef7d21a
LB		 1119 return 0;
1120
3f44a5c6 1121 if (DO_BIC(BIC_USEC)) {
f4fdf2b4
LB		 1122 /* on each row, print how many usec each timestamp took to gather */
1123 struct timeval tv;
1124
1125 timersub(&t->tv_end, &t->tv_begin, &tv);
1126 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
1127 }
1128
3f44a5c6
LB		 1129 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
1130 if (DO_BIC(BIC_TOD))
1131 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
1132
1b439f01 1133 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0;
103a8fea 1134
008d396e
LB		 1135 tsc = t->tsc * tsc_tweak;
1136
c98d5d94
LB		 1137 /* topo columns, print blanks on 1st (average) line */
1138 if (t == &average.threads) {
812db3f7 1139 if (DO_BIC(BIC_Package))
6168c2e0 1140 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
6de68fe1
LB		 1141 if (DO_BIC(BIC_Die))
1142 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
01235041
PB		 1143 if (DO_BIC(BIC_Node))
1144 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
812db3f7 1145 if (DO_BIC(BIC_Core))
6168c2e0 1146 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
812db3f7 1147 if (DO_BIC(BIC_CPU))
6168c2e0 1148 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
4c2122d4
LB		 1149 if (DO_BIC(BIC_APIC))
1150 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1151 if (DO_BIC(BIC_X2APIC))
1152 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
103a8fea 1153 } else {
812db3f7 1154 if (DO_BIC(BIC_Package)) {
c98d5d94 1155 if (p)
6168c2e0 1156 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
c98d5d94 1157 else
6168c2e0 1158 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
c98d5d94 1159 }
6de68fe1
LB		 1160 if (DO_BIC(BIC_Die)) {
1161 if (c)
1162 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
1163 else
1164 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1165 }
01235041
PB		 1166 if (DO_BIC(BIC_Node)) {
1167 if (t)
1168 outp += sprintf(outp, "%s%d",
1b439f01 1169 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id);
01235041 1170 else
1b439f01 1171 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
01235041 1172 }
812db3f7 1173 if (DO_BIC(BIC_Core)) {
c98d5d94 1174 if (c)
6168c2e0 1175 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
c98d5d94 1176 else
6168c2e0 1177 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
c98d5d94 1178 }
812db3f7 1179 if (DO_BIC(BIC_CPU))
6168c2e0 1180 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
4c2122d4
LB		 1181 if (DO_BIC(BIC_APIC))
1182 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
1183 if (DO_BIC(BIC_X2APIC))
1184 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
103a8fea 1185 }
fc04cc67 1186
812db3f7 1187 if (DO_BIC(BIC_Avg_MHz))
1b439f01 1188 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float);
fc04cc67 1189
812db3f7 1190 if (DO_BIC(BIC_Busy))
1b439f01 1191 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc);
103a8fea 1192
812db3f7 1193 if (DO_BIC(BIC_Bzy_MHz)) {
21ed5574 1194 if (has_base_hz)
1b439f01
LB		 1195 outp +=
1196 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
21ed5574 1197 else
6168c2e0 1198 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
1b439f01 1199 tsc / units * t->aperf / t->mperf / interval_float);
21ed5574 1200 }
103a8fea 1201
812db3f7 1202 if (DO_BIC(BIC_TSC_MHz))
1b439f01 1203 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float);
103a8fea 1204
2af4f9b8
LB		 1205 if (DO_BIC(BIC_IPC))
1206 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf);
1207
562a2d37 1208 /* IRQ */
0de6c0df
LB		 1209 if (DO_BIC(BIC_IRQ)) {
1210 if (sums_need_wide_columns)
6168c2e0 1211 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
0de6c0df 1212 else
6168c2e0 1213 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
0de6c0df 1214 }
562a2d37 1215
1cc21f7b 1216 /* SMI */
812db3f7 1217 if (DO_BIC(BIC_SMI))
6168c2e0 1218 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1cc21f7b 1219
678a3bd1 1220 /* Added counters */
388e9c81
LB		 1221 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1222 if (mp->format == FORMAT_RAW) {
1223 if (mp->width == 32)
1b439f01
LB		 1224 outp +=
1225 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]);
388e9c81 1226 else
6168c2e0 1227 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
388e9c81 1228 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1229 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1230 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
0de6c0df 1231 else
6168c2e0 1232 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
388e9c81 1233 } else if (mp->format == FORMAT_PERCENT) {
41618e63 1234 if (mp->type == COUNTER_USEC)
1b439f01
LB		 1235 outp +=
1236 sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1237 t->counter[i] / interval_float / 10000);
41618e63 1238 else
1b439f01 1239 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc);
388e9c81
LB		 1240 }
1241 }
1242
41618e63
LB		 1243 /* C1 */
1244 if (DO_BIC(BIC_CPU_c1))
1b439f01 1245 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc);
41618e63 1246
678a3bd1
LB		 1247 /* print per-core data only for 1st thread in core */
1248 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1249 goto done;
1250
562855ee 1251 if (DO_BIC(BIC_CPU_c3))
1b439f01 1252 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc);
812db3f7 1253 if (DO_BIC(BIC_CPU_c6))
1b439f01 1254 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc);
812db3f7 1255 if (DO_BIC(BIC_CPU_c7))
1b439f01 1256 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc);
678a3bd1 1257
0539ba11
LB		 1258 /* Mod%c6 */
1259 if (DO_BIC(BIC_Mod_c6))
6168c2e0 1260 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
0539ba11 1261
812db3f7 1262 if (DO_BIC(BIC_CoreTmp))
6168c2e0 1263 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
889facbe 1264
eae97e05
CY		 1265 /* Core throttle count */
1266 if (DO_BIC(BIC_CORE_THROT_CNT))
1267 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt);
1268
388e9c81
LB		 1269 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1270 if (mp->format == FORMAT_RAW) {
1271 if (mp->width == 32)
1b439f01
LB		 1272 outp +=
1273 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]);
388e9c81 1274 else
6168c2e0 1275 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
388e9c81 1276 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1277 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1278 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
0de6c0df 1279 else
6168c2e0 1280 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
388e9c81 1281 } else if (mp->format == FORMAT_PERCENT) {
1b439f01 1282 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc);
388e9c81
LB		 1283 }
1284 }
1285
9972d5d8 1286 fmt8 = "%s%.2f";
9392bd98
CW		 1287
1288 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1b439f01
LB		 1289 outp +=
1290 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
9392bd98
CW		 1291 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1292 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1293
c98d5d94
LB		 1294 /* print per-package data only for 1st core in package */
1295 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1296 goto done;
1297
0b2bb692 1298 /* PkgTmp */
812db3f7 1299 if (DO_BIC(BIC_PkgTmp))
6168c2e0 1300 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
889facbe 1301
fdf676e5 1302 /* GFXrc6 */
812db3f7 1303 if (DO_BIC(BIC_GFX_rc6)) {
ba3dec99 1304 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
6168c2e0 1305 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
9185e988 1306 } else {
6168c2e0 1307 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1b439f01 1308 p->gfx_rc6_ms / 10.0 / interval_float);
9185e988
LB		 1309 }
1310 }
fdf676e5 1311
27d47356 1312 /* GFXMHz */
812db3f7 1313 if (DO_BIC(BIC_GFXMHz))
6168c2e0 1314 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
27d47356 1315
b4b91569
RA		 1316 /* GFXACTMHz */
1317 if (DO_BIC(BIC_GFXACTMHz))
1318 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz);
1319
0b2bb692 1320 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
a99d8730 1321 if (DO_BIC(BIC_Totl_c0))
1b439f01 1322 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc);
a99d8730 1323 if (DO_BIC(BIC_Any_c0))
1b439f01 1324 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc);
a99d8730 1325 if (DO_BIC(BIC_GFX_c0))
1b439f01 1326 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc);
a99d8730 1327 if (DO_BIC(BIC_CPUGFX))
1b439f01 1328 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc);
0b2bb692 1329
0f47c08d 1330 if (DO_BIC(BIC_Pkgpc2))
1b439f01 1331 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc);
0f47c08d 1332 if (DO_BIC(BIC_Pkgpc3))
1b439f01 1333 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc);
0f47c08d 1334 if (DO_BIC(BIC_Pkgpc6))
1b439f01 1335 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc);
0f47c08d 1336 if (DO_BIC(BIC_Pkgpc7))
1b439f01 1337 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc);
0f47c08d 1338 if (DO_BIC(BIC_Pkgpc8))
1b439f01 1339 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc);
0f47c08d 1340 if (DO_BIC(BIC_Pkgpc9))
1b439f01 1341 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc);
0f47c08d 1342 if (DO_BIC(BIC_Pkgpc10))
1b439f01 1343 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc);
889facbe 1344
be0e54c4 1345 if (DO_BIC(BIC_CPU_LPI))
1b439f01
LB		 1346 outp +=
1347 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
be0e54c4 1348 if (DO_BIC(BIC_SYS_LPI))
1b439f01
LB		 1349 outp +=
1350 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
be0e54c4 1351
812db3f7 1352 if (DO_BIC(BIC_PkgWatt))
1b439f01
LB		 1353 outp +=
1354 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
eae97e05 1355
9392bd98 1356 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1b439f01
LB		 1357 outp +=
1358 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
812db3f7 1359 if (DO_BIC(BIC_GFXWatt))
1b439f01
LB		 1360 outp +=
1361 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
812db3f7 1362 if (DO_BIC(BIC_RAMWatt))
1b439f01
LB		 1363 outp +=
1364 sprintf(outp, fmt8, (printed++ ? delim : ""),
1365 p->energy_dram * rapl_dram_energy_units / interval_float);
812db3f7 1366 if (DO_BIC(BIC_Pkg_J))
6168c2e0 1367 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
9392bd98 1368 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
6168c2e0 1369 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
812db3f7 1370 if (DO_BIC(BIC_GFX_J))
6168c2e0 1371 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
812db3f7 1372 if (DO_BIC(BIC_RAM_J))
6168c2e0 1373 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
812db3f7 1374 if (DO_BIC(BIC_PKG__))
1b439f01
LB		 1375 outp +=
1376 sprintf(outp, fmt8, (printed++ ? delim : ""),
1377 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
812db3f7 1378 if (DO_BIC(BIC_RAM__))
1b439f01
LB		 1379 outp +=
1380 sprintf(outp, fmt8, (printed++ ? delim : ""),
1381 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
a5c6d65d
LB		 1382 /* UncMHz */
1383 if (DO_BIC(BIC_UNCORE_MHZ))
1384 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz);
812db3f7 1385
388e9c81
LB		 1386 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1387 if (mp->format == FORMAT_RAW) {
1388 if (mp->width == 32)
1b439f01
LB		 1389 outp +=
1390 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]);
388e9c81 1391 else
6168c2e0 1392 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
388e9c81 1393 } else if (mp->format == FORMAT_DELTA) {
0de6c0df 1394 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
6168c2e0 1395 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
0de6c0df 1396 else
6168c2e0 1397 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
388e9c81 1398 } else if (mp->format == FORMAT_PERCENT) {
1b439f01 1399 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc);
388e9c81
LB		 1400 }
1401 }
1402
c98d5d94 1403done:
94d6ab4b
LB		 1404 if (*(outp - 1) != '\n')
1405 outp += sprintf(outp, "\n");
c98d5d94
LB		 1406
1407 return 0;
103a8fea
LB		 1408}
1409
b7d8c148 1410void flush_output_stdout(void)
c98d5d94 1411{
b7d8c148
LB		 1412 FILE *filep;
1413
1414 if (outf == stderr)
1415 filep = stdout;
1416 else
1417 filep = outf;
1418
1419 fputs(output_buffer, filep);
1420 fflush(filep);
1421
c98d5d94
LB		 1422 outp = output_buffer;
1423}
1b439f01 1424
b7d8c148 1425void flush_output_stderr(void)
c98d5d94 1426{
b7d8c148
LB		 1427 fputs(output_buffer, outf);
1428 fflush(outf);
c98d5d94
LB		 1429 outp = output_buffer;
1430}
1b439f01 1431
c98d5d94 1432void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1433{
c7e399f8 1434 static int count;
103a8fea 1435
c7e399f8 1436 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only)
c8ade361 1437 print_header("\t");
103a8fea 1438
9d83601a 1439 format_counters(&average.threads, &average.cores, &average.packages);
103a8fea 1440
c7e399f8 1441 count++;
e23da037
LB		 1442
1443 if (summary_only)
1444 return;
1445
c98d5d94 1446 for_all_cpus(format_counters, t, c, p);
103a8fea
LB		 1447}
1448
889facbe 1449#define DELTA_WRAP32(new, old) \
7c2ccc50 1450 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32);
889facbe 1451
1b439f01 1452int delta_package(struct pkg_data *new, struct pkg_data *old)
c98d5d94 1453{
388e9c81
LB		 1454 int i;
1455 struct msr_counter *mp;
0b2bb692 1456
a99d8730 1457 if (DO_BIC(BIC_Totl_c0))
0b2bb692 1458 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
a99d8730 1459 if (DO_BIC(BIC_Any_c0))
0b2bb692 1460 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
a99d8730 1461 if (DO_BIC(BIC_GFX_c0))
0b2bb692 1462 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
a99d8730 1463 if (DO_BIC(BIC_CPUGFX))
0b2bb692 1464 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
a99d8730 1465
c98d5d94 1466 old->pc2 = new->pc2 - old->pc2;
0f47c08d 1467 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1468 old->pc3 = new->pc3 - old->pc3;
0f47c08d 1469 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1470 old->pc6 = new->pc6 - old->pc6;
0f47c08d 1471 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1472 old->pc7 = new->pc7 - old->pc7;
ca58710f
KCA		 1473 old->pc8 = new->pc8 - old->pc8;
1474 old->pc9 = new->pc9 - old->pc9;
1475 old->pc10 = new->pc10 - old->pc10;
be0e54c4
LB		 1476 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
1477 old->sys_lpi = new->sys_lpi - old->sys_lpi;
889facbe
LB		 1478 old->pkg_temp_c = new->pkg_temp_c;
1479
9185e988 1480 /* flag an error when rc6 counter resets/wraps */
1b439f01 1481 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
9185e988
LB		 1482 old->gfx_rc6_ms = -1;
1483 else
1484 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1485
a5c6d65d 1486 old->uncore_mhz = new->uncore_mhz;
27d47356 1487 old->gfx_mhz = new->gfx_mhz;
b4b91569 1488 old->gfx_act_mhz = new->gfx_act_mhz;
27d47356 1489
87e15da9
CY		 1490 old->energy_pkg = new->energy_pkg - old->energy_pkg;
1491 old->energy_cores = new->energy_cores - old->energy_cores;
1492 old->energy_gfx = new->energy_gfx - old->energy_gfx;
1493 old->energy_dram = new->energy_dram - old->energy_dram;
1494 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status;
1495 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status;
ba3dec99 1496
388e9c81
LB		 1497 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1498 if (mp->format == FORMAT_RAW)
1499 old->counter[i] = new->counter[i];
1500 else
1501 old->counter[i] = new->counter[i] - old->counter[i];
1502 }
1503
ba3dec99 1504 return 0;
c98d5d94 1505}
103a8fea 1506
1b439f01 1507void delta_core(struct core_data *new, struct core_data *old)
103a8fea 1508{
388e9c81
LB		 1509 int i;
1510 struct msr_counter *mp;
1511
c98d5d94
LB		 1512 old->c3 = new->c3 - old->c3;
1513 old->c6 = new->c6 - old->c6;
1514 old->c7 = new->c7 - old->c7;
889facbe 1515 old->core_temp_c = new->core_temp_c;
eae97e05 1516 old->core_throt_cnt = new->core_throt_cnt;
0539ba11 1517 old->mc6_us = new->mc6_us - old->mc6_us;
388e9c81 1518
9392bd98
CW		 1519 DELTA_WRAP32(new->core_energy, old->core_energy);
1520
388e9c81
LB		 1521 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1522 if (mp->format == FORMAT_RAW)
1523 old->counter[i] = new->counter[i];
1524 else
1525 old->counter[i] = new->counter[i] - old->counter[i];
1526 }
c98d5d94 1527}
103a8fea 1528
1e9042b9
SP		 1529int soft_c1_residency_display(int bic)
1530{
1531 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr)
1532 return 0;
1533
1534 return DO_BIC_READ(bic);
1535}
1536
c3ae331d
LB		 1537/*
1538 * old = new - old
1539 */
1b439f01 1540int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta)
c98d5d94 1541{
388e9c81
LB		 1542 int i;
1543 struct msr_counter *mp;
1544
4c2122d4
LB		 1545 /* we run cpuid just the 1st time, copy the results */
1546 if (DO_BIC(BIC_APIC))
1547 new->apic_id = old->apic_id;
1548 if (DO_BIC(BIC_X2APIC))
1549 new->x2apic_id = old->x2apic_id;
1550
3f44a5c6
LB		 1551 /*
1552 * the timestamps from start of measurement interval are in "old"
1553 * the timestamp from end of measurement interval are in "new"
1554 * over-write old w/ new so we can print end of interval values
1555 */
1556
d4794f25 1557 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
3f44a5c6
LB		 1558 old->tv_begin = new->tv_begin;
1559 old->tv_end = new->tv_end;
1560
c98d5d94
LB		 1561 old->tsc = new->tsc - old->tsc;
1562
1563 /* check for TSC < 1 Mcycles over interval */
b2c95d90
JT		 1564 if (old->tsc < (1000 * 1000))
1565 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1566 "You can disable all c-states by booting with \"idle=poll\"\n"
1567 "or just the deep ones with \"processor.max_cstate=1\"");
103a8fea 1568
c98d5d94 1569 old->c1 = new->c1 - old->c1;
103a8fea 1570
1b439f01 1571 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
a729617c
LB		 1572 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1573 old->aperf = new->aperf - old->aperf;
1574 old->mperf = new->mperf - old->mperf;
1575 } else {
ba3dec99 1576 return -1;
103a8fea 1577 }
c98d5d94 1578 }
103a8fea 1579
144b44b1
LB		 1580 if (use_c1_residency_msr) {
1581 /*
1582 * Some models have a dedicated C1 residency MSR,
1583 * which should be more accurate than the derivation below.
1584 */
1585 } else {
1586 /*
1587 * As counter collection is not atomic,
1588 * it is possible for mperf's non-halted cycles + idle states
1589 * to exceed TSC's all cycles: show c1 = 0% in that case.
1590 */
95149369 1591 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
144b44b1
LB		 1592 old->c1 = 0;
1593 else {
1594 /* normal case, derive c1 */
008d396e 1595 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1b439f01 1596 - core_delta->c6 - core_delta->c7;
144b44b1 1597 }
c98d5d94 1598 }
c3ae331d 1599
c98d5d94 1600 if (old->mperf == 0) {
b7d8c148
LB		 1601 if (debug > 1)
1602 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
c98d5d94 1603 old->mperf = 1; /* divide by 0 protection */
103a8fea 1604 }
c98d5d94 1605
2af4f9b8
LB		 1606 if (DO_BIC(BIC_IPC))
1607 old->instr_count = new->instr_count - old->instr_count;
1608
812db3f7 1609 if (DO_BIC(BIC_IRQ))
562a2d37
LB		 1610 old->irq_count = new->irq_count - old->irq_count;
1611
812db3f7 1612 if (DO_BIC(BIC_SMI))
1ed51011 1613 old->smi_count = new->smi_count - old->smi_count;
ba3dec99 1614
388e9c81
LB		 1615 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1616 if (mp->format == FORMAT_RAW)
1617 old->counter[i] = new->counter[i];
1618 else
1619 old->counter[i] = new->counter[i] - old->counter[i];
1620 }
ba3dec99 1621 return 0;
c98d5d94
LB		 1622}
1623
1624int delta_cpu(struct thread_data *t, struct core_data *c,
1b439f01 1625 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2)
c98d5d94 1626{
ba3dec99
LB		 1627 int retval = 0;
1628
c98d5d94
LB		 1629 /* calculate core delta only for 1st thread in core */
1630 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1631 delta_core(c, c2);
1632
1633 /* always calculate thread delta */
ba3dec99
LB		 1634 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1635 if (retval)
1636 return retval;
c98d5d94
LB		 1637
1638 /* calculate package delta only for 1st core in package */
1639 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
ba3dec99 1640 retval = delta_package(p, p2);
c98d5d94 1641
ba3dec99 1642 return retval;
103a8fea
LB		 1643}
1644
c98d5d94
LB		 1645void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1646{
388e9c81 1647 int i;
1b439f01 1648 struct msr_counter *mp;
388e9c81 1649
3f44a5c6
LB		 1650 t->tv_begin.tv_sec = 0;
1651 t->tv_begin.tv_usec = 0;
1652 t->tv_end.tv_sec = 0;
1653 t->tv_end.tv_usec = 0;
d4794f25
YG		 1654 t->tv_delta.tv_sec = 0;
1655 t->tv_delta.tv_usec = 0;
3f44a5c6 1656
c98d5d94
LB		 1657 t->tsc = 0;
1658 t->aperf = 0;
1659 t->mperf = 0;
1660 t->c1 = 0;
1661
2af4f9b8
LB		 1662 t->instr_count = 0;
1663
562a2d37
LB		 1664 t->irq_count = 0;
1665 t->smi_count = 0;
1666
c98d5d94
LB		 1667 /* tells format_counters to dump all fields from this set */
1668 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1669
1670 c->c3 = 0;
1671 c->c6 = 0;
1672 c->c7 = 0;
0539ba11 1673 c->mc6_us = 0;
889facbe 1674 c->core_temp_c = 0;
9392bd98 1675 c->core_energy = 0;
eae97e05 1676 c->core_throt_cnt = 0;
c98d5d94 1677
0b2bb692
LB		 1678 p->pkg_wtd_core_c0 = 0;
1679 p->pkg_any_core_c0 = 0;
1680 p->pkg_any_gfxe_c0 = 0;
1681 p->pkg_both_core_gfxe_c0 = 0;
1682
c98d5d94 1683 p->pc2 = 0;
0f47c08d 1684 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1685 p->pc3 = 0;
0f47c08d 1686 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1687 p->pc6 = 0;
0f47c08d 1688 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1689 p->pc7 = 0;
ca58710f
KCA		 1690 p->pc8 = 0;
1691 p->pc9 = 0;
1692 p->pc10 = 0;
be0e54c4
LB		 1693 p->cpu_lpi = 0;
1694 p->sys_lpi = 0;
889facbe
LB		 1695
1696 p->energy_pkg = 0;
1697 p->energy_dram = 0;
1698 p->energy_cores = 0;
1699 p->energy_gfx = 0;
1700 p->rapl_pkg_perf_status = 0;
1701 p->rapl_dram_perf_status = 0;
1702 p->pkg_temp_c = 0;
27d47356 1703
fdf676e5 1704 p->gfx_rc6_ms = 0;
a5c6d65d 1705 p->uncore_mhz = 0;
27d47356 1706 p->gfx_mhz = 0;
b4b91569 1707 p->gfx_act_mhz = 0;
388e9c81
LB		 1708 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1709 t->counter[i] = 0;
1710
1711 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1712 c->counter[i] = 0;
1713
1714 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1715 p->counter[i] = 0;
c98d5d94 1716}
1b439f01
LB		 1717
1718int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 1719{
388e9c81
LB		 1720 int i;
1721 struct msr_counter *mp;
1722
4c2122d4
LB		 1723 /* copy un-changing apic_id's */
1724 if (DO_BIC(BIC_APIC))
1725 average.threads.apic_id = t->apic_id;
1726 if (DO_BIC(BIC_X2APIC))
1727 average.threads.x2apic_id = t->x2apic_id;
1728
3f44a5c6
LB		 1729 /* remember first tv_begin */
1730 if (average.threads.tv_begin.tv_sec == 0)
1731 average.threads.tv_begin = t->tv_begin;
1732
1733 /* remember last tv_end */
1734 average.threads.tv_end = t->tv_end;
1735
c98d5d94
LB		 1736 average.threads.tsc += t->tsc;
1737 average.threads.aperf += t->aperf;
1738 average.threads.mperf += t->mperf;
1739 average.threads.c1 += t->c1;
103a8fea 1740
2af4f9b8
LB		 1741 average.threads.instr_count += t->instr_count;
1742
562a2d37
LB		 1743 average.threads.irq_count += t->irq_count;
1744 average.threads.smi_count += t->smi_count;
1745
388e9c81
LB		 1746 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1747 if (mp->format == FORMAT_RAW)
1748 continue;
1749 average.threads.counter[i] += t->counter[i];
1750 }
1751
c98d5d94
LB		 1752 /* sum per-core values only for 1st thread in core */
1753 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1754 return 0;
103a8fea 1755
c98d5d94
LB		 1756 average.cores.c3 += c->c3;
1757 average.cores.c6 += c->c6;
1758 average.cores.c7 += c->c7;
0539ba11 1759 average.cores.mc6_us += c->mc6_us;
c98d5d94 1760
889facbe 1761 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
eae97e05 1762 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt);
889facbe 1763
9392bd98
CW		 1764 average.cores.core_energy += c->core_energy;
1765
388e9c81
LB		 1766 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1767 if (mp->format == FORMAT_RAW)
1768 continue;
1769 average.cores.counter[i] += c->counter[i];
1770 }
1771
c98d5d94
LB		 1772 /* sum per-pkg values only for 1st core in pkg */
1773 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1774 return 0;
1775
a99d8730 1776 if (DO_BIC(BIC_Totl_c0))
0b2bb692 1777 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
a99d8730 1778 if (DO_BIC(BIC_Any_c0))
0b2bb692 1779 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
a99d8730 1780 if (DO_BIC(BIC_GFX_c0))
0b2bb692 1781 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
a99d8730 1782 if (DO_BIC(BIC_CPUGFX))
0b2bb692 1783 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
0b2bb692 1784
c98d5d94 1785 average.packages.pc2 += p->pc2;
0f47c08d 1786 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1787 average.packages.pc3 += p->pc3;
0f47c08d 1788 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1789 average.packages.pc6 += p->pc6;
0f47c08d 1790 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1791 average.packages.pc7 += p->pc7;
ca58710f
KCA		 1792 average.packages.pc8 += p->pc8;
1793 average.packages.pc9 += p->pc9;
1794 average.packages.pc10 += p->pc10;
c98d5d94 1795
be0e54c4
LB		 1796 average.packages.cpu_lpi = p->cpu_lpi;
1797 average.packages.sys_lpi = p->sys_lpi;
1798
889facbe
LB		 1799 average.packages.energy_pkg += p->energy_pkg;
1800 average.packages.energy_dram += p->energy_dram;
1801 average.packages.energy_cores += p->energy_cores;
1802 average.packages.energy_gfx += p->energy_gfx;
1803
fdf676e5 1804 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
a5c6d65d 1805 average.packages.uncore_mhz = p->uncore_mhz;
27d47356 1806 average.packages.gfx_mhz = p->gfx_mhz;
b4b91569 1807 average.packages.gfx_act_mhz = p->gfx_act_mhz;
27d47356 1808
889facbe
LB		 1809 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1810
1811 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1812 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
388e9c81
LB		 1813
1814 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1815 if (mp->format == FORMAT_RAW)
1816 continue;
1817 average.packages.counter[i] += p->counter[i];
1818 }
c98d5d94
LB		 1819 return 0;
1820}
1b439f01 1821
c98d5d94
LB		 1822/*
1823 * sum the counters for all cpus in the system
1824 * compute the weighted average
1825 */
1b439f01 1826void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p)
c98d5d94 1827{
388e9c81
LB		 1828 int i;
1829 struct msr_counter *mp;
1830
c98d5d94
LB		 1831 clear_counters(&average.threads, &average.cores, &average.packages);
1832
1833 for_all_cpus(sum_counters, t, c, p);
1834
d4794f25
YG		 1835 /* Use the global time delta for the average. */
1836 average.threads.tv_delta = tv_delta;
1837
c98d5d94
LB		 1838 average.threads.tsc /= topo.num_cpus;
1839 average.threads.aperf /= topo.num_cpus;
1840 average.threads.mperf /= topo.num_cpus;
2af4f9b8 1841 average.threads.instr_count /= topo.num_cpus;
c98d5d94
LB		 1842 average.threads.c1 /= topo.num_cpus;
1843
0de6c0df
LB		 1844 if (average.threads.irq_count > 9999999)
1845 sums_need_wide_columns = 1;
1846
c98d5d94
LB		 1847 average.cores.c3 /= topo.num_cores;
1848 average.cores.c6 /= topo.num_cores;
1849 average.cores.c7 /= topo.num_cores;
0539ba11 1850 average.cores.mc6_us /= topo.num_cores;
c98d5d94 1851
a99d8730 1852 if (DO_BIC(BIC_Totl_c0))
0b2bb692 1853 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
a99d8730 1854 if (DO_BIC(BIC_Any_c0))
0b2bb692 1855 average.packages.pkg_any_core_c0 /= topo.num_packages;
a99d8730 1856 if (DO_BIC(BIC_GFX_c0))
0b2bb692 1857 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
a99d8730 1858 if (DO_BIC(BIC_CPUGFX))
0b2bb692 1859 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
0b2bb692 1860
c98d5d94 1861 average.packages.pc2 /= topo.num_packages;
0f47c08d 1862 if (DO_BIC(BIC_Pkgpc3))
ee7e38e3 1863 average.packages.pc3 /= topo.num_packages;
0f47c08d 1864 if (DO_BIC(BIC_Pkgpc6))
ee7e38e3 1865 average.packages.pc6 /= topo.num_packages;
0f47c08d 1866 if (DO_BIC(BIC_Pkgpc7))
ee7e38e3 1867 average.packages.pc7 /= topo.num_packages;
ca58710f
KCA		 1868
1869 average.packages.pc8 /= topo.num_packages;
1870 average.packages.pc9 /= topo.num_packages;
1871 average.packages.pc10 /= topo.num_packages;
388e9c81
LB		 1872
1873 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1874 if (mp->format == FORMAT_RAW)
1875 continue;
0de6c0df
LB		 1876 if (mp->type == COUNTER_ITEMS) {
1877 if (average.threads.counter[i] > 9999999)
1878 sums_need_wide_columns = 1;
41618e63 1879 continue;
0de6c0df 1880 }
388e9c81
LB		 1881 average.threads.counter[i] /= topo.num_cpus;
1882 }
1883 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1884 if (mp->format == FORMAT_RAW)
1885 continue;
0de6c0df
LB		 1886 if (mp->type == COUNTER_ITEMS) {
1887 if (average.cores.counter[i] > 9999999)
1888 sums_need_wide_columns = 1;
1889 }
388e9c81
LB		 1890 average.cores.counter[i] /= topo.num_cores;
1891 }
1892 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1893 if (mp->format == FORMAT_RAW)
1894 continue;
0de6c0df
LB		 1895 if (mp->type == COUNTER_ITEMS) {
1896 if (average.packages.counter[i] > 9999999)
1897 sums_need_wide_columns = 1;
1898 }
388e9c81
LB		 1899 average.packages.counter[i] /= topo.num_packages;
1900 }
103a8fea
LB		 1901}
1902
c98d5d94 1903static unsigned long long rdtsc(void)
103a8fea 1904{
c98d5d94 1905 unsigned int low, high;
15aaa346 1906
1b439f01 1907 asm volatile ("rdtsc":"=a" (low), "=d"(high));
15aaa346 1908
c98d5d94
LB		 1909 return low | ((unsigned long long)high) << 32;
1910}
15aaa346 1911
495c7654
LB		 1912/*
1913 * Open a file, and exit on failure
1914 */
1915FILE *fopen_or_die(const char *path, const char *mode)
1916{
1917 FILE *filep = fopen(path, mode);
1918
1919 if (!filep)
1920 err(1, "%s: open failed", path);
1921 return filep;
1922}
1b439f01 1923
495c7654
LB		 1924/*
1925 * snapshot_sysfs_counter()
1926 *
1927 * return snapshot of given counter
1928 */
1929unsigned long long snapshot_sysfs_counter(char *path)
1930{
1931 FILE *fp;
1932 int retval;
1933 unsigned long long counter;
1934
1935 fp = fopen_or_die(path, "r");
1936
1937 retval = fscanf(fp, "%lld", &counter);
1938 if (retval != 1)
1939 err(1, "snapshot_sysfs_counter(%s)", path);
1940
1941 fclose(fp);
1942
1943 return counter;
1944}
1945
1946int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
1947{
1948 if (mp->msr_num != 0) {
1949 if (get_msr(cpu, mp->msr_num, counterp))
1950 return -1;
1951 } else {
46c27978 1952 char path[128 + PATH_BYTES];
41618e63
LB		 1953
1954 if (mp->flags & SYSFS_PERCPU) {
1b439f01 1955 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path);
41618e63
LB		 1956
1957 *counterp = snapshot_sysfs_counter(path);
1958 } else {
1959 *counterp = snapshot_sysfs_counter(mp->path);
1960 }
495c7654
LB		 1961 }
1962
1963 return 0;
1964}
1965
a5c6d65d
LB		 1966unsigned long long get_uncore_mhz(int package, int die)
1967{
1968 char path[128];
1969
1970 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package,
1971 die);
1972
1973 return (snapshot_sysfs_counter(path) / 1000);
1974}
1975
6d6501d9
BP		 1976int get_epb(int cpu)
1977{
1978 char path[128 + PATH_BYTES];
7f1b11ba 1979 unsigned long long msr;
6d6501d9
BP		 1980 int ret, epb = -1;
1981 FILE *fp;
1982
1983 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu);
1984
7f1b11ba
BP		 1985 fp = fopen(path, "r");
1986 if (!fp)
1987 goto msr_fallback;
6d6501d9
BP		 1988
1989 ret = fscanf(fp, "%d", &epb);
1990 if (ret != 1)
1991 err(1, "%s(%s)", __func__, path);
1992
1993 fclose(fp);
1994
1995 return epb;
7f1b11ba
BP		 1996
1997msr_fallback:
1998 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
1999
2000 return msr & 0xf;
6d6501d9
BP		 2001}
2002
4c2122d4
LB		 2003void get_apic_id(struct thread_data *t)
2004{
34041551 2005 unsigned int eax, ebx, ecx, edx;
4c2122d4 2006
34041551
LB		 2007 if (DO_BIC(BIC_APIC)) {
2008 eax = ebx = ecx = edx = 0;
2009 __cpuid(1, eax, ebx, ecx, edx);
4c2122d4 2010
34041551
LB		 2011 t->apic_id = (ebx >> 24) & 0xff;
2012 }
2013
2014 if (!DO_BIC(BIC_X2APIC))
4c2122d4
LB		 2015 return;
2016
c1c10cc7 2017 if (authentic_amd || hygon_genuine) {
34041551 2018 unsigned int topology_extensions;
4c2122d4 2019
34041551
LB		 2020 if (max_extended_level < 0x8000001e)
2021 return;
4c2122d4 2022
34041551
LB		 2023 eax = ebx = ecx = edx = 0;
2024 __cpuid(0x80000001, eax, ebx, ecx, edx);
1b439f01 2025 topology_extensions = ecx & (1 << 22);
34041551
LB		 2026
2027 if (topology_extensions == 0)
2028 return;
2029
2030 eax = ebx = ecx = edx = 0;
2031 __cpuid(0x8000001e, eax, ebx, ecx, edx);
2032
2033 t->x2apic_id = eax;
4c2122d4 2034 return;
34041551 2035 }
4c2122d4 2036
34041551
LB		 2037 if (!genuine_intel)
2038 return;
2039
2040 if (max_level < 0xb)
4c2122d4
LB		 2041 return;
2042
2043 ecx = 0;
2044 __cpuid(0xb, eax, ebx, ecx, edx);
2045 t->x2apic_id = edx;
2046
34041551 2047 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
1b439f01 2048 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id);
4c2122d4
LB		 2049}
2050
eae97e05
CY		 2051int get_core_throt_cnt(int cpu, unsigned long long *cnt)
2052{
2053 char path[128 + PATH_BYTES];
2054 unsigned long long tmp;
2055 FILE *fp;
2056 int ret;
2057
2058 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu);
2059 fp = fopen(path, "r");
2060 if (!fp)
2061 return -1;
2062 ret = fscanf(fp, "%lld", &tmp);
5e5fd36c 2063 fclose(fp);
eae97e05
CY		 2064 if (ret != 1)
2065 return -1;
eae97e05
CY		 2066 *cnt = tmp;
2067
2068 return 0;
2069}
2070
c98d5d94
LB		 2071/*
2072 * get_counters(...)
2073 * migrate to cpu
2074 * acquire and record local counters for that cpu
2075 */
2076int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2077{
2078 int cpu = t->cpu_id;
889facbe 2079 unsigned long long msr;
0102b067 2080 int aperf_mperf_retry_count = 0;
388e9c81
LB		 2081 struct msr_counter *mp;
2082 int i;
88c3281f 2083
e52966c0 2084 if (cpu_migrate(cpu)) {
3d7772ea 2085 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu);
c98d5d94 2086 return -1;
e52966c0 2087 }
15aaa346 2088
d4794f25
YG		 2089 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
2090
4c2122d4
LB		 2091 if (first_counter_read)
2092 get_apic_id(t);
0102b067 2093retry:
c98d5d94
LB		 2094 t->tsc = rdtsc(); /* we are running on local CPU of interest */
2095
1b439f01 2096 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
0102b067
LB		 2097 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
2098
2099 /*
2100 * The TSC, APERF and MPERF must be read together for
2101 * APERF/MPERF and MPERF/TSC to give accurate results.
2102 *
2103 * Unfortunately, APERF and MPERF are read by
2104 * individual system call, so delays may occur
2105 * between them. If the time to read them
2106 * varies by a large amount, we re-read them.
2107 */
2108
2109 /*
2110 * This initial dummy APERF read has been seen to
2111 * reduce jitter in the subsequent reads.
2112 */
2113
2114 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2115 return -3;
2116
2117 t->tsc = rdtsc(); /* re-read close to APERF */
2118
2119 tsc_before = t->tsc;
2120
9c63a650 2121 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
c98d5d94 2122 return -3;
0102b067
LB		 2123
2124 tsc_between = rdtsc();
2125
9c63a650 2126 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
c98d5d94 2127 return -4;
0102b067
LB		 2128
2129 tsc_after = rdtsc();
2130
2131 aperf_time = tsc_between - tsc_before;
2132 mperf_time = tsc_after - tsc_between;
2133
2134 /*
2135 * If the system call latency to read APERF and MPERF
2136 * differ by more than 2x, then try again.
2137 */
2138 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
2139 aperf_mperf_retry_count++;
2140 if (aperf_mperf_retry_count < 5)
2141 goto retry;
2142 else
1b439f01 2143 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time);
0102b067
LB		 2144 }
2145 aperf_mperf_retry_count = 0;
2146
b2b34dfe
HC		 2147 t->aperf = t->aperf * aperf_mperf_multiplier;
2148 t->mperf = t->mperf * aperf_mperf_multiplier;
c98d5d94
LB		 2149 }
2150
2af4f9b8
LB		 2151 if (DO_BIC(BIC_IPC))
2152 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long))
2153 return -4;
2154
812db3f7 2155 if (DO_BIC(BIC_IRQ))
562a2d37 2156 t->irq_count = irqs_per_cpu[cpu];
812db3f7 2157 if (DO_BIC(BIC_SMI)) {
1ed51011
LB		 2158 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
2159 return -5;
2160 t->smi_count = msr & 0xFFFFFFFF;
2161 }
0539ba11 2162 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
144b44b1
LB		 2163 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
2164 return -6;
2165 }
2166
388e9c81 2167 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
495c7654 2168 if (get_mp(cpu, mp, &t->counter[i]))
388e9c81
LB		 2169 return -10;
2170 }
2171
c98d5d94
LB		 2172 /* collect core counters only for 1st thread in core */
2173 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
f4fdf2b4 2174 goto done;
c98d5d94 2175
1e9042b9 2176 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
c98d5d94
LB		 2177 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
2178 return -6;
144b44b1
LB		 2179 }
2180
1e9042b9 2181 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) {
c98d5d94
LB		 2182 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
2183 return -7;
1e9042b9 2184 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) {
fb5d4327
DC		 2185 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
2186 return -7;
c98d5d94
LB		 2187 }
2188
7ab5ff49 2189 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) {
c98d5d94
LB		 2190 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
2191 return -8;
7ab5ff49
ZR		 2192 else if (t->is_atom) {
2193 /*
2194 * For Atom CPUs that has core cstate deeper than c6,
2195 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper.
2196 * Minus CC7 (and deeper cstates) residency to get
2197 * accturate cc6 residency.
2198 */
2199 c->c6 -= c->c7;
2200 }
2201 }
c98d5d94 2202
0539ba11
LB		 2203 if (DO_BIC(BIC_Mod_c6))
2204 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
2205 return -8;
2206
812db3f7 2207 if (DO_BIC(BIC_CoreTmp)) {
889facbe
LB		 2208 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2209 return -9;
55279aef 2210 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F);
889facbe
LB		 2211 }
2212
eae97e05
CY		 2213 if (DO_BIC(BIC_CORE_THROT_CNT))
2214 get_core_throt_cnt(cpu, &c->core_throt_cnt);
2215
9392bd98
CW		 2216 if (do_rapl & RAPL_AMD_F17H) {
2217 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
2218 return -14;
2219 c->core_energy = msr & 0xFFFFFFFF;
2220 }
2221
388e9c81 2222 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
495c7654 2223 if (get_mp(cpu, mp, &c->counter[i]))
388e9c81
LB		 2224 return -10;
2225 }
889facbe 2226
c98d5d94
LB		 2227 /* collect package counters only for 1st core in package */
2228 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
f4fdf2b4 2229 goto done;
c98d5d94 2230
a99d8730 2231 if (DO_BIC(BIC_Totl_c0)) {
0b2bb692
LB		 2232 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
2233 return -10;
a99d8730
LB		 2234 }
2235 if (DO_BIC(BIC_Any_c0)) {
0b2bb692
LB		 2236 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
2237 return -11;
a99d8730
LB		 2238 }
2239 if (DO_BIC(BIC_GFX_c0)) {
0b2bb692
LB		 2240 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
2241 return -12;
a99d8730
LB		 2242 }
2243 if (DO_BIC(BIC_CPUGFX)) {
0b2bb692
LB		 2244 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
2245 return -13;
2246 }
0f47c08d 2247 if (DO_BIC(BIC_Pkgpc3))
c98d5d94
LB		 2248 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
2249 return -9;
0f47c08d 2250 if (DO_BIC(BIC_Pkgpc6)) {
0539ba11
LB		 2251 if (do_slm_cstates) {
2252 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
2253 return -10;
2254 } else {
2255 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
2256 return -10;
2257 }
2258 }
2259
0f47c08d 2260 if (DO_BIC(BIC_Pkgpc2))
c98d5d94
LB		 2261 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
2262 return -11;
0f47c08d 2263 if (DO_BIC(BIC_Pkgpc7))
c98d5d94
LB		 2264 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
2265 return -12;
0f47c08d 2266 if (DO_BIC(BIC_Pkgpc8))
ca58710f
KCA		 2267 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
2268 return -13;
0f47c08d 2269 if (DO_BIC(BIC_Pkgpc9))
ca58710f
KCA		 2270 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
2271 return -13;
0f47c08d 2272 if (DO_BIC(BIC_Pkgpc10))
ca58710f
KCA		 2273 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
2274 return -13;
0f47c08d 2275
be0e54c4
LB		 2276 if (DO_BIC(BIC_CPU_LPI))
2277 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
2278 if (DO_BIC(BIC_SYS_LPI))
2279 p->sys_lpi = cpuidle_cur_sys_lpi_us;
2280
889facbe 2281 if (do_rapl & RAPL_PKG) {
9972d5d8 2282 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr))
889facbe 2283 return -13;
9972d5d8 2284 p->energy_pkg = msr;
889facbe 2285 }
9148494c 2286 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
9972d5d8 2287 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr))
889facbe 2288 return -14;
9972d5d8 2289 p->energy_cores = msr;
889facbe
LB		 2290 }
2291 if (do_rapl & RAPL_DRAM) {
9972d5d8 2292 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
889facbe 2293 return -15;
9972d5d8 2294 p->energy_dram = msr;
889facbe
LB		 2295 }
2296 if (do_rapl & RAPL_GFX) {
9972d5d8 2297 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr))
889facbe 2298 return -16;
9972d5d8 2299 p->energy_gfx = msr;
889facbe
LB		 2300 }
2301 if (do_rapl & RAPL_PKG_PERF_STATUS) {
9972d5d8 2302 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr))
889facbe 2303 return -16;
9972d5d8 2304 p->rapl_pkg_perf_status = msr;
889facbe
LB		 2305 }
2306 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
9972d5d8 2307 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr))
889facbe 2308 return -16;
9972d5d8 2309 p->rapl_dram_perf_status = msr;
889facbe 2310 }
3316f99a 2311 if (do_rapl & RAPL_AMD_F17H) {
9972d5d8 2312 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr))
3316f99a 2313 return -13;
9972d5d8 2314 p->energy_pkg = msr;
3316f99a 2315 }
812db3f7 2316 if (DO_BIC(BIC_PkgTmp)) {
889facbe
LB		 2317 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2318 return -17;
55279aef 2319 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F);
889facbe 2320 }
fdf676e5 2321
812db3f7 2322 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 2323 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2324
a5c6d65d
LB		 2325 /* n.b. assume die0 uncore frequency applies to whole package */
2326 if (DO_BIC(BIC_UNCORE_MHZ))
2327 p->uncore_mhz = get_uncore_mhz(p->package_id, 0);
2328
812db3f7 2329 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 2330 p->gfx_mhz = gfx_cur_mhz;
2331
b4b91569
RA		 2332 if (DO_BIC(BIC_GFXACTMHz))
2333 p->gfx_act_mhz = gfx_act_mhz;
2334
388e9c81 2335 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
495c7654 2336 if (get_mp(cpu, mp, &p->counter[i]))
388e9c81
LB		 2337 return -10;
2338 }
f4fdf2b4
LB		 2339done:
2340 gettimeofday(&t->tv_end, (struct timezone *)NULL);
388e9c81 2341
15aaa346 2342 return 0;
103a8fea
LB		 2343}
2344
ee7e38e3
LB		 2345/*
2346 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2347 * If you change the values, note they are used both in comparisons
2348 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2349 */
2350
1b439f01
LB		 2351#define PCLUKN 0 /* Unknown */
2352#define PCLRSV 1 /* Reserved */
2353#define PCL__0 2 /* PC0 */
2354#define PCL__1 3 /* PC1 */
2355#define PCL__2 4 /* PC2 */
2356#define PCL__3 5 /* PC3 */
2357#define PCL__4 6 /* PC4 */
2358#define PCL__6 7 /* PC6 */
2359#define PCL_6N 8 /* PC6 No Retention */
2360#define PCL_6R 9 /* PC6 Retention */
2361#define PCL__7 10 /* PC7 */
2362#define PCL_7S 11 /* PC7 Shrink */
2363#define PCL__8 12 /* PC8 */
2364#define PCL__9 13 /* PC9 */
2365#define PCL_10 14 /* PC10 */
2366#define PCLUNL 15 /* Unlimited */
ee7e38e3
LB		 2367
2368int pkg_cstate_limit = PCLUKN;
2369char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1b439f01
LB		 2370 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"
2371};
a2b7b749 2372
1b439f01
LB		 2373int nhm_pkg_cstate_limits[16] =
2374 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2375 PCLRSV, PCLRSV
2376};
2377
1b439f01
LB		 2378int snb_pkg_cstate_limits[16] =
2379 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2380 PCLRSV, PCLRSV
2381};
2382
1b439f01
LB		 2383int hsw_pkg_cstate_limits[16] =
2384 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2385 PCLRSV, PCLRSV
2386};
2387
1b439f01
LB		 2388int slv_pkg_cstate_limits[16] =
2389 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2390 PCL__6, PCL__7
2391};
2392
1b439f01
LB		 2393int amt_pkg_cstate_limits[16] =
2394 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2395 PCLRSV, PCLRSV
2396};
2397
1b439f01
LB		 2398int phi_pkg_cstate_limits[16] =
2399 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2400 PCLRSV, PCLRSV
2401};
2402
1b439f01
LB		 2403int glm_pkg_cstate_limits[16] =
2404 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2405 PCLRSV, PCLRSV
2406};
2407
1b439f01
LB		 2408int skx_pkg_cstate_limits[16] =
2409 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2410 PCLRSV, PCLRSV
2411};
2412
1b439f01 2413int icx_pkg_cstate_limits[16] =
a1b6f487 2414 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
38c6663a
LB		 2415 PCLRSV, PCLRSV
2416};
1b439f01
LB		 2417
2418static void calculate_tsc_tweak()
a2b7b749 2419{
a2b7b749
LB		 2420 tsc_tweak = base_hz / tsc_hz;
2421}
2422
aeb01e6d
CY		 2423void prewake_cstate_probe(unsigned int family, unsigned int model);
2424
1b439f01 2425static void dump_nhm_platform_info(void)
103a8fea
LB		 2426{
2427 unsigned long long msr;
2428 unsigned int ratio;
2429
ec0adc53 2430 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
103a8fea 2431
b7d8c148 2432 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
6574a5d5 2433
103a8fea 2434 ratio = (msr >> 40) & 0xFF;
1b439f01 2435 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk);
103a8fea
LB		 2436
2437 ratio = (msr >> 8) & 0xFF;
1b439f01 2438 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
103a8fea 2439
7ce7d5de 2440 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
b7d8c148 2441 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
bfae2052 2442 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
67920418 2443
aeb01e6d
CY		 2444 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
2445 if (dis_cstate_prewake)
1b439f01 2446 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN");
aeb01e6d 2447
fcd17211
LB		 2448 return;
2449}
2450
1b439f01 2451static void dump_hsw_turbo_ratio_limits(void)
fcd17211
LB		 2452{
2453 unsigned long long msr;
2454 unsigned int ratio;
2455
7ce7d5de 2456 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
fcd17211 2457
b7d8c148 2458 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
fcd17211
LB		 2459
2460 ratio = (msr >> 8) & 0xFF;
2461 if (ratio)
1b439f01 2462 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2463
2464 ratio = (msr >> 0) & 0xFF;
2465 if (ratio)
1b439f01 2466 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2467 return;
2468}
2469
1b439f01 2470static void dump_ivt_turbo_ratio_limits(void)
fcd17211
LB		 2471{
2472 unsigned long long msr;
2473 unsigned int ratio;
6574a5d5 2474
7ce7d5de 2475 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
6574a5d5 2476
b7d8c148 2477 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 2478
2479 ratio = (msr >> 56) & 0xFF;
2480 if (ratio)
1b439f01 2481 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2482
2483 ratio = (msr >> 48) & 0xFF;
2484 if (ratio)
1b439f01 2485 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2486
2487 ratio = (msr >> 40) & 0xFF;
2488 if (ratio)
1b439f01 2489 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2490
2491 ratio = (msr >> 32) & 0xFF;
2492 if (ratio)
1b439f01 2493 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2494
2495 ratio = (msr >> 24) & 0xFF;
2496 if (ratio)
1b439f01 2497 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2498
2499 ratio = (msr >> 16) & 0xFF;
2500 if (ratio)
1b439f01 2501 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2502
2503 ratio = (msr >> 8) & 0xFF;
2504 if (ratio)
1b439f01 2505 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk);
6574a5d5
LB		 2506
2507 ratio = (msr >> 0) & 0xFF;
2508 if (ratio)
1b439f01 2509 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk);
fcd17211
LB		 2510 return;
2511}
1b439f01 2512
31e07522
LB		 2513int has_turbo_ratio_group_limits(int family, int model)
2514{
2515
2516 if (!genuine_intel)
2517 return 0;
2518
9878bf7a
LB		 2519 if (family != 6)
2520 return 0;
2521
31e07522
LB		 2522 switch (model) {
2523 case INTEL_FAM6_ATOM_GOLDMONT:
2524 case INTEL_FAM6_SKYLAKE_X:
25368d7c 2525 case INTEL_FAM6_ICELAKE_X:
684e40e9 2526 case INTEL_FAM6_SAPPHIRERAPIDS_X:
5ebb34ed 2527 case INTEL_FAM6_ATOM_GOLDMONT_D:
20de0dab 2528 case INTEL_FAM6_ATOM_TREMONT_D:
31e07522 2529 return 1;
9878bf7a
LB		 2530 default:
2531 return 0;
31e07522 2532 }
31e07522 2533}
6574a5d5 2534
4af184ee 2535static void dump_turbo_ratio_limits(int trl_msr_offset, int family, int model)
fcd17211 2536{
31e07522 2537 unsigned long long msr, core_counts;
5d622845 2538 int shift;
103a8fea 2539
4af184ee
LB		 2540 get_msr(base_cpu, trl_msr_offset, &msr);
2541 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n",
884a1f95 2542 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr);
6574a5d5 2543
31e07522
LB		 2544 if (has_turbo_ratio_group_limits(family, model)) {
2545 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
2546 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
2547 } else {
2548 core_counts = 0x0807060504030201;
2549 }
2550
5d622845
LB		 2551 for (shift = 56; shift >= 0; shift -= 8) {
2552 unsigned int ratio, group_size;
6574a5d5 2553
5d622845
LB		 2554 ratio = (msr >> shift) & 0xFF;
2555 group_size = (core_counts >> shift) & 0xFF;
2556 if (ratio)
2557 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2558 ratio, bclk, ratio * bclk, group_size);
2559 }
103a8fea 2560
fcd17211
LB		 2561 return;
2562}
3a9a941d 2563
1b439f01 2564static void dump_atom_turbo_ratio_limits(void)
0f7887c4
LB		 2565{
2566 unsigned long long msr;
2567 unsigned int ratio;
2568
2569 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
2570 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2571
2572 ratio = (msr >> 0) & 0x3F;
2573 if (ratio)
1b439f01 2574 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2575
2576 ratio = (msr >> 8) & 0x3F;
2577 if (ratio)
1b439f01 2578 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2579
2580 ratio = (msr >> 16) & 0x3F;
2581 if (ratio)
1b439f01 2582 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2583
2584 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
2585 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2586
2587 ratio = (msr >> 24) & 0x3F;
2588 if (ratio)
1b439f01 2589 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2590
2591 ratio = (msr >> 16) & 0x3F;
2592 if (ratio)
1b439f01 2593 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2594
2595 ratio = (msr >> 8) & 0x3F;
2596 if (ratio)
1b439f01 2597 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2598
2599 ratio = (msr >> 0) & 0x3F;
2600 if (ratio)
1b439f01 2601 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk);
0f7887c4
LB		 2602}
2603
1b439f01 2604static void dump_knl_turbo_ratio_limits(void)
fb5d4327 2605{
cbf97aba
HC		 2606 const unsigned int buckets_no = 7;
2607
fb5d4327 2608 unsigned long long msr;
cbf97aba
HC		 2609 int delta_cores, delta_ratio;
2610 int i, b_nr;
2611 unsigned int cores[buckets_no];
2612 unsigned int ratio[buckets_no];
fb5d4327 2613
ebf5926a 2614 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
fb5d4327 2615
1b439f01 2616 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
fb5d4327 2617
1e3ec5cd 2618 /*
fb5d4327 2619 * Turbo encoding in KNL is as follows:
cbf97aba
HC		 2620 * [0] -- Reserved
2621 * [7:1] -- Base value of number of active cores of bucket 1.
fb5d4327
DC		 2622 * [15:8] -- Base value of freq ratio of bucket 1.
2623 * [20:16] -- +ve delta of number of active cores of bucket 2.
2624 * i.e. active cores of bucket 2 =
2625 * active cores of bucket 1 + delta
2626 * [23:21] -- Negative delta of freq ratio of bucket 2.
2627 * i.e. freq ratio of bucket 2 =
2628 * freq ratio of bucket 1 - delta
2629 * [28:24]-- +ve delta of number of active cores of bucket 3.
2630 * [31:29]-- -ve delta of freq ratio of bucket 3.
2631 * [36:32]-- +ve delta of number of active cores of bucket 4.
2632 * [39:37]-- -ve delta of freq ratio of bucket 4.
2633 * [44:40]-- +ve delta of number of active cores of bucket 5.
2634 * [47:45]-- -ve delta of freq ratio of bucket 5.
2635 * [52:48]-- +ve delta of number of active cores of bucket 6.
2636 * [55:53]-- -ve delta of freq ratio of bucket 6.
2637 * [60:56]-- +ve delta of number of active cores of bucket 7.
2638 * [63:61]-- -ve delta of freq ratio of bucket 7.
2639 */
cbf97aba
HC		 2640
2641 b_nr = 0;
2642 cores[b_nr] = (msr & 0xFF) >> 1;
2643 ratio[b_nr] = (msr >> 8) & 0xFF;
2644
2645 for (i = 16; i < 64; i += 8) {
fb5d4327 2646 delta_cores = (msr >> i) & 0x1F;
cbf97aba
HC		 2647 delta_ratio = (msr >> (i + 5)) & 0x7;
2648
2649 cores[b_nr + 1] = cores[b_nr] + delta_cores;
2650 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
2651 b_nr++;
fb5d4327 2652 }
cbf97aba
HC		 2653
2654 for (i = buckets_no - 1; i >= 0; i--)
2655 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
b7d8c148 2656 fprintf(outf,
710f273b 2657 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
cbf97aba 2658 ratio[i], bclk, ratio[i] * bclk, cores[i]);
fb5d4327
DC		 2659}
2660
1b439f01 2661static void dump_nhm_cst_cfg(void)
fcd17211
LB		 2662{
2663 unsigned long long msr;
2664
1df2e55a 2665 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
fcd17211 2666
1df2e55a 2667 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
fcd17211 2668
3e8b62bf 2669 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
fcd17211
LB		 2670 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
2671 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
2672 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
2673 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1b439f01 2674 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);
ac980e13
AB		 2675
2676#define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
2677 if (has_automatic_cstate_conversion) {
1b439f01 2678 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
ac980e13
AB		 2679 }
2680
2681 fprintf(outf, ")\n");
2682
fcd17211 2683 return;
103a8fea
LB		 2684}
2685
1b439f01 2686static void dump_config_tdp(void)
6fb3143b
LB		 2687{
2688 unsigned long long msr;
2689
2690 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
b7d8c148 2691 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
685b535b 2692 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
6fb3143b
LB		 2693
2694 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
b7d8c148 2695 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
6fb3143b 2696 if (msr) {
685b535b
CY		 2697 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2698 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2699 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2700 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 2701 }
b7d8c148 2702 fprintf(outf, ")\n");
6fb3143b
LB		 2703
2704 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
b7d8c148 2705 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
6fb3143b 2706 if (msr) {
685b535b
CY		 2707 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2708 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2709 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2710 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
6fb3143b 2711 }
b7d8c148 2712 fprintf(outf, ")\n");
6fb3143b
LB		 2713
2714 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
b7d8c148 2715 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
6fb3143b 2716 if ((msr) & 0x3)
b7d8c148
LB		 2717 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
2718 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2719 fprintf(outf, ")\n");
36229897 2720
6fb3143b 2721 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
b7d8c148 2722 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
685b535b 2723 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
b7d8c148
LB		 2724 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2725 fprintf(outf, ")\n");
6fb3143b 2726}
5a63426e 2727
1b439f01 2728unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
5a63426e
LB		 2729
2730void print_irtl(void)
2731{
2732 unsigned long long msr;
2733
2734 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
2735 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
2736 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2737 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2738
2739 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
2740 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
2741 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2742 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2743
2744 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
2745 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
2746 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2747 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2748
2749 if (!do_irtl_hsw)
2750 return;
2751
2752 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
2753 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
2754 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2755 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2756
2757 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
2758 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
2759 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2760 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2761
2762 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
2763 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
2764 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2765 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2766
2767}
1b439f01 2768
36229897
LB		 2769void free_fd_percpu(void)
2770{
2771 int i;
2772
01a67adf 2773 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
36229897
LB		 2774 if (fd_percpu[i] != 0)
2775 close(fd_percpu[i]);
2776 }
2777
2778 free(fd_percpu);
6fb3143b
LB		 2779}
2780
c98d5d94 2781void free_all_buffers(void)
103a8fea 2782{
0e2d8f05
LB		 2783 int i;
2784
c98d5d94
LB		 2785 CPU_FREE(cpu_present_set);
2786 cpu_present_set = NULL;
36229897 2787 cpu_present_setsize = 0;
103a8fea 2788
c98d5d94
LB		 2789 CPU_FREE(cpu_affinity_set);
2790 cpu_affinity_set = NULL;
2791 cpu_affinity_setsize = 0;
103a8fea 2792
c98d5d94
LB		 2793 free(thread_even);
2794 free(core_even);
2795 free(package_even);
103a8fea 2796
c98d5d94
LB		 2797 thread_even = NULL;
2798 core_even = NULL;
2799 package_even = NULL;
103a8fea 2800
c98d5d94
LB		 2801 free(thread_odd);
2802 free(core_odd);
2803 free(package_odd);
103a8fea 2804
c98d5d94
LB		 2805 thread_odd = NULL;
2806 core_odd = NULL;
2807 package_odd = NULL;
103a8fea 2808
c98d5d94
LB		 2809 free(output_buffer);
2810 output_buffer = NULL;
2811 outp = NULL;
36229897
LB		 2812
2813 free_fd_percpu();
562a2d37
LB		 2814
2815 free(irq_column_2_cpu);
2816 free(irqs_per_cpu);
0e2d8f05
LB		 2817
2818 for (i = 0; i <= topo.max_cpu_num; ++i) {
2819 if (cpus[i].put_ids)
2820 CPU_FREE(cpus[i].put_ids);
2821 }
2822 free(cpus);
103a8fea
LB		 2823}
2824
c98d5d94 2825/*
95aebc44 2826 * Parse a file containing a single int.
6de68fe1
LB		 2827 * Return 0 if file can not be opened
2828 * Exit if file can be opened, but can not be parsed
c98d5d94 2829 */
95aebc44 2830int parse_int_file(const char *fmt, ...)
103a8fea 2831{
95aebc44
JT		 2832 va_list args;
2833 char path[PATH_MAX];
c98d5d94 2834 FILE *filep;
95aebc44 2835 int value;
103a8fea 2836
95aebc44
JT		 2837 va_start(args, fmt);
2838 vsnprintf(path, sizeof(path), fmt, args);
2839 va_end(args);
6de68fe1
LB		 2840 filep = fopen(path, "r");
2841 if (!filep)
2842 return 0;
b2c95d90
JT		 2843 if (fscanf(filep, "%d", &value) != 1)
2844 err(1, "%s: failed to parse number from file", path);
c98d5d94 2845 fclose(filep);
95aebc44
JT		 2846 return value;
2847}
2848
c98d5d94
LB		 2849/*
2850 * cpu_is_first_core_in_package(cpu)
2851 * return 1 if given CPU is 1st core in package
2852 */
2853int cpu_is_first_core_in_package(int cpu)
103a8fea 2854{
95aebc44 2855 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
103a8fea
LB		 2856}
2857
2858int get_physical_package_id(int cpu)
2859{
95aebc44 2860 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
103a8fea
LB		 2861}
2862
6de68fe1
LB		 2863int get_die_id(int cpu)
2864{
2865 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
2866}
2867
103a8fea
LB		 2868int get_core_id(int cpu)
2869{
95aebc44 2870 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
103a8fea
LB		 2871}
2872
ef605741
PB		 2873void set_node_data(void)
2874{
2ffbb224
PB		 2875 int pkg, node, lnode, cpu, cpux;
2876 int cpu_count;
2877
2878 /* initialize logical_node_id */
2879 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
2880 cpus[cpu].logical_node_id = -1;
2881
2882 cpu_count = 0;
2883 for (pkg = 0; pkg < topo.num_packages; pkg++) {
2884 lnode = 0;
2885 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
2886 if (cpus[cpu].physical_package_id != pkg)
2887 continue;
2888 /* find a cpu with an unset logical_node_id */
2889 if (cpus[cpu].logical_node_id != -1)
2890 continue;
2891 cpus[cpu].logical_node_id = lnode;
2892 node = cpus[cpu].physical_node_id;
2893 cpu_count++;
2894 /*
2895 * find all matching cpus on this pkg and set
2896 * the logical_node_id
2897 */
2898 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
1b439f01 2899 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) {
2ffbb224
PB		 2900 cpus[cpux].logical_node_id = lnode;
2901 cpu_count++;
2902 }
2903 }
2904 lnode++;
2905 if (lnode > topo.nodes_per_pkg)
2906 topo.nodes_per_pkg = lnode;
2907 }
2908 if (cpu_count >= topo.max_cpu_num)
2909 break;
ef605741 2910 }
ef605741
PB		 2911}
2912
2913int get_physical_node_id(struct cpu_topology *thiscpu)
c98d5d94
LB		 2914{
2915 char path[80];
2916 FILE *filep;
0e2d8f05
LB		 2917 int i;
2918 int cpu = thiscpu->logical_cpu_id;
e275b388 2919
0e2d8f05 2920 for (i = 0; i <= topo.max_cpu_num; i++) {
1b439f01 2921 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i);
0e2d8f05
LB		 2922 filep = fopen(path, "r");
2923 if (!filep)
2924 continue;
2925 fclose(filep);
2926 return i;
e275b388 2927 }
0e2d8f05
LB		 2928 return -1;
2929}
c98d5d94 2930
0e2d8f05
LB		 2931int get_thread_siblings(struct cpu_topology *thiscpu)
2932{
2933 char path[80], character;
2934 FILE *filep;
2935 unsigned long map;
8cb48b32 2936 int so, shift, sib_core;
0e2d8f05
LB		 2937 int cpu = thiscpu->logical_cpu_id;
2938 int offset = topo.max_cpu_num + 1;
2939 size_t size;
8cb48b32 2940 int thread_id = 0;
0e2d8f05
LB		 2941
2942 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
8cb48b32
PB		 2943 if (thiscpu->thread_id < 0)
2944 thiscpu->thread_id = thread_id++;
0e2d8f05
LB		 2945 if (!thiscpu->put_ids)
2946 return -1;
2947
2948 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
2949 CPU_ZERO_S(size, thiscpu->put_ids);
2950
1b439f01 2951 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
3d7772ea
LB		 2952 filep = fopen(path, "r");
2953
2954 if (!filep) {
2955 warnx("%s: open failed", path);
2956 return -1;
2957 }
0e2d8f05
LB		 2958 do {
2959 offset -= BITMASK_SIZE;
8173c336
BH		 2960 if (fscanf(filep, "%lx%c", &map, &character) != 2)
2961 err(1, "%s: failed to parse file", path);
0e2d8f05
LB		 2962 for (shift = 0; shift < BITMASK_SIZE; shift++) {
2963 if ((map >> shift) & 0x1) {
8cb48b32
PB		 2964 so = shift + offset;
2965 sib_core = get_core_id(so);
2966 if (sib_core == thiscpu->physical_core_id) {
2967 CPU_SET_S(so, size, thiscpu->put_ids);
1b439f01
LB		 2968 if ((so != cpu) && (cpus[so].thread_id < 0))
2969 cpus[so].thread_id = thread_id++;
8cb48b32 2970 }
0e2d8f05
LB		 2971 }
2972 }
e13da9a1 2973 } while (character == ',');
c98d5d94 2974 fclose(filep);
0e2d8f05
LB		 2975
2976 return CPU_COUNT_S(size, thiscpu->put_ids);
c98d5d94
LB		 2977}
2978
103a8fea 2979/*
c98d5d94
LB		 2980 * run func(thread, core, package) in topology order
2981 * skip non-present cpus
103a8fea
LB		 2982 */
2983
1b439f01
LB		 2984int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *,
2985 struct pkg_data *, struct thread_data *, struct core_data *,
2986 struct pkg_data *), struct thread_data *thread_base,
2987 struct core_data *core_base, struct pkg_data *pkg_base,
2988 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2)
c98d5d94 2989{
40f5cfe7 2990 int retval, pkg_no, node_no, core_no, thread_no;
c98d5d94
LB		 2991
2992 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
40f5cfe7 2993 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
1b439f01
LB		 2994 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
2995 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
40f5cfe7
PB		 2996 struct thread_data *t, *t2;
2997 struct core_data *c, *c2;
2998 struct pkg_data *p, *p2;
2999
1b439f01 3000 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
40f5cfe7
PB		 3001
3002 if (cpu_is_not_present(t->cpu_id))
3003 continue;
3004
1b439f01 3005 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no);
40f5cfe7 3006
1b439f01
LB		 3007 c = GET_CORE(core_base, core_no, node_no, pkg_no);
3008 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no);
40f5cfe7
PB		 3009
3010 p = GET_PKG(pkg_base, pkg_no);
3011 p2 = GET_PKG(pkg_base2, pkg_no);
3012
3013 retval = func(t, c, p, t2, c2, p2);
3014 if (retval)
3015 return retval;
3016 }
c98d5d94
LB		 3017 }
3018 }
3019 }
3020 return 0;
3021}
3022
3023/*
3024 * run func(cpu) on every cpu in /proc/stat
3025 * return max_cpu number
3026 */
1b439f01 3027int for_all_proc_cpus(int (func) (int))
103a8fea
LB		 3028{
3029 FILE *fp;
c98d5d94 3030 int cpu_num;
103a8fea
LB		 3031 int retval;
3032
57a42a34 3033 fp = fopen_or_die(proc_stat, "r");
103a8fea
LB		 3034
3035 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
b2c95d90
JT		 3036 if (retval != 0)
3037 err(1, "%s: failed to parse format", proc_stat);
103a8fea 3038
c98d5d94
LB		 3039 while (1) {
3040 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
103a8fea
LB		 3041 if (retval != 1)
3042 break;
3043
c98d5d94
LB		 3044 retval = func(cpu_num);
3045 if (retval) {
3046 fclose(fp);
1b439f01 3047 return (retval);
c98d5d94 3048 }
103a8fea
LB		 3049 }
3050 fclose(fp);
c98d5d94 3051 return 0;
103a8fea
LB		 3052}
3053
3054void re_initialize(void)
3055{
c98d5d94
LB		 3056 free_all_buffers();
3057 setup_all_buffers();
3d7772ea 3058 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
103a8fea
LB		 3059}
3060
843c5791
PB		 3061void set_max_cpu_num(void)
3062{
3063 FILE *filep;
8201a028 3064 int base_cpu;
843c5791 3065 unsigned long dummy;
8201a028 3066 char pathname[64];
843c5791 3067
8201a028
PB		 3068 base_cpu = sched_getcpu();
3069 if (base_cpu < 0)
3070 err(1, "cannot find calling cpu ID");
1b439f01 3071 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu);
8201a028
PB		 3072
3073 filep = fopen_or_die(pathname, "r");
843c5791 3074 topo.max_cpu_num = 0;
843c5791 3075 while (fscanf(filep, "%lx,", &dummy) == 1)
0e2d8f05 3076 topo.max_cpu_num += BITMASK_SIZE;
843c5791 3077 fclose(filep);
1b439f01 3078 topo.max_cpu_num--; /* 0 based */
843c5791 3079}
c98d5d94 3080
103a8fea 3081/*
c98d5d94
LB		 3082 * count_cpus()
3083 * remember the last one seen, it will be the max
103a8fea 3084 */
c98d5d94 3085int count_cpus(int cpu)
103a8fea 3086{
9878bf7a
LB		 3087 UNUSED(cpu);
3088
843c5791 3089 topo.num_cpus++;
c98d5d94
LB		 3090 return 0;
3091}
1b439f01 3092
c98d5d94
LB		 3093int mark_cpu_present(int cpu)
3094{
3095 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
15aaa346 3096 return 0;
103a8fea
LB		 3097}
3098
8cb48b32
PB		 3099int init_thread_id(int cpu)
3100{
3101 cpus[cpu].thread_id = -1;
3102 return 0;
3103}
3104
562a2d37
LB		 3105/*
3106 * snapshot_proc_interrupts()
3107 *
3108 * read and record summary of /proc/interrupts
3109 *
3110 * return 1 if config change requires a restart, else return 0
3111 */
3112int snapshot_proc_interrupts(void)
3113{
3114 static FILE *fp;
3115 int column, retval;
3116
3117 if (fp == NULL)
3118 fp = fopen_or_die("/proc/interrupts", "r");
3119 else
3120 rewind(fp);
3121
3122 /* read 1st line of /proc/interrupts to get cpu* name for each column */
3123 for (column = 0; column < topo.num_cpus; ++column) {
3124 int cpu_number;
3125
3126 retval = fscanf(fp, " CPU%d", &cpu_number);
3127 if (retval != 1)
3128 break;
3129
3130 if (cpu_number > topo.max_cpu_num) {
3131 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
3132 return 1;
3133 }
3134
3135 irq_column_2_cpu[column] = cpu_number;
3136 irqs_per_cpu[cpu_number] = 0;
3137 }
3138
3139 /* read /proc/interrupt count lines and sum up irqs per cpu */
3140 while (1) {
3141 int column;
3142 char buf[64];
3143
3144 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
3145 if (retval != 1)
3146 break;
3147
3148 /* read the count per cpu */
3149 for (column = 0; column < topo.num_cpus; ++column) {
3150
3151 int cpu_number, irq_count;
3152
3153 retval = fscanf(fp, " %d", &irq_count);
3154 if (retval != 1)
3155 break;
3156
3157 cpu_number = irq_column_2_cpu[column];
3158 irqs_per_cpu[cpu_number] += irq_count;
3159
3160 }
3161
1b439f01 3162 while (getc(fp) != '\n') ; /* flush interrupt description */
562a2d37
LB		 3163
3164 }
3165 return 0;
3166}
1b439f01 3167
fdf676e5
LB		 3168/*
3169 * snapshot_gfx_rc6_ms()
3170 *
3171 * record snapshot of
3172 * /sys/class/drm/card0/power/rc6_residency_ms
3173 *
3174 * return 1 if config change requires a restart, else return 0
3175 */
3176int snapshot_gfx_rc6_ms(void)
3177{
3178 FILE *fp;
3179 int retval;
3180
3181 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
3182
3183 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
3184 if (retval != 1)
3185 err(1, "GFX rc6");
3186
3187 fclose(fp);
3188
3189 return 0;
3190}
1b439f01 3191
27d47356
LB		 3192/*
3193 * snapshot_gfx_mhz()
3194 *
3195 * record snapshot of
3196 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
3197 *
3198 * return 1 if config change requires a restart, else return 0
3199 */
3200int snapshot_gfx_mhz(void)
3201{
3202 static FILE *fp;
3203 int retval;
3204
3205 if (fp == NULL)
3206 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
22048c54 3207 else {
27d47356 3208 rewind(fp);
22048c54
LB		 3209 fflush(fp);
3210 }
27d47356
LB		 3211
3212 retval = fscanf(fp, "%d", &gfx_cur_mhz);
3213 if (retval != 1)
3214 err(1, "GFX MHz");
3215
3216 return 0;
3217}
562a2d37 3218
b4b91569
RA		 3219/*
3220 * snapshot_gfx_cur_mhz()
3221 *
3222 * record snapshot of
3223 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz
3224 *
3225 * return 1 if config change requires a restart, else return 0
3226 */
3227int snapshot_gfx_act_mhz(void)
3228{
3229 static FILE *fp;
3230 int retval;
3231
3232 if (fp == NULL)
3233 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r");
3234 else {
3235 rewind(fp);
3236 fflush(fp);
3237 }
3238
3239 retval = fscanf(fp, "%d", &gfx_act_mhz);
3240 if (retval != 1)
3241 err(1, "GFX ACT MHz");
3242
3243 return 0;
3244}
3245
be0e54c4
LB		 3246/*
3247 * snapshot_cpu_lpi()
3248 *
3249 * record snapshot of
3250 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
be0e54c4
LB		 3251 */
3252int snapshot_cpu_lpi_us(void)
3253{
3254 FILE *fp;
3255 int retval;
3256
3257 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
3258
3259 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
5ea7647b
PB		 3260 if (retval != 1) {
3261 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
3262 BIC_NOT_PRESENT(BIC_CPU_LPI);
605736c6 3263 fclose(fp);
5ea7647b
PB		 3264 return -1;
3265 }
be0e54c4
LB		 3266
3267 fclose(fp);
3268
3269 return 0;
3270}
1b439f01 3271
be0e54c4
LB		 3272/*
3273 * snapshot_sys_lpi()
3274 *
1f81c5ef 3275 * record snapshot of sys_lpi_file
be0e54c4
LB		 3276 */
3277int snapshot_sys_lpi_us(void)
3278{
3279 FILE *fp;
3280 int retval;
3281
1f81c5ef 3282 fp = fopen_or_die(sys_lpi_file, "r");
be0e54c4
LB		 3283
3284 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
5ea7647b
PB		 3285 if (retval != 1) {
3286 fprintf(stderr, "Disabling Low Power Idle System output\n");
3287 BIC_NOT_PRESENT(BIC_SYS_LPI);
15423b95 3288 fclose(fp);
5ea7647b
PB		 3289 return -1;
3290 }
be0e54c4
LB		 3291 fclose(fp);
3292
3293 return 0;
3294}
1b439f01 3295
562a2d37
LB		 3296/*
3297 * snapshot /proc and /sys files
3298 *
3299 * return 1 if configuration restart needed, else return 0
3300 */
3301int snapshot_proc_sysfs_files(void)
3302{
218f0e8d
LB		 3303 if (DO_BIC(BIC_IRQ))
3304 if (snapshot_proc_interrupts())
3305 return 1;
562a2d37 3306
812db3f7 3307 if (DO_BIC(BIC_GFX_rc6))
fdf676e5
LB		 3308 snapshot_gfx_rc6_ms();
3309
812db3f7 3310 if (DO_BIC(BIC_GFXMHz))
27d47356
LB		 3311 snapshot_gfx_mhz();
3312
b4b91569
RA		 3313 if (DO_BIC(BIC_GFXACTMHz))
3314 snapshot_gfx_act_mhz();
3315
be0e54c4
LB		 3316 if (DO_BIC(BIC_CPU_LPI))
3317 snapshot_cpu_lpi_us();
3318
3319 if (DO_BIC(BIC_SYS_LPI))
3320 snapshot_sys_lpi_us();
3321
562a2d37
LB		 3322 return 0;
3323}
3324
8aa2ed0b
LB		 3325int exit_requested;
3326
1b439f01 3327static void signal_handler(int signal)
8aa2ed0b
LB		 3328{
3329 switch (signal) {
3330 case SIGINT:
3331 exit_requested = 1;
3332 if (debug)
3333 fprintf(stderr, " SIGINT\n");
3334 break;
07211960
LB		 3335 case SIGUSR1:
3336 if (debug > 1)
3337 fprintf(stderr, "SIGUSR1\n");
3338 break;
8aa2ed0b
LB		 3339 }
3340}
3341
3342void setup_signal_handler(void)
3343{
3344 struct sigaction sa;
3345
3346 memset(&sa, 0, sizeof(sa));
3347
3348 sa.sa_handler = &signal_handler;
3349
3350 if (sigaction(SIGINT, &sa, NULL) < 0)
3351 err(1, "sigaction SIGINT");
07211960
LB		 3352 if (sigaction(SIGUSR1, &sa, NULL) < 0)
3353 err(1, "sigaction SIGUSR1");
8aa2ed0b 3354}
b9ad8ee0 3355
47936f94 3356void do_sleep(void)
b9ad8ee0 3357{
c026c236
AB		 3358 struct timeval tout;
3359 struct timespec rest;
b9ad8ee0
LB		 3360 fd_set readfds;
3361 int retval;
3362
3363 FD_ZERO(&readfds);
3364 FD_SET(0, &readfds);
3365
c026c236 3366 if (ignore_stdin) {
47936f94
AB		 3367 nanosleep(&interval_ts, NULL);
3368 return;
3369 }
b9ad8ee0 3370
c026c236
AB		 3371 tout = interval_tv;
3372 retval = select(1, &readfds, NULL, NULL, &tout);
b9ad8ee0
LB		 3373
3374 if (retval == 1) {
b9ad8ee0
LB		 3375 switch (getc(stdin)) {
3376 case 'q':
3377 exit_requested = 1;
3378 break;
c026c236
AB		 3379 case EOF:
3380 /*
3381 * 'stdin' is a pipe closed on the other end. There
3382 * won't be any further input.
3383 */
3384 ignore_stdin = 1;
3385 /* Sleep the rest of the time */
3386 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
3387 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
3388 nanosleep(&rest, NULL);
b9ad8ee0 3389 }
b9ad8ee0 3390 }
b9ad8ee0 3391}
47936f94 3392
87e15da9
CY		 3393int get_msr_sum(int cpu, off_t offset, unsigned long long *msr)
3394{
3395 int ret, idx;
3396 unsigned long long msr_cur, msr_last;
3397
3398 if (!per_cpu_msr_sum)
3399 return 1;
3400
3401 idx = offset_to_idx(offset);
3402 if (idx < 0)
3403 return idx;
3404 /* get_msr_sum() = sum + (get_msr() - last) */
3405 ret = get_msr(cpu, offset, &msr_cur);
3406 if (ret)
3407 return ret;
3408 msr_last = per_cpu_msr_sum[cpu].entries[idx].last;
3409 DELTA_WRAP32(msr_cur, msr_last);
3410 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum;
3411
3412 return 0;
3413}
3414
3415timer_t timerid;
3416
3417/* Timer callback, update the sum of MSRs periodically. */
3418static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3419{
3420 int i, ret;
3421 int cpu = t->cpu_id;
3422
9878bf7a
LB		 3423 UNUSED(c);
3424 UNUSED(p);
3425
87e15da9
CY		 3426 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) {
3427 unsigned long long msr_cur, msr_last;
13a779de 3428 off_t offset;
87e15da9
CY		 3429
3430 if (!idx_valid(i))
3431 continue;
3432 offset = idx_to_offset(i);
3433 if (offset < 0)
3434 continue;
3435 ret = get_msr(cpu, offset, &msr_cur);
3436 if (ret) {
1b439f01 3437 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset);
87e15da9
CY		 3438 continue;
3439 }
3440
3441 msr_last = per_cpu_msr_sum[cpu].entries[i].last;
3442 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff;
3443
3444 DELTA_WRAP32(msr_cur, msr_last);
3445 per_cpu_msr_sum[cpu].entries[i].sum += msr_last;
3446 }
3447 return 0;
3448}
3449
1b439f01 3450static void msr_record_handler(union sigval v)
87e15da9 3451{
9878bf7a
LB		 3452 UNUSED(v);
3453
87e15da9
CY		 3454 for_all_cpus(update_msr_sum, EVEN_COUNTERS);
3455}
3456
3457void msr_sum_record(void)
3458{
3459 struct itimerspec its;
3460 struct sigevent sev;
3461
3462 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array));
3463 if (!per_cpu_msr_sum) {
3464 fprintf(outf, "Can not allocate memory for long time MSR.\n");
3465 return;
3466 }
3467 /*
3468 * Signal handler might be restricted, so use thread notifier instead.
3469 */
3470 memset(&sev, 0, sizeof(struct sigevent));
3471 sev.sigev_notify = SIGEV_THREAD;
3472 sev.sigev_notify_function = msr_record_handler;
3473
3474 sev.sigev_value.sival_ptr = &timerid;
3475 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) {
3476 fprintf(outf, "Can not create timer.\n");
3477 goto release_msr;
3478 }
3479
3480 its.it_value.tv_sec = 0;
3481 its.it_value.tv_nsec = 1;
3482 /*
3483 * A wraparound time has been calculated early.
3484 * Some sources state that the peak power for a
3485 * microprocessor is usually 1.5 times the TDP rating,
3486 * use 2 * TDP for safety.
3487 */
3488 its.it_interval.tv_sec = rapl_joule_counter_range / 2;
3489 its.it_interval.tv_nsec = 0;
3490
3491 if (timer_settime(timerid, 0, &its, NULL) == -1) {
3492 fprintf(outf, "Can not set timer.\n");
3493 goto release_timer;
3494 }
3495 return;
3496
1b439f01 3497release_timer:
87e15da9 3498 timer_delete(timerid);
1b439f01 3499release_msr:
87e15da9
CY		 3500 free(per_cpu_msr_sum);
3501}
4c2122d4 3502
38c6663a
LB		 3503/*
3504 * set_my_sched_priority(pri)
3505 * return previous
3506 */
3507int set_my_sched_priority(int priority)
3508{
3509 int retval;
3510 int original_priority;
3511
3512 errno = 0;
3513 original_priority = getpriority(PRIO_PROCESS, 0);
3514 if (errno && (original_priority == -1))
3515 err(errno, "getpriority");
3516
3517 retval = setpriority(PRIO_PROCESS, 0, priority);
3518 if (retval)
9c085817
PB		 3519 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"",
3520 progname);
38c6663a
LB		 3521
3522 errno = 0;
3523 retval = getpriority(PRIO_PROCESS, 0);
3524 if (retval != priority)
164d7a96 3525 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority);
38c6663a
LB		 3526
3527 return original_priority;
3528}
3529
103a8fea
LB		 3530void turbostat_loop()
3531{
c98d5d94 3532 int retval;
e52966c0 3533 int restarted = 0;
9878bf7a 3534 unsigned int done_iters = 0;
c98d5d94 3535
8aa2ed0b
LB		 3536 setup_signal_handler();
3537
38c6663a
LB		 3538 /*
3539 * elevate own priority for interval mode
3540 */
3541 set_my_sched_priority(-20);
3542
103a8fea 3543restart:
e52966c0
LB		 3544 restarted++;
3545
562a2d37 3546 snapshot_proc_sysfs_files();
c98d5d94 3547 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
4c2122d4 3548 first_counter_read = 0;
d91bb17c
LB		 3549 if (retval < -1) {
3550 exit(retval);
3551 } else if (retval == -1) {
3d7772ea 3552 if (restarted > 10) {
e52966c0
LB		 3553 exit(retval);
3554 }
c98d5d94
LB		 3555 re_initialize();
3556 goto restart;
3557 }
e52966c0 3558 restarted = 0;
023fe0ac 3559 done_iters = 0;
103a8fea
LB		 3560 gettimeofday(&tv_even, (struct timezone *)NULL);
3561
3562 while (1) {
c98d5d94 3563 if (for_all_proc_cpus(cpu_is_not_present)) {
103a8fea
LB		 3564 re_initialize();
3565 goto restart;
3566 }
b9ad8ee0 3567 do_sleep();
562a2d37
LB		 3568 if (snapshot_proc_sysfs_files())
3569 goto restart;
c98d5d94 3570 retval = for_all_cpus(get_counters, ODD_COUNTERS);
d91bb17c
LB		 3571 if (retval < -1) {
3572 exit(retval);
3573 } else if (retval == -1) {
15aaa346
LB		 3574 re_initialize();
3575 goto restart;
3576 }
103a8fea 3577 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 3578 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 3579 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
3580 re_initialize();
3581 goto restart;
3582 }
c98d5d94
LB		 3583 compute_average(EVEN_COUNTERS);
3584 format_all_counters(EVEN_COUNTERS);
b7d8c148 3585 flush_output_stdout();
8aa2ed0b
LB		 3586 if (exit_requested)
3587 break;
023fe0ac
CY		 3588 if (num_iterations && ++done_iters >= num_iterations)
3589 break;
b9ad8ee0 3590 do_sleep();
562a2d37
LB		 3591 if (snapshot_proc_sysfs_files())
3592 goto restart;
c98d5d94 3593 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 3594 if (retval < -1) {
3595 exit(retval);
3596 } else if (retval == -1) {
103a8fea
LB		 3597 re_initialize();
3598 goto restart;
3599 }
103a8fea 3600 gettimeofday(&tv_even, (struct timezone *)NULL);
103a8fea 3601 timersub(&tv_even, &tv_odd, &tv_delta);
ba3dec99
LB		 3602 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
3603 re_initialize();
3604 goto restart;
3605 }
c98d5d94
LB		 3606 compute_average(ODD_COUNTERS);
3607 format_all_counters(ODD_COUNTERS);
b7d8c148 3608 flush_output_stdout();
8aa2ed0b
LB		 3609 if (exit_requested)
3610 break;
023fe0ac
CY		 3611 if (num_iterations && ++done_iters >= num_iterations)
3612 break;
103a8fea
LB		 3613 }
3614}
3615
3616void check_dev_msr()
3617{
3618 struct stat sb;
7ce7d5de 3619 char pathname[32];
103a8fea 3620
7ce7d5de
PB		 3621 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3622 if (stat(pathname, &sb))
1b439f01 3623 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
a21d38c8 3624 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
103a8fea
LB		 3625}
3626
fcaa681c
LB		 3627/*
3628 * check for CAP_SYS_RAWIO
3629 * return 0 on success
3630 * return 1 on fail
3631 */
3632int check_for_cap_sys_rawio(void)
103a8fea 3633{
fcaa681c
LB		 3634 cap_t caps;
3635 cap_flag_value_t cap_flag_value;
98481e79 3636
fcaa681c
LB		 3637 caps = cap_get_proc();
3638 if (caps == NULL)
3639 err(-6, "cap_get_proc\n");
98481e79 3640
fcaa681c
LB		 3641 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
3642 err(-6, "cap_get\n");
3643
3644 if (cap_flag_value != CAP_SET) {
1b439f01 3645 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname);
fcaa681c 3646 return 1;
98481e79
LB		 3647 }
3648
fcaa681c
LB		 3649 if (cap_free(caps) == -1)
3650 err(-6, "cap_free\n");
3651
3652 return 0;
3653}
1b439f01 3654
fcaa681c
LB		 3655void check_permissions(void)
3656{
3657 int do_exit = 0;
3658 char pathname[32];
3659
3660 /* check for CAP_SYS_RAWIO */
3661 do_exit += check_for_cap_sys_rawio();
3662
98481e79 3663 /* test file permissions */
7ce7d5de
PB		 3664 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3665 if (euidaccess(pathname, R_OK)) {
98481e79
LB		 3666 do_exit++;
3667 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
3668 }
3669
3670 /* if all else fails, thell them to be root */
3671 if (do_exit)
3672 if (getuid() != 0)
d7899447 3673 warnx("... or simply run as root");
98481e79
LB		 3674
3675 if (do_exit)
3676 exit(-6);
103a8fea
LB		 3677}
3678
d7899447
LB		 3679/*
3680 * NHM adds support for additional MSRs:
3681 *
3682 * MSR_SMI_COUNT 0x00000034
3683 *
ec0adc53 3684 * MSR_PLATFORM_INFO 0x000000ce
1df2e55a 3685 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
d7899447 3686 *
cf4cbe53
LB		 3687 * MSR_MISC_PWR_MGMT 0x000001aa
3688 *
d7899447
LB		 3689 * MSR_PKG_C3_RESIDENCY 0x000003f8
3690 * MSR_PKG_C6_RESIDENCY 0x000003f9
3691 * MSR_CORE_C3_RESIDENCY 0x000003fc
3692 * MSR_CORE_C6_RESIDENCY 0x000003fd
3693 *
ee7e38e3 3694 * Side effect:
1df2e55a 3695 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
33148d67 3696 * sets has_misc_feature_control
d7899447 3697 */
ee7e38e3 3698int probe_nhm_msrs(unsigned int family, unsigned int model)
103a8fea 3699{
ee7e38e3 3700 unsigned long long msr;
21ed5574 3701 unsigned int base_ratio;
ee7e38e3
LB		 3702 int *pkg_cstate_limits;
3703
103a8fea
LB		 3704 if (!genuine_intel)
3705 return 0;
3706
3707 if (family != 6)
3708 return 0;
3709
21ed5574
LB		 3710 bclk = discover_bclk(family, model);
3711
103a8fea 3712 switch (model) {
869ce69e 3713 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
869ce69e 3714 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
ee7e38e3
LB		 3715 pkg_cstate_limits = nhm_pkg_cstate_limits;
3716 break;
869ce69e
LB		 3717 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
3718 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
3719 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3720 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
ee7e38e3 3721 pkg_cstate_limits = snb_pkg_cstate_limits;
33148d67 3722 has_misc_feature_control = 1;
ee7e38e3 3723 break;
c66f78a6 3724 case INTEL_FAM6_HASWELL: /* HSW */
5e741407 3725 case INTEL_FAM6_HASWELL_G: /* HSW */
869ce69e 3726 case INTEL_FAM6_HASWELL_X: /* HSX */
77e5517c 3727 case INTEL_FAM6_HASWELL_L: /* HSW */
c66f78a6 3728 case INTEL_FAM6_BROADWELL: /* BDW */
5e741407 3729 case INTEL_FAM6_BROADWELL_G: /* BDW */
869ce69e 3730 case INTEL_FAM6_BROADWELL_X: /* BDX */
af239c44
PZ		 3731 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3732 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
ee7e38e3 3733 pkg_cstate_limits = hsw_pkg_cstate_limits;
33148d67 3734 has_misc_feature_control = 1;
ee7e38e3 3735 break;
d8ebb442 3736 case INTEL_FAM6_SKYLAKE_X: /* SKX */
0e4d42af 3737 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
d8ebb442 3738 pkg_cstate_limits = skx_pkg_cstate_limits;
33148d67 3739 has_misc_feature_control = 1;
d8ebb442 3740 break;
25368d7c
CY		 3741 case INTEL_FAM6_ICELAKE_X: /* ICX */
3742 pkg_cstate_limits = icx_pkg_cstate_limits;
3743 has_misc_feature_control = 1;
3744 break;
f2c4db1b 3745 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
cf4cbe53 3746 no_MSR_MISC_PWR_MGMT = 1;
9878bf7a 3747 /* FALLTHRU */
5ebb34ed 3748 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
ee7e38e3
LB		 3749 pkg_cstate_limits = slv_pkg_cstate_limits;
3750 break;
869ce69e 3751 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
ee7e38e3 3752 pkg_cstate_limits = amt_pkg_cstate_limits;
cf4cbe53 3753 no_MSR_MISC_PWR_MGMT = 1;
ee7e38e3 3754 break;
869ce69e 3755 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
ee7e38e3
LB		 3756 pkg_cstate_limits = phi_pkg_cstate_limits;
3757 break;
869ce69e 3758 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 3759 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5ebb34ed 3760 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
f6708400 3761 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
1b439f01 3762 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
445640a5 3763 pkg_cstate_limits = glm_pkg_cstate_limits;
e4085d54 3764 break;
103a8fea
LB		 3765 default:
3766 return 0;
3767 }
1df2e55a 3768 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
e9257f5f 3769 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
ee7e38e3 3770
ec0adc53 3771 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
21ed5574
LB		 3772 base_ratio = (msr >> 8) & 0xFF;
3773
3774 base_hz = base_ratio * bclk * 1000000;
3775 has_base_hz = 1;
ee7e38e3 3776 return 1;
103a8fea 3777}
1b439f01 3778
0f7887c4 3779/*
495c7654 3780 * SLV client has support for unique MSRs:
0f7887c4
LB		 3781 *
3782 * MSR_CC6_DEMOTION_POLICY_CONFIG
3783 * MSR_MC6_DEMOTION_POLICY_CONFIG
3784 */
3785
3786int has_slv_msrs(unsigned int family, unsigned int model)
3787{
3788 if (!genuine_intel)
3789 return 0;
3790
9878bf7a
LB		 3791 if (family != 6)
3792 return 0;
3793
0f7887c4 3794 switch (model) {
f2c4db1b
PZ		 3795 case INTEL_FAM6_ATOM_SILVERMONT:
3796 case INTEL_FAM6_ATOM_SILVERMONT_MID:
3797 case INTEL_FAM6_ATOM_AIRMONT_MID:
0f7887c4
LB		 3798 return 1;
3799 }
3800 return 0;
3801}
1b439f01 3802
7170a374
LB		 3803int is_dnv(unsigned int family, unsigned int model)
3804{
3805
3806 if (!genuine_intel)
3807 return 0;
3808
9878bf7a
LB		 3809 if (family != 6)
3810 return 0;
3811
7170a374 3812 switch (model) {
5ebb34ed 3813 case INTEL_FAM6_ATOM_GOLDMONT_D:
7170a374
LB		 3814 return 1;
3815 }
3816 return 0;
3817}
1b439f01 3818
ade0ebac
LB		 3819int is_bdx(unsigned int family, unsigned int model)
3820{
3821
3822 if (!genuine_intel)
3823 return 0;
3824
9878bf7a
LB		 3825 if (family != 6)
3826 return 0;
3827
ade0ebac
LB		 3828 switch (model) {
3829 case INTEL_FAM6_BROADWELL_X:
ade0ebac
LB		 3830 return 1;
3831 }
3832 return 0;
3833}
1b439f01 3834
34c76197
LB		 3835int is_skx(unsigned int family, unsigned int model)
3836{
3837
3838 if (!genuine_intel)
3839 return 0;
3840
9878bf7a
LB		 3841 if (family != 6)
3842 return 0;
3843
34c76197
LB		 3844 switch (model) {
3845 case INTEL_FAM6_SKYLAKE_X:
3846 return 1;
3847 }
3848 return 0;
3849}
25368d7c
CY		 3850
3851int is_icx(unsigned int family, unsigned int model)
3852{
3853
3854 if (!genuine_intel)
3855 return 0;
3856
9878bf7a
LB		 3857 if (family != 6)
3858 return 0;
3859
25368d7c
CY		 3860 switch (model) {
3861 case INTEL_FAM6_ICELAKE_X:
3862 return 1;
3863 }
3864 return 0;
3865}
3866
684e40e9
AB		 3867int is_spr(unsigned int family, unsigned int model)
3868{
3869
3870 if (!genuine_intel)
3871 return 0;
3872
3873 if (family != 6)
3874 return 0;
3875
3876 switch (model) {
3877 case INTEL_FAM6_SAPPHIRERAPIDS_X:
3878 return 1;
3879 }
3880 return 0;
3881}
3882
f6708400
CY		 3883int is_ehl(unsigned int family, unsigned int model)
3884{
3885 if (!genuine_intel)
3886 return 0;
3887
9878bf7a
LB		 3888 if (family != 6)
3889 return 0;
3890
f6708400
CY		 3891 switch (model) {
3892 case INTEL_FAM6_ATOM_TREMONT:
3893 return 1;
3894 }
3895 return 0;
3896}
1b439f01 3897
20de0dab
AL		 3898int is_jvl(unsigned int family, unsigned int model)
3899{
3900 if (!genuine_intel)
3901 return 0;
3902
9878bf7a
LB		 3903 if (family != 6)
3904 return 0;
3905
20de0dab
AL		 3906 switch (model) {
3907 case INTEL_FAM6_ATOM_TREMONT_D:
3908 return 1;
3909 }
3910 return 0;
3911}
0f7887c4 3912
31e07522 3913int has_turbo_ratio_limit(unsigned int family, unsigned int model)
d7899447 3914{
0f7887c4
LB		 3915 if (has_slv_msrs(family, model))
3916 return 0;
3917
9878bf7a
LB		 3918 if (family != 6)
3919 return 0;
3920
d7899447 3921 switch (model) {
1b439f01 3922 /* Nehalem compatible, but do not include turbo-ratio limit support */
869ce69e 3923 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
869ce69e 3924 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
d7899447
LB		 3925 return 0;
3926 default:
3927 return 1;
3928 }
3929}
1b439f01 3930
0f7887c4
LB		 3931int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
3932{
3933 if (has_slv_msrs(family, model))
3934 return 1;
3935
3936 return 0;
3937}
1b439f01 3938
6574a5d5
LB		 3939int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
3940{
3941 if (!genuine_intel)
3942 return 0;
3943
3944 if (family != 6)
3945 return 0;
3946
3947 switch (model) {
869ce69e
LB		 3948 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3949 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
fcd17211
LB		 3950 return 1;
3951 default:
3952 return 0;
3953 }
3954}
1b439f01 3955
fcd17211
LB		 3956int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
3957{
3958 if (!genuine_intel)
3959 return 0;
3960
3961 if (family != 6)
3962 return 0;
3963
3964 switch (model) {
869ce69e 3965 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
6574a5d5
LB		 3966 return 1;
3967 default:
3968 return 0;
3969 }
3970}
3971
fb5d4327
DC		 3972int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
3973{
3974 if (!genuine_intel)
3975 return 0;
3976
3977 if (family != 6)
3978 return 0;
3979
3980 switch (model) {
869ce69e 3981 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
fb5d4327
DC		 3982 return 1;
3983 default:
3984 return 0;
3985 }
3986}
1b439f01 3987
31e07522
LB		 3988int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
3989{
3990 if (!genuine_intel)
3991 return 0;
3992
3993 if (family != 6)
3994 return 0;
3995
3996 switch (model) {
3997 case INTEL_FAM6_ATOM_GOLDMONT:
3998 case INTEL_FAM6_SKYLAKE_X:
25368d7c 3999 case INTEL_FAM6_ICELAKE_X:
684e40e9 4000 case INTEL_FAM6_SAPPHIRERAPIDS_X:
31e07522
LB		 4001 return 1;
4002 default:
4003 return 0;
4004 }
4005}
1b439f01 4006
6fb3143b
LB		 4007int has_config_tdp(unsigned int family, unsigned int model)
4008{
4009 if (!genuine_intel)
4010 return 0;
4011
4012 if (family != 6)
4013 return 0;
4014
4015 switch (model) {
869ce69e 4016 case INTEL_FAM6_IVYBRIDGE: /* IVB */
c66f78a6 4017 case INTEL_FAM6_HASWELL: /* HSW */
869ce69e 4018 case INTEL_FAM6_HASWELL_X: /* HSX */
77e5517c 4019 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 4020 case INTEL_FAM6_HASWELL_G: /* HSW */
c66f78a6 4021 case INTEL_FAM6_BROADWELL: /* BDW */
5e741407 4022 case INTEL_FAM6_BROADWELL_G: /* BDW */
869ce69e 4023 case INTEL_FAM6_BROADWELL_X: /* BDX */
af239c44
PZ		 4024 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4025 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
869ce69e 4026 case INTEL_FAM6_SKYLAKE_X: /* SKX */
25368d7c 4027 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 4028 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
869ce69e 4029 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
6fb3143b
LB		 4030 return 1;
4031 default:
4032 return 0;
4033 }
4034}
4035
0b9a0b9b
ZR		 4036/*
4037 * tcc_offset_bits:
4038 * 0: Tcc Offset not supported (Default)
4039 * 6: Bit 29:24 of MSR_PLATFORM_INFO
4040 * 4: Bit 27:24 of MSR_PLATFORM_INFO
4041 */
4042void check_tcc_offset(int model)
4043{
4044 unsigned long long msr;
4045
4046 if (!genuine_intel)
4047 return;
4048
4049 switch (model) {
4050 case INTEL_FAM6_SKYLAKE_L:
4051 case INTEL_FAM6_SKYLAKE:
4052 case INTEL_FAM6_KABYLAKE_L:
4053 case INTEL_FAM6_KABYLAKE:
4054 case INTEL_FAM6_ICELAKE_L:
4055 case INTEL_FAM6_ICELAKE:
4056 case INTEL_FAM6_TIGERLAKE_L:
4057 case INTEL_FAM6_TIGERLAKE:
4058 case INTEL_FAM6_COMETLAKE:
4059 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) {
4060 msr = (msr >> 30) & 1;
4061 if (msr)
4062 tcc_offset_bits = 6;
4063 }
4064 return;
4065 default:
4066 return;
4067 }
4068}
4069
1b439f01 4070static void remove_underbar(char *s)
fecb3bc8
DA		 4071{
4072 char *to = s;
4073
4074 while (*s) {
4075 if (*s != '_')
4076 *to++ = *s;
4077 s++;
4078 }
4079
4080 *to = 0;
4081}
4082
3ea8e52e 4083static void dump_turbo_ratio_info(unsigned int family, unsigned int model)
fcd17211 4084{
3ea8e52e 4085 if (!has_turbo)
fcd17211
LB		 4086 return;
4087
fcd17211
LB		 4088 if (has_hsw_turbo_ratio_limit(family, model))
4089 dump_hsw_turbo_ratio_limits();
4090
4091 if (has_ivt_turbo_ratio_limit(family, model))
4092 dump_ivt_turbo_ratio_limits();
4093
4af184ee
LB		 4094 if (has_turbo_ratio_limit(family, model)) {
4095 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT, family, model);
4096
4097 if (is_hybrid)
4098 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT, family, model);
4099 }
fcd17211 4100
0f7887c4
LB		 4101 if (has_atom_turbo_ratio_limit(family, model))
4102 dump_atom_turbo_ratio_limits();
4103
fb5d4327
DC		 4104 if (has_knl_turbo_ratio_limit(family, model))
4105 dump_knl_turbo_ratio_limits();
4106
6fb3143b
LB		 4107 if (has_config_tdp(family, model))
4108 dump_config_tdp();
3ea8e52e 4109}
6fb3143b 4110
3ea8e52e
AB		 4111static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
4112{
4113 if (!do_nhm_platform_info)
4114 return;
4115
4116 dump_nhm_platform_info();
4117 dump_turbo_ratio_info(family, model);
fcd17211
LB		 4118 dump_nhm_cst_cfg();
4119}
4120
a5c6d65d
LB		 4121static int read_sysfs_int(char *path)
4122{
4123 FILE *input;
4124 int retval = -1;
4125
4126 input = fopen(path, "r");
4127 if (input == NULL) {
4128 if (debug)
4129 fprintf(outf, "NSFOD %s\n", path);
4130 return (-1);
4131 }
4132 if (fscanf(input, "%d", &retval) != 1)
4133 err(1, "%s: failed to read int from file", path);
4134 fclose(input);
4135
4136 return (retval);
4137}
4138
abdcbdb2
LB		 4139static void dump_sysfs_file(char *path)
4140{
4141 FILE *input;
4142 char cpuidle_buf[64];
4143
4144 input = fopen(path, "r");
4145 if (input == NULL) {
4146 if (debug)
4147 fprintf(outf, "NSFOD %s\n", path);
4148 return;
4149 }
4150 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input))
4151 err(1, "%s: failed to read file", path);
4152 fclose(input);
4153
4154 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf);
4155}
1b439f01 4156
a5c6d65d
LB		 4157static void intel_uncore_frequency_probe(void)
4158{
4159 int i, j;
4160 char path[128];
4161
4162 if (!genuine_intel)
4163 return;
4164
4165 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK))
4166 return;
4167
4168 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK))
4169 BIC_PRESENT(BIC_UNCORE_MHZ);
4170
4171 if (quiet)
4172 return;
4173
4174 for (i = 0; i < topo.num_packages; ++i) {
4175 for (j = 0; j < topo.num_die; ++j) {
4176 int k, l;
4177
4178 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz",
4179 i, j);
4180 k = read_sysfs_int(path);
4181 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz",
4182 i, j);
4183 l = read_sysfs_int(path);
4184 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000);
4185
4186 sprintf(path,
4187 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz",
4188 i, j);
4189 k = read_sysfs_int(path);
4190 sprintf(path,
4191 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz",
4192 i, j);
4193 l = read_sysfs_int(path);
4194 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000);
4195 }
4196 }
4197}
4198
1b439f01 4199static void dump_sysfs_cstate_config(void)
41618e63
LB		 4200{
4201 char path[64];
4202 char name_buf[16];
4203 char desc[64];
4204 FILE *input;
4205 int state;
4206 char *sp;
4207
abdcbdb2
LB		 4208 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) {
4209 fprintf(outf, "cpuidle not loaded\n");
4210 return;
4211 }
4212
4213 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver");
4214 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor");
4215 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro");
4216
41618e63
LB		 4217 for (state = 0; state < 10; ++state) {
4218
1b439f01 4219 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 4220 input = fopen(path, "r");
4221 if (input == NULL)
4222 continue;
8173c336
BH		 4223 if (!fgets(name_buf, sizeof(name_buf), input))
4224 err(1, "%s: failed to read file", path);
41618e63 4225
1b439f01 4226 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 4227 sp = strchr(name_buf, '-');
4228 if (!sp)
4229 sp = strchrnul(name_buf, '\n');
4230 *sp = '\0';
41618e63
LB		 4231 fclose(input);
4232
fecb3bc8
DA		 4233 remove_underbar(name_buf);
4234
1b439f01 4235 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state);
41618e63
LB		 4236 input = fopen(path, "r");
4237 if (input == NULL)
4238 continue;
8173c336
BH		 4239 if (!fgets(desc, sizeof(desc), input))
4240 err(1, "%s: failed to read file", path);
41618e63
LB		 4241
4242 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
4243 fclose(input);
4244 }
4245}
1b439f01
LB		 4246
4247static void dump_sysfs_pstate_config(void)
7293fccd
LB		 4248{
4249 char path[64];
4250 char driver_buf[64];
4251 char governor_buf[64];
4252 FILE *input;
4253 int turbo;
4254
1b439f01 4255 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu);
7293fccd
LB		 4256 input = fopen(path, "r");
4257 if (input == NULL) {
0a42d235 4258 fprintf(outf, "NSFOD %s\n", path);
7293fccd
LB		 4259 return;
4260 }
8173c336
BH		 4261 if (!fgets(driver_buf, sizeof(driver_buf), input))
4262 err(1, "%s: failed to read file", path);
7293fccd
LB		 4263 fclose(input);
4264
1b439f01 4265 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu);
7293fccd
LB		 4266 input = fopen(path, "r");
4267 if (input == NULL) {
0a42d235 4268 fprintf(outf, "NSFOD %s\n", path);
7293fccd
LB		 4269 return;
4270 }
8173c336
BH		 4271 if (!fgets(governor_buf, sizeof(governor_buf), input))
4272 err(1, "%s: failed to read file", path);
7293fccd
LB		 4273 fclose(input);
4274
4275 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
4276 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
4277
4278 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
4279 input = fopen(path, "r");
4280 if (input != NULL) {
8173c336
BH		 4281 if (fscanf(input, "%d", &turbo) != 1)
4282 err(1, "%s: failed to parse number from file", path);
7293fccd
LB		 4283 fprintf(outf, "cpufreq boost: %d\n", turbo);
4284 fclose(input);
4285 }
4286
4287 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
4288 input = fopen(path, "r");
4289 if (input != NULL) {
8173c336
BH		 4290 if (fscanf(input, "%d", &turbo) != 1)
4291 err(1, "%s: failed to parse number from file", path);
7293fccd
LB		 4292 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
4293 fclose(input);
4294 }
4295}
41618e63 4296
889facbe
LB		 4297/*
4298 * print_epb()
4299 * Decode the ENERGY_PERF_BIAS MSR
4300 */
4301int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4302{
889facbe 4303 char *epb_string;
6d6501d9 4304 int cpu, epb;
889facbe 4305
9878bf7a
LB		 4306 UNUSED(c);
4307 UNUSED(p);
4308
889facbe
LB		 4309 if (!has_epb)
4310 return 0;
4311
4312 cpu = t->cpu_id;
4313
4314 /* EPB is per-package */
4315 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4316 return 0;
4317
4318 if (cpu_migrate(cpu)) {
3d7772ea 4319 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 4320 return -1;
4321 }
4322
6d6501d9
BP		 4323 epb = get_epb(cpu);
4324 if (epb < 0)
889facbe
LB		 4325 return 0;
4326
6d6501d9 4327 switch (epb) {
889facbe
LB		 4328 case ENERGY_PERF_BIAS_PERFORMANCE:
4329 epb_string = "performance";
4330 break;
4331 case ENERGY_PERF_BIAS_NORMAL:
4332 epb_string = "balanced";
4333 break;
4334 case ENERGY_PERF_BIAS_POWERSAVE:
4335 epb_string = "powersave";
4336 break;
4337 default:
4338 epb_string = "custom";
4339 break;
4340 }
6d6501d9 4341 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string);
889facbe
LB		 4342
4343 return 0;
4344}
1b439f01 4345
7f5c258e
LB		 4346/*
4347 * print_hwp()
4348 * Decode the MSR_HWP_CAPABILITIES
4349 */
4350int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4351{
4352 unsigned long long msr;
4353 int cpu;
4354
9878bf7a
LB		 4355 UNUSED(c);
4356 UNUSED(p);
4357
7f5c258e
LB		 4358 if (!has_hwp)
4359 return 0;
4360
4361 cpu = t->cpu_id;
4362
4363 /* MSR_HWP_CAPABILITIES is per-package */
4364 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4365 return 0;
4366
4367 if (cpu_migrate(cpu)) {
3d7772ea 4368 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu);
7f5c258e
LB		 4369 return -1;
4370 }
4371
4372 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
4373 return 0;
4374
1b439f01 4375 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-");
7f5c258e
LB		 4376
4377 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
4378 if ((msr & (1 << 0)) == 0)
4379 return 0;
4380
4381 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
4382 return 0;
4383
b7d8c148 4384 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
1b439f01
LB		 4385 "(high %d guar %d eff %d low %d)\n",
4386 cpu, msr,
4387 (unsigned int)HWP_HIGHEST_PERF(msr),
4388 (unsigned int)HWP_GUARANTEED_PERF(msr),
4389 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr));
7f5c258e
LB		 4390
4391 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
4392 return 0;
4393
b7d8c148 4394 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
1b439f01
LB		 4395 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
4396 cpu, msr,
4397 (unsigned int)(((msr) >> 0) & 0xff),
4398 (unsigned int)(((msr) >> 8) & 0xff),
4399 (unsigned int)(((msr) >> 16) & 0xff),
4400 (unsigned int)(((msr) >> 24) & 0xff),
4401 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1));
7f5c258e
LB		 4402
4403 if (has_hwp_pkg) {
4404 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
4405 return 0;
4406
b7d8c148 4407 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
6dbd25a2 4408 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
7f5c258e
LB		 4409 cpu, msr,
4410 (unsigned int)(((msr) >> 0) & 0xff),
4411 (unsigned int)(((msr) >> 8) & 0xff),
4412 (unsigned int)(((msr) >> 16) & 0xff),
1b439f01 4413 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3));
7f5c258e
LB		 4414 }
4415 if (has_hwp_notify) {
4416 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
4417 return 0;
4418
b7d8c148 4419 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
7f5c258e 4420 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
1b439f01 4421 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis");
7f5c258e
LB		 4422 }
4423 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
4424 return 0;
4425
b7d8c148 4426 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
1b439f01 4427 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
92c25393 4428 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-");
889facbe
LB		 4429
4430 return 0;
4431}
4432
3a9a941d
LB		 4433/*
4434 * print_perf_limit()
4435 */
4436int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4437{
4438 unsigned long long msr;
4439 int cpu;
4440
9878bf7a
LB		 4441 UNUSED(c);
4442 UNUSED(p);
4443
3a9a941d
LB		 4444 cpu = t->cpu_id;
4445
4446 /* per-package */
4447 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4448 return 0;
4449
4450 if (cpu_migrate(cpu)) {
3d7772ea 4451 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu);
3a9a941d
LB		 4452 return -1;
4453 }
4454
4455 if (do_core_perf_limit_reasons) {
4456 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4457 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4458 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
e33cbe85 4459 (msr & 1 << 15) ? "bit15, " : "",
3a9a941d 4460 (msr & 1 << 14) ? "bit14, " : "",
e33cbe85
LB		 4461 (msr & 1 << 13) ? "Transitions, " : "",
4462 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
4463 (msr & 1 << 11) ? "PkgPwrL2, " : "",
4464 (msr & 1 << 10) ? "PkgPwrL1, " : "",
4465 (msr & 1 << 9) ? "CorePwr, " : "",
4466 (msr & 1 << 8) ? "Amps, " : "",
4467 (msr & 1 << 6) ? "VR-Therm, " : "",
4468 (msr & 1 << 5) ? "Auto-HWP, " : "",
4469 (msr & 1 << 4) ? "Graphics, " : "",
4470 (msr & 1 << 2) ? "bit2, " : "",
1b439f01 4471 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : "");
b7d8c148 4472 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
e33cbe85 4473 (msr & 1 << 31) ? "bit31, " : "",
3a9a941d 4474 (msr & 1 << 30) ? "bit30, " : "",
e33cbe85
LB		 4475 (msr & 1 << 29) ? "Transitions, " : "",
4476 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
4477 (msr & 1 << 27) ? "PkgPwrL2, " : "",
4478 (msr & 1 << 26) ? "PkgPwrL1, " : "",
4479 (msr & 1 << 25) ? "CorePwr, " : "",
4480 (msr & 1 << 24) ? "Amps, " : "",
4481 (msr & 1 << 22) ? "VR-Therm, " : "",
4482 (msr & 1 << 21) ? "Auto-HWP, " : "",
4483 (msr & 1 << 20) ? "Graphics, " : "",
4484 (msr & 1 << 18) ? "bit18, " : "",
1b439f01 4485 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : "");
3a9a941d
LB		 4486
4487 }
4488 if (do_gfx_perf_limit_reasons) {
4489 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4490 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4491 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3a9a941d
LB		 4492 (msr & 1 << 0) ? "PROCHOT, " : "",
4493 (msr & 1 << 1) ? "ThermStatus, " : "",
4494 (msr & 1 << 4) ? "Graphics, " : "",
4495 (msr & 1 << 6) ? "VR-Therm, " : "",
4496 (msr & 1 << 8) ? "Amps, " : "",
4497 (msr & 1 << 9) ? "GFXPwr, " : "",
1b439f01 4498 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 4499 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3a9a941d
LB		 4500 (msr & 1 << 16) ? "PROCHOT, " : "",
4501 (msr & 1 << 17) ? "ThermStatus, " : "",
4502 (msr & 1 << 20) ? "Graphics, " : "",
4503 (msr & 1 << 22) ? "VR-Therm, " : "",
4504 (msr & 1 << 24) ? "Amps, " : "",
4505 (msr & 1 << 25) ? "GFXPwr, " : "",
1b439f01 4506 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
3a9a941d
LB		 4507 }
4508 if (do_ring_perf_limit_reasons) {
4509 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 4510 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4511 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3a9a941d
LB		 4512 (msr & 1 << 0) ? "PROCHOT, " : "",
4513 (msr & 1 << 1) ? "ThermStatus, " : "",
4514 (msr & 1 << 6) ? "VR-Therm, " : "",
4515 (msr & 1 << 8) ? "Amps, " : "",
1b439f01 4516 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 4517 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3a9a941d
LB		 4518 (msr & 1 << 16) ? "PROCHOT, " : "",
4519 (msr & 1 << 17) ? "ThermStatus, " : "",
4520 (msr & 1 << 22) ? "VR-Therm, " : "",
4521 (msr & 1 << 24) ? "Amps, " : "",
1b439f01 4522 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
3a9a941d
LB		 4523 }
4524 return 0;
4525}
4526
889facbe 4527#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
1b439f01 4528#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
889facbe 4529
9392bd98 4530double get_tdp_intel(unsigned int model)
144b44b1
LB		 4531{
4532 unsigned long long msr;
4533
4534 if (do_rapl & RAPL_PKG_POWER_INFO)
7ce7d5de 4535 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
144b44b1
LB		 4536 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
4537
4538 switch (model) {
f2c4db1b 4539 case INTEL_FAM6_ATOM_SILVERMONT:
5ebb34ed 4540 case INTEL_FAM6_ATOM_SILVERMONT_D:
144b44b1
LB		 4541 return 30.0;
4542 default:
4543 return 135.0;
4544 }
4545}
4546
9392bd98
CW		 4547double get_tdp_amd(unsigned int family)
4548{
9878bf7a
LB		 4549 UNUSED(family);
4550
33eb8225
KP		 4551 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */
4552 return 280.0;
9392bd98
CW		 4553}
4554
40ee8e3b
AS		 4555/*
4556 * rapl_dram_energy_units_probe()
4557 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
4558 */
1b439f01 4559static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
40ee8e3b
AS		 4560{
4561 /* only called for genuine_intel, family 6 */
4562
4563 switch (model) {
869ce69e
LB		 4564 case INTEL_FAM6_HASWELL_X: /* HSX */
4565 case INTEL_FAM6_BROADWELL_X: /* BDX */
abdc75ab 4566 case INTEL_FAM6_SKYLAKE_X: /* SKX */
869ce69e 4567 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
6397b641 4568 case INTEL_FAM6_ICELAKE_X: /* ICX */
40ee8e3b
AS		 4569 return (rapl_dram_energy_units = 15.3 / 1000000);
4570 default:
4571 return (rapl_energy_units);
4572 }
4573}
4574
9392bd98 4575void rapl_probe_intel(unsigned int family, unsigned int model)
889facbe
LB		 4576{
4577 unsigned long long msr;
144b44b1 4578 unsigned int time_unit;
889facbe
LB		 4579 double tdp;
4580
889facbe
LB		 4581 if (family != 6)
4582 return;
4583
4584 switch (model) {
869ce69e
LB		 4585 case INTEL_FAM6_SANDYBRIDGE:
4586 case INTEL_FAM6_IVYBRIDGE:
c66f78a6 4587 case INTEL_FAM6_HASWELL: /* HSW */
77e5517c 4588 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 4589 case INTEL_FAM6_HASWELL_G: /* HSW */
c66f78a6 4590 case INTEL_FAM6_BROADWELL: /* BDW */
5e741407 4591 case INTEL_FAM6_BROADWELL_G: /* BDW */
144b44b1 4592 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4593 if (rapl_joules) {
4594 BIC_PRESENT(BIC_Pkg_J);
4595 BIC_PRESENT(BIC_Cor_J);
4596 BIC_PRESENT(BIC_GFX_J);
4597 } else {
4598 BIC_PRESENT(BIC_PkgWatt);
4599 BIC_PRESENT(BIC_CorWatt);
4600 BIC_PRESENT(BIC_GFXWatt);
4601 }
889facbe 4602 break;
869ce69e 4603 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 4604 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
e4085d54 4605 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4606 if (rapl_joules)
4607 BIC_PRESENT(BIC_Pkg_J);
4608 else
4609 BIC_PRESENT(BIC_PkgWatt);
e4085d54 4610 break;
f6708400 4611 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
1b439f01
LB		 4612 do_rapl =
4613 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4614 | RAPL_GFX | RAPL_PKG_POWER_INFO;
f6708400
CY		 4615 if (rapl_joules) {
4616 BIC_PRESENT(BIC_Pkg_J);
4617 BIC_PRESENT(BIC_Cor_J);
4618 BIC_PRESENT(BIC_RAM_J);
4619 BIC_PRESENT(BIC_GFX_J);
4620 } else {
4621 BIC_PRESENT(BIC_PkgWatt);
4622 BIC_PRESENT(BIC_CorWatt);
4623 BIC_PRESENT(BIC_RAMWatt);
4624 BIC_PRESENT(BIC_GFXWatt);
4625 }
4626 break;
20de0dab
AL		 4627 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
4628 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
4629 BIC_PRESENT(BIC_PKG__);
4630 if (rapl_joules)
4631 BIC_PRESENT(BIC_Pkg_J);
4632 else
4633 BIC_PRESENT(BIC_PkgWatt);
4634 break;
af239c44
PZ		 4635 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4636 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
1b439f01
LB		 4637 do_rapl =
4638 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4639 | RAPL_GFX | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4640 BIC_PRESENT(BIC_PKG__);
4641 BIC_PRESENT(BIC_RAM__);
4642 if (rapl_joules) {
4643 BIC_PRESENT(BIC_Pkg_J);
4644 BIC_PRESENT(BIC_Cor_J);
4645 BIC_PRESENT(BIC_RAM_J);
81824921 4646 BIC_PRESENT(BIC_GFX_J);
812db3f7
LB		 4647 } else {
4648 BIC_PRESENT(BIC_PkgWatt);
4649 BIC_PRESENT(BIC_CorWatt);
4650 BIC_PRESENT(BIC_RAMWatt);
81824921 4651 BIC_PRESENT(BIC_GFXWatt);
812db3f7 4652 }
0b2bb692 4653 break;
869ce69e
LB		 4654 case INTEL_FAM6_HASWELL_X: /* HSX */
4655 case INTEL_FAM6_BROADWELL_X: /* BDX */
869ce69e 4656 case INTEL_FAM6_SKYLAKE_X: /* SKX */
25368d7c 4657 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 4658 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
869ce69e 4659 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
1b439f01
LB		 4660 do_rapl =
4661 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4662 RAPL_PKG_POWER_INFO;
812db3f7
LB		 4663 BIC_PRESENT(BIC_PKG__);
4664 BIC_PRESENT(BIC_RAM__);
4665 if (rapl_joules) {
4666 BIC_PRESENT(BIC_Pkg_J);
4667 BIC_PRESENT(BIC_RAM_J);
4668 } else {
4669 BIC_PRESENT(BIC_PkgWatt);
4670 BIC_PRESENT(BIC_RAMWatt);
4671 }
e6f9bb3c 4672 break;
869ce69e
LB		 4673 case INTEL_FAM6_SANDYBRIDGE_X:
4674 case INTEL_FAM6_IVYBRIDGE_X:
1b439f01
LB		 4675 do_rapl =
4676 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS |
4677 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
812db3f7
LB		 4678 BIC_PRESENT(BIC_PKG__);
4679 BIC_PRESENT(BIC_RAM__);
4680 if (rapl_joules) {
4681 BIC_PRESENT(BIC_Pkg_J);
4682 BIC_PRESENT(BIC_Cor_J);
4683 BIC_PRESENT(BIC_RAM_J);
4684 } else {
4685 BIC_PRESENT(BIC_PkgWatt);
4686 BIC_PRESENT(BIC_CorWatt);
4687 BIC_PRESENT(BIC_RAMWatt);
4688 }
144b44b1 4689 break;
f2c4db1b 4690 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5ebb34ed 4691 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
9148494c 4692 do_rapl = RAPL_PKG | RAPL_CORES;
812db3f7
LB		 4693 if (rapl_joules) {
4694 BIC_PRESENT(BIC_Pkg_J);
4695 BIC_PRESENT(BIC_Cor_J);
4696 } else {
4697 BIC_PRESENT(BIC_PkgWatt);
4698 BIC_PRESENT(BIC_CorWatt);
4699 }
889facbe 4700 break;
5ebb34ed 4701 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
1b439f01
LB		 4702 do_rapl =
4703 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4704 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
812db3f7
LB		 4705 BIC_PRESENT(BIC_PKG__);
4706 BIC_PRESENT(BIC_RAM__);
4707 if (rapl_joules) {
4708 BIC_PRESENT(BIC_Pkg_J);
4709 BIC_PRESENT(BIC_Cor_J);
4710 BIC_PRESENT(BIC_RAM_J);
4711 } else {
4712 BIC_PRESENT(BIC_PkgWatt);
4713 BIC_PRESENT(BIC_CorWatt);
4714 BIC_PRESENT(BIC_RAMWatt);
4715 }
0f644909 4716 break;
889facbe
LB		 4717 default:
4718 return;
4719 }
4720
4721 /* units on package 0, verify later other packages match */
7ce7d5de 4722 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
889facbe
LB		 4723 return;
4724
4725 rapl_power_units = 1.0 / (1 << (msr & 0xF));
f2c4db1b 4726 if (model == INTEL_FAM6_ATOM_SILVERMONT)
144b44b1
LB		 4727 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
4728 else
4729 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
889facbe 4730
40ee8e3b
AS		 4731 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
4732
144b44b1
LB		 4733 time_unit = msr >> 16 & 0xF;
4734 if (time_unit == 0)
4735 time_unit = 0xA;
889facbe 4736
144b44b1 4737 rapl_time_units = 1.0 / (1 << (time_unit));
889facbe 4738
9392bd98 4739 tdp = get_tdp_intel(model);
889facbe 4740
144b44b1 4741 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
96e47158 4742 if (!quiet)
b7d8c148 4743 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
9392bd98 4744}
889facbe 4745
9392bd98
CW		 4746void rapl_probe_amd(unsigned int family, unsigned int model)
4747{
4748 unsigned long long msr;
4749 unsigned int eax, ebx, ecx, edx;
4750 unsigned int has_rapl = 0;
4751 double tdp;
4752
9878bf7a
LB		 4753 UNUSED(model);
4754
9392bd98
CW		 4755 if (max_extended_level >= 0x80000007) {
4756 __cpuid(0x80000007, eax, ebx, ecx, edx);
33eb8225 4757 /* RAPL (Fam 17h+) */
9392bd98
CW		 4758 has_rapl = edx & (1 << 14);
4759 }
4760
33eb8225 4761 if (!has_rapl || family < 0x17)
9392bd98
CW		 4762 return;
4763
33eb8225
KP		 4764 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY;
4765 if (rapl_joules) {
4766 BIC_PRESENT(BIC_Pkg_J);
4767 BIC_PRESENT(BIC_Cor_J);
4768 } else {
4769 BIC_PRESENT(BIC_PkgWatt);
4770 BIC_PRESENT(BIC_CorWatt);
9392bd98
CW		 4771 }
4772
4773 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
4774 return;
4775
4776 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
4777 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
4778 rapl_power_units = ldexp(1.0, -(msr & 0xf));
4779
9cfa8e04 4780 tdp = get_tdp_amd(family);
9392bd98
CW		 4781
4782 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4783 if (!quiet)
4784 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4785}
4786
4787/*
4788 * rapl_probe()
4789 *
4790 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
4791 */
4792void rapl_probe(unsigned int family, unsigned int model)
4793{
4794 if (genuine_intel)
4795 rapl_probe_intel(family, model);
c1c10cc7 4796 if (authentic_amd || hygon_genuine)
9392bd98 4797 rapl_probe_amd(family, model);
889facbe
LB		 4798}
4799
1b69317d 4800void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3a9a941d
LB		 4801{
4802 if (!genuine_intel)
4803 return;
4804
4805 if (family != 6)
4806 return;
4807
4808 switch (model) {
c66f78a6 4809 case INTEL_FAM6_HASWELL: /* HSW */
77e5517c 4810 case INTEL_FAM6_HASWELL_L: /* HSW */
5e741407 4811 case INTEL_FAM6_HASWELL_G: /* HSW */
3a9a941d 4812 do_gfx_perf_limit_reasons = 1;
9878bf7a 4813 /* FALLTHRU */
869ce69e 4814 case INTEL_FAM6_HASWELL_X: /* HSX */
3a9a941d
LB		 4815 do_core_perf_limit_reasons = 1;
4816 do_ring_perf_limit_reasons = 1;
4817 default:
4818 return;
4819 }
4820}
4821
ac980e13
AB		 4822void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
4823{
eade39b2
AB		 4824 if (family != 6)
4825 return;
4826
4827 switch (model) {
4828 case INTEL_FAM6_BROADWELL_X:
4829 case INTEL_FAM6_SKYLAKE_X:
ac980e13 4830 has_automatic_cstate_conversion = 1;
eade39b2 4831 }
ac980e13
AB		 4832}
4833
aeb01e6d
CY		 4834void prewake_cstate_probe(unsigned int family, unsigned int model)
4835{
684e40e9 4836 if (is_icx(family, model) || is_spr(family, model))
aeb01e6d
CY		 4837 dis_cstate_prewake = 1;
4838}
4839
889facbe
LB		 4840int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4841{
4842 unsigned long long msr;
f4896fa5 4843 unsigned int dts, dts2;
889facbe
LB		 4844 int cpu;
4845
9878bf7a
LB		 4846 UNUSED(c);
4847 UNUSED(p);
4848
889facbe
LB		 4849 if (!(do_dts || do_ptm))
4850 return 0;
4851
4852 cpu = t->cpu_id;
4853
4854 /* DTS is per-core, no need to print for each thread */
388e9c81 4855 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
889facbe
LB		 4856 return 0;
4857
4858 if (cpu_migrate(cpu)) {
3d7772ea 4859 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 4860 return -1;
4861 }
4862
4863 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
4864 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
4865 return 0;
4866
4867 dts = (msr >> 16) & 0x7F;
1b439f01 4868 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts);
889facbe 4869
889facbe
LB		 4870 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
4871 return 0;
4872
4873 dts = (msr >> 16) & 0x7F;
4874 dts2 = (msr >> 8) & 0x7F;
b7d8c148 4875 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
55279aef 4876 cpu, msr, tj_max - dts, tj_max - dts2);
889facbe
LB		 4877 }
4878
f4896fa5 4879 if (do_dts && debug) {
889facbe
LB		 4880 unsigned int resolution;
4881
4882 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
4883 return 0;
4884
4885 dts = (msr >> 16) & 0x7F;
4886 resolution = (msr >> 27) & 0xF;
b7d8c148 4887 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
55279aef 4888 cpu, msr, tj_max - dts, resolution);
889facbe 4889
889facbe
LB		 4890 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
4891 return 0;
4892
4893 dts = (msr >> 16) & 0x7F;
4894 dts2 = (msr >> 8) & 0x7F;
b7d8c148 4895 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
55279aef 4896 cpu, msr, tj_max - dts, tj_max - dts2);
889facbe
LB		 4897 }
4898
4899 return 0;
4900}
36229897 4901
889facbe
LB		 4902void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
4903{
6b398625 4904 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n",
889facbe
LB		 4905 cpu, label,
4906 ((msr >> 15) & 1) ? "EN" : "DIS",
4907 ((msr >> 0) & 0x7FFF) * rapl_power_units,
1b439f01 4908 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
889facbe
LB		 4909 (((msr >> 16) & 1) ? "EN" : "DIS"));
4910
4911 return;
4912}
4913
4914int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4915{
4916 unsigned long long msr;
9392bd98 4917 const char *msr_name;
889facbe 4918 int cpu;
889facbe 4919
9878bf7a
LB		 4920 UNUSED(c);
4921 UNUSED(p);
4922
889facbe
LB		 4923 if (!do_rapl)
4924 return 0;
4925
4926 /* RAPL counters are per package, so print only for 1st thread/package */
4927 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4928 return 0;
4929
4930 cpu = t->cpu_id;
4931 if (cpu_migrate(cpu)) {
3d7772ea 4932 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu);
889facbe
LB		 4933 return -1;
4934 }
4935
9392bd98
CW		 4936 if (do_rapl & RAPL_AMD_F17H) {
4937 msr_name = "MSR_RAPL_PWR_UNIT";
4938 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
4939 return -1;
4940 } else {
4941 msr_name = "MSR_RAPL_POWER_UNIT";
4942 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
4943 return -1;
4944 }
889facbe 4945
9392bd98 4946 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
96e47158
LB		 4947 rapl_power_units, rapl_energy_units, rapl_time_units);
4948
144b44b1
LB		 4949 if (do_rapl & RAPL_PKG_POWER_INFO) {
4950
889facbe 4951 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
1b439f01 4952 return -5;
889facbe 4953
b7d8c148 4954 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe 4955 cpu, msr,
1b439f01 4956 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
889facbe
LB		 4957 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4958 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4959 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4960
144b44b1
LB		 4961 }
4962 if (do_rapl & RAPL_PKG) {
4963
889facbe
LB		 4964 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
4965 return -9;
4966
b7d8c148 4967 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
96e47158 4968 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
889facbe
LB		 4969
4970 print_power_limit_msr(cpu, msr, "PKG Limit #1");
6b398625 4971 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n",
889facbe
LB		 4972 cpu,
4973 ((msr >> 47) & 1) ? "EN" : "DIS",
4974 ((msr >> 32) & 0x7FFF) * rapl_power_units,
1b439f01 4975 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
889facbe 4976 ((msr >> 48) & 1) ? "EN" : "DIS");
f52ba931
SP		 4977
4978 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
4979 return -9;
4980
4981 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr);
4982 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n",
164d7a96 4983 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN");
889facbe
LB		 4984 }
4985
0b2bb692 4986 if (do_rapl & RAPL_DRAM_POWER_INFO) {
889facbe 4987 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
1b439f01 4988 return -6;
889facbe 4989
b7d8c148 4990 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe 4991 cpu, msr,
1b439f01 4992 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
889facbe
LB		 4993 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4994 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4995 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
0b2bb692
LB		 4996 }
4997 if (do_rapl & RAPL_DRAM) {
889facbe
LB		 4998 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
4999 return -9;
b7d8c148 5000 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5001 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
889facbe
LB		 5002
5003 print_power_limit_msr(cpu, msr, "DRAM Limit");
5004 }
144b44b1 5005 if (do_rapl & RAPL_CORE_POLICY) {
96e47158
LB		 5006 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
5007 return -7;
889facbe 5008
96e47158 5009 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
144b44b1 5010 }
9148494c 5011 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
96e47158
LB		 5012 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
5013 return -9;
5014 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5015 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
96e47158 5016 print_power_limit_msr(cpu, msr, "Cores Limit");
889facbe
LB		 5017 }
5018 if (do_rapl & RAPL_GFX) {
96e47158
LB		 5019 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
5020 return -8;
889facbe 5021
96e47158 5022 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
889facbe 5023
96e47158
LB		 5024 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
5025 return -9;
5026 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
1b439f01 5027 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
96e47158 5028 print_power_limit_msr(cpu, msr, "GFX Limit");
889facbe
LB		 5029 }
5030 return 0;
5031}
5032
d7899447
LB		 5033/*
5034 * SNB adds support for additional MSRs:
5035 *
5036 * MSR_PKG_C7_RESIDENCY 0x000003fa
5037 * MSR_CORE_C7_RESIDENCY 0x000003fe
5038 * MSR_PKG_C2_RESIDENCY 0x0000060d
5039 */
103a8fea 5040
d7899447 5041int has_snb_msrs(unsigned int family, unsigned int model)
103a8fea
LB		 5042{
5043 if (!genuine_intel)
5044 return 0;
5045
9878bf7a
LB		 5046 if (family != 6)
5047 return 0;
5048
103a8fea 5049 switch (model) {
869ce69e
LB		 5050 case INTEL_FAM6_SANDYBRIDGE:
5051 case INTEL_FAM6_SANDYBRIDGE_X:
1b439f01
LB		 5052 case INTEL_FAM6_IVYBRIDGE: /* IVB */
5053 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
5054 case INTEL_FAM6_HASWELL: /* HSW */
5055 case INTEL_FAM6_HASWELL_X: /* HSW */
5056 case INTEL_FAM6_HASWELL_L: /* HSW */
5057 case INTEL_FAM6_HASWELL_G: /* HSW */
5058 case INTEL_FAM6_BROADWELL: /* BDW */
5059 case INTEL_FAM6_BROADWELL_G: /* BDW */
5060 case INTEL_FAM6_BROADWELL_X: /* BDX */
5061 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5062 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5063 case INTEL_FAM6_SKYLAKE_X: /* SKX */
5064 case INTEL_FAM6_ICELAKE_X: /* ICX */
684e40e9 5065 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
1b439f01 5066 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5067 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5ebb34ed 5068 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
1b439f01
LB		 5069 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
5070 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
103a8fea
LB		 5071 return 1;
5072 }
5073 return 0;
5074}
5075
d7899447 5076/*
570992fc 5077 * HSW ULT added support for C8/C9/C10 MSRs:
d7899447 5078 *
5a63426e
LB		 5079 * MSR_PKG_C8_RESIDENCY 0x00000630
5080 * MSR_PKG_C9_RESIDENCY 0x00000631
5081 * MSR_PKG_C10_RESIDENCY 0x00000632
5082 *
5083 * MSR_PKGC8_IRTL 0x00000633
5084 * MSR_PKGC9_IRTL 0x00000634
5085 * MSR_PKGC10_IRTL 0x00000635
5086 *
d7899447 5087 */
570992fc 5088int has_c8910_msrs(unsigned int family, unsigned int model)
ca58710f
KCA		 5089{
5090 if (!genuine_intel)
5091 return 0;
5092
9878bf7a
LB		 5093 if (family != 6)
5094 return 0;
5095
ca58710f 5096 switch (model) {
77e5517c 5097 case INTEL_FAM6_HASWELL_L: /* HSW */
c66f78a6 5098 case INTEL_FAM6_BROADWELL: /* BDW */
af239c44
PZ		 5099 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5100 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
869ce69e 5101 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5102 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
f6708400 5103 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
0b2bb692
LB		 5104 return 1;
5105 }
5106 return 0;
5107}
5108
5109/*
5110 * SKL adds support for additional MSRS:
5111 *
5112 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
5113 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
5114 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
5115 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
5116 */
5117int has_skl_msrs(unsigned int family, unsigned int model)
5118{
5119 if (!genuine_intel)
5120 return 0;
5121
9878bf7a
LB		 5122 if (family != 6)
5123 return 0;
5124
0b2bb692 5125 switch (model) {
af239c44
PZ		 5126 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5127 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
ca58710f
KCA		 5128 return 1;
5129 }
5130 return 0;
5131}
5132
144b44b1
LB		 5133int is_slm(unsigned int family, unsigned int model)
5134{
5135 if (!genuine_intel)
5136 return 0;
9878bf7a
LB		 5137
5138 if (family != 6)
5139 return 0;
5140
144b44b1 5141 switch (model) {
f2c4db1b 5142 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5ebb34ed 5143 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
144b44b1
LB		 5144 return 1;
5145 }
5146 return 0;
5147}
5148
fb5d4327
DC		 5149int is_knl(unsigned int family, unsigned int model)
5150{
5151 if (!genuine_intel)
5152 return 0;
9878bf7a
LB		 5153
5154 if (family != 6)
5155 return 0;
5156
fb5d4327 5157 switch (model) {
869ce69e 5158 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
fb5d4327
DC		 5159 return 1;
5160 }
5161 return 0;
5162}
5163
997e5395
SP		 5164int is_cnl(unsigned int family, unsigned int model)
5165{
5166 if (!genuine_intel)
5167 return 0;
5168
9878bf7a
LB		 5169 if (family != 6)
5170 return 0;
5171
997e5395 5172 switch (model) {
1b439f01 5173 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
997e5395
SP		 5174 return 1;
5175 }
5176
5177 return 0;
5178}
5179
b2b34dfe
HC		 5180unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
5181{
5182 if (is_knl(family, model))
5183 return 1024;
5184 return 1;
5185}
5186
144b44b1 5187#define SLM_BCLK_FREQS 5
1b439f01 5188double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 };
144b44b1
LB		 5189
5190double slm_bclk(void)
5191{
5192 unsigned long long msr = 3;
5193 unsigned int i;
5194 double freq;
5195
7ce7d5de 5196 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
b7d8c148 5197 fprintf(outf, "SLM BCLK: unknown\n");
144b44b1
LB		 5198
5199 i = msr & 0xf;
5200 if (i >= SLM_BCLK_FREQS) {
b7d8c148 5201 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
0a91e551 5202 i = 3;
144b44b1
LB		 5203 }
5204 freq = slm_freq_table[i];
5205
96e47158 5206 if (!quiet)
8f6196c1 5207 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
144b44b1
LB		 5208
5209 return freq;
5210}
5211
103a8fea
LB		 5212double discover_bclk(unsigned int family, unsigned int model)
5213{
121b48bb 5214 if (has_snb_msrs(family, model) || is_knl(family, model))
103a8fea 5215 return 100.00;
144b44b1
LB		 5216 else if (is_slm(family, model))
5217 return slm_bclk();
103a8fea
LB		 5218 else
5219 return 133.33;
5220}
5221
7ab5ff49
ZR		 5222int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5223{
5224 unsigned int eax, ebx, ecx, edx;
5225
9878bf7a
LB		 5226 UNUSED(c);
5227 UNUSED(p);
5228
7ab5ff49
ZR		 5229 if (!genuine_intel)
5230 return 0;
5231
5232 if (cpu_migrate(t->cpu_id)) {
5233 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id);
5234 return -1;
5235 }
5236
5237 if (max_level < 0x1a)
5238 return 0;
5239
5240 __cpuid(0x1a, eax, ebx, ecx, edx);
5241 eax = (eax >> 24) & 0xFF;
1b439f01 5242 if (eax == 0x20)
7ab5ff49
ZR		 5243 t->is_atom = true;
5244 return 0;
5245}
5246
889facbe
LB		 5247/*
5248 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
5249 * the Thermal Control Circuit (TCC) activates.
5250 * This is usually equal to tjMax.
5251 *
5252 * Older processors do not have this MSR, so there we guess,
5253 * but also allow cmdline over-ride with -T.
5254 *
5255 * Several MSR temperature values are in units of degrees-C
5256 * below this value, including the Digital Thermal Sensor (DTS),
5257 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
5258 */
b2b94be7 5259int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
889facbe
LB		 5260{
5261 unsigned long long msr;
55279aef 5262 unsigned int tcc_default, tcc_offset;
b2b94be7 5263 int cpu;
6ff7cb37 5264
9878bf7a
LB		 5265 UNUSED(c);
5266 UNUSED(p);
5267
55279aef 5268 /* tj_max is used only for dts or ptm */
889facbe
LB		 5269 if (!(do_dts || do_ptm))
5270 return 0;
5271
5272 /* this is a per-package concept */
5273 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
5274 return 0;
5275
b2b94be7
LB		 5276 cpu = t->cpu_id;
5277 if (cpu_migrate(cpu)) {
5278 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
5279 return -1;
5280 }
5281
55279aef
ZR		 5282 if (tj_max_override != 0) {
5283 tj_max = tj_max_override;
1b439f01 5284 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max);
889facbe
LB		 5285 return 0;
5286 }
5287
b2b94be7
LB		 5288 /* Temperature Target MSR is Nehalem and newer only */
5289 if (!do_nhm_platform_info)
5290 goto guess;
5291
5292 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
5293 goto guess;
5294
55279aef 5295 tcc_default = (msr >> 16) & 0xFF;
b2b94be7 5296
0b9a0b9b
ZR		 5297 if (!quiet) {
5298 switch (tcc_offset_bits) {
5299 case 4:
5300 tcc_offset = (msr >> 24) & 0xF;
5301 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
1b439f01 5302 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
0b9a0b9b
ZR		 5303 break;
5304 case 6:
5305 tcc_offset = (msr >> 24) & 0x3F;
5306 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
1b439f01 5307 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
0b9a0b9b
ZR		 5308 break;
5309 default:
1b439f01 5310 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default);
0b9a0b9b
ZR		 5311 break;
5312 }
5313 }
b2b94be7 5314
55279aef 5315 if (!tcc_default)
b2b94be7
LB		 5316 goto guess;
5317
55279aef 5318 tj_max = tcc_default;
b2b94be7
LB		 5319
5320 return 0;
889facbe 5321
b2b94be7 5322guess:
55279aef 5323 tj_max = TJMAX_DEFAULT;
1b439f01 5324 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max);
889facbe
LB		 5325
5326 return 0;
5327}
69807a63 5328
aa8d8cc7
LB		 5329void decode_feature_control_msr(void)
5330{
5331 unsigned long long msr;
5332
f6505c88 5333 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
aa8d8cc7 5334 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
1b439f01 5335 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");
aa8d8cc7
LB		 5336}
5337
69807a63
LB		 5338void decode_misc_enable_msr(void)
5339{
5340 unsigned long long msr;
5341
f26b1519
LB		 5342 if (!genuine_intel)
5343 return;
5344
69807a63 5345 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
e6512624 5346 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
69807a63 5347 base_cpu, msr,
e6512624
LB		 5348 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
5349 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
fd3933ca 5350 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
e6512624
LB		 5351 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
5352 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
69807a63
LB		 5353}
5354
33148d67
LB		 5355void decode_misc_feature_control(void)
5356{
5357 unsigned long long msr;
5358
5359 if (!has_misc_feature_control)
5360 return;
5361
5362 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
1b439f01
LB		 5363 fprintf(outf,
5364 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
5365 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "",
5366 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");
33148d67 5367}
1b439f01 5368
f0057310
LB		 5369/*
5370 * Decode MSR_MISC_PWR_MGMT
5371 *
5372 * Decode the bits according to the Nehalem documentation
5373 * bit[0] seems to continue to have same meaning going forward
5374 * bit[1] less so...
5375 */
5376void decode_misc_pwr_mgmt_msr(void)
5377{
5378 unsigned long long msr;
5379
5380 if (!do_nhm_platform_info)
5381 return;
5382
cf4cbe53
LB		 5383 if (no_MSR_MISC_PWR_MGMT)
5384 return;
5385
f0057310 5386 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
ddadb8ad 5387 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
f0057310 5388 base_cpu, msr,
1b439f01 5389 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");
f0057310 5390}
1b439f01 5391
71616c8e
LB		 5392/*
5393 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
5394 *
5395 * This MSRs are present on Silvermont processors,
5396 * Intel Atom processor E3000 series (Baytrail), and friends.
5397 */
5398void decode_c6_demotion_policy_msr(void)
5399{
5400 unsigned long long msr;
5401
5402 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
5403 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
5404 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5405
5406 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
5407 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
5408 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5409}
7f5c258e 5410
f5a4c76a
LB		 5411/*
5412 * When models are the same, for the purpose of turbostat, reuse
5413 */
5414unsigned int intel_model_duplicates(unsigned int model)
5415{
5416
1b439f01 5417 switch (model) {
f5a4c76a
LB		 5418 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
5419 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
1b439f01 5420 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
f5a4c76a
LB		 5421 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
5422 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
5423 return INTEL_FAM6_NEHALEM;
5424
5425 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
5426 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
5427 return INTEL_FAM6_NEHALEM_EX;
5428
5429 case INTEL_FAM6_XEON_PHI_KNM:
5430 return INTEL_FAM6_XEON_PHI_KNL;
5431
f5a4c76a 5432 case INTEL_FAM6_BROADWELL_X:
5ebb34ed 5433 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
f5a4c76a
LB		 5434 return INTEL_FAM6_BROADWELL_X;
5435
af239c44 5436 case INTEL_FAM6_SKYLAKE_L:
c66f78a6 5437 case INTEL_FAM6_SKYLAKE:
af239c44 5438 case INTEL_FAM6_KABYLAKE_L:
c66f78a6 5439 case INTEL_FAM6_KABYLAKE:
081c5432
CY		 5440 case INTEL_FAM6_COMETLAKE_L:
5441 case INTEL_FAM6_COMETLAKE:
af239c44 5442 return INTEL_FAM6_SKYLAKE_L;
937807d3 5443
af239c44 5444 case INTEL_FAM6_ICELAKE_L:
d93ea567 5445 case INTEL_FAM6_ICELAKE_NNPI:
4bf7132a
CY		 5446 case INTEL_FAM6_TIGERLAKE_L:
5447 case INTEL_FAM6_TIGERLAKE:
e7af1ed3
LB		 5448 case INTEL_FAM6_ROCKETLAKE:
5449 case INTEL_FAM6_LAKEFIELD:
5450 case INTEL_FAM6_ALDERLAKE:
5683460b 5451 case INTEL_FAM6_ALDERLAKE_L:
1c1313b5 5452 case INTEL_FAM6_ALDERLAKE_N:
fb5e29df 5453 case INTEL_FAM6_RAPTORLAKE:
6f9cf553 5454 case INTEL_FAM6_RAPTORLAKE_P:
9b1c2ecf 5455 case INTEL_FAM6_RAPTORLAKE_S:
8e45a9bf
ZR		 5456 case INTEL_FAM6_METEORLAKE:
5457 case INTEL_FAM6_METEORLAKE_L:
af239c44 5458 return INTEL_FAM6_CANNONLAKE_L;
b62b3184 5459
d7814c30
CY		 5460 case INTEL_FAM6_ATOM_TREMONT_L:
5461 return INTEL_FAM6_ATOM_TREMONT;
5462
6c5c6560 5463 case INTEL_FAM6_ICELAKE_D:
25368d7c 5464 return INTEL_FAM6_ICELAKE_X;
93cac415
ZR		 5465
5466 case INTEL_FAM6_EMERALDRAPIDS_X:
5467 return INTEL_FAM6_SAPPHIRERAPIDS_X;
f5a4c76a
LB		 5468 }
5469 return model;
5470}
d76bb7a0
LB		 5471
5472void print_dev_latency(void)
5473{
5474 char *path = "/dev/cpu_dma_latency";
5475 int fd;
5476 int value;
5477 int retval;
5478
5479 fd = open(path, O_RDONLY);
5480 if (fd < 0) {
9c085817
PB		 5481 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"",
5482 progname);
d76bb7a0
LB		 5483 return;
5484 }
5485
5486 retval = read(fd, (void *)&value, sizeof(int));
5487 if (retval != sizeof(int)) {
6cbfedc7 5488 warn("read failed %s", path);
d76bb7a0
LB		 5489 close(fd);
5490 return;
5491 }
1b439f01 5492 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained");
d76bb7a0
LB		 5493
5494 close(fd);
5495}
5496
2af4f9b8 5497/*
2db0e5eb 5498 * Linux-perf manages the HW instructions-retired counter
2af4f9b8
LB		 5499 * by enabling when requested, and hiding rollover
5500 */
5501void linux_perf_init(void)
5502{
5503 if (!BIC_IS_ENABLED(BIC_IPC))
5504 return;
5505
5506 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK))
5507 return;
5508
5509 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5510 if (fd_instr_count_percpu == NULL)
5511 err(-1, "calloc fd_instr_count_percpu");
5512
5513 BIC_PRESENT(BIC_IPC);
5514}
5515
fcd17211 5516void process_cpuid()
103a8fea 5517{
34041551
LB		 5518 unsigned int eax, ebx, ecx, edx;
5519 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
ed0757b8 5520 unsigned long long ucode_patch = 0;
103a8fea
LB		 5521
5522 eax = ebx = ecx = edx = 0;
5523
5aea2f7f 5524 __cpuid(0, max_level, ebx, ecx, edx);
103a8fea 5525
34041551 5526 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
103a8fea 5527 genuine_intel = 1;
34041551
LB		 5528 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
5529 authentic_amd = 1;
c1c10cc7
PW		 5530 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
5531 hygon_genuine = 1;
103a8fea 5532
96e47158 5533 if (!quiet)
ed0757b8
LB		 5534 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n",
5535 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level);
103a8fea 5536
5aea2f7f 5537 __cpuid(1, fms, ebx, ecx, edx);
103a8fea
LB		 5538 family = (fms >> 8) & 0xf;
5539 model = (fms >> 4) & 0xf;
5540 stepping = fms & 0xf;
5aa3d1a2
CW		 5541 if (family == 0xf)
5542 family += (fms >> 20) & 0xff;
5543 if (family >= 6)
103a8fea 5544 model += ((fms >> 16) & 0xf) << 4;
34041551
LB		 5545 ecx_flags = ecx;
5546 edx_flags = edx;
103a8fea 5547
ed0757b8 5548 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
6cbfedc7 5549 warnx("get_msr(UCODE)");
ed0757b8 5550
103a8fea
LB		 5551 /*
5552 * check max extended function levels of CPUID.
5553 * This is needed to check for invariant TSC.
5554 * This check is valid for both Intel and AMD.
5555 */
5556 ebx = ecx = edx = 0;
5aea2f7f 5557 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
103a8fea 5558
34041551 5559 if (!quiet) {
ed0757b8 5560 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n",
1b439f01
LB		 5561 family, model, stepping, family, model, stepping,
5562 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));
ed0757b8 5563 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);
34041551
LB		 5564 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
5565 ecx_flags & (1 << 0) ? "SSE3" : "-",
5566 ecx_flags & (1 << 3) ? "MONITOR" : "-",
5567 ecx_flags & (1 << 6) ? "SMX" : "-",
5568 ecx_flags & (1 << 7) ? "EIST" : "-",
5569 ecx_flags & (1 << 8) ? "TM2" : "-",
5570 edx_flags & (1 << 4) ? "TSC" : "-",
5571 edx_flags & (1 << 5) ? "MSR" : "-",
5572 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
1b439f01 5573 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-");
34041551 5574 }
25368d7c 5575 if (genuine_intel) {
e9d3092f 5576 model_orig = model;
f5a4c76a 5577 model = intel_model_duplicates(model);
25368d7c 5578 }
34041551
LB		 5579
5580 if (!(edx_flags & (1 << 5)))
5581 errx(1, "CPUID: no MSR");
5582
61a87ba7 5583 if (max_extended_level >= 0x80000007) {
103a8fea 5584
d7899447
LB		 5585 /*
5586 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
5587 * this check is valid for both Intel and AMD
5588 */
5aea2f7f 5589 __cpuid(0x80000007, eax, ebx, ecx, edx);
d7899447
LB		 5590 has_invariant_tsc = edx & (1 << 8);
5591 }
103a8fea
LB		 5592
5593 /*
5594 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
5595 * this check is valid for both Intel and AMD
5596 */
5597
5aea2f7f 5598 __cpuid(0x6, eax, ebx, ecx, edx);
8209e054 5599 has_aperf = ecx & (1 << 0);
812db3f7
LB		 5600 if (has_aperf) {
5601 BIC_PRESENT(BIC_Avg_MHz);
5602 BIC_PRESENT(BIC_Busy);
5603 BIC_PRESENT(BIC_Bzy_MHz);
5604 }
889facbe 5605 do_dts = eax & (1 << 0);
812db3f7
LB		 5606 if (do_dts)
5607 BIC_PRESENT(BIC_CoreTmp);
b3a34e93 5608 has_turbo = eax & (1 << 1);
889facbe 5609 do_ptm = eax & (1 << 6);
812db3f7
LB		 5610 if (do_ptm)
5611 BIC_PRESENT(BIC_PkgTmp);
7f5c258e
LB		 5612 has_hwp = eax & (1 << 7);
5613 has_hwp_notify = eax & (1 << 8);
5614 has_hwp_activity_window = eax & (1 << 9);
5615 has_hwp_epp = eax & (1 << 10);
5616 has_hwp_pkg = eax & (1 << 11);
889facbe
LB		 5617 has_epb = ecx & (1 << 3);
5618
96e47158 5619 if (!quiet)
b3a34e93 5620 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
7f5c258e
LB		 5621 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
5622 has_aperf ? "" : "No-",
b3a34e93 5623 has_turbo ? "" : "No-",
7f5c258e
LB		 5624 do_dts ? "" : "No-",
5625 do_ptm ? "" : "No-",
5626 has_hwp ? "" : "No-",
5627 has_hwp_notify ? "" : "No-",
5628 has_hwp_activity_window ? "" : "No-",
1b439f01 5629 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-");
103a8fea 5630
96e47158 5631 if (!quiet)
69807a63
LB		 5632 decode_misc_enable_msr();
5633
96e47158 5634 if (max_level >= 0x7 && !quiet) {
aa8d8cc7 5635 int has_sgx;
103a8fea 5636
aa8d8cc7
LB		 5637 ecx = 0;
5638
5639 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
5640
5641 has_sgx = ebx & (1 << 2);
774627c5
LB		 5642
5643 is_hybrid = edx & (1 << 15);
5644
5645 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-");
aa8d8cc7
LB		 5646
5647 if (has_sgx)
5648 decode_feature_control_msr();
5649 }
5650
61a87ba7 5651 if (max_level >= 0x15) {
8a5bdf41
LB		 5652 unsigned int eax_crystal;
5653 unsigned int ebx_tsc;
5654
5655 /*
5656 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
5657 */
5658 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5aea2f7f 5659 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
8a5bdf41
LB		 5660
5661 if (ebx_tsc != 0) {
5662
96e47158 5663 if (!quiet && (ebx != 0))
b7d8c148 5664 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
8a5bdf41
LB		 5665 eax_crystal, ebx_tsc, crystal_hz);
5666
5667 if (crystal_hz == 0)
1b439f01 5668 switch (model) {
af239c44 5669 case INTEL_FAM6_SKYLAKE_L: /* SKL */
e8efbc80
LB		 5670 crystal_hz = 24000000; /* 24.0 MHz */
5671 break;
5ebb34ed 5672 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
ec53e594
LB		 5673 crystal_hz = 25000000; /* 25.0 MHz */
5674 break;
869ce69e 5675 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
f2c4db1b 5676 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
e8efbc80 5677 crystal_hz = 19200000; /* 19.2 MHz */
8a5bdf41
LB		 5678 break;
5679 default:
5680 crystal_hz = 0;
1b439f01 5681 }
8a5bdf41
LB		 5682
5683 if (crystal_hz) {
1b439f01 5684 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal;
96e47158 5685 if (!quiet)
b7d8c148 5686 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
1b439f01 5687 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
8a5bdf41
LB		 5688 }
5689 }
5690 }
61a87ba7
LB		 5691 if (max_level >= 0x16) {
5692 unsigned int base_mhz, max_mhz, bus_mhz, edx;
5693
5694 /*
5695 * CPUID 16H Base MHz, Max MHz, Bus MHz
5696 */
5697 base_mhz = max_mhz = bus_mhz = edx = 0;
5698
5aea2f7f 5699 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
96e47158 5700 if (!quiet)
b7d8c148 5701 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
61a87ba7
LB		 5702 base_mhz, max_mhz, bus_mhz);
5703 }
8a5bdf41 5704
b2b34dfe
HC		 5705 if (has_aperf)
5706 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
5707
812db3f7
LB		 5708 BIC_PRESENT(BIC_IRQ);
5709 BIC_PRESENT(BIC_TSC_MHz);
5710
5711 if (probe_nhm_msrs(family, model)) {
5712 do_nhm_platform_info = 1;
5713 BIC_PRESENT(BIC_CPU_c1);
5714 BIC_PRESENT(BIC_CPU_c3);
5715 BIC_PRESENT(BIC_CPU_c6);
5716 BIC_PRESENT(BIC_SMI);
5717 }
d7899447 5718 do_snb_cstates = has_snb_msrs(family, model);
812db3f7
LB		 5719
5720 if (do_snb_cstates)
5721 BIC_PRESENT(BIC_CPU_c7);
5722
5a63426e 5723 do_irtl_snb = has_snb_msrs(family, model);
0f47c08d
LB		 5724 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
5725 BIC_PRESENT(BIC_Pkgpc2);
5726 if (pkg_cstate_limit >= PCL__3)
5727 BIC_PRESENT(BIC_Pkgpc3);
5728 if (pkg_cstate_limit >= PCL__6)
5729 BIC_PRESENT(BIC_Pkgpc6);
5730 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
5731 BIC_PRESENT(BIC_Pkgpc7);
0539ba11 5732 if (has_slv_msrs(family, model)) {
0f47c08d
LB		 5733 BIC_NOT_PRESENT(BIC_Pkgpc2);
5734 BIC_NOT_PRESENT(BIC_Pkgpc3);
5735 BIC_PRESENT(BIC_Pkgpc6);
5736 BIC_NOT_PRESENT(BIC_Pkgpc7);
0539ba11
LB		 5737 BIC_PRESENT(BIC_Mod_c6);
5738 use_c1_residency_msr = 1;
5739 }
20de0dab
AL		 5740 if (is_jvl(family, model)) {
5741 BIC_NOT_PRESENT(BIC_CPU_c3);
5742 BIC_NOT_PRESENT(BIC_CPU_c7);
5743 BIC_NOT_PRESENT(BIC_Pkgpc2);
5744 BIC_NOT_PRESENT(BIC_Pkgpc3);
5745 BIC_NOT_PRESENT(BIC_Pkgpc6);
5746 BIC_NOT_PRESENT(BIC_Pkgpc7);
5747 }
7170a374
LB		 5748 if (is_dnv(family, model)) {
5749 BIC_PRESENT(BIC_CPU_c1);
5750 BIC_NOT_PRESENT(BIC_CPU_c3);
5751 BIC_NOT_PRESENT(BIC_Pkgpc3);
5752 BIC_NOT_PRESENT(BIC_CPU_c7);
5753 BIC_NOT_PRESENT(BIC_Pkgpc7);
5754 use_c1_residency_msr = 1;
5755 }
684e40e9 5756 if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) {
34c76197
LB		 5757 BIC_NOT_PRESENT(BIC_CPU_c3);
5758 BIC_NOT_PRESENT(BIC_Pkgpc3);
5759 BIC_NOT_PRESENT(BIC_CPU_c7);
5760 BIC_NOT_PRESENT(BIC_Pkgpc7);
5761 }
ade0ebac
LB		 5762 if (is_bdx(family, model)) {
5763 BIC_NOT_PRESENT(BIC_CPU_c7);
5764 BIC_NOT_PRESENT(BIC_Pkgpc7);
5765 }
570992fc 5766 if (has_c8910_msrs(family, model)) {
c315a09b
LB		 5767 if (pkg_cstate_limit >= PCL__8)
5768 BIC_PRESENT(BIC_Pkgpc8);
5769 if (pkg_cstate_limit >= PCL__9)
5770 BIC_PRESENT(BIC_Pkgpc9);
5771 if (pkg_cstate_limit >= PCL_10)
5772 BIC_PRESENT(BIC_Pkgpc10);
0f47c08d 5773 }
570992fc 5774 do_irtl_hsw = has_c8910_msrs(family, model);
a99d8730
LB		 5775 if (has_skl_msrs(family, model)) {
5776 BIC_PRESENT(BIC_Totl_c0);
5777 BIC_PRESENT(BIC_Any_c0);
5778 BIC_PRESENT(BIC_GFX_c0);
5779 BIC_PRESENT(BIC_CPUGFX);
5780 }
144b44b1 5781 do_slm_cstates = is_slm(family, model);
1b439f01 5782 do_knl_cstates = is_knl(family, model);
103a8fea 5783
1b439f01 5784 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model))
562855ee 5785 BIC_NOT_PRESENT(BIC_CPU_c3);
103a8fea 5786
96e47158 5787 if (!quiet)
f0057310
LB		 5788 decode_misc_pwr_mgmt_msr();
5789
96e47158 5790 if (!quiet && has_slv_msrs(family, model))
71616c8e
LB		 5791 decode_c6_demotion_policy_msr();
5792
889facbe 5793 rapl_probe(family, model);
3a9a941d 5794 perf_limit_reasons_probe(family, model);
ac980e13 5795 automatic_cstate_conversion_probe(family, model);
889facbe 5796
0b9a0b9b
ZR		 5797 check_tcc_offset(model_orig);
5798
96e47158 5799 if (!quiet)
1b69317d 5800 dump_cstate_pstate_config_info(family, model);
a5c6d65d 5801 intel_uncore_frequency_probe();
fcd17211 5802
d76bb7a0
LB		 5803 if (!quiet)
5804 print_dev_latency();
41618e63
LB		 5805 if (!quiet)
5806 dump_sysfs_cstate_config();
7293fccd
LB		 5807 if (!quiet)
5808 dump_sysfs_pstate_config();
41618e63 5809
8c69da29 5810 if (has_skl_msrs(family, model) || is_ehl(family, model))
a2b7b749
LB		 5811 calculate_tsc_tweak();
5812
812db3f7
LB		 5813 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
5814 BIC_PRESENT(BIC_GFX_rc6);
fdf676e5 5815
812db3f7
LB		 5816 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
5817 BIC_PRESENT(BIC_GFXMHz);
27d47356 5818
b4b91569
RA		 5819 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK))
5820 BIC_PRESENT(BIC_GFXACTMHz);
5821
be0e54c4
LB		 5822 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
5823 BIC_PRESENT(BIC_CPU_LPI);
5824 else
5825 BIC_NOT_PRESENT(BIC_CPU_LPI);
5826
eae97e05
CY		 5827 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK))
5828 BIC_PRESENT(BIC_CORE_THROT_CNT);
5829 else
5830 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT);
5831
1f81c5ef
LB		 5832 if (!access(sys_lpi_file_sysfs, R_OK)) {
5833 sys_lpi_file = sys_lpi_file_sysfs;
be0e54c4 5834 BIC_PRESENT(BIC_SYS_LPI);
1f81c5ef
LB		 5835 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
5836 sys_lpi_file = sys_lpi_file_debugfs;
5837 BIC_PRESENT(BIC_SYS_LPI);
5838 } else {
5839 sys_lpi_file_sysfs = NULL;
be0e54c4 5840 BIC_NOT_PRESENT(BIC_SYS_LPI);
1f81c5ef 5841 }
be0e54c4 5842
96e47158 5843 if (!quiet)
33148d67
LB		 5844 decode_misc_feature_control();
5845
889facbe 5846 return;
103a8fea
LB		 5847}
5848
103a8fea
LB		 5849/*
5850 * in /dev/cpu/ return success for names that are numbers
5851 * ie. filter out ".", "..", "microcode".
5852 */
5853int dir_filter(const struct dirent *dirp)
5854{
5855 if (isdigit(dirp->d_name[0]))
5856 return 1;
5857 else
5858 return 0;
5859}
5860
c98d5d94
LB		 5861void topology_probe()
5862{
5863 int i;
5864 int max_core_id = 0;
5865 int max_package_id = 0;
6de68fe1 5866 int max_die_id = 0;
c98d5d94 5867 int max_siblings = 0;
c98d5d94
LB		 5868
5869 /* Initialize num_cpus, max_cpu_num */
843c5791 5870 set_max_cpu_num();
c98d5d94 5871 topo.num_cpus = 0;
c98d5d94
LB		 5872 for_all_proc_cpus(count_cpus);
5873 if (!summary_only && topo.num_cpus > 1)
812db3f7 5874 BIC_PRESENT(BIC_CPU);
c98d5d94 5875
d8af6f5f 5876 if (debug > 1)
b7d8c148 5877 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
c98d5d94 5878
1b439f01 5879 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
b2c95d90
JT		 5880 if (cpus == NULL)
5881 err(1, "calloc cpus");
c98d5d94
LB		 5882
5883 /*
5884 * Allocate and initialize cpu_present_set
5885 */
5886 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 5887 if (cpu_present_set == NULL)
5888 err(3, "CPU_ALLOC");
c98d5d94
LB		 5889 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5890 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
5891 for_all_proc_cpus(mark_cpu_present);
5892
1ef7d21a
LB		 5893 /*
5894 * Validate that all cpus in cpu_subset are also in cpu_present_set
5895 */
5896 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
5897 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
5898 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
5899 err(1, "cpu%d not present", i);
5900 }
5901
c98d5d94
LB		 5902 /*
5903 * Allocate and initialize cpu_affinity_set
5904 */
5905 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 5906 if (cpu_affinity_set == NULL)
5907 err(3, "CPU_ALLOC");
c98d5d94
LB		 5908 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5909 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
5910
8cb48b32 5911 for_all_proc_cpus(init_thread_id);
c98d5d94
LB		 5912
5913 /*
5914 * For online cpus
5915 * find max_core_id, max_package_id
5916 */
5917 for (i = 0; i <= topo.max_cpu_num; ++i) {
5918 int siblings;
5919
5920 if (cpu_is_not_present(i)) {
d8af6f5f 5921 if (debug > 1)
b7d8c148 5922 fprintf(outf, "cpu%d NOT PRESENT\n", i);
c98d5d94
LB		 5923 continue;
5924 }
c98d5d94 5925
0e2d8f05
LB		 5926 cpus[i].logical_cpu_id = i;
5927
5928 /* get package information */
c98d5d94
LB		 5929 cpus[i].physical_package_id = get_physical_package_id(i);
5930 if (cpus[i].physical_package_id > max_package_id)
5931 max_package_id = cpus[i].physical_package_id;
5932
6de68fe1
LB		 5933 /* get die information */
5934 cpus[i].die_id = get_die_id(i);
5935 if (cpus[i].die_id > max_die_id)
5936 max_die_id = cpus[i].die_id;
5937
0e2d8f05 5938 /* get numa node information */
ef605741
PB		 5939 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
5940 if (cpus[i].physical_node_id > topo.max_node_num)
5941 topo.max_node_num = cpus[i].physical_node_id;
0e2d8f05
LB		 5942
5943 /* get core information */
5944 cpus[i].physical_core_id = get_core_id(i);
5945 if (cpus[i].physical_core_id > max_core_id)
5946 max_core_id = cpus[i].physical_core_id;
5947
5948 /* get thread information */
5949 siblings = get_thread_siblings(&cpus[i]);
c98d5d94
LB		 5950 if (siblings > max_siblings)
5951 max_siblings = siblings;
4f206a0f 5952 if (cpus[i].thread_id == 0)
8cb48b32 5953 topo.num_cores++;
c98d5d94 5954 }
ef605741 5955
70a9c6e8 5956 topo.cores_per_node = max_core_id + 1;
d8af6f5f 5957 if (debug > 1)
1b439f01 5958 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node);
70a9c6e8 5959 if (!summary_only && topo.cores_per_node > 1)
812db3f7 5960 BIC_PRESENT(BIC_Core);
c98d5d94 5961
6de68fe1
LB		 5962 topo.num_die = max_die_id + 1;
5963 if (debug > 1)
1b439f01 5964 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die);
6de68fe1
LB		 5965 if (!summary_only && topo.num_die > 1)
5966 BIC_PRESENT(BIC_Die);
5967
c98d5d94 5968 topo.num_packages = max_package_id + 1;
d8af6f5f 5969 if (debug > 1)
1b439f01 5970 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages);
7da6e3e2 5971 if (!summary_only && topo.num_packages > 1)
812db3f7 5972 BIC_PRESENT(BIC_Package);
c98d5d94 5973
ef605741
PB		 5974 set_node_data();
5975 if (debug > 1)
70a9c6e8 5976 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
01235041
PB		 5977 if (!summary_only && topo.nodes_per_pkg > 1)
5978 BIC_PRESENT(BIC_Node);
ef605741 5979
70a9c6e8 5980 topo.threads_per_core = max_siblings;
d8af6f5f 5981 if (debug > 1)
b7d8c148 5982 fprintf(outf, "max_siblings %d\n", max_siblings);
2ffbb224
PB		 5983
5984 if (debug < 1)
5985 return;
5986
5987 for (i = 0; i <= topo.max_cpu_num; ++i) {
0ec712e3
LB		 5988 if (cpu_is_not_present(i))
5989 continue;
2ffbb224 5990 fprintf(outf,
6de68fe1
LB		 5991 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
5992 i, cpus[i].physical_package_id, cpus[i].die_id,
1b439f01 5993 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id);
2ffbb224
PB		 5994 }
5995
c98d5d94
LB		 5996}
5997
1b439f01 5998void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
c98d5d94
LB		 5999{
6000 int i;
1b439f01 6001 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages;
40f5cfe7 6002 int num_threads = topo.threads_per_core * num_cores;
c98d5d94 6003
40f5cfe7 6004 *t = calloc(num_threads, sizeof(struct thread_data));
c98d5d94
LB		 6005 if (*t == NULL)
6006 goto error;
6007
40f5cfe7 6008 for (i = 0; i < num_threads; i++)
c98d5d94
LB		 6009 (*t)[i].cpu_id = -1;
6010
40f5cfe7 6011 *c = calloc(num_cores, sizeof(struct core_data));
c98d5d94
LB		 6012 if (*c == NULL)
6013 goto error;
6014
40f5cfe7 6015 for (i = 0; i < num_cores; i++)
c98d5d94
LB		 6016 (*c)[i].core_id = -1;
6017
678a3bd1 6018 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
c98d5d94
LB		 6019 if (*p == NULL)
6020 goto error;
6021
6022 for (i = 0; i < topo.num_packages; i++)
6023 (*p)[i].package_id = i;
6024
6025 return;
6026error:
b2c95d90 6027 err(1, "calloc counters");
c98d5d94 6028}
1b439f01 6029
c98d5d94
LB		 6030/*
6031 * init_counter()
6032 *
c98d5d94 6033 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
c98d5d94 6034 */
1b439f01 6035void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id)
c98d5d94 6036{
8cb48b32 6037 int pkg_id = cpus[cpu_id].physical_package_id;
40f5cfe7 6038 int node_id = cpus[cpu_id].logical_node_id;
8cb48b32
PB		 6039 int core_id = cpus[cpu_id].physical_core_id;
6040 int thread_id = cpus[cpu_id].thread_id;
c98d5d94
LB		 6041 struct thread_data *t;
6042 struct core_data *c;
6043 struct pkg_data *p;
6044
42dd4520
NC		 6045 /* Workaround for systems where physical_node_id==-1
6046 * and logical_node_id==(-1 - topo.num_cpus)
6047 */
6048 if (node_id < 0)
6049 node_id = 0;
6050
40f5cfe7
PB		 6051 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
6052 c = GET_CORE(core_base, core_id, node_id, pkg_id);
8cb48b32 6053 p = GET_PKG(pkg_base, pkg_id);
c98d5d94
LB		 6054
6055 t->cpu_id = cpu_id;
8cb48b32 6056 if (thread_id == 0) {
c98d5d94
LB		 6057 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
6058 if (cpu_is_first_core_in_package(cpu_id))
6059 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
6060 }
6061
8cb48b32
PB		 6062 c->core_id = core_id;
6063 p->package_id = pkg_id;
c98d5d94
LB		 6064}
6065
c98d5d94
LB		 6066int initialize_counters(int cpu_id)
6067{
8cb48b32
PB		 6068 init_counter(EVEN_COUNTERS, cpu_id);
6069 init_counter(ODD_COUNTERS, cpu_id);
c98d5d94
LB		 6070 return 0;
6071}
6072
6073void allocate_output_buffer()
6074{
eeb71c95 6075 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
c98d5d94 6076 outp = output_buffer;
b2c95d90
JT		 6077 if (outp == NULL)
6078 err(-1, "calloc output buffer");
c98d5d94 6079}
1b439f01 6080
36229897
LB		 6081void allocate_fd_percpu(void)
6082{
01a67adf 6083 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
36229897
LB		 6084 if (fd_percpu == NULL)
6085 err(-1, "calloc fd_percpu");
6086}
1b439f01 6087
562a2d37
LB		 6088void allocate_irq_buffers(void)
6089{
6090 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
6091 if (irq_column_2_cpu == NULL)
6092 err(-1, "calloc %d", topo.num_cpus);
c98d5d94 6093
01a67adf 6094 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
562a2d37 6095 if (irqs_per_cpu == NULL)
01a67adf 6096 err(-1, "calloc %d", topo.max_cpu_num + 1);
562a2d37 6097}
1b439f01 6098
c98d5d94
LB		 6099void setup_all_buffers(void)
6100{
6101 topology_probe();
562a2d37 6102 allocate_irq_buffers();
36229897 6103 allocate_fd_percpu();
c98d5d94
LB		 6104 allocate_counters(&thread_even, &core_even, &package_even);
6105 allocate_counters(&thread_odd, &core_odd, &package_odd);
6106 allocate_output_buffer();
6107 for_all_proc_cpus(initialize_counters);
6108}
3b4d5c7f 6109
7ce7d5de
PB		 6110void set_base_cpu(void)
6111{
6112 base_cpu = sched_getcpu();
6113 if (base_cpu < 0)
6114 err(-ENODEV, "No valid cpus found");
6115
6116 if (debug > 1)
b7d8c148 6117 fprintf(outf, "base_cpu = %d\n", base_cpu);
7ce7d5de
PB		 6118}
6119
103a8fea
LB		 6120void turbostat_init()
6121{
7ce7d5de
PB		 6122 setup_all_buffers();
6123 set_base_cpu();
103a8fea 6124 check_dev_msr();
98481e79 6125 check_permissions();
fcd17211 6126 process_cpuid();
2af4f9b8 6127 linux_perf_init();
103a8fea 6128
96e47158 6129 if (!quiet)
7f5c258e
LB		 6130 for_all_cpus(print_hwp, ODD_COUNTERS);
6131
96e47158 6132 if (!quiet)
889facbe
LB		 6133 for_all_cpus(print_epb, ODD_COUNTERS);
6134
96e47158 6135 if (!quiet)
3a9a941d
LB		 6136 for_all_cpus(print_perf_limit, ODD_COUNTERS);
6137
96e47158 6138 if (!quiet)
889facbe
LB		 6139 for_all_cpus(print_rapl, ODD_COUNTERS);
6140
6141 for_all_cpus(set_temperature_target, ODD_COUNTERS);
6142
7ab5ff49
ZR		 6143 for_all_cpus(get_cpu_type, ODD_COUNTERS);
6144 for_all_cpus(get_cpu_type, EVEN_COUNTERS);
6145
96e47158 6146 if (!quiet)
889facbe 6147 for_all_cpus(print_thermal, ODD_COUNTERS);
5a63426e 6148
96e47158 6149 if (!quiet && do_irtl_snb)
5a63426e 6150 print_irtl();
164d7a96
LB		 6151
6152 if (DO_BIC(BIC_IPC))
6153 (void)get_instr_count_fd(base_cpu);
103a8fea
LB		 6154}
6155
6156int fork_it(char **argv)
6157{
103a8fea 6158 pid_t child_pid;
d91bb17c 6159 int status;
d15cf7c1 6160
218f0e8d 6161 snapshot_proc_sysfs_files();
d91bb17c 6162 status = for_all_cpus(get_counters, EVEN_COUNTERS);
4c2122d4 6163 first_counter_read = 0;
d91bb17c
LB		 6164 if (status)
6165 exit(status);
c98d5d94
LB		 6166 /* clear affinity side-effect of get_counters() */
6167 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
103a8fea
LB		 6168 gettimeofday(&tv_even, (struct timezone *)NULL);
6169
6170 child_pid = fork();
6171 if (!child_pid) {
6172 /* child */
6173 execvp(argv[0], argv);
0815a3d0 6174 err(errno, "exec %s", argv[0]);
103a8fea 6175 } else {
103a8fea
LB		 6176
6177 /* parent */
b2c95d90
JT		 6178 if (child_pid == -1)
6179 err(1, "fork");
103a8fea
LB		 6180
6181 signal(SIGINT, SIG_IGN);
6182 signal(SIGQUIT, SIG_IGN);
b2c95d90
JT		 6183 if (waitpid(child_pid, &status, 0) == -1)
6184 err(status, "waitpid");
2a954966
DA		 6185
6186 if (WIFEXITED(status))
6187 status = WEXITSTATUS(status);
103a8fea 6188 }
c98d5d94
LB		 6189 /*
6190 * n.b. fork_it() does not check for errors from for_all_cpus()
6191 * because re-starting is problematic when forking
6192 */
218f0e8d 6193 snapshot_proc_sysfs_files();
c98d5d94 6194 for_all_cpus(get_counters, ODD_COUNTERS);
103a8fea 6195 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 6196 timersub(&tv_odd, &tv_even, &tv_delta);
ba3dec99
LB		 6197 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
6198 fprintf(outf, "%s: Counter reset detected\n", progname);
6199 else {
6200 compute_average(EVEN_COUNTERS);
6201 format_all_counters(EVEN_COUNTERS);
6202 }
103a8fea 6203
1b439f01 6204 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0);
b7d8c148
LB		 6205
6206 flush_output_stderr();
103a8fea 6207
d91bb17c 6208 return status;
103a8fea
LB		 6209}
6210
3b4d5c7f
AS		 6211int get_and_dump_counters(void)
6212{
6213 int status;
6214
218f0e8d 6215 snapshot_proc_sysfs_files();
3b4d5c7f
AS		 6216 status = for_all_cpus(get_counters, ODD_COUNTERS);
6217 if (status)
6218 return status;
6219
6220 status = for_all_cpus(dump_counters, ODD_COUNTERS);
6221 if (status)
6222 return status;
6223
b7d8c148 6224 flush_output_stdout();
3b4d5c7f
AS		 6225
6226 return status;
6227}
6228
1b439f01
LB		 6229void print_version()
6230{
9992dd77 6231 fprintf(outf, "turbostat version 2022.10.04 - Len Brown <lenb@kernel.org>\n");
d8af6f5f
LB		 6232}
6233
03331233
CY		 6234#define COMMAND_LINE_SIZE 2048
6235
6236void print_bootcmd(void)
6237{
6238 char bootcmd[COMMAND_LINE_SIZE];
6239 FILE *fp;
6240 int ret;
6241
6242 memset(bootcmd, 0, COMMAND_LINE_SIZE);
6243 fp = fopen("/proc/cmdline", "r");
6244 if (!fp)
6245 return;
6246
6247 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp);
6248 if (ret) {
6249 bootcmd[ret] = '\0';
6250 /* the last character is already '\n' */
6251 fprintf(outf, "Kernel command line: %s", bootcmd);
6252 }
6253
6254 fclose(fp);
6255}
6256
495c7654 6257int add_counter(unsigned int msr_num, char *path, char *name,
1b439f01
LB		 6258 unsigned int width, enum counter_scope scope,
6259 enum counter_type type, enum counter_format format, int flags)
388e9c81
LB		 6260{
6261 struct msr_counter *msrp;
6262
6263 msrp = calloc(1, sizeof(struct msr_counter));
6264 if (msrp == NULL) {
6265 perror("calloc");
6266 exit(1);
6267 }
6268
6269 msrp->msr_num = msr_num;
d8d005ba 6270 strncpy(msrp->name, name, NAME_BYTES - 1);
495c7654 6271 if (path)
d8d005ba 6272 strncpy(msrp->path, path, PATH_BYTES - 1);
388e9c81
LB		 6273 msrp->width = width;
6274 msrp->type = type;
6275 msrp->format = format;
41618e63 6276 msrp->flags = flags;
388e9c81
LB		 6277
6278 switch (scope) {
6279
6280 case SCOPE_CPU:
388e9c81
LB		 6281 msrp->next = sys.tp;
6282 sys.tp = msrp;
678a3bd1 6283 sys.added_thread_counters++;
0748eaf0 6284 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
1b439f01 6285 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6286 exit(-1);
6287 }
388e9c81
LB		 6288 break;
6289
6290 case SCOPE_CORE:
388e9c81
LB		 6291 msrp->next = sys.cp;
6292 sys.cp = msrp;
678a3bd1
LB		 6293 sys.added_core_counters++;
6294 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
1b439f01 6295 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6296 exit(-1);
6297 }
388e9c81
LB		 6298 break;
6299
6300 case SCOPE_PACKAGE:
388e9c81
LB		 6301 msrp->next = sys.pp;
6302 sys.pp = msrp;
678a3bd1
LB		 6303 sys.added_package_counters++;
6304 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
1b439f01 6305 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS);
678a3bd1
LB		 6306 exit(-1);
6307 }
388e9c81
LB		 6308 break;
6309 }
6310
6311 return 0;
6312}
6313
6314void parse_add_command(char *add_command)
6315{
6316 int msr_num = 0;
495c7654 6317 char *path = NULL;
0f47c08d 6318 char name_buffer[NAME_BYTES] = "";
388e9c81
LB		 6319 int width = 64;
6320 int fail = 0;
6321 enum counter_scope scope = SCOPE_CPU;
6322 enum counter_type type = COUNTER_CYCLES;
6323 enum counter_format format = FORMAT_DELTA;
6324
6325 while (add_command) {
6326
6327 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
6328 goto next;
6329
6330 if (sscanf(add_command, "msr%d", &msr_num) == 1)
6331 goto next;
6332
495c7654
LB		 6333 if (*add_command == '/') {
6334 path = add_command;
6335 goto next;
6336 }
6337
388e9c81
LB		 6338 if (sscanf(add_command, "u%d", &width) == 1) {
6339 if ((width == 32) || (width == 64))
6340 goto next;
6341 width = 64;
6342 }
6343 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
6344 scope = SCOPE_CPU;
6345 goto next;
6346 }
6347 if (!strncmp(add_command, "core", strlen("core"))) {
6348 scope = SCOPE_CORE;
6349 goto next;
6350 }
6351 if (!strncmp(add_command, "package", strlen("package"))) {
6352 scope = SCOPE_PACKAGE;
6353 goto next;
6354 }
6355 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
6356 type = COUNTER_CYCLES;
6357 goto next;
6358 }
6359 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
6360 type = COUNTER_SECONDS;
6361 goto next;
6362 }
41618e63
LB		 6363 if (!strncmp(add_command, "usec", strlen("usec"))) {
6364 type = COUNTER_USEC;
6365 goto next;
6366 }
388e9c81
LB		 6367 if (!strncmp(add_command, "raw", strlen("raw"))) {
6368 format = FORMAT_RAW;
6369 goto next;
6370 }
6371 if (!strncmp(add_command, "delta", strlen("delta"))) {
6372 format = FORMAT_DELTA;
6373 goto next;
6374 }
6375 if (!strncmp(add_command, "percent", strlen("percent"))) {
6376 format = FORMAT_PERCENT;
6377 goto next;
6378 }
6379
6380 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
6381 char *eos;
6382
6383 eos = strchr(name_buffer, ',');
6384 if (eos)
6385 *eos = '\0';
6386 goto next;
6387 }
6388
6389next:
6390 add_command = strchr(add_command, ',');
495c7654
LB		 6391 if (add_command) {
6392 *add_command = '\0';
388e9c81 6393 add_command++;
495c7654 6394 }
388e9c81
LB		 6395
6396 }
495c7654
LB		 6397 if ((msr_num == 0) && (path == NULL)) {
6398 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
388e9c81
LB		 6399 fail++;
6400 }
6401
6402 /* generate default column header */
6403 if (*name_buffer == '\0') {
5f3aea57
LB		 6404 if (width == 32)
6405 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6406 else
6407 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
388e9c81
LB		 6408 }
6409
41618e63 6410 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
388e9c81
LB		 6411 fail++;
6412
6413 if (fail) {
6414 help();
6415 exit(1);
6416 }
6417}
41618e63 6418
0fc521bc
ZLCH		 6419int is_deferred_add(char *name)
6420{
6421 int i;
6422
6423 for (i = 0; i < deferred_add_index; ++i)
6424 if (!strcmp(name, deferred_add_names[i]))
6425 return 1;
6426 return 0;
6427}
6428
dd778a5e
LB		 6429int is_deferred_skip(char *name)
6430{
6431 int i;
6432
6433 for (i = 0; i < deferred_skip_index; ++i)
6434 if (!strcmp(name, deferred_skip_names[i]))
6435 return 1;
6436 return 0;
6437}
6438
41618e63
LB		 6439void probe_sysfs(void)
6440{
6441 char path[64];
6442 char name_buf[16];
6443 FILE *input;
6444 int state;
6445 char *sp;
6446
0748eaf0 6447 for (state = 10; state >= 0; --state) {
41618e63 6448
1b439f01 6449 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 6450 input = fopen(path, "r");
6451 if (input == NULL)
6452 continue;
8173c336
BH		 6453 if (!fgets(name_buf, sizeof(name_buf), input))
6454 err(1, "%s: failed to read file", path);
41618e63 6455
1b439f01 6456 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 6457 sp = strchr(name_buf, '-');
6458 if (!sp)
6459 sp = strchrnul(name_buf, '\n');
6460 *sp = '%';
6461 *(sp + 1) = '\0';
6462
fecb3bc8
DA		 6463 remove_underbar(name_buf);
6464
41618e63
LB		 6465 fclose(input);
6466
6467 sprintf(path, "cpuidle/state%d/time", state);
6468
0fc521bc
ZLCH		 6469 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6470 continue;
6471
dd778a5e
LB		 6472 if (is_deferred_skip(name_buf))
6473 continue;
6474
1b439f01 6475 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU);
41618e63
LB		 6476 }
6477
0748eaf0 6478 for (state = 10; state >= 0; --state) {
41618e63 6479
1b439f01 6480 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
41618e63
LB		 6481 input = fopen(path, "r");
6482 if (input == NULL)
6483 continue;
8173c336
BH		 6484 if (!fgets(name_buf, sizeof(name_buf), input))
6485 err(1, "%s: failed to read file", path);
1b439f01 6486 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
41618e63
LB		 6487 sp = strchr(name_buf, '-');
6488 if (!sp)
6489 sp = strchrnul(name_buf, '\n');
6490 *sp = '\0';
6491 fclose(input);
fecb3bc8
DA		 6492
6493 remove_underbar(name_buf);
41618e63
LB		 6494
6495 sprintf(path, "cpuidle/state%d/usage", state);
6496
0fc521bc
ZLCH		 6497 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6498 continue;
6499
dd778a5e
LB		 6500 if (is_deferred_skip(name_buf))
6501 continue;
6502
1b439f01 6503 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU);
41618e63
LB		 6504 }
6505
6506}
6507
1ef7d21a
LB		 6508/*
6509 * parse cpuset with following syntax
6510 * 1,2,4..6,8-10 and set bits in cpu_subset
6511 */
6512void parse_cpu_command(char *optarg)
6513{
6514 unsigned int start, end;
6515 char *next;
6516
4e4e1e7c
LB		 6517 if (!strcmp(optarg, "core")) {
6518 if (cpu_subset)
6519 goto error;
6520 show_core_only++;
6521 return;
6522 }
6523 if (!strcmp(optarg, "package")) {
6524 if (cpu_subset)
6525 goto error;
6526 show_pkg_only++;
6527 return;
6528 }
6529 if (show_core_only || show_pkg_only)
6530 goto error;
6531
1ef7d21a
LB		 6532 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
6533 if (cpu_subset == NULL)
6534 err(3, "CPU_ALLOC");
6535 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
6536
6537 CPU_ZERO_S(cpu_subset_size, cpu_subset);
6538
6539 next = optarg;
6540
6541 while (next && *next) {
6542
6543 if (*next == '-') /* no negative cpu numbers */
6544 goto error;
6545
6546 start = strtoul(next, &next, 10);
6547
6548 if (start >= CPU_SUBSET_MAXCPUS)
6549 goto error;
6550 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6551
6552 if (*next == '\0')
6553 break;
6554
6555 if (*next == ',') {
6556 next += 1;
6557 continue;
6558 }
6559
6560 if (*next == '-') {
6561 next += 1; /* start range */
6562 } else if (*next == '.') {
6563 next += 1;
6564 if (*next == '.')
6565 next += 1; /* start range */
6566 else
6567 goto error;
6568 }
6569
6570 end = strtoul(next, &next, 10);
6571 if (end <= start)
6572 goto error;
6573
6574 while (++start <= end) {
6575 if (start >= CPU_SUBSET_MAXCPUS)
6576 goto error;
6577 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6578 }
6579
6580 if (*next == ',')
6581 next += 1;
6582 else if (*next != '\0')
6583 goto error;
6584 }
6585
6586 return;
6587
6588error:
4e4e1e7c
LB		 6589 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
6590 help();
1ef7d21a
LB		 6591 exit(-1);
6592}
6593
103a8fea
LB		 6594void cmdline(int argc, char **argv)
6595{
6596 int opt;
d8af6f5f
LB		 6597 int option_index = 0;
6598 static struct option long_options[] = {
1b439f01
LB		 6599 { "add", required_argument, 0, 'a' },
6600 { "cpu", required_argument, 0, 'c' },
6601 { "Dump", no_argument, 0, 'D' },
6602 { "debug", no_argument, 0, 'd' }, /* internal, not documented */
6603 { "enable", required_argument, 0, 'e' },
6604 { "interval", required_argument, 0, 'i' },
6605 { "IPC", no_argument, 0, 'I' },
6606 { "num_iterations", required_argument, 0, 'n' },
c7e399f8 6607 { "header_iterations", required_argument, 0, 'N' },
1b439f01
LB		 6608 { "help", no_argument, 0, 'h' },
6609 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help
6610 { "Joules", no_argument, 0, 'J' },
6611 { "list", no_argument, 0, 'l' },
6612 { "out", required_argument, 0, 'o' },
6613 { "quiet", no_argument, 0, 'q' },
6614 { "show", required_argument, 0, 's' },
6615 { "Summary", no_argument, 0, 'S' },
6616 { "TCC", required_argument, 0, 'T' },
6617 { "version", no_argument, 0, 'v' },
6618 { 0, 0, 0, 0 }
d8af6f5f 6619 };
103a8fea
LB		 6620
6621 progname = argv[0];
6622
1b439f01 6623 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) {
103a8fea 6624 switch (opt) {
388e9c81
LB		 6625 case 'a':
6626 parse_add_command(optarg);
6627 break;
1ef7d21a
LB		 6628 case 'c':
6629 parse_cpu_command(optarg);
6630 break;
d8af6f5f 6631 case 'D':
3b4d5c7f
AS		 6632 dump_only++;
6633 break;
3f44a5c6
LB		 6634 case 'e':
6635 /* --enable specified counter */
4c2122d4 6636 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
3f44a5c6 6637 break;
d8af6f5f
LB		 6638 case 'd':
6639 debug++;
3f44a5c6 6640 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
103a8fea 6641 break;
812db3f7 6642 case 'H':
3f44a5c6
LB		 6643 /*
6644 * --hide: do not show those specified
6645 * multiple invocations simply clear more bits in enabled mask
6646 */
6647 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
812db3f7 6648 break;
d8af6f5f
LB		 6649 case 'h':
6650 default:
6651 help();
6652 exit(1);
103a8fea 6653 case 'i':
2a0609c0
LB		 6654 {
6655 double interval = strtod(optarg, NULL);
6656
6657 if (interval < 0.001) {
1b439f01 6658 fprintf(outf, "interval %f seconds is too small\n", interval);
2a0609c0
LB		 6659 exit(2);
6660 }
6661
47936f94 6662 interval_tv.tv_sec = interval_ts.tv_sec = interval;
b9ad8ee0 6663 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
47936f94 6664 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
2a0609c0 6665 }
103a8fea 6666 break;
d8af6f5f
LB		 6667 case 'J':
6668 rapl_joules++;
8e180f3c 6669 break;
c8ade361 6670 case 'l':
3f44a5c6 6671 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
c8ade361
LB		 6672 list_header_only++;
6673 quiet++;
6674 break;
b7d8c148
LB		 6675 case 'o':
6676 outf = fopen_or_die(optarg, "w");
6677 break;
96e47158
LB		 6678 case 'q':
6679 quiet = 1;
6680 break;
023fe0ac
CY		 6681 case 'n':
6682 num_iterations = strtod(optarg, NULL);
6683
6684 if (num_iterations <= 0) {
1b439f01 6685 fprintf(outf, "iterations %d should be positive number\n", num_iterations);
023fe0ac
CY		 6686 exit(2);
6687 }
6688 break;
c7e399f8
ZLCH		 6689 case 'N':
6690 header_iterations = strtod(optarg, NULL);
6691
6692 if (header_iterations <= 0) {
164d7a96 6693 fprintf(outf, "iterations %d should be positive number\n", header_iterations);
c7e399f8 6694 exit(2);
023fe0ac
CY		 6695 }
6696 break;
812db3f7 6697 case 's':
3f44a5c6
LB		 6698 /*
6699 * --show: show only those specified
6700 * The 1st invocation will clear and replace the enabled mask
6701 * subsequent invocations can add to it.
6702 */
6703 if (shown == 0)
6704 bic_enabled = bic_lookup(optarg, SHOW_LIST);
6705 else
6706 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
6707 shown = 1;
812db3f7 6708 break;
d8af6f5f
LB		 6709 case 'S':
6710 summary_only++;
889facbe
LB		 6711 break;
6712 case 'T':
55279aef 6713 tj_max_override = atoi(optarg);
889facbe 6714 break;
d8af6f5f
LB		 6715 case 'v':
6716 print_version();
6717 exit(0);
5c56be9a 6718 break;
103a8fea
LB		 6719 }
6720 }
6721}
6722
6723int main(int argc, char **argv)
6724{
b7d8c148 6725 outf = stderr;
103a8fea
LB		 6726 cmdline(argc, argv);
6727
03331233 6728 if (!quiet) {
d8af6f5f 6729 print_version();
03331233
CY		 6730 print_bootcmd();
6731 }
103a8fea 6732
41618e63
LB		 6733 probe_sysfs();
6734
103a8fea
LB		 6735 turbostat_init();
6736
6799ba84
DM		 6737 msr_sum_record();
6738
3b4d5c7f
AS		 6739 /* dump counters and exit */
6740 if (dump_only)
6741 return get_and_dump_counters();
6742
c8ade361
LB		 6743 /* list header and exit */
6744 if (list_header_only) {
6745 print_header(",");
6746 flush_output_stdout();
6747 return 0;
6748 }
6749
103a8fea
LB		 6750 /*
6751 * if any params left, it must be a command to fork
6752 */
6753 if (argc - optind)
6754 return fork_it(argv + optind);
6755 else
6756 turbostat_loop();
6757
6758 return 0;
6759}
Linux 6.x block layer and io_uring tree(s)